ICSI IC62C1024-55Q 128k x 8 high speed cmos static ram Datasheet

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128K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 35, 45, 55, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 500 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
DESCRIPTION
The 1+51 IC62C1024 is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using 1+51 's highperformance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62C1024 is available in 32-pin 600mil DIP, 450mil SOP
and 8*20mm TSOP-1 packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 x 2048
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
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PIN CONFIGURATION
PIN CONFIGURATION
32-Pin SOP and DIP
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE1
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
GND
16
17
I/O3
32-Pin 8x20mm TSOP-1
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Commercial
Ambient Temperature
0°C to +70°C
VCC
5V ± 10%
–40°C to +85°C
5V ± 10%
Industrial
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
2
WE
CE1
CE2
OE
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
DOUT
DIN
Vcc Current
ISB, ISB
ISB, ISB
ICC
ICC
ICC
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ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–10 to +85
–65 to +150
1.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
Conditions
CIN
Input Capacitance
COUT
Output Capacitance
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
Output Leakage
GND ≤ VOUT ≤ VCC
—
0.4
VCC + 0.5
0.8
5
10
5
10
V
V
V
V
µA
ILO
2.4
—
2.2
–0.3
–5
–10
–5
–10
GND ≤ VIN ≤ VCC
Com.
Ind.
Com.
Ind.
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-35 ns
Min. Max.
-45 ns
Min. Max.
-55 ns
Min. Max.
-70 ns
Min. Max.
Symbol Parameter
Test Conditions
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
150
160
—
—
135
145
—
—
120
130
—
—
90
100
Unit
mA
ISB
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
VIN = VIH or VIL, CE1 ≥ VIH, Ind.
or CE2 ≤ VIL, f = 0
—
—
40
60
—
—
40
60
—
—
40
60
—
—
40
60
mA
ISB
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
CE1 ≥ VCC – 0.2V,
Ind.
CE2 ≤ 0.2V, VIN > VCC – 0.2V,
or VIN ≤ 0.2V, f = 0
—
—
30
40
—
—
30
40
—
—
30
40
—
—
30
40
mA
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
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READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
Min.
-35
-45
Min. Max.
Max.
Min.
-55
Max.
Min.
-70
Max.
Unit
tRC
Read Cycle Time
35
—
45
—
55
—
70
—
tAA
Address Access Time
—
35
—
45
—
55
—
70
ns
tOHA
Output Hold Time
3
—
3
—
3
—
3
—
ns
tACE
CE1 Access Time
—
35
—
45
—
55
—
70
ns
tACE
CE2 Access Time
—
35
—
45
—
55
—
70
ns
tDOE
OE Access Time
—
10
—
20
—
25
—
35
ns
ns
tLZOE OE to Low-Z Output
0
—
0
—
0
—
0
—
ns
tHZOE OE to High-Z Output
0
10
0
15
0
20
0
25
ns
3
—
5
—
7
—
10
—
ns
tLZCE
CE1 to Low-Z Output
tLZCE
CE2 to Low-Z Output
3
—
5
—
7
—
10
—
ns
tHZCE CE1 or CE2 to High-Z Output
0
10
0
15
0
20
0
25
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
Figure 1a.
4
255 Ω
5 pF
Including
jig and
scope
255 Ω
Figure 1b.
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AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CE
t ACE
t HZCE
t LZCE
DOUT
HIGH-Z
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
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WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low
Power)
Symbol
Parameter
Min.
-35
Max.
Min.
—
45
-45
Max.
Min.
-55
Max.
Min.
—
70
-70
Max.
Unit
tWC
Write Cycle Time
tSCE
CE1 to Write End
25
—
35
—
50
—
60
—
ns
tSCE
CE2 to Write End
25
—
35
—
50
—
60
—
ns
tAW
Address Setup Time to Write End
25
—
35
—
45
—
60
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
Address Setup Time
0
—
0
—
0
—
0
—
ns
tSA
35
—
55
—
ns
tPWE
WE Pulse Width
25
—
35
—
40
—
50
—
ns
tSD
Data Setup to Write End
20
—
25
—
25
—
30
—
ns
tHD
Data Hold from Write End
"
0
—
0
—
0
—
0
—
ns
tHZWE WE LOW to High-Z Output
—
10
—
15
—
20
—
25
ns
tLZWE
3
—
5
—
5
—
5
—
ns
WE HIGH to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (99- Controlled)(1,2)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
6
t HD
DATAIN VALID
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WRITE CYCLE NO. 2 (+-
+-, CE2 Controlled)(1,2)
+-
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
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ORDERING INFORMATION
Commercial Range: 0°C to +70°C
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
Speed (ns)
35
35
35
IC62C1024-35W
IC62C1024-35Q
IC62C1024-35T
600mil DIP
450mil SOP
8*20mm TSOP-1
45
45
45
IC62C1024-45W
IC62C1024-45Q
IC62C1024-45T
55
55
55
70
70
70
Order Part No.
Package
35
35
35
IC62C1024-35WI
IC62C1024-35QI
IC62C1024-35TI
600mil DIP
450mil SOP
8*20mm TSOP-1
600mil DIP
450mil SOP
8*20mm TSOP-1
45
45
45
IC62C1024-45WI
IC62C1024-45QI
IC62C1024-45TI
600mil DIP
450mil SOP
8*20mm TSOP-1
IC62C1024-55W
IC62C1024-55Q
IC62C1024-55T
600mil DIP
450mil SOP
8*20mm TSOP-1
55
55
55
IC62C1024-55WI
IC62C1024-55QI
IC62C1024-55TI
600mil DIP
450mil SOP
8*20mm TSOP-1
IC62C1024-70W
IC62C1024-70Q
IC62C1024-70T
6600mil DIP
450mil SOP
8*20mm TSOP-1
70
70
70
IC62C1024-70WI
IC62C1024-70QI
IC62C1024-70TI
600mil DIP
450mil SOP
8*20mm TSOP-1
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
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