TI LMR16006Y-Q1 Simple switcher buck regulators with high-efficiency eco mode Datasheet

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LMR16006Y-Q1
SNVSAC1 – JUNE 2015
LMR16006Y-Q1 SIMPLE SWITCHER® Buck Regulators With High-Efficiency ECO Mode
1 Features
3 Description
•
The LMR16006Y-Q1 is a PWM DC-DC buck (stepdown) regulator. It is suitable for a wide range of
application from industrial to automotive for power
conditioning from an unregulated source. The
regulator’s standby current is 28 µA in ECO mode,
which is suitable for battery operating systems. An
ultra-low 1 µA shutdown current can further prolong
battery life. Operating frequency is fixed at 2.1 MHz
allowing the use of small external components while
still being able to have low output ripple voltage. Softstart and compensation circuits are implemented
internally, which allows the device to be used with
minimized external components. The LMR16006Y-Q1
is optimized for up to 600 mA load currents. It has a
0.765 V typical feedback voltage. The device has
built-in protection features such as pulse by pulse
current limit, thermal sensing and shutdown due to
excessive power dissipation. The LMR16006Y-Q1 is
available in a low profile SOT-6L package (2.9 mm x
1.6 mm).
LMR16006Y-Q1 is an Automotive Grade Product
that is a AEC-Q100 Grade 1 Qualified (-40°C to
+125°C Operating Junction Temperature)
Input Voltage Range 4 V to 40 V with Transient
Up to 65 V
Output Current up to 600 mA
2.1 MHz Switching Frequency
Ultra Low 28 µA Standby Current in ECO Mode
1 µA Shutdown Current
High Duty Cycle Operation Supported
ADJ, Fixed 3.3 V and Fixed 5 V Output Option
Internal Compensation
High Voltage Enable Input
Internal Soft Start
Over Current Protection
Over Temperature Protection
Small Overall Solution Size (SOT-6L Package)
1
•
•
•
•
•
•
•
•
•
•
•
•
•
PART NUMBER
2 Applications
•
•
•
•
•
•
Device Information(1)
Automotive
Battery Powered Equipment
Industrial Distributed Power Systems
Portable Handheld Instruments
Portable Media Players
Aftermarket Automotive Accessories: Video, GPS,
Entertainment
PACKAGE
OUTPUT VOLTAGE
SOT (6)
Fixed 3.3 V
LMR16006YQ
LMR16006YQ3
Adjustable
LMR16006YQ5
Fixed 5 V
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
Efficiency vs Output Current
(ƒSW= 2.1 MHz, VOUT= 3.3 V)
VIN
100
CB
Cboot
Cin
L1
90
SW
SHDN
Cout
LMR16006Y
80
D1
GND
FB
R2
Efficiency (%)
R1
70
60
50
40
30
VIN = 12 V
20
1
10
100
Output Current (mA)
1000
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR16006Y-Q1
SNVSAC1 – JUNE 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
5
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
8.3 Feature Description................................................... 8
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
12.5
Detailed Description .............................................. 7
Related Documentation .......................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
5 Revision History
2
DATE
REVISION
NOTES
June 2015
*
Initial release.
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6 Pin Configuration and Functions
DDC Package
6-Pin SOT
Top View
LMR16006Y
CB
1
GND
2
FB
PIN 1 ID
3
6
SW
5
VIN
4
SHDN
Pin Functions
PIN
NAME
NUMBER
I/O
DESCRIPTION
CB
1
I
Switch FET gate bias voltage. Connect Cboot capacitor between CB and SW.
GND
2
G
Ground connection.
FB
3
I
Feedback Input. Set feedback voltage divider ratio with VOUT = VFB (1 + (R1/R2)).
SHDN
4
I
Enable and disable input (high voltage tolerant). Internal pull-up current source. Pull below
1.25 V to disable. Float to enable. Establish input undervoltage lockout with two resistor
divider.
VIN
5
I
Power input voltage pin. Input for internal supply and drain node input for internal high-side
MOSFET.
SW
6
O
Switch node. Connect to inductor, diode, and Cboot capacitor.
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7 Specifications
7.1 Absolute Maximum Ratings
(1)
MIN
MAX
VIN to GND
-0.3
65
SHDN to GND
-0.3
65
FB to GND
-0.3
7
CB to SW
-0.3
7
SW to GND
-1
60
SW to GND less than 30 ns transients
-2
60
TJ Operation junction temperature
-40
150
°C
Storage temperature, Tstg
-55
165
°C
Input voltages
Output voltages
(1)
UNIT
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±2000
Charged-device model (CDM), per AEC Q100-011
V
±500
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Buck regulator
(1)
MIN
MAX
VIN
4
40
CB
4
46
CB to SW
-0.3
6
SW
-1
40
FB
0
5.5
Control
SHDN
0
40
Temperature
Operating junction temperature range, TJ
-40
125
(1)
UNIT
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
THERMAL METRIC
(1)
LMR16006Y-Q1
UNIT
DDC (SOT)
(6 PINS)
RθJA
Junction-to-ambient thermal resistance
102
RθJCtop
Junction-to-case (top) thermal resistance
36.9
RθJB
Junction-to board characterization parameter
28.4
(1)
4
°C/W
All numbers apply for packages soldered directly onto a 3" x 3" PC board with 2 oz. copper on 4 layers in still air in accordance to
JEDEC standards. Thermal resistance varies greatly with layout, copper thickness, number of layers in PCB, power distribution,
numberof thermal vias, board size, ambient temperature, and air flow.
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7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, the following
conditions apply: VIN = SHDN = 12 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN (INPUT POWER SUPPLY)
VIN
Operating input voltage
ISHDN
Shutdown supply current
VEN = 0 V
4
IQ
Operating quiescent current (nonswitching)
no load, VIN = 12 V
UVLO
Undervoltage lockout thresholds
Rising threshold
Falling threshold
1
40
V
3
µA
28
µA
4
3
V
SHDN
VSHDN_Thre
Rising SHDN Threshold Voltage
ISHDN
Input current
ISHDN_HYS
1.05
1.25
SHDN = 2.3 V
-4.2
SHDN = 0.9 V
-1
Hysteresis current
1.38
V
µA
-3
µA
900
mΩ
HIGH-SIDE MOSFET
RDS_ON
On-resistance
VIN = 12 V, CB to SW = 5.8 V
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
VOUT
Output voltage
Fixed 3.3 V output version
Fixed 5 V output version
0.747
0.765
0.782
V
3.201
3.3
3.399
V
4.85
5
5.15
V
1200
1700
mA
CURRENT LIMIT
ILIMIT
Peak current limit
VIN = 12 V, TJ = 25°C
THERMAL PERFORMANCE
TSHDN
THYS
(1)
(1)
(1)
Thermal shutdown threshold
Hysteresis
170
ºC
10
ºC
Ensured by design.
7.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1785
2100
2415
kHz
SW (SW PIN)
ƒSW
Switching frequency
TON_MIN
DMAX
(1)
(1)
Minimum turn-on time
ƒSW = 2.1 MHz
Maximum duty cycle
80
ns
97%
Ensured by design.
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7.7 Typical Characteristics
100
100
90
90
80
80
Efficiency (%)
Efficiency (%)
Unless otherwise specified the following conditions apply: VIN = 12 V, ƒSW = 2100 kHz, L1 = 6.8 µH, Cout = 10 µF, TA = 25°C.
70
60
50
40
70
60
50
40
30
30
VIN = 15 V
VIN = 18 V
20
VIN = 12 V
VIN = 15 V
20
1
10
100
Output Current (mA)
VOUT = 12 V
1000
1
ƒSW = 2100 kHz
VOUT = 5 V
Figure 1. Efficiency vs. Load Current
1000
D003
ƒSW = 2100 kHz
Figure 2. Efficiency vs. Load Current
100
1.5
1
Input Current (µA)
Output Voltage Change (%)
10
100
Output Current (mA)
D002
0.5
0
-0.5
10
1
-1
Shutdown
ECO
0.1
-1.5
0
100
200
300
400
Load Current (mA)
VOUT = 5 V
500
4
600
14
24
D004
ƒSW = 2.1 MHz
34
44
Input Voltage (V)
54
D005
VOUT = 5 V
Figure 3. Load Regulation
Figure 4. Shutdown Current and Quiescent Current
6
3.6
UVLO_H
UVLO_L
Undervoltage Lockout (V)
3.55
5
VOUT (V)
64
4
3
600 mA Load
300 mA Load
100 mA Load
10 mA Load
2
3.8
4.3
4.8
5.3
VIN (V)
5.8
6.3
3.5
3.45
3.4
3.35
3.3
3.25
3.2
3.15
6.8
3.1
-50
D006
0
50
Temperature (°C)
100
150
D007
VOUT = 5 V
Figure 5. Dropout Curve
6
Figure 6. UVLO Threshold
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8 Detailed Description
8.1 Overview
The LMR16006Y-Q1 device is a 60 V, 600 mA, step-down (buck) regulator. The buck regulator has a very low
quiescent current during light load to prolong battery life.
LMR16006Y-Q1 improves performance during line and load transients by implementing a constant frequency,
current mode control which requires less output capacitance and simplifies frequency compensation design. The
switching frequency is fixed at 2.1 MHz, thus smaller inductor and capacitor can be used. The device reduces
the external component count by integrating the boot recharge diode. The bias voltage for the integrated high
side MOSFET is supplied by a capacitor on the CB to SW pin. The boot capacitor voltage is monitored by an
UVLO circuit and will turn the high side MOSFET off when the boot voltage falls below a preset threshold. The
LMR16006Y-Q1 can operate at high duty cycles because of the boot UVLO and refresh the wimp FET. The
output voltage can be stepped down to as low as the 0.8 V reference. Internal soft-start is featured to minimize
inrush currents.
8.2 Functional Block Diagram
VIN
Current Sense
Leading Edge
Blanking
Bootstrap
Regulator
CB
Logic &
PWM Latch
HS
Driver
PWM
Comparator
SW
Frequency
Shift
Wimp FET
CB Refresh
±
+
COMP
+
EA +
0.765 V
SS
±
Main OSC
SHDN
Bandgap
Ref
FB
™
Slope
Compensation
GND
Fixed Output Option
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8.3 Feature Description
8.3.1 Fixed Frequency PWM Control
The LMR16006Y-Q1 implements peak current mode control. The output voltage is compared through external
resistors on the FB pin to an internal voltage reference by an error amplifier which drives the internal COMP
node. An internal oscillator initiates the turn on of the high side power switch. The error amplifier output is
compared to the high side power switch current. When the power switch current reaches the level set by the
internal COMP voltage, the power switch is turned off. The internal COMP node voltage will increase and
decrease as the output current increases and decreases. The device implements a current limit by clamping the
COMP node voltage to a maximum level.
8.3.2 Bootstrap Voltage (CB)
The LMR16006Y-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the CB
and SW pins to provide the gate drive voltage for the high side MOSFET. The CB capacitor is refreshed when
the high side MOSFET is off and the low side diode conducts. To improve drop out, the LMR16006Y-Q1 is
designed to operate at 97% duty cycle as long as the CB to SW pin voltage is greater than 3 V. When the
voltage from CB to SW drops below 3 V, the high side MOSFET is turned off using an UVLO circuit which allows
the low side diode to conduct and refresh the charge on the CB capacitor. Since the supply current sourced from
the CB capacitor is low, the high side MOSFET can remain on for more switching cycles than are required to
refresh the capacitor, thus the effective duty cycle of the switching regulator is high. Attention must be taken in
maximum duty cycle applications with light load. To ensure SW can be pulled to ground to refresh the CB
capacitor, an internal circuit will charge the CB capacitor when the load is light or the device is working in dropout
condition.
8.3.3 Output Voltage Setting
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown on the
front page schematic. The feedback pin voltage 0.765 V, so the ratio of the feedback resistors sets the output
voltage according to the following equation: VOUT = 0.765 V (1 + (R1/R2)). Typically R2 will be given as 1 kΩ to
100 kΩ for a starting value. To solve for R1 given R2 and VOUT use R1 = R2 ((VOUT/0.765 V) – 1).
8.3.4 Enable SHDN and VIN Undervoltage Lockout
LMR16006Y-Q1 SHDN pin is a high voltage tolerant input with an internal pull up circuit. The device can be
enabled even if the SHDN pin is floating. The regulator can also be turned on using 1.23 V or higher logic
signals. If the use of a higher voltage is desired due to system or other constraints, a 100 kΩ or larger resistor is
recommended between the applied voltage and the SHDN pin to protect the device. When SHDN is pulled down
to 0 V, the chip is turned off and enters the lowest shutdown current mode. In shutdown mode the supply current
will be decreased to approximately 1 µA. If the shutdown function is not to be used the SHDN pin may be tied to
VIN via 100 kΩ resistor. The maximum voltage to the SHDN pin should not exceed 60 V. LMR16006Y-Q1 has an
internal UVLO circuit to shutdown the output if the input voltage falls below an internally fixed UVLO threshold
level. This ensures that the regulator is not latched into an unknown state during low input voltage conditions.
The regulator will power up when the input voltage exceeds the voltage level. If there is a requirement for a
higher UVLO voltage, the SHDN can be used to adjust the system UVLO by using external resistors.
8.3.5 Current Limit
The LMR16006Y-Q1 implements current mode control which uses the internal COMP voltage to turn off the high
side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and internal COMP voltage are
compared, when the peak switch current intersects the COMP voltage, the high side switch is turned off. During
overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP node
high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch
current limit.
8
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Feature Description (continued)
8.3.6 Overvoltage Transient Protection
The LMR16006Y-Q1 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage
overshoot when recovering from output fault conditions or strong unload transients on power supply designs with
low value output capacitance. For example, when the power supply output is overloaded the error amplifier
compares the actual output voltage to the internal reference voltage. If the FB pin voltage is lower than the
internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the
error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is
removed, the regulator output rises and the error amplifier output transitions to the steady state duty cycle. In
some applications, the power supply output voltage can respond faster than the error amplifier output can
respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output
overshoot, when using a low value output capacitor, by implementing a circuit to compare the FB pin voltage to
OVTP threshold which is 108% of the internal voltage reference. If the FB pin voltage is greater than the OVTP
threshold, the high side MOSFET is disabled preventing current from flowing to the output and minimizing output
overshoot. When the FB voltage drops lower than the OVTP threshold, the high side MOSFET is allowed to turn
on at the next clock cycle.
8.3.7 Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds
170°C(typ). The thermal shutdown forces the device to stop switching when the junction temperature exceeds
the thermal trip threshold. Once the junction temperature decreases below 160°C(typ), the device reinitiates the
power up sequence.
8.4 Device Functional Modes
8.4.1 Continuous Conduction Mode
The LMR16006Y-Q1 steps the input voltage down to a lower output voltage. In continuous conduction mode
(when the inductor current never reaches zero at CCM), the buck regulator operates in two cycles. The power
switch is connected between VIN and SW. In the first cycle of operation the transistor is closed and the diode is
reverse biased. Energy is collected in the inductor and the load current is supplied by Cout and the rising current
through the inductor. During the second cycle the transistor is open and the diode is forward biased due to the
fact that the inductor current cannot instantaneously change direction. The energy stored in the inductor is
transferred to the load and output capacitor. The ratio of these two cycles determines the output voltage. The
output voltage is defined approximately as: D = VOUT/VIN and D' = (1-D) where D is the duty cycle of the switch,
D and D' will be required for design calculations.
8.4.2 ECO Mode
The LMR16006Y-Q1 operates in ECO mode at light load currents to improve efficiency by reducing switching
and gate drive losses. The LMR16006Y-Q1 is designed so that if the output voltage is within regulation and the
peak switch current at the end of any switching cycle is below the sleep current threshold, IINDUCTOR ≤ 80 mA, the
device enters ECO mode. For ECO mode operation, the LMR16006Y-Q1 senses peak current, not average or
load current, so the load current where the device enters ECO mode is dependent on VIN, VOUT and the output
inductor value. When the load current is low and the output voltage is within regulation, the device enters an
ECO mode and draws only 28 µA input quiescent current.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LMR16006Y-Q1 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 600 mA. Detailed Design Procedure can be used to select
components for the LMR16006Y-Q1.
9.2 Typical Application
Figure 7 shows typical application where user can adjust output by R1 and R2.
VIN
VIN
Cin
2.2 µF
CB
100 k Cboot
100 nF
SW
SHDN
L1
6.8 µH
5 V, 0.6 A
LMR16006Y
D1
GND
Cout
10 µF
R1
54.9 k
FB
R2
10 k
Figure 7. Application Circuit, 5 V Output
9.2.1 Design Requirements
Example requirements for typical buck regulators with high-efficiency applications:
Table 1. Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage, VIN
9 V to 16 V, typical 12 V
Output voltage, VOUT
5 V ± 3%
Maximum output current IO_max
0.6 A
Minimum output current IO_min
0.03 A
Transient response 0.03 A to 0.6 A
5%
Output voltage ripple
1%
Switching frequency ƒSW
2.1 MHz
Target during Load Transient
Overvoltage peak value
106% of output voltage
Undervoltage value
91% of output voltage
9.2.2 Detailed Design Procedure
This example details the design of a high frequency switching regulator using ceramic output capacitors. A few
parameters must be known in order to start the design process. These parameters are typically determined at the
system level:
10
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9.2.2.1 Output Inductor Selection
The most critical parameters for the inductor are the inductance, peak current and the DC resistance. The
inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages. Since the
ripple current increases with the input voltage, the maximum input voltage is always used to determine the
inductance. To calculate the minimum value of the output inductor, use Equation 1. KIND is a coefficient that
represents the amount of inductor ripple current relative to the maximum output current. A reasonable value is
setting the ripple current to be 30%-40% of the DC output current. For this design example, the minimum
inductor value is calculated to be 6.82 µH, and a nearest standard value was chosen: 6.8 µH. For the output filter
inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak
inductor current can be found from Equation 3 and Equation 4. The inductor ripple current is 0.074 A, and the
RMS current is 0.60 A. As the equation set demonstrates, lower ripple currents will reduce the output voltage
ripple of the regulator but will require a larger value of inductance. A good starting point for most applications is
6.8 μH with a 1.6 A current rating. Using a rating near 1.6 A will enable the LMR16006Y-Q1 to current limit
without saturating the inductor. This is preferable to the LMR16006Y-Q1 going into thermal shutdown mode and
the possibility of damaging the inductor if the output is shorted to ground or other long-term overload.
Vin max Vout
Vout
Lo min
u
I o u K IND
Vin max u f sw
(1)
I ripple
I L-RMS
I L peak
Vout u (Vin max Vout )
Vin max u Lo u f sw
(2)
1
I ripple2
12
(3)
I o2 Io I ripple
2
(4)
9.2.2.2 Output Capacitor Selection
The selection of Cout is mainly driven by three primary considerations. The output capacitor will determine the
modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The
output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The regulator usually needs two or
more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty
cycle to react to the change. The output capacitance must be large enough to supply the difference in current for
2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 5 shows the
minimum output capacitance necessary to accomplish this. The transient load response is specified as a 3%
change in VOUT for a load step from 0.03 A to 0.6 A (full load), ΔIOUT = 0.6 – 0.03 = 0.57 A and ΔVOUT = 0.03 × 5
= 0.15 V. Using these numbers gives a minimum capacitance of 3.62 µF. For ceramic capacitors, the ESR is
usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher
ESR that should be taken into account.
The stored energy in the inductor will produce an output voltage overshoot when the load current rapidly
decreases. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning
from a high load current to a lower load current. Equation 6 is used to calculate the minimum capacitance to
keep the output voltage overshoot to a desired value. Where L is the value of the inductor, IOH is the output
current under heavy load, IOL is the output under light load, Vf is the final peak output voltage, and Vi is the initial
capacitor voltage. For this example, the worst case load step will be from 0.6 A to 0.03 A. The output voltage will
increase during this load transition and the stated maximum in our specification is 3% of the output voltage. This
will make Vo_overshoot = 1.03 × 5 = 5.15 V. Vi is the initial capacitor voltage which is the nominal output voltage
of 5 V. Using these numbers in Equation 6 yields a minimum capacitance of 1.6 µF.
Equation 7 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where ƒsw is the switching frequency, Vo_ripple is the maximum allowable output voltage ripple, and IL_ripple is the
inductor ripple current. Equation 7 yields 95 nF.
Equation 8 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification. Equation 8 indicates the ESR should be less than 623 mΩ.
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Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase
this minimum value. For this example, 10 µF ceramic capacitors will be used. Capacitors in the range of 4.7 µF100 µF are a good starting point with an ESR of 0.7 Ω or less.
2 u 'I out
Cout !
fsw u 'Vout
(5)
Cout ! Lo u
Cout
( Ioh2 Iol 2 )
(Vf 2 Vi 2 )
1
1
!
u
8 u fsw Vo _ ripple
(6)
I L _ ripple
RESR (7)
Vo _ ripple
I L _ ripple
(8)
9.2.2.3 Schottky Diode Selection
The breakdown voltage rating of the diode is preferred to be 25% higher than the maximum input voltage. In the
target application, the current rating for the diode should be equal or greater to the maximum output current for
best reliability in most applications. In cases where the input voltage is not much greater than the output voltage
the average diode current is lower. In this case it is possible to use a diode with a lower average current rating,
approximately (1-D) × IOUT. However the peak current rating should be higher than the maximum load current. A
0.5 A to 1 A rated diode is a good starting point.
9.2.2.4 Input Capacitor Selection
A low ESR ceramic capacitor is needed between the VIN pin and ground pin. This capacitor prevents large
switching voltage transients from appearing at the input. Use a 1 µF-10 µF value with X5R or X7R dielectric.
Depending on construction, a ceramic capacitor’s value can decrease up to 50% of its nominal value when rated
voltage is applied. Consult with the capacitor manufactures data sheet for information on capacitor derating over
voltage and temperature. The capacitor must also have a ripple current rating greater than the maximum input
current ripple of the LMR16006Y-Q1. The input ripple current can be calculated using below Equation 9.
For this example design, one 2.2 µF, 50 V capacitor is selected. The input capacitance value determines the
input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 10. Using the
design example values, IOUT_max = 0.6 A, Cin = 2.2 µF, ƒSW = 2100 kHz, yields an input voltage ripple of 33 mV
and a rms input ripple current of 0.3 A.
I cirms
'Vin
I out u
(Vin min Vout )
Vout
u
Vin min
Vin min
(9)
I out max u 0.25
Cin u fsw
(10)
9.2.2.5 Bootstrap Capacitor Selection
A 0.1 μF ceramic capacitor or larger is recommended for the bootstrap capacitor (CBOOT). For applications where
the input voltage is close to output voltage a larger capacitor is recommended, generally 0.1 µF to 1 µF to ensure
plenty of gate drive for the internal switches and a consistently low RDSON. A ceramic capacitor with an X7R or
X5R grade dielectric with a voltage rating of 10 V or higher is recommended because of the stable characteristics
over temperature and voltage.
12
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, ƒSW = 2100 kHz, L1 = 6.8 µH, COUT = 10
µF, TA = 25°C.
VOUT = 5 V
IOUT = 0 mA
VOUT = 5 V
Figure 8. Steady State Waveform
VIN = 15 V
VOUT = 12 V
IOUT = 600 mA
Figure 9. Steady State Waveform
VIN = 15 V
Figure 10. Start-Up
VIN = 12 V
VOUT = 5 V
IOUT = 600 mA
VOUT = 12 V
IOUT = 600 mA
Figure 11. Shutdown
IOUT = 600 mA
VIN = 12 V
Figure 12. Load Transient from 0.1 A to 0.6 A
VOUT = 5 V
Figure 13. Short Circuit Entry
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9.2.4 Additional Application Circuit
Figure 14 shows the typical application circuit with a fixed output.
VIN
VIN
CB
Cin
2.2 µF
Cboot
100 nF
SW
SHDN
L1
6.8 µH
LMR16006Y
D1
Cout
10 µF
FB
GND
Figure 14. LMR16006Y-Q1 Application Circuit, Fixed Output
10 Power Supply Recommendations
The LMR16006Y-Q1 is designed to operate from an input voltage supply range between 4 V and 60 V. This input
supply should be able to withstand the maximum input current and maintain a voltage above 4 V. The resistance
of the input supply rail should be low enough that an input current transient does not cause a high enough drop
at the LMR16006Y-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input
supply is located more than a few inches from the LMR16006Y-Q1, additional bulk capacitance may be required
in addition to the ceramic input capacitors.
14
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11 Layout
11.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The feedback network, resistors R1 and R2, should be kept close to the FB pin, and away from the inductor
to minimize coupling noise into the feedback pin.
2. The input bypass capacitor Cin must be placed close to the VIN pin. This will reduce copper trace resistance
which effects input voltage ripple of the IC.
3. The inductor L1 should be placed close to the SW pin to reduce magnetic and electrostatic noise.
4. The output capacitor, Cout should be placed close to the junction of L1 and the diode D1. The L1, D1, and
Cout trace should be as short as possible to reduce conducted and radiated noise and increase overall
efficiency.
5. The ground connection for the diode, Cin, and Cout should be as small as possible and tied to the system
ground plane in only one spot (preferably at the Cout ground point) to minimize conducted noise in the
system ground plane.
6. For more detail on switching power supply layout considerations see AN-1149 Layout Guidelines for
Switching Power Supplies SNVA021
11.2 Layout Example
Figure 15. Layout
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12 Device and Documentation Support
12.1 Related Documentation
AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021).
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
SIMPLE SWITCHER is a registered trademark of TI .
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMR16006YQ3DDCRQ1
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Q32Y
LMR16006YQ3DDCTQ1
ACTIVE
SOT
DDC
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Q32Y
LMR16006YQ5DDCRQ1
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Q52Y
LMR16006YQ5DDCTQ1
ACTIVE
SOT
DDC
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Q52Y
LMR16006YQDDCRQ1
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Q02Y
LMR16006YQDDCTQ1
ACTIVE
SOT
DDC
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
Q02Y
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jul-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMR16006YQ3DDCRQ1
SOT
DDC
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMR16006YQ3DDCTQ1
SOT
DDC
6
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMR16006YQ5DDCRQ1
SOT
DDC
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMR16006YQ5DDCTQ1
SOT
DDC
6
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMR16006YQDDCRQ1
SOT
DDC
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LMR16006YQDDCTQ1
SOT
DDC
6
250
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMR16006YQ3DDCRQ1
SOT
DDC
6
3000
210.0
185.0
35.0
LMR16006YQ3DDCTQ1
SOT
DDC
6
250
210.0
185.0
35.0
LMR16006YQ5DDCRQ1
SOT
DDC
6
3000
210.0
185.0
35.0
LMR16006YQ5DDCTQ1
SOT
DDC
6
250
210.0
185.0
35.0
LMR16006YQDDCRQ1
SOT
DDC
6
3000
210.0
185.0
35.0
LMR16006YQDDCTQ1
SOT
DDC
6
250
210.0
185.0
35.0
Pack Materials-Page 2
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