LINER LTC4215IUFD-1 Hot swap controller with i2c compatible monitoring Datasheet

LTC4215-1
Hot Swap Controller with
I2C Compatible Monitoring
FEATURES
DESCRIPTION
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The LTC®4215-1 Hot Swap™ controller allows a board to be
safely inserted and removed from a live backplane. Using
an external N-channel pass transistor, board supply voltage
and inrush current are ramped up at an adjustable rate.
An I2C interface and onboard ADC allow for monitoring
of load current, voltage and fault status.
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Allows Safe Insertion into Live Backplane
8-Bit ADC Monitors Current and Voltage
I2C/SMBus Interface
Wide Operating Voltage Range: 2.9V to 15V
dI/dt Controlled Soft-Start
Three General Purpose Outputs
High Side Drive for External N-channel MOSFET
No External Gate Capacitor Required
Input Overvoltage/Undervoltage Protection
Optional Latchoff or Auto-Retry After Faults
Alerts Host After Faults
Inrush Current Limit with Foldback
Available in 24-Pin (4mm × 5mm) QFN
The device features adjustable foldback current limit and
a soft-start pin that sets the dI/dt of the inrush current.
An I2C interface may configure the part to latch off or
automatically restart after the LTC4215-1 detects a current limit fault.
The controller has additional features to interrupt the host
when a fault has occurred, provide three general purpose
outputs, notify when output power is good, detect insertion
of a load card, and power-up either automatically upon
insertion or wait for an I2C command to turn on.
APPLICATIONS
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Live Board Insertion
Electronic Circuit Breakers
Computers, Servers
Platform Management
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Hot Swap
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners. Protected by U.S. Patent 7330065.
TYPICAL APPLICATION
12V Application With 5A Circuit Breaker
Start-Up Waveform
0.003Ω
12V
VOUT
12V
+
CL
CONNECTOR 1
CONNECTOR 2
34k
VDD
10V/DIV
10Ω
3.57k
0.1μF
1.74k
2.67k
SMBJ14A
SDA
SCL
30.1k
UV VDD SENSE+ SENSE– GATE SOURCE
FB
OV
SDAI
GPIO1
SDAO
LTC4215-1
GPIO2
SCL
GPIO3
ADR0
ADIN
ADR1
INTVCC
ON TIMER SS
GND
EN
POWERGOOD
INRUSH
CURRENT
2.5A/DIV
CONTACT
BOUNCE
VOUT
10V/DIV
RESET
OK LED
MEASURED
VOLTAGE
VGPIO1
10V/DIV
5k PULL-UP TO VDD
0.1μF
68nF
CL = 12000μF
GND
40ms/DIV
42151 TA01b
4215 TA01a
BACKPLANE PLUG-IN
CARD
42151fa
1
LTC4215-1
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
SOURCE
GATE
SENSE–
SENSE+
VDD
TOP VIEW
24 23 22 21 20
UV 1
19 FB
OV 2
18 GPIO1
SS 3
17 INTVCC
25
GND 4
16 TIMER
ON 5
15 ADIN
EN 6
14 GPIO3
13 ADR1
ADR0
NC
9 10 11 12
GPIO2
8
SCL
SDAO 7
SDAI
Supply Voltage (VDD) ................................ –0.3V to 24V
Supply Voltage (INTVCC) .......................... –0.3V to 6.5V
Input Voltages
GATE-SOURCE (Note 3) .......................... –0.3V to 5V
SENSE+, SENSE– ................ VDD – 0.3V to VDD + 0.3V
SOURCE.................................................... –5V to 24V
EN, FB, ON, OV, UV ................................ –0.3V to 12V
ADR0, ADR1, TIMER,
ADIN, SS................................ –0.3V to INTVCC + 0.3V
GPIO2, GPIO3, SCL, SDA, SDAI, SDAO –0.3V to 6.5V
Output Voltages
GATE, GPIO1.......................................... –0.3V to 24V
GPIO2, GPIO3 ....................................... –0.3V to 6.5V
Operating Temperature Range
LTC4215C-1 ............................................. 0°C to 70°C
LTC4215I-1 .......................................... –40°C to 85°C
Storage Temperature Range
QFN.................................................... –65°C to 125°C
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 25) PCB GND CONNECTION OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4215CUFD-1#PBF
LTC4215IUFD-1#PBF
LTC4215CUFD-1#TRPBF
LTC4215IUFD-1#TRPBF
42151
42151
24-Lead (4mm × 5mm) Plastic QFN
24-Lead (4mm × 5mm) Plastic QFN
0°C to 70°C
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4215CUFD-1
LTC4215IUFD-1
LTC4215CUFD-1#TR
LTC4215IUFD-1#TR
42151
42151
24-Lead (4mm × 5mm) Plastic QFN
24-Lead (4mm × 5mm) Plastic QFN
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supplies
VDD
Input Supply Range
l
2.9
VOV(VDD)
Input Supply Overvoltage Threshold
l
15
IDD
Input Supply Current
l
VDD(UVL)
Input Supply Undervoltage Lockout
VDD(HYST)
Input Supply Undervoltage Lockout Hysteresis
VDD Rising
15
V
15.6
16.5
V
3
5
mA
l
2.75
2.84
2.89
V
l
75
100
125
mV
42151fa
2
LTC4215-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
INTVCC
Internal Regulator Voltage
VDD ≥ 3.3V
l
2.9
3.1
3.4
UNITS
V
INTVCC(UVL)
INTVC Undervoltage Lockout
INTVCC Rising
l
2.55
2.64
2.79
V
INTVCC(HYST)
INTVC Undervoltage Lockout Hysteresis
l
20
55
75
mV
Current Limit and Circuit Breaker
l
22.5
25
27.5
mV
l
l
l
OC Fault Filter
VFB = 1.3V
VFB = 0V
Start-Up Timer Expired
ΔVSENSE = 50mV
l
22
6.5
65
15
25
10
75
20
29
13
90
30
mV
mV
mV
μs
SENSE± Pin Input Current
VSENSE = 12V
l
10
20
35
μA
VDD = 2.9V to 15V
l
4.7
5.9
6.5
V
IGATE(UP)
External N-channel Gate Drive (VGATE – VSOURCE)
(Note 3)
External N-channel Gate Pull-Up Current
Gate On, VGATE = 0V
l
–15
–20
–30
μA
IGATE(DN)
External N-channel Gate Pull-Down Current
Gate Off, VGATE = 15V
l
0.8
1
1.6
mA
IGATE(DN) Fast
Pull-Down Current from GATE to SOURCE During VDD – SENSE = 100mV, VAS = 4V
OC/UVLO
(VDD – SENSE) High to GATE Low
VDD – SENSE = 100mV, CAS = 10nF
300
450
700
mA
l
0.5
1
μs
Gate-Source Voltage for Power Bad Fault
VSOURCE = 2.9V – 15V
l
3.8
4.3
4.7
V
VON Rising
l
1.210
1.235
1.26
V
l
60
128
180
mV
0
±1
μA
ΔVSENSE(TH)
Circuit Breaker Threshold (VDD – VSENSE)
ΔVSENSE
Current Limit Voltage (VDD – VSENSE)
tD(OC)
ISENSE(IN)
Gate Drive
ΔVGATE
tPHL(SENSE)
VGS(POWERBAD)
Comparator Inputs
VON(TH)
ON Pin Threshold Voltage
ΔVON(HYST)
ON Pin Hysteresis
ION(IN)
ON Pin Input Current
VEN(TH)
EN Input Threshold
ΔVEN(HYST)
EN Hysteresis
IEN
EN Pin Input Current
EN = 3.5V
l
VOV(TH)
OV Pin Threshold Voltage
VOV Rising
l
ΔVOV(HYST)
OV Pin Hysteresis
l
IOV(IN)
OV Pin Input Current
VOV = 1.8V
l
VUV(TH)
UV Pin Threshold Voltage
VUV Rising
ΔVUV(HYST)
UV Pin Hysteresis
IUV(IN)
UV Pin Input Current
VUV = 1.8V
l
VUV(RTH)
UV Pin Reset Threshold Voltage
VUV Falling
l
VON = 1.2V
l
VEN = Rising
l
1.215
1.235
1.255
l
50
128
200
mV
0
±1
μA
1.215
1.235
1.255
V
10
30
40
mV
0.2
±1
μA
l
1.215
1.235
1.255
V
l
60
80
100
mV
0.2
±1
μA
0.4
0.47
V
mV
0.33
V
l
60
125
210
l
1.215
1.235
1.255
l
3
8
15
mV
0.2
±1
μA
ΔVUV(RHYST)
UV Pin Reset Threshold Hysteresis
VFB
Foldback Pin Power Good Threshold
ΔVFB(HYST)
FB Pin Power Good Hysteresis
IFB
Foldback Pin Input Current
FB = 1.8V
l
VGPIO1(TH)
GPIO1 Pin Input Threshold
VGPIO1 Rising
l
0.8
1
1.2
V
VGPIO2(TH)
GPIO2 Pin Input Threshold
VGPIO2 Rising
l
1
1.6
2
V
VGPIO3 Rising
l
1
1.6
2
V
VGPIO3(TH)
GPIO3 Pin Input Threshold
FB Rising
V
42151fa
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LTC4215-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Other Pin Functions
VGPIO1(OL)
GPIO1 Pin Output Low Voltage
IGPIO1 = 5mA
l
0.25
0.4
V
VGPIO2(OL)
GPIO2 Output Low Voltage
IGPIO2 = 3mA
l
0.2
0.4
V
VGPIO3(OL)
GPIO3 Output Low Voltage
IGPIO3 = 1mA
l
0.2
0.4
V
IGPIO1-3(OH)
GPIO1-3 Pin Input Leakage Current
VGPIO1 = 15V, VGPIO2-3 = 5V
l
0
±1
μA
SOURCE = 15V
l
80
120
μA
3
5
μs
1
100
5
0.2
2
150
75
0.23
μs
ms
s
V
ISOURCE
SOURCE Pin Input Current
tP(GATE)
Input (ON, OV, UV, EN) to GATE Off
Propagation Delay
Turn-On Delay
tD(GATE)
40
l
ON
UV, OV, EN
Overcurrent Auto-Retry
l
l
l
VTIMERL(TH)
Timer Low Threshold
l
50
2.5
0.17
VTIMERH(TH)
Timer High Threshold
l
1.2
1.235
1.26
V
ITIMER(UP)
TIMER Pin Pull-Up Current
l
–80
–100
–120
μA
ITIMER(DOWN)
TIMER Pin Pull-Down Current for OC Auto-Retry
l
1.4
2
2.6
μA
l
40
50
60
l
l
–7.5
–0.4
–10
–0.7
–12.5
–1.0
l
8
l
l
l
–2
–1.25
–1.25
0.5
0.2
0.2
37.625
15.14
1.205
1
38.45
15.44
1.23
2
l
ITIMER(UP/DOWN) TIMER Current Up/Down Ratio
ISS
Soft-Start Ramp Pull-Up Current
Ramping
Waiting for GATE to Slew
μA
μA
ADC
RES
Resolution (No Missing Codes)
INL
Integral Nonlinearity
VOS
Offset Error (Note 4)
TUE
Total Unadjusted Error
FSE
Full-Scale Error
VFS
Full-Scale Voltage (255 • VLSB)
RADIN
ADIN Pin Sampling Resistance
VDD – SENSE (Note 5)
SOURCE
ADIN
VDD – SENSE
SOURCE
ADIN
VDD – SENSE
SOURCE
ADIN
VDD – SENSE
SOURCE
ADIN
VDD – SENSE
SOURCE
ADIN
VADIN = 1.28V
IADIN
ADIN Pin Input Current
VADIN = 1.28V
Bits
l
l
l
l
l
l
l
l
l
l
l
l
l
0
Conversion Rate
2
1.25
1.25
±2.0
±1.0
±1.0
±5.5
±5.0
±5.0
±5.5
±5.0
±5.0
39.275
15.74
1.255
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
mV
V
V
MΩ
±0.1
μA
10
Hz
I2C Interface
VADR(H)
ADR0, ADR1, Input High Voltage
IADR(IN,Z)
ADR0, ADR1, Hi-Z Input Current
VADR(L)
ADR0, ADR1, Input Low Voltage
IADR(IN)
ADR0, ADR1, Input Current
l
ADR0, ADR1= 0.8V
ADR0, ADR1= INTVCC – 0.8V
ADR0, ADR1 = 0V, INTVCC
l
l
INTVCC
–0.8
l
3
0.2
l
–80
INTVCC
–0.4
0.4
INTVCC
–0.2
–3
V
0.8
μA
μA
V
80
μA
42151fa
4
LTC4215-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
l
VSDA,SCL(TH)
SDA, SCL Input Threshold
ISDA,SCL(OH)
SDA, SCL Input Current
SCL, SDA = 5V
l
VSDA(OL)
SDA Output Low Voltage
ISDA = 3mA
l
Operates with fSCL ≤ fSCL(MAX)
l
MIN
TYP
MAX
1.3
1.7
1.9
V
±1
μA
0.4
V
0.2
UNITS
I2C Interface Timing
SCL Clock Frequency
fSCL(MAX)
400
1000
kHz
tBUF(MIN)
Bus Free Time Between Stop/Start Condition
l
0.12
1.3
μs
tHD,STA(MIN)
Hold Time After (Repeated) Start Condition
l
30
600
ns
tSU,STA(MIN)
Repeated Start Condition Set-Up Time
l
30
600
ns
tSU,STO(MIN)
Stop Condition Set-Up Time
l
140
600
ns
tHD,DAT(MIN)
Data Hold Time (Input)
l
30
100
ns
tHD,DATO
Data Hold Time (Output)
l
tSU,DAT(MIN)
Data Set-Up Time
l
tSP
Suppressed Spike Pulse Width
l
CX
SCL, SDA Input Capacitance
50
500
900
ns
30
600
ns
110
250
ns
10
pF
l
SDAI Tied to SDAO (Note 6)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the
device.
300
Note 4: Offset error is the offset voltage measured from 1LSB when the
output code flickers between 0000 0000 and 0000 0001.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
precise analog input voltage. Maximum specifications are limited by the
LSB step size and the single shot measurement. Typical specifications are
measured from the 1/4, 1/2 and 3/4 areas of the quantization band.
Note 6: Guaranteed by design and not subject to test.
TYPICAL PERFORMANCE CHARACTERISTICS. TA = 25°C, VDD = 12V unless otherwise noted.
IDD vs VDD
INTVCC vs VDD
INTVCC vs ILOAD
4.0
4
4
VDD = 12V, 5V
3
3
VDD = 3.3V
2
VCC (V)
VDD (V)
IDD (mA)
3.5
2
3.0
1
1
2.5
0
0
5
15
10
VDD (V)
20
25
0
2.5
3.0
3.5
4.0
INTVCC (V)
4215 G01
4215 G02
0
2
6
4
ILOAD (mA)
8
10
4215 G03
42151fa
5
LTC4215-1
TYPICAL PERFORMANCE CHARACTERISTICS
VTH(UV) vs Temperature
TA = 25°C, VDD = 12V unless otherwise noted.
VHYST(UV) vs Temperature
1.240
ITIMER vs Temperature
90
110
85
105
1.236
1.234
ITIMER (μA)
VHYST(UV) (mV)
VTH (UV) RISING (V)
1.238
80
75
1.232
1.230
–50
–25
50
25
0
TEMPERATURE (°C)
95
70
–50
100
75
–25
50
25
0
TEMPERATURE (°C)
10
5
0
0.2
0.6
0.4
0.8
1.0
1.2
26
VDD = 5V, 12V
VDD = 3.3V
25
24
10
1
23
22
–50
1.4
100
100
TPHL V(GATE) (μs)
CIRCUIT BREAKER THRESHOLD (mV)
15
75
TPHL(GATE) vs Sense Voltage
27
30
20
50
25
0
TEMPERATURE (°C)
4215 G06
VTH Circuit Breaker vs Temperature
25
–25
4215 G05
Current Limit vs VFB
ILIM (mV)
90
–50
100
75
4215 G04
0
100
–25
VFB (V)
50
25
0
TEMPERATURE (°C)
75
0.1
100
0
25
50
75
100
125
V(SENSE+) – V(SENSE–) (mV)
150
4215 G17
4215 G08
4215 G07
7
VDD = 5V
VDD = 5V
6
VDD = 12V
–25
5
ΔVGATE (V)
5.9
–30
5.8
5.7
VDD = 12V
IGATE (μA)
6.0
ΔVGATE(SOURCE) (V)
IGATE Pull-Up vs Temperature
ΔVGATE vs IGATE
ΔVGATE vs Temperature
6.1
4
VDD = 3.3V
3
–20
VDD = 3.3V
5.6
2
5.5
1
5.4
–50
–15
0
–25
0
25
50
75
100
TEMPERATURE (°C)
0
5
10
15
20
25
IGATE (μA)
4215 G09
4215 G10
–10
–50
–25
50
25
0
TEMPERATURE (°C)
75
100
4315 G11
42151fa
6
LTC4215-1
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD = 12V unless otherwise noted.
Total Unadjusted Error
vs Code (ADIN)
VOL(GPIO1) vs IGPIO1
0.6
0.006
0.5
0.005
ADC INL vs Code (ADIN)
0.5
VDD = 3.3V, 5V, 12V
0.3
0.3
0.2
0.004
INL (LSB)
ERROR (mV)
0.4
0.003
0.2
0.002
0.1
0.001
0
0
0.1
0
–0.1
–0.2
–0.3
–0.4
2
4
6
IGPIO1 (mA)
8
10
–0.5
0
64
4215 G12
128
CODE
192
1.0
0.4
0.8
0.3
0.6
0.2
0.1
0
–0.1
–0.2
–0.3
192
256
4215 G14
0
–0.2
–0.4
–0.6
–0.8
–1.0
–50
192
128
CODE
0.4
–0.5
128
CODE
64
0.2
–0.4
64
0
ADC Full-Scale Error
vs Temperature
0.5
0
256
4215 G13
ADC DNL vs Code (ADIN)
FULL-SCALE ERROR (LSB)
0
DNL (LSB)
VOL(GPIO1) (V)
0.4
256
4215 G15
–25
50
25
0
TEMPERATURE (°C)
75
100
4215 G05
42151fa
7
LTC4215-1
PIN FUNCTIONS
ADIN: ADC Input. A voltage between 0V and 1.235V applied to this pin is measured by the onboard ADC. Tie to
ground if unused.
ADR0, ADR1: Serial Bus Address Inputs. Tying these pins
to ground, to the INTVCC pin or leaving open configures
one of 9 possible addresses. See Table 1 in Applications
Information.
EN: Enable Input. Ground this pin to indicate a board is
present and enable the N-channel MOSFET to turn on. When
this pin is high, the MOSFET is not allowed to turn on. An
internal 10μA current source pulls up this pin. Transitions
on this pin are recorded in the Fault register. A high-to-low
transition activates the logic to read the state of the ON
pin and clear Faults. See Applications Information.
Exposed Pad (Pin 25): Exposed Pad may be left open or
connected to device ground.
FB: Foldback Current Limit and Power Good Input. A
resistive divider from the output is tied to this pin. When
the voltage at this pin drops below 1.235V, power is not
considered good. The power bad condition may result
in the GPIO1 pin pulling low or going high impedance
depending on the configuration of control register bits
A6 and A7. Also a power bad fault is logged in this condition if the LTC4215-1 has finished the start-up cycle and
the GATE pin is high (See Applications Information). The
start-up current limit folds back from a 25mV sense voltage to 10mV as the FB pin voltage drops from 1.3V to 0V.
Foldback is not active once the part leaves start-up and
the current limit is increased to 75mV.
GATE: Gate Drive for External N-channel MOSFET. An
internal 20μA current source charges the gate of the
MOSFET. No compensation capacitor is required on the
GATE pin, but a resistor and capacitor network from this
pin to ground may be used to set the turn-on output
voltage slew rate (See Applications Information). During
turn-off there is a 1mA pull-down current. During a short
circuit or undervoltage lockout (VDD or INTVCC), a 450mA
pull-down current source between GATE and SOURCE is
activated.
GND: Device Ground.
GPIO1: General Purpose Input/Output and Signals Power
Good/Bad. Open drain logic output that is pulled to ground
if bit B6 is reset. Status register bit C6 indicates if GPIO1
is high or low. High impedance output (high) by default.
GPIO1 may also be configured to indicate power-good
or power-bad as detected by the FB pin in status bit C3.
See applications information. Tie to ground if unused.
Configure according to Table 2 and 3.
GPIO2: General Purpose Input/Output and Fault Alert
Output. Open drain logic output that is pulled to ground
when bit D6 is set. Status register bit C5 indicates if GPIO2
is high or low. GPIO2 may be configured as an output that
is pulled to ground when a fault occurs to alert the host
controller. A fault alert is enabled by the ALERT register.
GPIO2 is configured as a general purpose output (high)
with all alerts disabled by default. See Applications Information. Tie to ground if unused. Configure according
to Tables 3 and 5.
GPIO3: General Purpose Input/Output. Open drain logic
output that is pulled to ground when bit D7 is set. Status
register bit C2 indicates if GPIO3 is high or low. GPIO3
is configured as output low by default. See Applications
Information. Tie to ground if unused. Configure according to Table 5.
INTVCC: Low Voltage Supply Decoupling Output. Connect
a 0.1μF capacitor from this pin to ground.
ON: On Control Input. A rising edge turns on the external
N-channel MOSFET and a falling edge turns it off. This
pin also configures the state of the FET On bit in the control register (and hence the external MOSFET) at power
up. For example, if the ON pin is tied high, then the FET
On bit (A3 in Table 2) goes high 100ms after power-up.
Likewise if the ON pin is tied low then the part remains
off after power-up until the FET On bit is set high using
the I2C bus. A high-to-low transition on this pin clears
the fault register.
42151fa
8
LTC4215-1
PIN FUNCTIONS
OV: Overvoltage Comparator Input. Connect this pin to an
external resistive divider from VDD. If the voltage at this
pin rises above 1.235V, an overvoltage fault is detected
and the GATE turns off. Tie to GND if unused.
SCL: Serial Bus Clock Input. Data at the SDA pin is shifted
in or out on rising edges of SCL. This is a high impedance
pin that is generally driven by an open-collector output
from a master controller. An external pull-up resistor or
current source is required.
SDAO: Serial Bus Data Output. Open-drain output for
sending data back to the master controller or acknowledging a write operation. Normally tied to SDAI to form the
SDA line. An external pull-up resistor or current source
is required.
SDAI: Serial Bus Data Input. A high impedance input for
shifting in address, command or data bits. Normally tied
to SDAO to form the SDA line.
SENSE+: Positive Current Sense Input. Connect this pin to
the input of the current sense resistor. Must be connected
to the same trace as VDD.
SENSE–: Negative Current Sense Input. Connect this
pin to the output of the current sense resistor. This pin
provides sense voltage feedback and monitoring for the
current limit, circuit breaker and ADC.
SOURCE: N-channel MOSFET Source and ADC Input.
Connect this pin to the source of the external N-channel
MOSFET switch for gate drive return. This pin also serves
as the ADC input to monitor output voltage. The pin provides a return for the gate pull-down circuit.
SS: Soft Start Input. Sets the inrush current slew rate at
start-up. Connect a 68nF capacitor to provide 5mV/ms as
the slew rate for the sense voltage in start-up. This corresponds to 1A/ms with a 5mΩ sense resistor. Note that
a large soft-start capacitor and a small TIMER capacitor
may result in a condition where the timer expires before
the inrush current has started. Allow an additional 10nF
of timer capacitance per 1nF of soft-start capacitor to
ensure proper start-up. Use 1nF minimum to ensure an
accurate inrush current.
TIMER: Start-Up Timer Input. Connect a capacitor between this pin and ground to set a 12.3ms/μF duration
for start-up, after which an overcurrent fault is logged if
the inrush is still current limited. The duration of the off
time is 600ms/μF when overcurrent auto retry is enabled,
resulting in a 1:50 duty cycle. An internal timer provides
a 100ms start-up time and 5 seconds auto-retry time if
this pin is tied to INTVCC. Allow an additional 10nF of
timer capacitance per 1nF of soft-start (SS) capacitor to
ensure proper start-up. The minimum value for the TIMER
capacitor is 10nF.
UV: Undervoltage Comparator Input. Connect this pin
to an external resistive divider from VDD. If the voltage
at this pin falls below 1.155V, an undervoltage fault is
detected and the GATE turns off. Pulling this pin below
0.4V resets all faults and allows the GATE to turn back
on. Tie to INTVCC if unused.
VDD: Supply Voltage Input. This pin has an undervoltage
lockout threshold of 2.84V and overvoltage lockout
threshold of 15.6V
42151fa
9
LTC4215-1
FUNCTIONAL DIAGRAM
SENSE–
VCC
10μA
FOLDBACK
AND dI/dt
SS
1.235V
0.6V
FB
1.235V
UV
0.4V
OV
INTVCC
1.235V
10μA
1.235V
EN
ON
1.235V
2.84V
VDD
15.6V
+
–
+
–
OV1
+
–
+
–
FAULT
UV
RST
RESET
+
–
+
– –+
–
+
+–
GATE
CS
CHARGE
PUMP AND
GATE DRIVER
SOURCE
75mV
25mV
FET ON
UV
+
–
+
–
CB
SENSE+
1.235V
PG
+
–
PWRGD
GP
LOGIC
EN
ON
GP
ON
UVLO1
VDD(UVLO)
OV2
GPI03
1.6V
OV
GP
EN
+
–
TM1
OV2
TM2
+
–
+
–
+
–
+
–
GPI02
1.6V
GPI01
1V
0.2V
100μA
TIMER
2μA
3.1V
GEN
1.235V
UVLO2
A/D
CONVERTER
ADIN
+
–
INTVCC
2.64V
8
SDAI
SOURCE
SDAO
VDD – VSENSE
I2C
SCL
I2C ADDR 5
ALERT
ADRO
1 OF 9
ADR1
4215 BD
TIMING DIAGRAM
SDAI/SDAO
tSU, DAT
tHD, DATO,
tHD, DATI
tSU, STA
tSP
tHD, STA
tSP
tBUF
tSU, STO
4215 TD01
SCL
tHD, STA
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
42151fa
10
LTC4215-1
OPERATION
The LTC4215-1 is designed to turn a board’s supply voltage
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. During
normal operation, the charge pump and gate driver turn
on an external N-channel MOSFET’s gate to pass power
to the load. The gate driver uses a charge pump that
derives its power from the VDD pin. Also included in the
gate driver is an internal 6.5V GATE-to-SOURCE clamp.
During start-up the inrush current is tightly controlled by
using current limit foldback, soft start dI/dt limiting and
output dV/dt limiting.
The current sense (CS) amplifier monitors the load current
using the difference between the SENSE+ and SENSE– pin
voltages. The CS amplifier limits the current in the load by
pulling back on the GATE-to-SOURCE voltage in an active
control loop when the sense voltage exceeds the commanded value. The CS amplifier requires 20μA input bias
current from both the SENSE+ and the SENSE– pins.
A short circuit on the output to ground results in excessive
power dissipation during active current limiting. To limit
this power, the CS amplifier regulates the voltage between
the SENSE+ and SENSE– pins at 75mV.
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage exceeds 25mV for more than 20μs. This indicates to the logic
that it is time to turn off the GATE to prevent overheating.
At this point the start-up TIMER capacitor voltage ramps
down using the 2μA current source until the voltage drops
below 0.2V (comparator TM1) which tells the logic that
the pass transistor has cooled and it is safe to turn it on
again if overcurrent auto-retry is enabled. If the TIMER
pin is tied to INTVCC, the cool-down time defaults to 5
seconds on an internal system timer in the logic.
The output voltage is monitored using the FB pin and the
Power Good (PG) comparator to determine if the power
is available for the load. The power good condition can be
signaled by the GPIO1 pin using an open-drain pull-down
transistor. The GPIO1 pin may also be configured to signal
power bad, or as a general purpose input (GP comparator),
or a general purpose open drain output.
GPIO2 and GPIO3 may also be configured as a general
purpose inputs or general purpose open drain outputs.
GPIO2 may also be configured to generate interrupts
when faults occur.
The Functional Diagram shows the monitoring blocks of
the LTC4215-1. The group of comparators on the left side
includes the undervoltage (UV), overvoltage (OV), reset
(RST), enable (EN) and (ON) comparators. These comparators determine if the external conditions are valid prior to
turning on the GATE. But first the two undervoltage lockout
circuits, UVLO1 and UVLO2, validate the input supply and
the internally generated 3.1V supply, INTVCC. UVLO2 also
generates the power-up initialization to the logic circuits as
INTVCC crosses this rising threshold. If the fixed internal
overvoltage comparator, OV2, detects that VDD is greater
than 15.6V, the part immediately generates an overvoltage
fault and turns the GATE off.
Included in the LTC4215-1 is an 8-bit A/D converter. The
converter has a 3-input multiplexer to select between
the ADIN pin, the SOURCE pin and the VDD – SENSE
voltage.
An I2C interface is provided to read the A/D registers. It
also allows the host to poll the device and determine if
faults have occurred. If the GPIO2 line is configured as an
ALERT interrupt, the host is enabled to respond to faults
in real time. The typical SDA line is divided into an SDAI
(input) and SDAO (output). This simplifies applications
using an optoisolator driven directly from the SDAO output. An application which uses optoisolation is shown in
the Typical Applications section. The I2C device address
is decoded using the ADR0 and ADR1 pins. These inputs
have three states each that decode into a total of 9 device
addresses.
42151fa
11
LTC4215-1
APPLICATIONS INFORMATION
A typical LTC4215-1 application is in a high availability
system in which a positive voltage supply is distributed
to power individual cards. The device measures card
voltages and currents and records past and present fault
conditions. The system queries each LTC4215-1 over
the I2C periodically and reads status and measurement
information.
Several conditions must be present before the external
MOSFET turns on. First the external supply, VDD, must
exceed its 2.84V undervoltage lockout levels. Next the
internally generated supply, INTVCC, must cross its 2.64V
undervoltage threshold. This generates a 60μs to 120μs
power-on-reset pulse. During reset the fault registers are
cleared and the control registers are set or cleared as
described in the register section.
A basic LTC4215-1 application circuit is shown in Figure 1.
The following sections cover turn-on, turn-off and various
faults that the LTC4215-1 detects and acts upon. External
component selection is discussed in detail in the Design
Example section.
After a power-on-reset pulse, the LTC4215-1 goes through
the following turn-on sequence. First the UV and OV
comparators indicate that input power is within the acceptable range, which is indicated by bits C0-C1 in Table 4.
Second, the EN pin is externally pulled low. Finally, all
of these conditions must be satisfied for the duration of
100ms to ensure that any contact bounce during insertion has ended.
Turn-On Sequence
The power supply on a board is controlled by using an
external N-channel pass transistor (Q1) placed in the power
path. Note that resistor RS provides current detection. Resistors R1, R2 and R3 define undervoltage and overvoltage
levels. R5 prevents high frequency oscillations in Q1, and
R6 and C1 form an optional network that may be used to
provide an output dV/dt limited start-up.
When these initial conditions are satisfied, the ON pin is
checked and its state written to bit A3 in Table 2. If it is
high, the external MOSFET is turned on. If the ON pin is
low, the external MOSFET is turned on when the ON pin
is brought high or if a serial bus turn-on command is sent
by setting bit A3.
RS
0.005Ω
Q1
FDC653N
12V
CONNECTOR 1
CONNECTOR 2
Z1*
SA14A
SDA
SCL
CF
0.1μF
R1
34.8k
1%
R2
1.18k
1%
R3
3.4K
1%
R5
10Ω
R6
15k
C1
6.8nF
UV VDD SENSE+ SENSE– GATE
OV
ON
SDAI
LTC4215-1
SDA0
SCL
SOURCE
FB
GPIO3
GPIO2
CTIMER
0.68μF
BACKPLANE PLUG-IN
CARD
C3
0.1μF
NC
24k
VOUT
12V
+
CL
330μF
3.3V
24k
24k
RESET
GPIO1
TIMER INTVCC ADR0 ADR1 SS
GND
R7
30.1k
1%
R8
3.57k
1%
GND
ADIN
EN
CSS
7.5nF
4215 F01
Figure 1. Typical Application
42151fa
12
LTC4215-1
APPLICATIONS INFORMATION
The MOSFET is turned on by charging up the GATE with
a 20μA current source. When the GATE voltage reaches
the MOSFET threshold voltage, the MOSFET begins to
turn on and the SOURCE voltage then follows the GATE
voltage as it increases.
When the MOSFET is turning on, it ramps inrush current
up linearly at a dI/dt rate selected by capacitor CSS. Once
the inrush current reaches the limit set by the FB pin, the
dI/dt ramp stops and the inrush current follows the foldback profile as shown in Figure 2. The TIMER capacitor
integrates at 100μA during start-up and once it reaches its
threshold of 1.235V, the part checks to see if it is in current
limit, which indicates that it has started up into a shortcircuit condition. If this is the case, the overcurrent fault
bit, D2 in Table 5, is set and the part turns off. If the part
is not in current limit, the 25mV circuit breaker is armed
and the current limit is switched to 75mV. Alternately an
internal 100ms start-up timer may be selected by tying
the TIMER pin to INTVCC.
As the SOURCE voltage rises, the FB pin follows as set by
R7 and R8. Once FB crosses its 1.235V threshold, and the
start-up timer has expired, the GPIO1 pin, if configured
to indicate power-good, ceases to pull low and indicates
that power is now good. Alternately bit C3 can be read
to check power-good status, where a zero indicates that
power is good.
If R6 and C1 are employed for a constant current during
start-up, which produces a constant dV/dt at the output,
a 20μA pull-up current from the gate pin slews the gate
upwards and the part is not in current limit. The start-up
TIMER may expire in this condition and an overcurrent
(OC) fault is not generated even though start-up has not
completed. Either the sense voltage increases to the
25mV CB threshold and generates an OC fault, or the FB
pin voltage crosses its 1.235V power good threshold and
is indicated in bit C3 as well as the GPIO1 pin if GPIO1 is
configured to do so.
GATE Pin Voltage
A curve of GATE-to-SOURCE drive vs VDD is shown in the
Typical Performance Characteristics. At minimum input
supply voltage of 2.9V, the minimum GATE-to-SOURCE
drive voltage is 4.7V. The GATE-to-SOURCE voltage is
clamped below 6.5V to protect the gates of logic level
N-channel MOSFETs.
Turn-Off Sequence
The GATE is turned off by a variety of conditions. A normal
turn-off is initiated by the ON pin going low or a serial bus
turn-off command. Additionally, several fault conditions
turn off the GATE. These include an input overvoltage
VDD + 6V
VGATE
VDD
VOUT
GPIO1
(POWER GOOD)
tSTARTUP
VSENSE
25mV
10mV
ILOAD • RSENSE
4215 F02
SS
LIMITED
FB
LIMITED
TIMER
EXPIRES
Figure 2. Power-Up Waveforms
42151fa
13
LTC4215-1
APPLICATIONS INFORMATION
(OV pin), input undervoltage (UV pin), overcurrent circuit
breaker (SENSE– pin), or EN transitioning high. Writing
a logic one into the UV, OV or OC fault bits (D0-D2 in
Table 5) also latches off the GATE if their auto-retry bits
are set to false.
Normally the MOSFET is turned off with a 1mA current
pulling down the GATE pin to ground. With the MOSFET
turned off, the SOURCE and FB voltages drop as CL discharges. When the FB voltage crosses below its threshold,
GPIO1 may be configured to pull low to indicate that the
output power is no longer good.
If the VDD pin falls below 2.74V for greater than 2μs or
INTVCC drops below 2.60V for greater than 1μs, a fast shut
down of the MOSFET is initiated. The GATE pin is pulled
down with a 450mA current to the SOURCE pin.
and regulated in order to limit the current sense voltage to
75mV. When the 20μs circuit breaker time out has expired,
the external MOSFET is turned off and the overcurrent fault
bit D2 is set.
After the MOSFET is turned off, the TIMER capacitor
begins discharging with a 2μA pull-down current. When
the TIMER pin reaches its 0.2V threshold the MOSFET is
allowed to turn on again if the overcurrent fault has been
cleared. However, if the overcurrent auto-retry bit, A2 has
been set then the MOSFET turns on again automatically
without resetting the overcurrent fault. Use a minimum
value of 10nF for CT. If the TIMER pin is bypassed by tying
it to INTVCC, the part is allowed to turn on again after an
internal 5 second timer has expired, in the same manner
as the TIMER pin passing its 0.2V threshold.
Overvoltage Fault
Overcurrent Fault
The LTC4215-1 features an adjustable current limit that
protects against short circuits or excessive load current.
An overcurrent fault occurs when the circuit breaker 25mV
threshold has been exceeded for longer than the 20μs
time-out delay. Current limiting begins immediately when
the current sense voltage between the VDD and SENSE
pins reaches 75mV. The GATE pin is then brought down
An overvoltage fault occurs when either the OV pin rises
above its 1.235V threshold, or the VDD pin rises above its
15.6V threshold, for more than 2μs. This shuts off the GATE
with a 1mA current to ground and sets the overvoltage
present bit C0 and the overvoltage fault bit D0. If the pin
subsequently falls back below the threshold for 100ms,
the GATE is allowed to turn on again unless overvoltage
auto-retry has been disabled by clearing bit A0.
Undervoltage Fault
VGATE
10V/DIV
VSOURCE
10V/DIV
VDD
10V/DIV
ILOAD
10A/DIV
RS = 5mΩ
CL = 0
RSHORT = 1Ω
R6 = 30k
C1 = 0.1μF
5μs/DIV
4215 F03
An undervoltage fault occurs when the UV pin falls below
its 1.235V threshold for more than 2μs. This turns off the
GATE with a 1mA current to ground and sets undervoltage
present bit C1 and undervoltage fault bit D1. If the UV pin
subsequently rises above the threshold for 100ms, the
GATE is turned on again unless undervoltage auto-retry
has been disabled by clearing bit A1. When power is applied to the device, if UV is below its 1.235V threshold after
INTVCC crosses its 2.64V undervoltage lockout threshold,
an undervoltage fault is logged in the fault register.
Figure 3. Short-Circuit Waveforms
42151fa
14
LTC4215-1
APPLICATIONS INFORMATION
Board Present Change of State
Whenever the EN pin toggles, bit D4 is set to indicate a
change of state. When the EN pin goes high, indicating
board removal, the GATE turns off immediately (with a 1mA
current to ground) and clears the board present bit, C4. If
the EN pin is pulled low, indicating a board insertion, all
fault bits except D4 are cleared and enable bit, C4, is set.
If the EN pin remains low for 100ms the state of the ON
pin is captured in ‘FET On’ control bit A3. This turns the
switch on if the ON pin is tied high. There is an internal
10μA pull-up current source on the EN pin.
If the system shuts down due to a fault, it may be desirable
to restart the system simply by removing and reinserting
a load card. In cases where the LTC4215-1 and the switch
reside on a backplane or midplane and the load resides on
a plug-in card, the EN pin detects when the plug-in card is
removed. Figure 4 shows an example where the EN pin is
used to detect insertion. Once the plug-in card is reinserted
the fault register is cleared (except for D4). After 100ms
the state of the ON pin is latched into bit A3 of the control
register. At this point the system starts up again.
If a connection sense on the plug-in card is driving the EN
pin, insertion or removal of the card may cause the pin
voltage to bounce. This results in clearing the fault register
OUT
LTC4215-1
SOURCE
10μA
EN
+
LOAD
CEN
–
1.235V
GND
4215 F04
MOTHERBOARD
CONNECTOR
Figure 4. Plug-In Card Insertion/Removal
PLUG-IN
CARD
when the card is removed. The pin may be debounced
using a filter capacitor, C EN, on the EN pin as shown in
Figure 4. The filter time is given by:
tFILTER = C EN • 123 [ms/μF]
FET Short Fault
A FET short fault is reported if the data converter measures a current sense voltage greater than or equal to
1.6mV while the GATE is turned off. This condition sets
FET short fault bit D5.
Power Bad Fault
A power bad fault is reported if the FB pin voltage drops
below its 1.235V threshold for more than 2μs when the
GATE is high. This pulls the GPIO1 pin low immediately
when configured as power-good, and sets power-bad present bit, C3, and power bad fault bit D3. A circuit prevents
power-bad faults if the GATE-to-SOURCE voltage is low,
eliminating false power-bad faults during power-up or
power-down. If the FB pin voltage subsequently rises back
above the threshold, a power-good configured GPIO1 pin
returns to a high impedance state and bit C3 is reset.
Fault Alerts
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in the
ALERT register B has been set. This allows only selected
faults to generate alerts. At power-up the default state is
to not alert on faults and the GPIO2 pin is high. If an alert
is enabled, the corresponding fault causes the GPIO2 pin
to pull low. After the bus master controller broadcasts the
Alert Response Address, the LTC4215-1 responds with its
address on the SDA line and releases GPIO2 as shown in
Table 6. If there is a collision between two LTC4215-1s
responding with their addresses simultaneously, then
the device with the lower address wins arbitration and
responds first. The GPIO2 line is also released if the
device is addressed by the bus master if GPIO2 is pulled
low due to an alert.
42151fa
15
LTC4215-1
APPLICATIONS INFORMATION
Once the GPIO2 signal has been released for one fault, it
is not pulled low again until the FAULT register indicates a
different fault has occurred or the original fault is cleared
and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated
FAULT register bit has been cleared.
The GPIO2 pin may also be used as a general purpose output by setting or resetting bit D6. When D6 is set, GPIO2
will pull low, and when D6 is reset (default) GPIO2 will be
high or pulled low due to an alert. The LTC4215-1 will not
respond to the alert response address if the GPIO2 pin is
being pulled low due to bit D6 being set. See Figure 12 for
a schematic detailing the behavior of the GPIO2 pin.
Resetting Faults
Faults are reset with any of the following conditions. First,
a serial bus command writing zeros to the FAULT register
D bits 0-5 clears the associated faults. Second, FAULT
register bits 0-5 are cleared when the switch is turned
off by the ON pin or bit A3 going from high to low, if the
UV pin is brought below its 0.4V reset threshold for 2μs,
or if INTVCC falls below its 2.64V undervoltage lockout
threshold. Finally, when EN is brought from high to low,
only FAULT bits D0-D3 and D5 are cleared, and bit D4,
which indicates a EN change of state, is set. Note that faults
that are still present, as indicated in STATUS Register C,
cannot be cleared.
The FAULT register is not cleared when auto-retrying.
When auto-retry is disabled the existence of a D0, D1
or D2 fault keeps the switch off. As soon as the fault is
cleared, the switch turns on. If auto-retry is enabled, then
a high value in C0 or C1 holds the switch off and the fault
register is ignored. Subsequently, when bits C0 and C1
are cleared by removal of the fault condition, the switch is
allowed to turn on again. The LTC4215-1 will set bit D2 and
turn off in the event of an overcurrent fault, preventing it
from remaining in an overcurrent condition. If configured
to auto-retry, the LTC4215-1 will continually attempt to
restart after cool-down cycles until it succeeds in starting
up without generating an overcurrent fault.
Data Converter
The LTC4215-1 incorporates an 8-bit A/D converter
that continuously monitors three different voltages. The
SOURCE pin has a 1/12.5 resistive divider to monitor a full
scale voltage of 15.4V with 60mV resolution. The ADIN
pin is monitored with a 1.235V full scale and 4.82mV
resolution, and the voltage between the VDD and SENSE
pins is monitored with a 38.6mV full scale and 151μV
resolution.
Results from each conversion are stored in registers E
(Sense), F (Source) and G (ADIN), as seen in Tables 6-8,
and are updated 10 times per second. Setting CONTROL
register bit A5 invokes a test mode that halts the data
converter so that registers E, F, and G may be written to
and read from for software testing.
Configuring the GPIO Pins
Table 2 describes the possible states of the GPIO1 pin
using the control register bits A6 and A7. At power-up, the
default state is for the GPIO1 pin to be a general purpose
output with output value set by bit B6 (default 1 = GPIO1
Hi-Z). Other applications for the GPIO1 pin are to go high
impedance when power is good (FB pin greater than
1.235V), pull down when power is good, and a general
purpose input. Digital input information can be read from
bit C6 (Table 4).
Table 3 is used to configure the GPIO2 pin as a fault
alert output (See Fault alerts) and also can be used as a
general purpose output and a general purpose input. By
default the GPIO2 pin is a general purpose output in the
high-impedance state as set by bit D6 (default 0 = GPIO2
Hi-Z, Table 5). Digital input information can be read from
bit C5 (Table 4).
The GPIO3 pin is a general purpose output/input that
defaults to output-low as set by bit D7 (default 1 = GPIO3
pulled low, Table 5). Digital input information can be read
from bit C2 (Table 4).
42151fa
16
LTC4215-1
APPLICATIONS INFORMATION
Current Limit Stability
Supply Transients
For many applications the LTC4215-1 current limit will be
stable without additional components. However there are
certain conditions where additional components may be
needed to improve stability. The dominant pole of the current limit circuit is set by the capacitance and resistance at
the gate of the external MOSFET, and larger gate capacitance makes the current limit loop more stable. Usually
a total of 8nF gate to source capacitance is sufficient for
stability and is typically provided by inherent MOSFET CGS,
however the stability of the loop is degraded by increasing
RSENSE or by reducing the size of the resistor on a gate RC
network if one is used, which may require additional gate
to source capacitance. Board level shout-circuit testing
is highly recommended as board layout can also affect
transient performance, for stability testing the worst case
condition for current limit stability occurs when the output
is shorted to ground after a normal startup.
The LTC4215-1 is designed to ride through supply transients caused by load steps. If there is a shorted load and
the parasitic inductance back to the supply is greater than
0.5μH, there is a chance that the supply collapses before
the active current limit circuit brings down the GATE pin.
If this occurs, the undervoltage monitors pull the GATE
pin low. The undervoltage lockout circuit has a 2μs filter
time after VDD drops below 2.74V. The UV pin reacts in
2μs to shut the GATE off, but it is recommended to add a
filter capacitor CF to prevent unwanted shutdown caused
by a transient. Eventually either the UV pin or undervoltage
lockout responds to bring the current under control before
the supply completely collapses.
ILOAD
SENSE RESISTOR RS
R3
SS
SOURCE
OV
GATE
UV
SENSE–
R2
FB
GPIO1
INTVCC
C3
GND
R8
TIMER
LTC4215-1
ON
ADIN
ADR1
ADR0
GPIO3
SDAO
NC
EN
GPIO2
CF
SENSE+
Z1
VDD
R1
SCL
The second type of source follower oscillation occurs
at frequencies between 200kHz and 800kHz due to load
capacitance being between 0.2μF and 9μF, the presence
of R5 resistance, the absence of a drain bypass capacitor,
a combination of bus wiring inductance and bus supply
output impedance. To prevent the second type of oscillation
avoid load capacitance below 10μF, alternately connect an
external capacitor from the MOSFET gate to ground with
a value greater than 1.5nF.
The LTC4215-1 is safe from damage with supply voltages
up to 24V. However, spikes above 24V may damage the
part. During a short-circuit condition, large changes in
SDAI
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping
at power-up or during current limiting. The first type of
oscillation occurs at high frequencies, typically above
1MHz. This high frequency oscillation is easily damped
with R5 as shown in Figure 1. In some applications, one
may find that R5 helps in short-circuit transient recovery
as well. However, too large of an R5 value will slow down
the turn-off time. The recommended R5 range is between
5Ω and 500Ω.
Supply Transient Protection
ILOAD
4215 F05
Figure 5. Recommended Layout
42151fa
17
LTC4215-1
APPLICATIONS INFORMATION
current flowing through power supply traces may cause
inductive voltage spikes which exceed 24V. To minimize
such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Also,
a snubber circuit dampens inductive voltage spikes. Build
a snubber by using a 100Ω resistor in series with a 0.1μF
capacitor between VDD and GND. A surge suppressor, Z1
in Figure 1, at the input can also prevent damage from
voltage surges.
The SOA (safe operating area) curves of candidate MOSFETs
must be evaluated to ensure that the heat capacity of the
package tolerates 6W for 4ms. The SOA curves of the
Fairchild FDC653N provide for 2A at 12V (24W) for 10ms,
satisfying this requirement. Since the FDC653N has less
than 8nF of gate capacitance and we are using a GATE
RC network, the short circuit stability of the current limit
should be checked and improved by adding a capacitor
from GATE to SOURCE if needed.
Design Example
The inrush current is set to 1A using C1:
As a design example, take the following specifications:
VIN = 12V, IMAX = 5A, IINRUSH = 1A, dI/dtINRUSH = 10A/ms,
CL = 330μF, VUV(ON) = 10.75V, VOV(OFF) = 14.0V, VPWRGD(UP)
= 11.6V, and I2C ADDRESS = 1001011. This completed
design is shown in Figure 1.
Selection of the sense resistor, RS, is set by the overcurrent
threshold of 25mV:
25mV
RS =
= 0.005
IMAX
The MOSFET is sized to handle the power dissipation during inrush when output capacitor COUT is being charged.
A method to determine power dissipation during inrush
is based on the principle that:
Energy in CL = Energy in Q1
This uses:
1
1
2
Energy in CL = CV 2 = ( 0.33mF ) (12)
2
2
or 0.024 Joules. Calculate the time it takes to charge up
COUT:
t STARTUP = CL •
VDD
IINRUSH
= 0.33mF •
12V
= 4ms
1A
C1= CL •
IGATE
IINRUSH
C1= 0.33mF •
20µA
or C1= 6.8nF
1A
The inrush dI/dt is set to 10A/ms using CSS:
ISS
1
• 0.0375 •
RSENSE
A
dI / dt s
10µA
1
=
• 0.0375 •
= 7.5nF
10000
5m
CSS =
For a start-up time of 4ms with a 2x safety margin we
choose:
t
CTIMER = 2 • STARTUP + CSS • 10
12.3ms/µF
8ms
+ 7.5nF • 10 0.68µF
CTIMER =
12.3ms/µF
Note the minimum value of CTIMER is 10nF, and each 1nF
of soft-start capacitance needs 10nF of TIMER capacitance/time during start-up.
The UV and OV resistor string values can be solved in the
following method. First pick R3 based on ISTRING being
The power dissipated in the MOSFET:
PDISS =
Energyin CL
= 6W
t STARTUP
42151fa
18
LTC4215-1
APPLICATIONS INFORMATION
1.235V/R3 at the edge of the OV rising threshold, where
ISTRING > 40μA. Then solve the following equations:
R2 =
R1 =
VOV(OFF)
VUV(ON)
• R3 •
UVTH(RISING)
– R3
OVTH(FALLING)
VUV(ON) • (R3+R2)
UVTH(RISING)
– R3 – R2
In our case we choose R3 to be 3.4k to give a resistor
string currrent below 100μA. Then solving the equations
results in R2 = 1.16k and R1 = 34.6k.
The FB divider is solved by picking R8 and solving for R7,
choosing 3.57k for R8 we get:
R7 =
VPWRGD(UP) • R8
FBTH(RISING)
Resulting in R7 = 30k.
A 0.1μF capacitor, CF, is placed on the UV pin to prevent
supply glitches from turning off the GATE via UV or OV.
The address is set with the help of Table 1, which indicates
binary address 1001011 corresponds to address 4. Address
4 is set by setting ADR1 open and ADR0 high.
Next the value of R5 and R6 are chosen to be the default
values 10Ω and 15k as discussed previously.
In addition a 0.1μF ceramic bypass capacitor is placed on
the INTVCC pin.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is required. The minimum trace width for 1oz copper
a6 - a0
SCL
1-7
Digital Interface
The LTC4215-1 communicates with a bus master using a
2-wire interface compatible with I2C Bus and SMBus, an
I2C extension for low power devices.
– R8
SDA
foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530μΩ. Small resistances add up
quickly in high current applications. To improve noise
immunity, put the resistive dividers to the UV, OV and FB
pins close to the device and keep traces to VDD and GND
short. It is also important to put the bypass capacitor for
the INTVCC pin, C3, as close as possible between INTVCC
and GND. A 0.1μF capacitor from the UV pin (and OV pin
through resistor R2) to GND also helps reject supply noise.
Figure 4 shows a layout that addresses these issues. Note
that a surge suppressor, Z1, is placed between supply and
ground using wide traces.
The LTC4215-1 is a read-write slave device and supports
SMBus bus Read Byte, Write Byte, Read Word and Write
Word commands. The second word in a Read Word command is identical to the first word. The second word in a
Write Word command is ignored. Data formats for these
commands are shown in Figures 6 to 11.
START and STOP Conditions
When the bus is idle, both SCL and SDA are high. A bus
master signals the beginning of a transmission with a start
condition by transitioning SDA from high to low while SCL
is high, as shown in Figure 6. When the master has finished
communicating with the slave, it issues a STOP condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for another transmission.
b7 - b0
8
9
1-7
b7 - b0
8
9
1-7
8
9
S
START
CONDITION
P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
CONDITION
4215 F06
Figure 6. Data Transfer Over I2C or SMBus
42151fa
19
LTC4215-1
APPLICATIONS INFORMATION
I2C Device Addressing
that writes to all LTC4215-1s, regardless of their individual
address settings. Mass write can be disabled by setting
register bit A4 to zero. Address (0001 100) is the SMBus
Alert Response Address. If the LTC4215-1 is pulling low
on the GPIO2 pin due to an alert, it acknowledges this
address by broadcasting its address and releasing the
GPIO2 pin.
Nine distinct bus addresses are available using two 3state address pins, ADR0 and ADR1. Table 1 shows the
correspondence between pin states and addresses. Note
that address bits B7 and B6 are internally configured to
“10”. In addition, the LTC4215-1 responds to two special
addresses. Address (1011 111) is a mass write address
S
ADDRESS W A
1 0 a4:a0
0 0
COMMAND
A DATA A P
X X X X X b2:b0
FROM MASTER TO SLAVE
0 b7:b0 0
A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
FROM SLAVE TO MASTER
4215 F07
Figure 7. LTC4215-1 Serial Bus SDA Write Byte Protocol
S
ADDRESS W A
1 0 a4:a0
0 0
COMMAND
A DATA A
DATA
X X X X X b2:b0
0 b7:b0 0
XXXXXXXX
A P
0
4215 F08
Figure 8. LTC4215-1 Serial Bus SDA Write Word Protocol
S
ADDRESS W A
1 0 a4:a0
0 0
COMMAND
X X X X X b2:b0
A S
ADDRESS
R A DATA A P
0
1 0 a4:a0
1 0 b7:b0 1
4215 F10
Figure 9. LTC4215-1 Serial Bus SDA Read Byte Protocol
S
ADDRESS W A
1 0 a4:a0
0 0
COMMAND
X X X X X b2:b0
A S
ADDRESS
R A DATA A DATA A P
0
1 0 a4:a0
1 0 b7:b0 0 b7:b0 1
4215 F11
Figure 10. LTC4215-1 Serial Bus SDA Read Word Protocol
ALERT
S RESPONSE R A
ADDRESS
0001100 1 0
DEVICE
ADDRESS
A P
1 0 a4:a0 0
1
4215 F11
Figure 11. LTC4215-1 Serial Bus SDA Alert Response Protocol
42151fa
20
LTC4215-1
APPLICATIONS INFORMATION
Acknowledge
The acknowledge signal is used in handshaking between
transmitter and receiver to indicate that the last byte of
data was received. The transmitter always releases the
SDA line during the acknowledge clock pulse. When the
slave is the receiver, it pulls down the SDA line so that it
remains LOW during this pulse to acknowledge receipt
of the data. If the slave fails to acknowledge by leaving
SDA high, then the master may abort the transmission by
generating a STOP condition. When the master is receiving data from the slave, the master pulls down the SDA
line during the clock pulse to indicate receipt of the data.
After the last byte has been received the master leaves
the SDA line HIGH (not acknowledge) and issues a stop
condition to terminate the transmission.
Write Protocol
The master begins communication with a START condition
followed by the seven bit slave address and the R/W bit set
to zero, as shown in Figure 7. The addressed LTC4215-1
acknowledges this and then the master sends a command
byte which indicates which internal register the master
wishes to write. The LTC4215-1 acknowledges this and
STATUS BIT C0
ALERT ENABLE BIT B0
RISING
EDGE
DETECT
Q
I
RISING
EDGE
DETECT
Q
Read Protocol
The master begins a read operation with a START condition
followed by the seven bit slave address and the R/W bit set
to zero, as shown in Figure 9. The addressed LTC4215-1
acknowledges this and then the master sends a command
byte which indicates which internal register the master
wishes to read. The LTC4215-1 acknowledges this and
then latches the lower three bits of the command byte
into its internal Register Address pointer. The master then
sends a repeated START condition followed by the same
seven bit address with the R/W bit now set to one. The
LTC4215-1 acknowledges and send the contents of the
requested register. The transmission is ended when the
• • •
I
then latches the lower three bits of the command byte
into its internal Register Address pointer. The master then
delivers the data byte and the LTC4215-1 acknowledges
once more and latches the data into its control register.
The transmission is ended when the master sends a STOP
condition. If the master continues sending a second data
byte, as in a Write Word command, the second data byte
is acknowledged by the LTC4215-1 but ignored, as shown
in Figure 8.
STATUS BIT C5
ALERT ENABLE BIT B5
S
Q
R
GPIO2 PIN
POWER ON RESET
I2C ADDRESS ACK
REGISTER BIT D6
4215 TA02
Figure 12. Control Logic for GPIO2 Pin
42151fa
21
LTC4215-1
APPLICATIONS INFORMATION
the bus master controller broadcasts the Alert Response
Address, the LTC4215-1 responds with its address on the
SDA line and then release GPIO2 as shown in Figure 11.
The GPIO2 line is also released if the device is addressed
by the bus master. The GPIO2 signal is not pulled low
again until the FAULT register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
do not generate alerts until the associated FAULT register
bit has been cleared.
master sends a STOP condition. If the master acknowledges
the transmitted data byte, as in a Read Word command,
Figure 10, the LTC4215-1 repeats the requested register
as the second data byte.
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in
the ALERT register B is also set. If an alert is enabled, the
corresponding fault causes the GPIO2 pin to pull low. After
Table 1. LTC4215-1 Device Addressing
DESCRIPTION*
DEVICE
ADDRESS
Mass Write
Alert Response
8
9
10
11
12
13
14
15
25
h
BE
19
90
92
94
96
98
9A
9C
9E
B2
LTC4215-1
ADDRESS PINS
DEVICE ADDRESS
7
1
0
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
0
0
0
0
5
1
0
0
0
0
0
0
0
0
0
1
4
1
1
1
1
1
1
1
1
1
1
1
3
1
1
0
0
0
0
1
1
1
1
0
2
1
0
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
X
X
X
X
X
X
X
X
X
ADR1
X
X
NC
H
NC
NC
L
H
L
L
H
ADR0
X
X
L
NC
NC
H
L
H
NC
H
L
*Subset of LTC4215 addresses
42151fa
22
LTC4215-1
APPLICATIONS INFORMATION
Table 2. CONTROL Register A (00h)—Read/Write
BIT
NAME
A7:6
GPIO1 Configure
OPERATION
FUNCTION
A6
A7
GPIO PIN
Power Good
0
0
GPIO = C3
Power Good
0
1
GPIO = C3
General Purpose Output (Default)
1
0
GPIO = B6
General Purpose Input
1
1
C6 = GPIO1
A5
Test Mode Enable
A4
Mass Write Enable Allows Mass Write Addressing; 1 = Mass Write Enabled (Default), 0 = Mass Write Disabled
A3
FET On Control
On Control Bit Latches the State of the ON Pin at the End of the Debounce Delay; 1 = FET On, 0 = FET Off
A2
Overcurrent
Auto-Retry
Undervoltage
Auto-Retry
Overvoltage
Auto-Retry
Overcurrent Auto-Retry Bit; 1 = Auto-Retry After Overcurrent, 0 = Latch Off After Overcurrent (Default)
A1
A0
Enables Test Mode to Disable the ADC; 1 = ADC Disable, 0 = ADC Enable (Default)
Undervoltage Auto-Retry; 1 = Auto-Retry After Undervoltage (Default), 0 = Latch Off After Undervoltage
Overvoltage Auto-Retry; 1 = Auto-Retry After Overvoltage (Default), 0 = Latch Off After Overvoltage
Table 3. ALERT Register B (01h)—Read/Write
BIT
NAME
OPERATION
B7
Reserved
Not Used
B6
GPIO1 Output
Output Data Bit to GPIO1 Pin when Configured as Output. Defaults to 1
B5
FET Short Alert
Enables Alert for FET Short Condition; 1 = Enable Alert, 0 = Disable Alert (Default)
B4
EN State
Change Alert
Power Bad
Alert
Overcurrent
Alert
Undervoltage
Alert
Overvoltage
Alert
Enables Alert when EN Changes State; 1 = Enable Alert, 0 Disable Alert (Default)
B3
B2
B1
B0
Enables Alert when Output Power is Bad; 1 = Enable Alert, 0 Disable Alert (Default)
Enables Alert for Overcurrent Condition; 1 = Enable Alert, 0 Disable Alert (Default)
Enables Alert for Undervoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default)
Enables Alert for Overvoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default)
42151fa
23
LTC4215-1
APPLICATIONS INFORMATION
Table 4. STATUS Register C (02h)—Read
BIT
NAME
OPERATION
C7
FET On
1 = FET On, 0 = FET Off
C6
GPIO1 Input
Reports the State of the GPIO1 Pin; 1 = GPIO1 High, 0 = GPIO1 Low
C5
GPIO2 Input
Reports the State of the GPIO2 Pin; 1 = GPIO2 High, 0 = GPIO2 Low
C4
EN
Indicates if the LTC4215 is Enabled when EN is Low; 1 = EN Pin Low, 0 = EN Pin High
C3
Power Bad
Indicates Power is Bad when FB is Low; 1 = FB Low, 0 = FB High
C2
GPIO3 Input
Reports the State of the GPIO3 Pin; 1 = GPIO3 High, 0 = GPIO3 Low
C1
Undervoltage
Indicates Input Undervoltage when UV is Low; 1 = UV Low, 0 = UV High
C0
Overvoltage
Indicates VDD or OV Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low
Table 5. FAULT Register D (03h)—Read/Write
BIT
NAME
OPERATION
D7
GPIO3 Output
Sets the State of the GPIO3 Pin; 1 = GPIO3 Pulled Low (Default), 0 = GPIO3 High Impedance
D6
GPIO2 Output
Sets the State of the GPIO2 Pin; 1 = GPIO2 Pulled Low, 0 = GPIO2 High Impedance (Default)
D5
FET Short Fault
Occurred
EN Changed
State
Power Bad
Fault Occurred
Overcurrent
Fault Occurred
Undervoltage
Fault Occurred
Overvoltage
Fault Occurred
Indicates Potential FET Short was Detected when Measured Current Sense Volage Exceeded 1mV While FET was Off;
1 = FET is Shorted, 0 = FET is Good
Indicates That the LTC4215 was Enabled or Disabled when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged
D4
D3
D2
D1
D0
Indicates Power was Bad when FB when Low; 1 = FB was Low, 0 = FB was High
Indicates Overcurrent Fault Occured; 1 = Overcurrent Fault Occured, 0 = Not Overcurrent Faults
Indicates Input Undervoltage Fault Occured when UV went Low; 1 = UV was Low, 0 = UV was High
Indicates Input Overvoltage Fault Occured when OV went High; 1 = OV was High, 0 = OV was Low
Table 6. SENSE Register E (04h)—Read/Write
BIT
NAME
OPERATION
E7:0
SENSE Voltage Measurement
Sense Voltage Data, 8-Bit Data with 151μV LSB and 38.45mV Full Scale
Table 7. SOURCE Register F (05h)—Read/Write
BIT
NAME
OPERATION
F7:0
SOURCE Voltage
Measurement
SOURCE Voltage Data, 8-Bit Data with 60.5mV LSB and 15.44V Full Scale
Table 8. ADIN Register G (06h)—Read/Write
BIT
NAME
OPERATION
G7:0
ADIN Voltage Measurement
ADIN Voltage Data, 8-Bit Data with 4.82mV LSB and 1.23V Full Scale
42151fa
24
LTC4215-1
TYPICAL APPLICATIONS
5V Card Resident Application with Inverting LED Driver and 16.6A Current Limit
RS
0.0015Ω
VIN
5V
Q1
Si7880DP
+
CF
0.1μF
R1
11.5k
1%
R2
1.74k
1%
R3
2.67k
1%
SDA
SCL
ALERT
R5
10Ω
R6
15k
BACKPLANE PLUG-IN
CARD
R8
2.94k
1%
C1
22nF
UV VDD
OV
SDAI
SDA0
SCL
GPIO2
SENSE GATE
LTC4215-1
ON INTVCC ADR0 ADR1 TIMER
GND
R7
24.3k
1%
C3
0.1μF
NC
R4
24k
R9
24k
CL
1000μF
R10
910Ω
SOURCE
FB
GPIO1
GPIO3
ADIN
SS
EN GND
CTIMER
1μF
CSS
68nF
4215 TA03
42151fa
25
LTC4215-1
TYPICAL APPLICATIONS
12V Application with High Current Non-Inverting LED Drivers and 8.3A Current Limit
0.003Ω
12V
VOUT
12V
+
CL
CONNECTOR 1
CONNECTOR 2
34k
3.57k
0.1ΩF
3.3V
1.74k
2.67k
SMBJ14A
SDA
SCL
30.1k
10Ω
UV VDD SENSE+ SENSE– GATE SOURCE
FB
OV
SDAI
GPIO3
SDAO
LTC4215-1
GPIO2
SCL
GPIO1
ADR0
ADR1 ON INTVCC TIMER SS
0.1μF
24k
24k
24k
220Ω
220Ω
LED
LED
RESET
ADIN
GND EN
68nF
GND
BACKPLANE PLUG-IN
CARD
4215 TA04
42151fa
26
LTC4215-1
PACKAGE DESCRIPTION
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1696 Rev A)
0.70 ±0.05
4.50 ± 0.05
3.10 ± 0.05
2.00 REF
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
3.00 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
R = 0.05 TYP
2.00 REF
R = 0.115
TYP
23
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 OR C = 0.35
24
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
3.00 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD24) QFN 0506 REV A
0.25 ± 0.05
0.200 REF
0.50 BSC
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
42151fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC4215-1
TYPICAL APPLICATION
–12V Card Resident Application with Optically Isolated I2C and 16.6A Current Limit
RS
0.0015Ω
Q1
Si7880DP
OUTPUT
GND
R1
22.1k
1%
R10
3.3k
–7V
5V
2
8
7
6
CF
0.1μF
3 HCPL-0300 5
R2
1k
1%
R3
2.05k
1%
–12V
SDA
R4
3.3k
8
5 HCPL-0300 3
SENSE– GATE
SOURCE
FB
OV
INTVCC
GPIO1
GPIO2
LTC4215-1
GPIO3
R7
24.3k
1%
R8
2.94k
1%
–12V
CL
1000μF
ADIN
ADR0
ADR1
EN GND TIMER
NC
C3
0.1μF
R12
10k
R13
3.3k
SCL
–12V
UV VDD SENSE+
INTVCC
2
C1
22nF
R6
15k
SDAI
SDAO
SCL
ON
–7V
6
R5
10Ω
SS
CTIMER
1μF
CSS
68nF
–7V
2
8
7
6
R9
10k
3 HCPL-0300 5
Q2
–7V
VIN
–12V
D1
5.6V
–12V
4215 TA05
BACKPLANE PLUG-IN
CARD
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Single Channel, Hot Swap Controller
Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10
LTC4212
Single Channel, Hot Swap Controller
Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10
LTC4215
Single Channel, Hot Swap Controller
with I2C, ADC
Operates from 2.9V to 15V, 27 Device Addresses, Fault Alert Output
LTC4216
Single Channel, Hot Swap Controller
Operates from 0V to 6V, MSOP-10 or 12-Lead (4mm × 3mm) DFN
LT4220
Positive and Negative Voltage, Dual
Channel, Hot Swap Controller
Operates from ±2.7V to ±16.5V, SSOP-16
LTC4221
Dual Hot Swap Controller/Sequencer
Operates from 1V to 13.5V, Multifunction Current Control, SSOP-16
LTC4230
Triple Channel, Hot Swap Controller
Operates from 1.7V to 16.5V, Multifunction Current Control, SSOP-20
LTC4260
Single Channel, Hot Swap Controller
with I2C, ADC
ADC for Board Power Monitoring, 8.5V to 80V
LTC4261
Negative Voltage, Hot Swap Controller
with I2C, ADC
Operates from 9.5V to –100V or More (Shunt Regulated), 24-Lead (4mm × 5mm) QFN or
SSOP-28
42151fa
28
Linear Technology Corporation
LT 0808 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008