Renesas ISL6261AIRZ Single-phase core regulator for imvp-6â® mobile cpus Datasheet

DATASHEET
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ISL6261A
EME DESIGN
84C
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NT P
ART
Single-Phase Core Regulator for IMVP-6® Mobile CPUs
FN6354
Rev 3.00
November 5, 2009
The ISL6261A is a single-phase buck regulator
implementing lntel® IMVP-6® protocol, with embedded gate
drivers. lntel® Mobile Voltage Positioning (IMVP) is a smart
voltage regulation technology effectively reducing power
dissipation in lntel® Pentium processors.
Features
The heart of the ISL6261A is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. Compared with
the traditional multi-phase buck regulator, the R3
Technology™ has faster transient response. This is due to
the R3 modulator commanding variable switching frequency
during a load transient.
• Internal gate driver with 2A driving capability
The ISL6261A provides three operation modes: the
Continuous Conduction Mode (CCM), the Diode Emulation
Mode (DEM) and the Enhanced Diode Emulation Mode
(EDEM). To boost battery life, the ISL6261A changes its
operation mode based on CPU mode signals DPRSLRVR
and DPRSTP#, and the FDE pin setting, to maximize the
efficiency. In CPU active mode, the ISL6261A commands
the CCM operation. When the CPU enters deeper sleep
mode, the ISL6261A enables the DEM to maximize the
efficiency at light load. Asserting the FDE pin of the
ISL6261A in CPU deeper sleep mode will enable the EDEM
to further decrease the switching frequency at light load and
increase the regulator efficiency.
A 7-bit Digital-to-Analog Converter (DAC) allows dynamic
adjustment of the core output voltage from 0.300V to 1.500V.
The ISL6261A has 0.5% system voltage accuracy over
temperature.
A unity-gain differential amplifier provides remote voltage
sensing at the CPU die. This allows the voltage on the CPU
die to be accurately measured and regulated per lntel®
IMVP-6 specification. Current sensing can be implemented
through either lossless inductor DCR sensing or precise
resistor sensing. If DCR sensing is used, an NTC thermistor
network will thermally compensates the gain and the time
constant variations caused by the inductor DCR change.
The ISL6261A provides the power monitor function through
the PMON pin. PMON output is a high-bandwidth analog
voltage signal representing the CPU instantaneous power.
The power monitor function can be used by the system to
optimize the overall power consumption, extending battery
run time.
FN6354 Rev 3.00
November 5, 2009
• Precision single-phase CORE voltage regulator
- 0.5% system accuracy over temperature
- Enhanced load line accuracy
• Microprocessor voltage identification input
- 7-Bit VID input
- 0.300V to 1.500V in 12.5mV steps
- Support VID change on-the-fly
• Multiple current sensing schemes supported
- Lossless inductor DCR current sensing
- Precision resistive current sensing
• Thermal monitor
• Power monitor indicating CPU instantaneous power
• User programmable switching frequency
• Differential remote voltage sensing at CPU die
• Overvoltage, undervoltage, and overcurrent protection
• Pb-free (RoHS compliant)
Ordering Information
PART NUMBER
(Notes 2, 3)
ISL6261ACRZ
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
ISL6261ACRZ-T* ISL6261 ACRZ -10 to +100 40 Ld 6x6 QFN L40.6x6
(Note 1)
Tape and Reel
ISL6261AIRZ
6261A IRZ
-40 to +100 40 Ld 6x6 QFN L40.6x6
ISL6261AIRZ-T* 6261A IRZ
(Note 1)
-40 to +100 40 Ld 6x6 QFN L40.6x6
Tape and Reel
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pbfree material sets, molding compounds/die attach materials, and
100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free
soldering operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information
page for ISL6261A. For more information on MSL please see
techbrief TB363.
Page 1 of 34
ISL6261A
Pinout
FN6354 Rev 3.00
November 5, 2009
PGOOD
3V3
CLK_EN
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
ISL6261A
(40 LD QFN)
TOP VIEW
40
39
38
37
36
35
34
33
32
31
FDE
1
30 VID2
PMON
2
29 VID1
RBIAS
3
28 VID0
VR_TT#
4
27 VCCP
NTC
5
SOFT
6
OCSET
7
24 PHASE
VW
8
23 UGATE
COMP
9
22 BOOT
FB
10
21 NC
26 LGATE
GND PAD
(BOTTOM)
11
12
13
14
15
16
17
18
19
20
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
25 VSSP
Page 2 of 34
ISL6261A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE). . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage (LGATE) . . . . . . . . . . . . . . -0.3V (DC) to VDD+0.3V
. . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD+0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)
Open Drain Outputs, PGOOD, VR_TT# . . . . . . . . . . . . -0.3 to +7V
Thermal Resistance (Typical, Notes 4, 5) JA (°C/W)
JC (°C/W)
QFN Package. . . . . . . . . . . . . . . . . . . .
33
6
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V to 21V
Ambient Temperature
ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
ISL6261ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
ISL6261AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. Boldface limits apply over the operating
temperature range, -40°C to +100°C.
SYMBOL
MIN
(Note 7)
TYP
VR_ON = 3.3V
-
3.1
3.6
mA
VR_ON = 0V
-
-
1
µA
TEST CONDITIONS
MAX
(Note 7) UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
+3.3V Supply Current
I3V3
No load on CLK_EN# pin
-
-
1
µA
Battery Supply Current at VIN Pin
IVIN
VR_ON = 0, VIN = 25V
-
-
1
µA
POR (Power-On Reset) Threshold
PORr
VDD rising
-
4.35
4.5
V
PORf
VDD falling
3.85
4.1
-
V
%Error
(Vcc_core)
ISL6261ACRZ
No load, close loop, active mode,
TA =-10°C to +100°C, VID = 0.75V to 1.5V
-0.5
-
0.5
%
-8
-
8
mV
VID = 0.3V to 0.4875V
-15
-
15
mV
%Error
(Vcc_core)
ISL6261AIRZ
No load, close loop, active mode,
VID = 0.75V to 1.5V
-0.8
-
0.8
%
VID = 0.5V to 0.7375V
-10
-
10
mV
VID = 0.3V to 0.4875V
-18
-
18
mV
SYSTEM AND REFERENCES
System Accuracy
RBIAS Voltage
RRBIAS
Boot Voltage
VBOOT
VID = 0.5V to 0.7375V
RRBIAS = 147k
1.45
1.47
1.49
V
1.188
1.2
1.212
V
Maximum Output Voltage
VCC_CORE
(max)
VID = [0000000]
-
1.5
-
V
Minimum Output Voltage
VCC_CORE
(min)
VID = [1100000]
-
0.3
-
V
VID = [1111111]
-
0.0
-
V
318
333
348
kHz
VID Off State
CHANNEL FREQUENCY
Nominal Channel Frequency
FN6354 Rev 3.00
November 5, 2009
fSW
RFSET = 7k, Vcomp = 2V
Page 3 of 34
ISL6261A
Electrical Specifications
VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued) Boldface limits apply over the
operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
Adjustment Range
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
200
-
500
kHz
-0.3
-
0.3
mV
-
90
-
dB
-
MHz
AMPLIFIERS
Droop Amplifier Offset
Error Amp DC Gain (Note 6)
Error Amp Gain-Bandwidth Product
(Note 6)
Error Amp Slew Rate (Note 6)
FB Input Current
AV0
GBW
CL = 20pF
-
18
SR
CL = 20pF
-
5.0
-
V/µs
-
10
150
nA
IIN(FB)
SOFT-START CURRENT
Soft-start Current
ISS
Soft Geyserville Current
IGV
|SOFT - REF|>100mV
Soft Deeper Sleep Entry Current
-47
-42
-37
µA
±180
±205
±230
µA
IC4
DPRSLPVR = 3.3V
-46
-41
-36
µA
Soft Deeper Sleep Exit Current
IC4EA
DPRSLPVR = 3.3V
36
41
46
µA
Soft Deeper Sleep Exit Current
IC4EB
DPRSLPVR = 0V
175
200
225
µA
VSEN = 1.2V, VDROOP - VO = 40mV
1.638
1.680
1.722
V
VSEN = 1V, VDROOP - VO = 10mV
0.308
0.350
0.392
V
2.8
3.0
-
V
2
-
-
mA
2
-
POWER MONITOR
PMON Output Voltage Range
VPMON
PMON Maximum Voltage
VPMONMAX
PMON Sourcing Current
ISC_PMON
VSEN = 1V, VDROOP - VO = 25mV
PMON Sinking Current
ISK_PMON
VSEN = 1V, VDROOP - VO = 25mV
Maximum Current Sinking Capability
PMON Impedance
PMON/250 PMON/180
ZPMON
-
mA
PMON
/130
A
When PMON current is within its
ourcing/sinking current range (Note 6)
-
7
-

GATE DRIVER DRIVING CAPABILITY (Note 6)
UGATE Source Resistance
RSRC(UGATE)
500mA source current
-
1
1.5

UGATE Source Current
ISRC(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
UGATE Sink Resistance
RSNK(UGATE)
500mA sink current
-
1
1.5

UGATE Sink Current
ISNK(UGATE)
VUGATE_PHASE = 2.5V
-
2
-
A
LGATE Source Resistance
RSRC(LGATE)
500mA source current
-
1
1.5

LGATE Source Current
ISRC(LGATE)
VLGATE = 2.5V
-
2
-
A
LGATE Sink Resistance
RSNK(LGATE)
500mA sink current
-
0.5
0.9

LGATE Sink Current
ISNK(LGATE)
VLGATE = 2.5V
-
4
-
A
UGATE to PHASE Resistance
RP(UGATE)
-
1.1
-
k
GATE DRIVER SWITCHING TIMING (Refer to “Gate Driver Timing Diagram” on page 6)
UGATE Turn-on Propagation Delay
LGATE Turn-on Propagation Delay
tPDHU
ISL6261ACRZ
TA = -10°C to +100°C,
PVCC = 5V, output unloaded
20
30
44
ns
tPDHU
ISL6261AIRZ
PVCC = 5V, output unloaded
18
30
44
ns
tPDHL
ISL6261ACRZ
TA = -10°C to +100°C,
PVCC = 5V, output unloaded
7
15
30
ns
tPDHL
ISL6261AIRZ
PVCC = 5V, output unloaded
5
15
30
ns
0.43
0.58
0.72
V
BOOTSTRAP DIODE
Forward Voltage
FN6354 Rev 3.00
November 5, 2009
VDDP = 5V, forward bias current = 2mA
Page 4 of 34
ISL6261A
Electrical Specifications
VDD = 5V, TA = -40°C to +100°C, unless otherwise specified. (Continued) Boldface limits apply over the
operating temperature range, -40°C to +100°C. (Continued)
PARAMETER
MIN
(Note 7)
TYP
VR = 16V
-
-
1
A
SYMBOL
Leakage
TEST CONDITIONS
MAX
(Note 7) UNITS
POWER GOOD and PROTECTION MONITOR
PGOOD Low Voltage
VOL
IPGOOD = 4mA
-
0.11
0.4
V
PGOOD Leakage Current
IOH
PGOOD = 3.3V
-1
-
1
µA
PGOOD Delay
tpgd
CLK_EN# low to PGOOD high
5.5
6.8
8.1
ms
Overvoltage Threshold
OVH
VO rising above setpoint > 1ms
155
195
235
mV
Severe Overvoltage Threshold
OVHS
VO rising above setpoint > 0.5µs
1.675
1.7
1.725
V
OCSET Reference Current
I(RBIAS) = 10µA
9.8
10
10.2
µA
OC Threshold Offset
DROOP rising above OCSET > 120µs
-3.5
-
3.5
mV
VO below set point for > 1ms
-360
-300
-240
mV
Undervoltage Threshold
(VDIFF-SOFT)
UVf
LOGIC THRESHOLDS
VR_ON and DPRSLPVR Input Low
VIL(3.3V)
-
-
1
V
VR_ON and DPRSLPVR Input High
VIH(3.3V)
2.3
-
-
V
Leakage Current on VR_ON
Leakage Current on DPRSLPVR
IIL
Logic input is low
-1
0
-
A
IIH
Logic input is high
-
0
1
A
IIL_DPRSLP
DPRSLPVR logic input is low
-1
0
-
A
IIH_DPRSLP
DPRSLPVR logic input is high
-
0.45
1
A
DAC(VID0-VID6), PSI# and
DPRSTP# Input Low
VIL(1.0V)
-
-
0.3
V
DAC(VID0-VID6), PSI# and
DPRSTP# Input High
VIH(1.0V)
0.7
-
-
V
Leakage Current of DAC(VID0-VID6)
and DPRSTP#
IIL
DPRSLPVR logic input is low
-1
0
-
A
IIH
DPRSLPVR logic input is high
-
0.45
1
A
53
60
67
µA
1.17
1.2
1.25
V
-
5
9

THERMAL MONITOR
NTC Source Current
NTC = 1.3 V
Over-temperature Threshold
V(NTC) falling
RTT
I = 20mA
CLK_EN# High Output Voltage
VOH
3V3 = 3.3V, I = -4mA
CLK_EN# Low Output Voltage
VOL
ICLK_EN# = 4mA
VR_TT# Low Output Resistance
CLK_EN# OUTPUT LEVELS
2.9
3.1
-
V
-
0.18
0.4
V
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6354 Rev 3.00
November 5, 2009
Page 5 of 34
ISL6261A
Gate Driver Timing Diagram
PWM
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tFL
FN6354 Rev 3.00
November 5, 2009
tRL
tPDHL
Page 6 of 34
ISL6261A
PGOOD
3V3
CLK_EN
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
Functional Pin Description
40
39
38
37
36
35
34
33
32
31
FDE
1
30 VID2
PMON
2
29 VID1
RBIAS
3
28 VID0
VR_TT#
4
27 VCCP
NTC
5
SOFT
6
OCSET
7
24 PHASE
VW
8
23 UGATE
COMP
9
22 BOOT
FB
10
21 NC
26 LGATE
GND PAD
(BOTTOM)
11
12
13
14
15
16
17
18
19
20
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
25 VSSP
FDE
VW
Forced diode emulation enable signal. Logic high of FDE with
logic low of DPRSTP# forces the ISL6261A to operate in diode
emulation mode with an increased VW-COMP voltage window.
A resistor from this pin to COMP programs the switching
frequency (eg. 6.81k = 300kHz).
PMON
The output of the error amplifier.
Analog voltage output pin. The voltage potential on this pin
indicates the power delivered to the output.
FB
RBIAS
A 147K resistor to VSS sets internal current reference.
VR_TT#
COMP
The inverting input of the error amplifier.
VDIFF
The output of the differential amplifier.
Thermal overload output indicator with open-drain output.
Over-temperature pull-down resistance is 10.
VSEN
NTC
RTN
Thermistor input to VR_TT# circuit and a 60µA current source
is connected internally to this pin.
Remote core voltage sense return.
SOFT
The output of the droop amplifier. DROOP-VO voltage is the
droop voltage.
A capacitor from this pin to GND pin sets the maximum slew
rate of the output voltage. The SOFT pin is the non-inverting
input of the error amplifier.
OCSET
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10µA current source is
connected internally to this pin.
FN6354 Rev 3.00
November 5, 2009
Remote core voltage sense input.
DROOP
DFB
The inverting input of the droop amplifier.
VO
An input to the IC that reports the local output voltage.
Page 7 of 34
ISL6261A
VSUM
VC24CP
This pin is connected to one terminal of the capacitor in the
current sensing R-C network.
5V power supply for the gate driver.
VIN
VID input with VID0 as the least significant bit (LSB) and VID6
as the most significant bit (MSB).
Power stage input voltage. It is used for input voltage feed
forward to improve the input line transient performance.
VSS
VID0, VID1, VID2, VID3, VID4, VID5, VID6
VR_ON
Signal ground. Connect to controller local ground.
VR enable pin. A logic high signal on this pin enables the
regulator.
VDD
DPRSLPVR
5V control power supply.
Not connected. Ground this pin in the practical layout.
Deeper sleep enable signal. A logic high indicates that the
microprocessor is in Deeper Sleep Mode and also indicates a
slow Vo slew rate with 41A discharging or charging the SOFT
cap.
BOOT
DPRSTP#
Upper gate driver supply voltage. An internal bootstrap diode is
connected to the VCCP pin.
Deeper sleep slow wake up signal. A logic low signal on this
pin indicates that the microprocessor is in Deeper Sleep Mode.
UGATE
CLK_EN#
The upper-side MOSFET gate signal.
Digital output for system PLL clock. Goes active 13 clock
cycles after Vcore is within 20mV of the boot voltage.
NC
PHASE
The phase node. This pin should connect to the source of
upper MOSFET.
3V3
VSSP
PGOOD
The return path of the lower gate driver.
Power good open-drain output. Needs to be pulled up
externally by a 680 resistor to VCCP or 1.9k to 3.3V.
LGATE
3.3V supply voltage for CLK_EN#.
The lower-side MOSFET gate signal.
FN6354 Rev 3.00
November 5, 2009
Page 8 of 34
RBIAS
VR_ON
FDE
DPRSLPVR
DPRSTP#
CLK_EN#
PGOOD
3V3
VIN
VDD
VCCP
VID0
MODE CONTROL
VID1
VIN
PGOOD MONITOR AND LOGIC
VCCP
60µA
VID2
FLT
VID3
DAC
SOFT
PGOOD
FAULT AND PGOOD LOGIC
VID4
VID5
VO
1.22V
VID6
10µA
OCSET
VCCP
OC
VSUM
DROOP
OC
DFB
VIN
VSOFT
FLT
DROOP
1
E/A
DRIVER
LOGIC
MODULATOR
VCCP
VO
1
Mupti-plier
VW
VO
VSEN
RTN
PMON
VDIFF
SOFT
FB
COMP
VW
VSS
FIGURE 1. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL6261A
ISL6261A
FN6354 Rev 3.00
November 5, 2009
Function Block Diagram
Page 9 of 34
ISL6261A
Simplified Application Circuit for DCR Current Sensing
V
+5
V
+3.3
V
in
R4
C4
3V3
R5
VDD
VCCP
VIN
RBIAS
R6
C8
NTC
C5
UGATE
SOFT
VR_TT#
BOOT
L
C6
VR_TT#
o
V
o
PHASE
C
VIDs
VID<0:6>
o
DPRSTP#
DPRSTP#
DPRSLPVR
DPRSLPVR
LGATE
FDE
PMON
VSSP
PMON
CLK_ENABLE#
CLK_EN#
VR_ON
R8
VR_ON
IMVP6_PWRGD
VSUM
PGOOD
VCC-SENSE
C9
VSEN
VSS-SENSE
R7
RTN
R9
NTC
Network
VO
ISL6261A
C7
C3
R10
R11
VW
OCSET
C2
R2
C10
DFB
COMP
R12
FB
C1
R3
DROOP
VDIFF
R1
VSS
FIGURE 2. ISL6261A-BASED IMVP-6® SOLUTION WITH INDUCTOR DCR CURRENT SENSING
FN6354 Rev 3.00
November 5, 2009
Page 10 of 34
ISL6261A
Simplified Application Circuit for Resistive Current Sensing
V
+5
V
+3.3
V
in
R4
C4
3V3
R5
VDD
VCCP
VIN
RBIAS
R6
C8
NTC
C5
UGATE
SOFT
VR_TT#
BOOT
L
C6
VR_TT#
o
R
sen
V
o
PHASE
VID<0:6>
C
VIDs
DPRSTP#
o
DPRSTP#
DPRSLPVR
DPRSLPVR
LGATE
FDE
PMON
VSSP
PMON
CLK_ENABLE#
CLK_EN#
VR_ON
R8
VR_ON
IMVP6_PWRGD
VSUM
PGOOD
VCC-SENSE
C9
VSEN
VSS-SENSE
R7
RTN
VO
ISL6261A
C7
C3
R10
R11
VW
OCSET
C2
R2
C10
DFB
COMP
R12
FB
C1
R3
DROOP
VDIFF
R1
VSS
FIGURE 3. ISL6261A-BASED IMVP-6® SOLUTION WITH RESISTIVE CURRENT SENSING
FN6354 Rev 3.00
November 5, 2009
Page 11 of 34
ISL6261A
Theory of Operation
The ISL6261A is a single-phase regulator implementing Intel®
IMVP-6® protocol and includes an integrated gate driver for
reduced system cost and board area. The ISL6261A IMVP-6®
solution provides optimum steady state and transient
performance for microprocessor core voltage regulation
applications up to 25A. Implementation of Diode Emulation
Mode (DEM) operation further enhances system efficiency.
The heart of the ISL6261A is the patented R3 Technology™,
Intersil’s Robust Ripple Regulator modulator. The R3™
modulator combines the best features of fixed frequency and
hysteretic PWM controllers while eliminating many of their
shortcomings. The ISL6261A modulator internally synthesizes
an analog of the inductor ripple current and uses hysteretic
comparators on those signals to establish PWM pulses.
Operating on the large-amplitude and noise-free synthesized
signals allows the ISL6261A to achieve lower output ripple and
lower phase jitter than either conventional hysteretic or fixed
frequency PWM controllers. Unlike conventional hysteretic
converters, the ISL6261A has an error amplifier that allows the
controller to maintain 0.5% voltage regulation accuracy
throughout the VID range from 0.75V to 1.5V.
The hysteretic window voltage is with respect to the error
amplifier output. Therefore the load current transient results in
increased switching frequency, which gives the R3™ regulator
a faster response than conventional fixed frequency PWM
regulators.
Start-up Timing
With the controller’s VDD pin voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. In approximately
100s, SOFT and VO start ramping to the boot voltage of 1.2V.
At start-up, the regulator always operates in Continuous
Current Mode (CCM), regardless of the control signals. During
this interval, the SOFT cap is charged by a 41A current
source. If the SOFT capacitor is 20nF, the SOFT ramp will be
2mV/µs for a soft-start time of 600µs. Once VO is within 20mV
of the boot voltage the ISL6261A will count 13 clock cycles,
then pull CLK_EN# low, and charge/discharge the SOFT cap
with approximately 200µA, therefore VO slews at 10mV/µs to
the voltage set by the VID pins. In approximately 7ms, PGOOD
is asserted HIGH. Figure 4 shows typical start-up timing.
Static Operation
After the start-up sequence, the output voltage will be
regulated to the value set by the VID inputs per Table 1, which
is presented in the lntel® IMVP-6® specification. The ISL6261A
regulates the output voltage with ±0.5% accuracy over the
range of 0.7V to 1.5V.
FN6354 Rev 3.00
November 5, 2009
VDD
10mV/µs
VR_ON
100µs
20mV
SOFT &VO
Vboot
13xTs
2mV/µs
CLK_EN#
~7ms
IMVP-VI PGOOD
FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
A true differential amplifier remotely senses the core voltage to
precisely control the voltage at the microprocessor die. VSEN
and RTN pins are the inputs to the differential amplifier.
As the load current increases from zero, the output voltage
droops from the VID value proportionally to achieve the IMVP6® load line. The ISL6261A can sense the inductor current
through the intrinsic series resistance of the inductors, as
shown in Figure 2, or through a precise resistor in series with
the inductor, as shown in Figure 3. The inductor current
information is fed to the VSUM pin, which is the non-inverting
input to the droop amplifier. The DROOP pin is the output of
the droop amplifier, and DROOP-VO voltage is a highbandwidth analog representation of the inductor current. This
voltage is used as an input to a differential amplifier to achieve
the IMVP-6® load line, and also as the input to the overcurrent
protection circuit.
The PMON pin is the power monitor output. The voltage
potential on this pin (VPMON) is given by VPMON = 35x(VSENVRTN)x(VDROOP-VO). Since VSEN-VRTN is the CPU voltage and
VDROOP-VO represents the inductor current, VPMON is an
analog voltage indicating the power consumed by the CPU.
VPMON has high bandwidth so it represents the instantaneous
power including the pulsation caused inductor current
switching ripple. The maximum available VPMON is
approximately 3V.
When using inductor DCR current sensing, an NTC thermistor
is used to compensate the positive temperature coefficient of
the copper winding resistance to maintain the load-line
accuracy.
The switching frequency of the ISL6261A controller is set by
the resistor RFSET between pins VW and COMP, as shown in
Figures 2 and 3.
Page 12 of 34
ISL6261A
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO (V)
0
0
0
0
0
0
0
1.5000
0
1
0
1
0
1
0
0.9750
1
0
1
0
1
1
0.9625
0
0
0
0
0
0
1
1.4875
0
0
0
0
0
0
1
0
1.4750
0
1
0
1
1
0
0
0.9500
0
0
0
0
0
1
1
1.4625
0
1
0
1
1
0
1
0.9375
0
0
0
0
1
0
0
1.4500
0
1
0
1
1
1
0
0.9250
1
0
1
1
1
1
0.9125
0
0
0
0
1
0
1
1.4375
0
0
0
0
0
1
1
0
1.4250
0
1
1
0
0
0
0
0.9000
0
0
0
0
1
1
1
1.4125
0
1
1
0
0
0
1
0.8875
0
0
0
1
0
0
0
1.4000
0
1
1
0
0
1
0
0.8750
1
1
0
0
1
1
0.8625
0
0
0
1
0
0
1
1.3875
0
0
0
0
1
0
1
0
1.3750
0
1
1
0
1
0
0
0.8500
0
0
0
1
0
1
1
1.3625
0
1
1
0
1
0
1
0.8375
0
0
0
1
1
0
0
1.3500
0
1
1
0
1
1
0
0.8250
1
1
0
1
1
1
0.8125
0
0
0
1
1
0
1
1.3375
0
0
0
0
1
1
1
0
1.3250
0
1
1
1
0
0
0
0.8000
0
0
0
1
1
1
1
1.3125
0
1
1
1
0
0
1
0.7875
0
0
1
0
0
0
0
1.3000
0
1
1
1
0
1
0
0.7750
1
1
1
0
1
1
0.7625
0
0
1
0
0
0
1
1.2875
0
0
0
1
0
0
1
0
1.2750
0
1
1
1
1
0
0
0.7500
0
0
1
0
0
1
1
1.2625
0
1
1
1
1
0
1
0.7375
0
0
1
0
1
0
0
1.2500
0
1
1
1
1
1
0
0.7250
1
1
1
1
1
1
0.7125
0
0
1
0
1
0
1
1.2375
0
0
0
1
0
1
1
0
1.2250
1
0
0
0
0
0
0
0.7000
0
0
1
0
1
1
1
1.2125
1
0
0
0
0
0
1
0.6875
0
0
1
1
0
0
0
1.2000
1
0
0
0
0
1
0
0.6750
0
0
0
0
1
1
0.6625
0
0
1
1
0
0
1
1.1875
1
0
0
1
1
0
1
0
1.1750
1
0
0
0
1
0
0
0.6500
0
0
1
1
0
1
1
1.1625
1
0
0
0
1
0
1
0.6375
0
0
1
1
1
0
0
1.1500
1
0
0
0
1
1
0
0.6250
0
0
0
1
1
1
0.6125
0
0
1
1
1
0
1
1.1375
1
0
0
1
1
1
1
0
1.1250
1
0
0
1
0
0
0
0.6000
0
0
1
1
1
1
1
1.1125
1
0
0
1
0
0
1
0.5875
0
1
0
0
0
0
0
1.1000
1
0
0
1
0
1
0
0.5750
0
0
1
0
1
1
0.5625
0
1
0
0
0
0
1
1.0875
1
0
1
0
0
0
1
0
1.0750
1
0
0
1
1
0
0
0.5500
0
1
0
0
0
1
1
1.0625
1
0
0
1
1
0
1
0.5375
0
1
0
0
1
0
0
1.0500
1
0
0
1
1
1
0
0.5250
0
0
1
1
1
1
0.5125
0
1
0
0
1
0
1
1.0375
1
0
1
0
0
1
1
0
1.0250
1
0
1
0
0
0
0
0.5000
0
1
0
0
1
1
1
1.0125
1
0
1
0
0
0
1
0.4875
0
1
0
1
0
0
0
1.0000
1
0
1
0
0
1
0
0.4750
0.9875
1
0
1
0
0
1
1
0.4625
0
1
0
FN6354 Rev 3.00
November 5, 2009
1
0
0
1
Page 13 of 34
ISL6261A
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VO (V)
1
0
1
0
1
0
0
0.4500
1
1
0
1
0
1
1
0.1625
1
0
1
0
1
0
1
0.4375
1
1
0
1
1
0
0
0.1500
1
0
1
0
1
1
0
0.4250
1
1
0
1
1
0
1
0.1375
1
0
1
0
1
1
1
0.4125
1
1
0
1
1
1
0
0.1250
1
0
1
1
0
0
0
0.4000
1
1
0
1
1
1
1
0.1125
1
0
1
1
0
0
1
0.3875
1
1
1
0
0
0
0
0.1000
1
0
1
1
0
1
0
0.3750
1
1
1
0
0
0
1
0.0875
1
0
1
1
0
1
1
0.3625
1
1
1
0
0
1
0
0.0750
1
0
1
1
1
0
0
0.3500
1
1
1
0
0
1
1
0.0625
1
0
1
1
1
0
1
0.3375
1
1
1
0
1
0
0
0.0500
1
0
1
1
1
1
0
0.3250
1
1
1
0
1
0
1
0.0375
1
0
1
1
1
1
1
0.3125
1
1
1
0
1
1
0
0.0250
1
1
0
0
0
0
0
0.3000
1
1
1
0
1
1
1
0.0125
1
1
0
0
0
0
1
0.2875
1
1
1
1
0
0
0
0.0000
1
1
0
0
0
1
0
0.2750
1
1
1
1
0
0
1
0.0000
1
1
0
0
0
1
1
0.2625
1
1
1
1
0
1
0
0.0000
1
1
0
0
1
0
0
0.2500
1
1
1
1
0
1
1
0.0000
1
1
0
0
1
0
1
0.2375
1
1
1
1
1
0
0
0.0000
1
1
0
0
1
1
0
0.2250
1
1
1
1
1
0
1
0.0000
1
1
0
0
1
1
1
0.2125
1
1
1
1
1
1
0
0.0000
1
1
0
1
0
0
0
0.2000
1
1
1
1
1
1
1
0.0000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
TABLE 2. ISL6261A OPERATING CONFIGURATIONS
DPRSTP#
0
PHASE DETECTOR HISTORY
x
FDE
DPRSLPVR
OPERATIONAL MODE
VW-COMP VOLTAGE
WINDOW INCREASE
0
0
CCM
0%
1
DEM
<3 consecutive PWM with PHASE>0V
1
0
+20%
1
Three consecutive PWM with PHASE>0V
0
1
1
0
EDEM
+40%
CCM
0%
1
1
x
FN6354 Rev 3.00
November 5, 2009
x
x
Page 14 of 34
ISL6261A
High Efficiency Operation Mode
The operational modes of the ISL6261A depend on the control
signal states of DPRSTP#, FDE, and DPRSLPVR, as shown in
Table 2. These control signals can be tied to lntel® IMVP-6®
control signals to maintain the optimal system configuration for
all IMVP-6® conditions.
DPRSTP# = 0, FDE = 0 and DPRSLPVR = 1 enables the
ISL6261A to operate in Diode Emulation Mode (DEM) by
monitoring the low-side FET current. In diode emulation mode,
when the low-side FET current flows from source to drain, it
turns on as a synchronous FET to reduce the conduction loss.
When the current reverses its direction, trying to flow from drain
to source, the ISL6261A turns off the low-side FET to prevent
the output capacitor from discharging through the inductor,
therefore eliminating the extra conduction loss. When DEM is
enabled, the regulator works in automatic Discontinuous
Conduction Mode (DCM), meaning that the regulator operates in
CCM in heavy load, and operates in DCM in light load. DCM in
light load decreases the switching frequency to increase
efficiency. This mode can be used to support the deeper sleep
mode of the microprocessor.
DPRSTP# = 0 and FDE = 1 enables the Enhanced Diode
Emulation Mode (EDEM), which increases the VW-COMP
window voltage by 33%. This further decreases the switching
frequency at light load to boost efficiency in the deeper sleep
mode.
For other combinations of DPRSTP#, FDE, and DPRSLPVR,
the ISL6261A operates in forced CCM.
The ISL6261A operational modes can be set according to CPU
mode signals to achieve the best performance. There are two
options: (1) Tie FDE to DPRSLPVR, and tie DPRSTP# and
DPRSLPVR to the corresponding CPU mode signals. This
configuration enables EDEM in deeper sleep mode to increase
efficiency. (2) Tie FDE to “1” and DPRSTP# to “0” permanently,
and tie DPRSLPVR to the corresponding CPU mode signal.
This configuration sets the regulator in EDEM all the time. The
regulator will enter DCM based on load current. Light-load
efficiency is increased in both active mode and deeper sleep
mode.
CPU mode-transition sequences often occur in concert with VID
changes. The ISL6261A employs carefully designed modetransition timing to work in concert with the VID changes.
The ISL6261A is equipped with internal counters to prevent
control signal glitches from triggering unintended mode
transitions. For example: Control signals lasting less than
seven switching periods will not enable the diode emulation
mode.
Dynamic Operation
The ISL6261A responds to VID changes by slewing to new
voltages with a dv/dt set by the SOFT capacitor and the logic of
DPRSLPVR. If CSOFT = 20nF and DPRSLPVR = 0, the output
voltage will move at a maximum dv/dt of ±10mV/s for large
changes. The maximum dv/dt can be used to achieve fast
recovery from Deeper Sleep to Active mode. If CSOFT = 20nF and
DPRSLPVR = 1, the output voltage will move at a dv/dt of
±2mV/s for large changes. The slow dv/dt into and out of deeper
sleep mode will minimize the audible noise. As the output voltage
approaches the VID command value, the dv/dt moderates to
prevent overshoot. The ISL6261A is IMVP-6® compliant for
DPRSTP# and DPRSLPVR logic.
Intersil R3™ has an intrinsic voltage feed forward function.
High-speed input voltage transients have little effect on the
output voltage.
Intersil R3™ commands variable switching frequency during
transients to achieve fast response. Upon load application, the
ISL6261A will transiently increase the switching frequency to
deliver energy to the output more quickly. Compared with
steady state operation, the PWM pulses during load
application are generated earlier, which effectively increases
the duty cycle and the response speed of the regulator. Upon
load release, the ISL6261A will transiently decrease the
switching frequency to effectively reduce the duty cycle to
achieve fast response.
TABLE 3. FAULT-PROTECTION SUMMARY OF ISL6261A
FAULT TYPE
FAULT DURATION
PRIOR TO PROTECTION
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120µs
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Way-Overcurrent fault
<2µs
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Overvoltage fault (1.7V)
Immediately
Low-side FET on until Vcore < 0.85V, then
PWM tri-state, PGOOD latched low
(OV-1.7V always)
VDD toggle
Overvoltage fault (+200mV)
1ms
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
Undervoltage fault (-300mV)
1ms
PWM tri-state, PGOOD latched low
VR_ON toggle or VDD toggle
VR_TT# goes high
N/A
Over-temperature fault (NTC<1.18) Immediately
FN6354 Rev 3.00
November 5, 2009
Page 15 of 34
ISL6261A
Protection
The ISL6261A provides overcurrent (OC), overvoltage (OV),
undervoltage (UV) and over-temperature (OT) protections as
shown in Table 3.
Overcurrent is detected through the droop voltage, which is
designed as described in the “Component Selection and
Application” section. The OCSET resistor sets the overcurrent
protection level. An overcurrent fault will be declared when the
droop voltage exceeds the overcurrent set point for more than
120µs. A way-overcurrent fault will be declared in less than
2µs when the droop voltage exceeds twice the overcurrent set
point. In both cases, the UGATE and LGATE outputs will be tristated and PGOOD will go low.
The overcurrent condition is detected through the droop
voltage. The droop voltage is equal to Icore Rdroop, where
Rdroop is the load line slope. A 10A current source flows out of
the OCSET pin and creates a voltage drop across ROCSET
(shown as R10 in Figure 2). Overcurrent is detected when the
droop voltage exceeds the voltage across ROCSET. Equation 1
gives the selection of ROCSET.
ROCSET 
I OC  Rdroop
10 A
(EQ. 1)
For example: The desired overcurrent trip level, Ioc, is 30A,
Rdroop is 2.1m, Equation 1 gives ROCSET = 6.3k.
Undervoltage protection is independent of the overcurrent limit.
A UV fault is declared when the output voltage is lower than
(VID-300mV) for more than 1ms. The gate driver outputs will be
tri-stated and PGOOD will go low. Note that a practical core
regulator design usually trips OC before it trips UV.
There are two levels of overvoltage protection and response.
An OV fault is declared when the output voltage exceeds the
VID by +200mV for more than 1ms. The gate driver outputs will
be tri-stated and PGOOD will go low. The inductor current will
decay through the low-side FET body diode. Toggling of
VR_ON or bringing VDD below 4V will reset the fault latch. A
way-overvoltage (WOV) fault is declared immediately when the
output voltage exceeds 1.7V. The ISL6261A will latch PGOOD
low and turn on the low-side FETs. The low-side FETs will
remain on until the output voltage drops below approximately
0.85V, then all the FETs are turned off. If the output voltage
again rises above 1.7V, the protection process repeats. This
mechanism provides maximum protection against a shorted
high-side FET while preventing the output from ringing below
ground. Toggling VR_ON cannot reset the WOV protection;
recycling VDD will reset it. The WOV detector is active all the
time, even when other faults are declared, so the processor is
still protected against the high-side FET leakage while the
FETs are commanded off.
FN6354 Rev 3.00
November 5, 2009
The ISL6261A has a thermal throttling feature. If the voltage on
the NTC pin goes below the 1.2V over-temperature threshold,
the VR_TT# pin is pulled low indicating the need for thermal
throttling to the system oversight processor. No other action is
taken within the ISL6261A.
Component Selection and Application
Soft-Start and Mode Change Slew Rates
The ISL6261A commands two different output voltage slew rates
for various modes of operation. The slow slew rate reduces the
inrush current during start-up and the audible noise during the
entry and the exit of Deeper Sleep Mode. The fast slew rate
enhances the system performance by achieving active mode
regulation quickly during the exit of Deeper Sleep Mode. The
SOFT current is bidirectional-charging the SOFT capacitor when
the output voltage is commanded to rise, and discharging the
SOFT capacitor when the output voltage is commanded to fall.
Figure 5 shows the circuitry on the SOFT pin. The SOFT pin,
the non-inverting input of the error amplifier, is connected to
ground through capacitor CSOFT. ISS is an internal current
source connected to the SOFT pin to charge or discharge
CSOFT. The ISL6261A controls the output voltage slew rate by
connecting or disconnecting another internal current source IZ
to the SOFT pin, depending on the state of the system, i.e.
Start-up or Active mode, and the logic state on the DPRSLPVR
pin. The SOFT-START CURRENT section of the Electrical
Specification Table shows the specs of these two current
sources.
I
I
SS
Z
INTERNAL TO
ISL6261A
ERROR
AMPLIFLIER
C
V
SOFT
REF
FIGURE 5. SOFT PIN CURRENT SOURCES FOR FAST AND
SLOW SLEW RATES
ISS is 41µA typical and is used during start-up and mode
changes. When connected to the SOFT pin, IZ adds to ISS to
get a larger current, labeled IGV in the “Electrical Specification
Table” starting on page 3, on the SOFT pin. IGV is typically
200µA with a minimum of 175µA.
Page 16 of 34
ISL6261A
10µA
R ocset
OCSET
I phase
OC
L
DCR
Vo
Rs
VSUM
C
o
DROOP
INTERNAL TO ISL6261A
series
DFB
R
ESR
par
R
Cn
0~10
R
1000pF
VSEN
opn1
R drp1
R
ntc
VO
R drp2
DROOP
1
VCC-SENSE
1000pF
1
TO PROCESSOR
SOCKET KELVIN
CONECTIONS
RTN
R
opn2
VSS-SENSE
330pF
VDIFF
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING
The IMVP-6® specification reveals the critical timing
associated with regulating the output voltage. SLEWRATE,
given in the IMVP-6® specification, determines the choice of
the SOFT capacitor, CSOFT, through Equation 2:
CSOFT 
I GV
SLEWRATE
(EQ. 2)
If SLEWRATE is 10mV/s, and IGV is typically 200A, CSOFT is
calculated as:
C SOFT  200 μA 10 mV μs   20 nF
(EQ. 3)
Choosing 0.015F will guarantee 10mV/s SLEWRATE at
minimum IGV value. This choice of CSOFT controls the start-up
slew rate as well. One should expect the output voltage to slew
to the Boot value of 1.2V at a rate given by Equation 4:
dV soft
dt

I ss
41μA

 2.8 mV
μs
C SOFT 0.015 μF
(EQ. 4)
Selecting Rbias
To properly bias the ISL6261A, a reference current needs to be
derived by connecting a 147k, 1% tolerance resistor from the
RBIAS pin to ground. This provides a very accurate 10A current
source from which OCSET reference current is derived.
Caution should be used during layout. This resistor should be
placed in close proximity to the RBIAS pin and be connected to
good quality signal ground. Do not connect any other
components to this pin, as they will negatively impact the
performance. Capacitance on this pin may create instabilities
and should be avoided.
FN6354 Rev 3.00
November 5, 2009
Start-up Operation - CLK_EN# and PGOOD
The ISL6261A provides a 3.3V logic output pin for CLK_EN#.
The system 3.3V voltage source connects to the 3V3 pin,
which powers internal circuitry that is solely devoted to the
CLK_EN# function. The output is a CMOS signal with 4mA
sourcing and sinking capability. CMOS logic eliminates the
need for an external pull-up resistor on this pin, eliminating the
loss on the pull-up resistor caused by CLK_EN# being low in
normal operation. This prolongs battery run time. The 3.3V
supply should be decoupled to digital ground, not to analog
ground, for noise immunity.
At start-up, CLK_EN# remains high until 13 clock cycles after
the core voltage is within 20mV of the boot voltage. The
ISL6261A triggers an internal timer for the IMVP6_PWRGD
signal (PGOOD pin). This timer allows PGOOD to go high
approximately 7ms after CLK_EN# goes low.
Static Mode of Operation - Processor Die Sensing
Remote sensing enables the ISL6261A to regulate the core
voltage at a remote sensing point, which compensates for
various resistive voltage drops in the power delivery path.
The VSEN and RTN pins of the ISL6261A are connected to
Kelvin sense leads at the die of the processor through the
processor socket. (The signal names are Vcc_sense and
Vss_sense respectively). Processor die sensing allows the
voltage regulator to tightly control the processor voltage at the
die, free of the inconsistencies and the voltage drops due to
layouts. The Kelvin sense technique provides for extremely
tight load line regulation at the processor die side.
Page 17 of 34
ISL6261A
These traces should be laid out as noise sensitive traces. For
optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor should be laid out away from rapidly rising voltage
nodes (switching nodes) and other noisy traces. Common
mode and differential mode filters are recommended as shown
in Figure 6. The recommended filter resistance range is 0~10
so it does not interact with the 50k input resistance of the
differential amplifier. The filter resistor may be inserted
between VCC-SENSE and the VSEN pin. Another option is to
place one between VCC-SENSE and the VSEN pin and
another between VSS-SENSE and the RTN pin. The need of
these filters also depends on the actual board layout and the
noise environment.
Since the voltage feedback is sensed at the processor die, if
the CPU is not installed, the regulator will drive the output
voltage all the way up to damage the output capacitors due to
lack of output voltage feedback. Ropn1 and Ropn2 are
recommended, as shown in Figure 6, to prevent this potential
issue. Ropn1 and Ropn2, typically ranging 20~100, provide
voltage feedback from the regulator local output in the absence
of the CPU.
Setting the Switching Frequency - FSET
The R3 modulator scheme is not a fixed frequency PWM
architecture. The switching frequency increases during the
application of a load to improve transient performance.
It also varies slightly depending on the input and output
voltages and output current, but this variation is normally less
than 10% in continuous conduction mode.
Resistor Rfset (R7 in Figure 2), connected between the VW and
COMP pins of the ISL6261A, sets the synthetic ripple window
voltage, and therefore sets the switching frequency. This
relationship between the resistance and the switching frequency
in CCM is approximately given by Equation 5.
R fset kΩ    period(s)  0.29  2.33
(EQ. 5)
In diode emulation mode, the ISL6261A stretches the
switching period. The switching frequency decreases as the
load becomes lighter. Diode emulation mode reduces the
switching loss at light load, which is important in conserving
battery power.
Voltage Regulator Thermal Throttling
lntel® IMVP-6® technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the
voltage regulator. The ISL6261A features a thermal monitor
sensing the voltage across an externally placed negative
temperature coefficient (NTC) thermistor. Proper selection and
placement of the NTC thermistor allows for detection of a
designated temperature rise by the system.
FN6354 Rev 3.00
November 5, 2009
54µA
NTC
V
NTC
R
6µA
Internal to
ISL6261A
VR_TT#
SW1
NTC
SW2
R
S
1.23V
1.20V
FIGURE 7. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE
Figure 7 shows the circuitry associated with the thermal
throttling feature of the ISL6261A. At low temperature, SW1 is
on and SW2 connects to the 1.20V side. The total current
going into the NTC pin is 60µA. The voltage on the NTC pin is
higher than 1.20V threshold voltage and the comparator output
is low. VR_TT# is pulled up high by an external resistor.
Temperature increase will decrease the NTC thermistor
resistance. This decreases the NTC pin voltage. When the
NTC pin voltage drops below 1.2V, the comparator output goes
high to pull VR_TT# low, signaling a thermal throttle. In
addition, SW1 turns off and SW2 connects to 1.23V, which
decreases the NTC pin current by 6uA and increases the
threshold voltage by 30mV. The VR_TT# signal can be used by
the system to change the CPU operation and decrease the
power consumption. As the temperature drops, the NTC pin
voltage goes up. If the NTC pin voltage exceeds 1.23V,
VR_TT# will be pulled high. Figure 8 illustrates the temperature
hysteresis feature of VR_TT#. T1 and T2 (T1>T2) are two
threshold temperatures. VR_TT# goes low when the
temperature is higher than T1 and goes high when the
temperature is lower than T2.
VR_TT#
Logic_1
Logic_0
T2
T1
T (oC)
FIGURE 8. VR_TT# TEMPERATURE HYSTERISIS
Page 18 of 34
ISL6261A
The NTC thermistor’s resistance is approximately given by the
following formula:
R
NTC
(T )  R
NTCTo
1
1
b(

)
 e T  273 To  273
(EQ. 6)
T is the temperature of the NTC thermistor and b is a constant
determined by the thermistor material. To is the reference
temperature at which the approximation is derived. The most
commonly used To is +25C. For most commercial NTC
thermistors, there is b = 2750k, 2600k, 4500k or 4250k.
From the operation principle of VR_TT#, the NTC resistor
satisfies the following equation group:
R NTC (T1 )  Rs 
1.20V
 20kΩ
60 μA
(EQ. 7)
R NTC (T2 )  Rs 
1.23V
 22.78kΩ
54 μA
(EQ. 8)
From Equation 7 and Equation 8, the following can be derived:
RNTC(T2 )  RNTC(T1 )  2.78kΩ
(EQ. 9)
Substitution of Equation 6 into Equation 9 yields the required
nominal NTC resistor value:
2.78kΩ  e
RNTCTo 
e
b(
1
)
T2  273
b(
1
)
To  273
b(
e
(EQ. 10)
1
)
T1  273
One example of using Equations 10, 11 and 12 to design a
thermal throttling circuit with the temperature hysteresis +100C
to +105C is illustrated as follows. Since T1 = +105C and
T2 = +100C, if we use a Panasonic NTC with b = 4700,
Equation 9 gives the required NTC nominal resistance as
R NTC_To  431kΩ
The NTC thermistor datasheet gives the resistance ratio as
0.03956 at +100C and 0.03322 at +105C. The b value of
4700k in Panasonic datasheet only covers up to +85C;
therefore, using Equation 11 is more accurate for +100C
design and the required NTC nominal resistance at +25C is
438k. The closest NTC resistor value from manufacturers is
470k. So Equation 12 gives the series resistance as follows:
Rs  20k  R NTC _ 105C  20k  15.61k  4.39k
The closest standard value is 4.42k. Furthermore, Equation
13 gives the NTC resistance at T2:
RNTC _ T 2  2.78k  RNTC _ T 1  18.39k
The NTC branch is designed to have a 470k NTC and a 4.42k
resistor in series. The part number of the NTC thermistor is
ERTJ0EV474J. It is a 0402 package. The NTC thermistor
should be placed in the spot that gives the best indication of
the temperature of the voltage regulator. The actual
temperature hysteretic window is approximately +105°C to
+100°C.
In some cases, the constant b is not accurate enough to
approximate the resistor value; manufacturers provide the
resistor ratio information at different temperatures. The
nominal NTC resistor value may be expressed in another way
as follows:
RNTCTo 
2.78kΩ
Λ
Λ
(EQ. 11)
R NTC (T2 )  R NTC (T1 )

where R NTC (T ) is the normalized NTC resistance to its
nominal value. The normalized resistor value on most NTC
thermistor datasheets is based on the value at +25°C.
Once the NTC thermistor resistor is determined, the series
resistor can be derived by:
Rs 
1.20V
 R NTC (T1 )  20kΩ  R NTC_T1
60 μA
(EQ. 12)
Once RNTCTo and Rs is designed, the actual NTC resistance at
T2 and the actual T2 temperature can be found in:
RNTC _ T 2  2.78k  RNTC _ T 1
T2 _ actual 
1
R NTC _ T2
1
ln(
)  1 ( 273  To )
b
R NTCTo
FN6354 Rev 3.00
November 5, 2009
(EQ. 13)
 273
(EQ. 14)
Page 19 of 34
ISL6261A
10µA
R ocset
OCSET
VO
OC
Rs
VSUM
Internal to ISL6261A
DROOP
DFB
DROOP
VO
Cn
R drp2
1
Vdcr
R series
I
o
DCR
R par
R ntc
Rn
(Rntc +Rseries )
Rpar
R drp1
Rntc +Rseries +Rpar
FIGURE 9. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DCR SENSING
Static Mode of Operation - Static Droop Using DCR
Sensing

The ISL6261A has an internal differential amplifier to
accurately regulate the voltage at the processor die.
G1 (T ) 
For DCR sensing, the process to compensate the DCR
resistance variation takes several iterative steps. Figure 2
shows the DCR sensing method. Figure 9 shows the simplified
model of the droop circuitry. The inductor DC current generates
a DC voltage drop on the inductor DCR. Equation 15 gives this
relationship.
V DCR  I o  DCR
(EQ. 15)
An R-C network senses the voltage across the inductor to get
the inductor current information. Rn represents the NTC
network consisting of Rntc, Rseries and Rpar. The choice of Rs
will be discussed in the next section.
The first step in droop load line compensation is to choose Rn
and Rs such that the correct droop voltage appears even at
light loads between the VSUM and VO nodes. As a rule of
thumb, the voltage drop across the Rn network, Vn, is set to be
0.5 to 0.8 times VDCR. This gain, defined as G1, provides a
fairly reasonable amount of light load signal from which to
derive the droop voltage.
The NTC network resistor value is dependent on the
temperature and is given by Equation 16:
Rn (T ) 
( Rseries  Rntc )  R par
Rseries  Rntc  R par
G1, the gain of Vn to VDCR, is also dependent on the
temperature of the NTC thermistor:
Rn (T )
Rn (T )  Rs
The inductor DCR is a function of the temperature and is
approximately given by Equation 18:
DCR(T )  DCR25C  (1  0.00393 * (T  25))
(EQ. 18)
in which 0.00393 is the temperature coefficient of the copper.
The droop amplifier output voltage divided by the total load
current is given by Equation 19:
Rdroop  G1(T)  DCR (T )  k droopamp
(EQ. 19)
Rdroop is the actual load line slope. To make Rdroop
independent of the inductor temperature, it is desired to have:
G1 (T )  (1  0.00393 * (T  25))  G1t arg et
(EQ. 20)
where G1target is the desired ratio of Vn/VDCR. Therefore, the
temperature characteristics G1 is described by Equation 21:
G 1 (T ) 
G 1 t arg et
(1  0.00393* (T  25)
(EQ. 21)
For different G1 and NTC thermistor preference, Intersil
provides a design spreadsheet to generate the proper value of
Rntc, Rseries, Rpar.
(EQ. 16)
Rdrp1 (R11 in Fig. 2) and Rdrp2 (R12 in Figure 2) sets the droop
amplifier gain, according to Equation 22:
k droopamp  1 
FN6354 Rev 3.00
November 5, 2009
(EQ. 17)
Rdrp 2
R drp1
(EQ. 22)
Page 20 of 34
ISL6261A
After determining Rs and Rn networks, use Equation 23 to
calculate the droop resistances Rdrp1 and Rdrp2.
Rdrp 2  (
Rdroop
DCR  G1(25 o C )
 1)  Rdrp1
(EQ. 23)
excessively upon load application to create a system failure.
Figure 12 shows the transient response when Cn is too large.
Vcore is sluggish in drooping to its final value. There will be
excessive overshoot if a load occurs during this time, which
may potentially hurt the CPU reliability.
Rdroop is 2.1mV/A per lntel® IMVP-6® specification.
The effectiveness of the Rn network is sensitive to the coupling
coefficient between the NTC thermistor and the inductor. The
NTC thermistor should be placed in close proximity of the
inductor.
To verify whether the NTC network successfully compensates
the DCR change over temperature, one can apply full load
current, wait for the thermal steady state, and see how much the
output voltage deviates from the initial voltage reading. Good
thermal compensation can limit the drift to less than 2mV. If the
output voltage decreases when the temperature increases, that
ratio between the NTC thermistor value and the rest of the
resistor divider network has to be increased. Following the
evaluation board value and layout of NTC placement will
minimize the engineering time.
The current sensing traces should be routed directly to the
inductor pads for accurate DCR voltage drop measurement.
However, due to layout imperfection, the calculated Rdrp2 may
still need slight adjustment to achieve optimum load line slope.
It is recommended to adjust Rdrp2 after the system has
achieved thermal equilibrium at full load. For example, if the
max current is 20A, one should apply 20A load current and
look for 42mV output voltage droop. If the voltage droop is
40mV, the new value of Rdpr2 is calculated by:
R drp 2 _ new
42 mV

( R drp 1  R drp 2 )  R drp 1
40 mV
(EQ. 24)
For the best accuracy, the effective resistance on the DFB and
VSUM pins should be identical so that the bias current of the
droop amplifier does not cause an offset voltage. The effective
resistance on the VSUM pin is the parallel of Rs and Rn, and
the effective resistance on the DFB pin is the parallel of Rdrp1
and Rdrp2.
Dynamic Mode of Operation – Droop Capacitor
Design in DCR Sensing
Figure 10 shows the desired waveforms during load transient
response. Vcore needs to be as square as possible at Icore
change. The Vcore response is determined by several factors,
namely the choice of output inductor and output capacitor, the
compensator design, and the droop capacitor design.
The droop capacitor refers to Cn in Figure 9. If Cn is designed
correctly, its voltage will be a high-bandwidth analog voltage of
the inductor current. If Cn is not designed correctly, its voltage
will be distorted from the actual waveform of the inductor
current and worsen the transient response. Figure 11 shows
the transient response when Cn is too small. Vcore may sag
FN6354 Rev 3.00
November 5, 2009
Vcore
icore
Icore
Vcore
Vcore
Vcore= IcoreRdroop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
icore
Vcore
Vcore
FIGURE 11. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
SMALL
icore
Vcore
Vcore
FIGURE 12. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO
LARGE
The current sensing network consists of Rn, Rs and Cn. The
effective resistance is the parallel of Rn and Rs. The RC time
constant of the current sensing network needs to match the
L/DCR time constant of the inductor to get correct
representation of the inductor current waveform. Equation 25
shows this equation:
 R  Rs 
L
  Cn
  n
DCR  Rn  Rs 
(EQ. 25)
Solving for Cn yields:
L
C n  DCR
Rn  Rs
Rn  Rs
(EQ. 26)
Page 21 of 34
ISL6261A
For example: L = 0.45µH, DCR = 1.1m, Rs = 7.68k, and
Rn = 3.4k
0.45H
0.0011
 174nF
Cn 
parallel(7.68k ,3.4k )
(EQ. 27)
Since the inductance and the DCR typically have 20% and 7%
tolerance respectively, the L/DCR time constant of each
individual inductor may not perfectly match the RC time
constant of the current sensing network. In mass production,
this effect will make the transient response vary a little bit from
board to board. Compared with potential long-term damage on
CPU reliability, an immediate system failure is worse. So it is
desirable to avoid the waveforms shown in Figure 11. It is
recommended to choose the minimum Cn value based on the
maximum inductance so only the scenarios of Figures 10 and
12 may happen. It should be noted that, after calculation, finetuning of Cn value may still be needed to account for board
parasitics. Cn also needs to be a high-grade cap like X7R with
low tolerance. Another good option is the NPO/COG (class-I)
capacitor, featuring only 5% tolerance and very good thermal
characteristics. But the NPO/COG caps are only available in
small capacitance values. In order to use such capacitors, the
resistors and thermistors surrounding the droop voltage
sensing and droop amplifier need to be scaled up 10X to
reduce the capacitance by 10X. Attention needs to be paid in
balancing the impedance of droop amplifier.
Dynamic Mode of Operation - Compensation
Parameters
The voltage regulator is equivalent to a voltage source equal to
VID in series with the output impedance. The output
impedance needs to be 2.1m in order to achieve the 2.1mV/A
load line. It is highly recommended to design the compensation
such that the regulator output impedance is 2.1m. A type-III
compensator is recommended to achieve the best
performance. Intersil provides a spreadsheet to design the
compensator parameters. Figure 13 shows an example of the
spreadsheet. After the user inputs the parameters in the blue
font, the spreadsheet will calculate the recommended
compensator parameters (in the pink font), and show the loop
gain curves and the regulator output impedance curve. The
loop gain curves need to be stable for regulator stability, and
the impedance curve needs to be equal to or smaller than
2.1m in the entire frequency range to achieve good transient
response.
Droop using Discrete Resistor Sensing Static/Dynamic Mode of Operation
Figure 3 shows a detailed schematic using discrete resistor
sensing of the inductor current. Figure 14 shows the equivalent
circuit. Since the current sensing resistor voltage represents
the actual inductor current information, Rs and Cn simply
provide noise filtering. The most significant noise comes from
the ESL of the current sensing resistor. A low low ESL sensing
resistor is strongly recommended. The recommended Rs is
100 and the recommended Cn is 220pF. Since the current
sensing resistance does not appreciably change with
temperature, the NTC network is not needed for thermal
compensation.
Droop is designed the same way as the DCR sensing
approach. The voltage on the current sensing resistor is given
by the following Equation 28:
Vrsen  Rsen  I o
(EQ. 28)
Equation 21 shows the droop amplifier gain. So the actual
droop is given by Equation 29:
 Rdrp 2 

Rdroop  Rsen  1 
 R 
drp
1


(EQ. 29)
Solving for Rdrp2 yields:
 Rdroop 
Rdrp 2  Rdrp1  
 1
R

 sen
(EQ. 30)
For example: Rdroop = 2.1m. If Rsen = 1m and Rdrp1 = 1k,
easy calculation gives that Rdrp2 is 1.1k.
The current sensing traces should be routed directly to the
current sensing resistor pads for accurate measurement.
However, due to layout imperfections, the calculated Rdrp2 may
still need slight adjustment to achieve optimum load line slope.
It is recommended to adjust Rdrp2 after the system has
achieved thermal equilibrium at full load.
The user can choose the actual resistor and capacitor values
based on the recommendation and input them in the
spreadsheet, then see the actual loop gain curves and the
regulator output impedance curve.
Caution needs to be used in choosing the input resistor to the
FB pin. Excessively high resistance will cause an error to the
output voltage regulation due to the bias current flowing in the
FB pin. It is recommended to keep this resistor below 3k.
FN6354 Rev 3.00
November 5, 2009
Page 22 of 34
VSS
ISL6261A
FIGURE 13. AN EXAMPLE OF ISL6261A COMPENSATION SPREADSHEET
FN6354 Rev 3.00
November 5, 2009
Page 23 of 34
ISL6261A
10µA
Rocset
OCSET
VO
OC
Rs
VSUM
Internal to ISL6261A
DROOP
DFB
Vrsen
VO
Rsen
Cn
I
o
R drp1
1
R drp2
DROOP
FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING
Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board)
FIGURE 15. CCM EFFICIENCY, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 16. CCM LOAD LINE AND THE SPEC, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 17. DEM EFFICIENCY, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 18. DEM LOAD LINE AND THE SPEC, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FN6354 Rev 3.00
November 5, 2009
Page 24 of 34
ISL6261A
Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
FIGURE 19. ENHANCED DEM EFFICIENCY, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 20. ENHANCED DEM LOAD LINE, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 21. ENHANCED DEM EFFICIENCY, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 22. ENHANCED DEM LOAD LINE, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
5V/div
5V/div
0.5V/div
0.5V/div
1V/div
1V/div
10V/div
10V/div
FIGURE 23. SOFT-START, VIN = 19V, Io = 0A, VID = 1.5V,
Ch1: VR_ON, Ch2: VO, Ch3: PMON, Ch4: PHASE
FN6354 Rev 3.00
November 5, 2009
FIGURE 24. SOFT-START, VIN = 19V, Io = 0A, VID = 1.1V,
Ch1: VR_ON, Ch2: VO, Ch3: PMON, Ch4: PHASE
Page 25 of 34
ISL6261A
Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
5V/div
5V/div
0.1V/div
0.1V/div
1V/div
1V/div
10V/div
10V/div
FIGURE 25. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 1.5V,
Ch1: CLK_EN#, Ch2: VO, Ch3: PMON,
Ch4: PHASE
FIGURE 26. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 0.7625V,
Ch1: CLK_EN#, Ch2: VO, Ch3: PMON,
Ch4: PHASE
5V/div
0.5V/div
7.68ms
5V/div
10V/div
FIGURE 27. CLK_EN AND PGOOD ASSERTION DELAY,
VIN = 19V, Io = 2A, VID = 1.1V, Ch1: CLK_EN#,
Ch2: VO, Ch3: PGOOD, Ch4: PHASE
FIGURE 28. SHUT DOWN, VIN = 12.6V, Io = 2A, VID = 1.1V,
Ch1: VR_ON, Ch2: VO, Ch3: PGOOD,
Ch4: PHASE
FIGURE 29. SOFT START INRUSH CURRENT, VIN = 19V,
Io = 2A, VID = 1.1V, Ch1: DROOP-VO
(2.1mV = 1A), Ch2: VO, Ch3: Vcomp, Ch4: PHASE
FIGURE 30. VIN TRANSIENT TEST, VIN = 819V, Io = 2A,
VID = 1.1V, Ch2: VO, Ch3: VIN, Ch4: PHASE
FN6354 Rev 3.00
November 5, 2009
Page 26 of 34
ISL6261A
Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
FIGURE 31. C4 ENTRY/EXIT, VIN = 12.6V, Io = 0.7A,
HFM/LFM/C4 VID = 1.05V/0.8375V/0.7625V,
FDE = DPRSLPVR, Ch1: PMON, Ch2: VO,
Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE
FIGURE 32. VID TOGGLING, VIN = 12.6V, Io= 16.5A,
HFM/LFM VID = 1.05V/0.8375V,
FDE = DPRSLPVR, Ch1: PMON, Ch2: VO,
Ch3: 40k/100pF FILTERED PMON, Ch4: PHASE
FIGURE 33. LOAD TRANSIENT RESPONSE IN CCM
VIN = 12.6V, Io = 2A20A (100A/µs), VID = 1.1V,
Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED
PMON, Ch4: PHASE
FIGURE 34. LOAD TRANSIENT RESPONSE IN CCM
VIN = 12.6V, Io = 20A2A (50A/µs), VID = 1.1V,
Ch1: PMON, Ch2: VO, Ch3: 40k/100pF FILTERED
PMON, Ch4: PHASE
100A/us
FIGURE 35. LOAD TRANSIENT RESPONSE IN CCM
VIN = 12.6V, Io = 2A20A (100A/µs)2A (50A/µs),
VID = 1.1V, Ch1: PMON, Ch2: VO, Ch3: 40k/100pF
FILTERED PMON, Ch4: PHASE
FN6354 Rev 3.00
November 5, 2009
50A/us
FIGURE 36. LOAD TRANSIENT RESPONSE IN EDEM
VIN = 8V, Io = 2A20A, VID = 1.1V,
Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE
Page 27 of 34
ISL6261A
Typical Performance (ISL6261 Data, Taken on ISL6261A Eval1 Rev.A Evaluation Board) (Continued)
100A/us
50A/us
FIGURE 37. LOAD TRANSIENT RESPONSE IN EDEM
VIN = 8V, Io = 2A20A, VID = 1.1V,
Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE
FIGURE 38. LOAD TRANSIENT RESPONSE IN EDEM
VIN = 8V, Io = 2A20A, VID = 1.1V,
Ch1: Io, Ch2: VO, Ch3: PMON, Ch4: PHASE
120us
FIGURE 39. OVERCURRENT PROTECTION, VIN = 12.6V,
Io = 0A28A, VID = 1.1V, Ch1: DROOP-VO
(2.1mV = 1A), Ch2: VO, Ch3: PGOOD,
Ch4: PHASE
FIGURE 40. OVERVOLTAGE (>1.7V) PROTECTION,
VIN = 12.6V, Io = 2A, VID = 1.1V,
Ch2: VO, Ch3: PGOOD, Ch4: PHASE
© Copyright Intersil Americas LLC 2006-2009. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6354 Rev 3.00
November 5, 2009
Page 28 of 34
ISL6261A
0
1000PF
C18
C6
IN
J1
P30 DNP
100
10
9
8
J3
10
R46
10UF
C30
2
R39
P34
C31
10UF
1UF
J4
C29
C28
0.01UF
J2
OUT
OUT
P32
2
R47
10K
10K
R42
10K
R41
10K
R40
10K
R38
10K
R37
10K
R36
P33
P31
P28
P27
P25
P24
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
DNP
C25
3.57K 10K NTC
R31
4.53K
R29
R28
8200PF
R27
Page 29 of 34
VSUM
0.068UF
C21
IN
P22
VCC_PRM
0.12UF
C19
1K
C7
330PF
R33
11
+3.3V
+3.3V
1
1 2 2 5V
IN
VR_ON1
J16
R44
10K
R45
10K
3
1 S4
J19
OFF
2
VR_ON
ON
1
2 21
3 3
1X3
R34
0
R35
0
R15
0.1UF
C16
5.23K
RTN
DFB
DNP R8 DNP
C15
P3
R7
0
C26
0
OUT
12
3.3V
10K
VSEN
P15
330PF
OUT
13
5V
1
R43
R30
VDIFF1
OUT
14
MST7_SPST
DNP
1UF
C14
P11
1000PF
R12
C11
P9
R6
R24
2.21K
R25
J17
2 2 1
14
13
12
11
10
9
8
C23
C27
390PF
LGATE
GND_POWER
PHASE
UGATE
BOOT
P29
5.49K
ISL6261A
IN
IN
IN
IN
IN
IN
IN
+5V
P26
464K
0
0
DROOP
P23
R32
P14
150PF
U6
VID2
VID1
VID0
VCCP
LGATE
VSSP
PHASE
UGATE
BOOT
NC
0.22UF
P4
P5
10UF
C2
VSSSENSE
C20
R11
0
FDE
PMON
RBIAS
VR_TT
NTC
SOFT
OCSET
VW
COMP
FB
P21
IN
R23
C12
3V3
P17
IN
R19
VID6
VID5
VID4
VID3
VID2
VID1
VID0
1UF
EP
47PF
7
PGOOD
3V3
CLK_EN
DPRSTP
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
OUT
147K
FB
C9
COMP
R5
GND_POWER
4
6
C17
PMON/PGD_IN
RBIAS
VR_TT
1000PF
6.81K
C13
R9
P8
VCORE
3
C24
J10
1X3
DNP
P1
R22
499
R20
0
DNP
R17 DNP R16
C8
VW
1
2
3
4
5
6
7
2
J15
1 1 2 2
1
2 21
3 3
PSI#
U1
1
5
P12
IN
P20
VR_ON
DPRSLPVR
DPRSTP#
CLK_EN#
SOFT
OCSET
DNP
IN
P19
P18
P16
P2
DNP
10K
10K
R21
10K
R14
10K
R10
R103
P7
2
6.34K
C3
VCCSENSE
+3.3V
P6
R3
10K
OUT
FDE
R4
VCC_PRM
0
+3.3V
1
Q5
R107
IN
0.015UF
C10
2N7002
IN
+3.3V
PGOOD
DPRSLPVR
SSL_LXA3025IGC
R1 510
3 R2 510 J9
1 12 2
1
RED
GRN
D3
34
2
PGOOD
IN
C92
DNP
DPRSTP#
FDE
SD05H0SK
+3.3V
DPRSLPVR
PSI#
PMON/PGD_IN
R108
10K
R18
10
9
8
7
6
ON
ON
ON
ON
ON
1
2
3
4
5
3
4
5
DNP
R13
+3.3V1
S1
J8
1 2 2 21
P13
Controller
P10
FN6354 Rev 3.00
November 5, 2009
ISL6261A Eval1 Evaluation Board Schematics
VIN
IN
NOTE:
RUN LGATE1 TRACE PARALLEL TO TRACE CONNECTING
PGND1 AND SOURCE OF Q3 AND Q4.
TITLE:
ISL6261 EVAL1
CONTROLLER
ENGINEER:
JIA WEI
DRAWN BY:
REV:
?
DATE:
MAR-14
SHEET:
1 OF
C34
J21 4
1
2
VCCSENSE
IN
VSSSENSE
IN
J22 4
1
2
1
C55
22UF
C61
22UF
C67
C56
22UF
C62
22UF
C68
22UF
C57
22UF
C63
22UF
C69
22UF
C43
C47
C59
C66
C70
22UF
22UF
22UF
C65
22UF
C60
22UF
22UF
C53
22UF
22UF
C54
22UF
C48
C37
22UF
C38
DNP
22UF
C71
330UF
C90
330UF
C44
330UF
22UF
22UF
C49
22UF
C50
22UF
C51
22UF
C39
22UF
C42
J13
22UF
R54
C45
DNP
22UF
0
R60
BUS WIRE
0.1UF
R52
R53
0
R50
1
2
L1
0.45UH
0.1UF
C91
3
DNP
1
DNP
J20 4
3
Q4
D2
IRF7832
Q2
R49
IRF7832
C35
R51
LGATE
0.22UF
C4
P35
22UF
C64
22UF
C58
22UF
C52
22UF
C46
22UF
C36
P41
P40
P39
P38
56UF
56UF
R83
R82
10UF C5
10UF C5B
10UF
1UF
C32
1
7.68K
IN
0
Q3
VCC_PRM
VSUM
PHASE
C1
0.1UF
IN
R48
1
OUT
OUT
3
BOOT
IRF7821
Q1
2
IN
IRF7821
DNP
C33
UGATE
OUT
C40
330UF
C89
330UF
C41
330UF
P37
J6
IN
P36
Power Stage
VCORE
1
OUT
GND_POWER
J14
OUT
ISL6261A
VIN
J5
FN6354 Rev 3.00
November 5, 2009
ISL6261A Eval1 Evaluation Board Schematics (Continued)
Page 30 of 34
ISL6261A
F26
G2
G3
G5
G6
G22
G24
G25
H1
H2
H4
H5
H22
H23
H25
H26
J1
J3
J4
J23
J24
J26
K2
K3
K5
K22
K24
K25
L1
L2
L4
L5
L22
L23
L25
L26
M1
M3
M4
M23
M24
M26
N2
N3
N5
N22
N24
N25
P1
P2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSSENSE
OUT
W6
W5
W3
W2
V26
V24
V23
V4
V3
U25
U23
U22
U5
U4
U2
T25
T24
T22
T5
T3
T2
R24
R23
R4
R3
R1
P26
P25
P23
P22
P5
P4
IN
SOCKET1
V1
U26
U1
R26
AA4
AA3
AA1
Y26
Y25
Y23
Y22
Y5
Y4
Y2
Y1
W25
W24
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
AE7
INTEL_IMPV6
COMP3
COMP1
COMP2
COMP0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
GND_POWER
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
INTEL_IMPV6
A3
A5
A6
A21
A22
A24
A25
B1
B2
B3
B4
B5
B22
B23
B25
C1
C3
C4
C6
C7
C20
C21
C23
C24
C26
D2
D3
D5
D6
D7
D20
D21
D22
D24
D25
E1
E2
E4
E5
E22
E23
E25
E26
F1
F3
F4
F6
F21
F23
F24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SOCKET1
AF20
AF18
AF17
AF15
AF14
AF12
AF10
AF9
AE20
AE18
AE17
AE15
AE13
AE12
AE10
AE9
AD18
AD17
AD15
AD14
AD12
AD10
AD9
AD7
AC18
AC17
AC15
AC13
AC12
AC10
AC9
AC7
AB20
AB18
AB17
AB15
AB14
AB12
AB10
AB9
AB7
AA20
AA18
W22
G21
J6
J21
K6
K21
M6
M21
N6
N21
R6
R21
T6
T21
V6
V21
W21
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C2
C5
C8
C11
C14
C16
C19
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F2
F5
F8
F11
F13
F16
F19
F22
F25
G1
G4
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
VSSSENSE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
INTEL_IMPV6
SOCKET1
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
VCCA
VCCSENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PSI
GTLREF
VID6
VID5
VID4
VID3
VID2
VID1
VID0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
IN
VCORE
AF7
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
B26
VCCSENSE
OUT
PSI#
AE6
OUT
AD26
AE2 VID6 OUT
AF2 VID5 OUT
AE3 VID4 OUT
AF4 VID3 OUT
AE5 VID2 OUT
AF5 VID1 OUT
AD6 VID0 OUT
AF26
AF25
AF23
AF22
AF1
AE25
AE24
AE22
AE21
AD24
AD23
AD21
AD20
AD4
AD3
AD1
AC26
AC25
AC23
AC22
AC20
AC5
AC4
AC2
AC1
AB25
AB24
AB22
AB21
AB6
AB5
AB3
AB2
AA26
AA24
AA23
AA21
AA6
AF24
AF21
AF19
AF16
AF13
AF11
AF8
AF6
AF3
AE26
AE23
AE19
AE16
AE14
AE11
AE8
AE4
Socket
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FN6354 Rev 3.00
November 5, 2009
ISL6261A Eval1 Evaluation Board Schematics (Continued)
AE1
AD25
AD22
AD19
AD16
AD13
AD11
AD8
AD5
AD2
AC24
AC21
AC19
AC16
AC14
AC11
AC8
AC6
AC3
AB26
AB23
AB19
AB16
AB13
AB11
AB8
AB4
AB1
AA25
AA22
AA19
AA16
AA14
AA11
AA8
AA5
AA2
Y24
Y21
Y6
Y3
W26
W23
W4
W1
V25
V22
V5
V2
U24
U21
U6
U3
T26
T23
T4
T1
R25
R22
R5
R2
P24
P21
P6
P3
Page 31 of 34
ISL6261A
Dynamic Load
J11
J12
+12V
2
3
4
LO
VSS
LI
HI
8
7
6
R74
5
249
HIP2100
R73
+12V
49.9K
2
ON
R72
2
10UF
499
C81
Q14
D1
3
1
1
BAV99
HUF76129D3S
Q15
1
2
GND_POWER
3
R71
+12V
1
2
R75
249
2N7002
VCORE
IN
3
S5 1
OFF
4 J23
3
1UF
VDD
HB
HO
HS
0.12
1
U5
2
C80
3
GND_POWER
0.1
R76
FN6354 Rev 3.00
November 5, 2009
ISL6261A Eval1 Evaluation Board Schematics (Continued)
Page 32 of 34
ISL6261A
8
8
9
MST7_SPST
10
Y7
GND
Y8
U4
G1
VCC
G2
A2
Y1
A3
Y2
A4
Y3
A5
Y4
A6
Y5
A7
Y6
A8
Y7
HC540
11
Y8
20
19
18
+3.3V_GEY
C74
0.1UF
+3.3V_GEY
17
16
15
12
2
2
+3.3V_GEY
R59
10K
R61
10K
R62
10K
10K
J25
1 2 2
1
2
+3.3V_GEY
10K
10K
3
EVQPA
PSI# S7
R102
Page 33 of 34
R58
R64
10K
C76
10K
R57
4
LOOP
+3.3V_GEY
0.1UF
+3.3V
J24
1 1 2 2 +3.3V_GEY
10K
R56
C87
1X3
15PF
15PF
1
2
3
4
5
6
7
Vcc
1A
1Y
2A
2Y
3A
3Y
GND
AC04
6A
6Y
5A
5Y
4A
4Y
14
13
12
11
10
9
8
4
3
EVQPA
PSI#
1
1
2 21
3 3
J7
EVQPA
1
11
4
1UF
10K
3
DPRSLP
S6
14
13
S2
1
C86
U12
R77
MODE TRANS
1
R55
C85
+3.3V_GEY
A1
GND
12
+3.3V
3
A8
DNP
3
EVQPA
J28
1 1 2 2
P45
Y6
CLK_EN#
13
4
2
P43
A7
IN
14
0
R67
C79
Y5
15
1
0.01UF
A6
16
RESETS8
P42
Y4
17
BAV99
7
A5
1UF
PIC16F874 +3.3V_GEYR69
R104
10K
2
HCM49
R80 0
9
Y3
7
28
1
S9
6
A4
C73
0.1UF
C78
2
1
5
10
Y2
18
U11
18
3
10K
10K
R101
10K
R98
10K
R95
10K
R92
10K
R89
11
A3
19
VDD
VDD
OUT
OUT
OUT
R79 0
7
4
Y1
6
29
OUT
DELAY
DPRSLPVR
C88
6
12
G2
A2
+3.3V_GEY
31
DIRECT
OUT
DNP
5
3
A1
20
DNP
30
P44
4
12
11
10
9
8
2
25
26
27
VCC
HC540
11
BAV99
3
1
2
3
4
5
6
7
14 14
13 13
1
U3
G1
Y8
R78 0
2
10K
R86
R83
U9
1
10
HC540
R106
DNP
9
MST7_SPST
GND
12
PSI#
DPRSTP#
PGD_IN
VR_ON1
2
1
7
8
Y7
13
OUT
OUT
OUT
OUT
OUT
OUT
OUT
33
34
19
20
21
22
23
24
0
10K
10K
R100
10K
R97
10K
R94
10K
R91
10K
R88
6
Y6
A8
38
39
40
41
2
3
4
5
C84
7
5
A7
14
S3
6
4
Y5
12
13
15
R70 0
5
3
A6
16
R105
4
2
Y4
VID0
VID1
VID2
VID3
VID4
VID5
VID6
8
9
10
11
14
15
16
17
DNP
3
14 14
13 13
12 12
11 11
10 10
9 9
8 8
1
2
3
4
5
6
7
1
A5
17
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
NC
NC
RA0
RA1
RA2
RA3
RA4
RA5
OSC1
OSC2
MCLR
R68
1
10K
R85
R82
U8
2
10
Y3
10K
MST7_SPST
A4
18
R65
9
Y2
0.1UF
C77
10K
10K
R99
10K
R96
10K
R93
10K
R90
8
Y1
A3
C72
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
NC
NC
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
VSS
VSS
0.1UF
7
7
A2
19
32
35
36
37
42
43
44
1
10K
6
6
G2
+3.3V_GEY
R66
5
5
A1
20
10K
4
3
4
VCC
R63
3
2
U2
G1
C75
2
14 14
13 13
12 12
11 11
10 10
9 9
8 8
1
2
3
4
5
6
7
U10
1
0.1UF
1
10K
R87
U7
10K
R84
Geyserville Transition Gen.
R81
FN6354 Rev 3.00
November 5, 2009
ISL6261A Eval1 Evaluation Board Schematics (Continued)
J29
1 2 2
REV:
TITLE:
ISL6261 EVAL1
GEYSERVILLE TRANSITION GEN.
ENGINEER:
DATE:
MARJIA WEI
DRAWN BY:
SHEET:
5
ISL6261A
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X 4.5
6.00
36X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
31
30
1
6.00
4 . 10 ± 0 . 15
21
10
0.15
(4X)
11
20
TOP VIEW
0.10 M C A B
40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
(
C
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
C
0 . 2 REF
5
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6354 Rev 3.00
November 5, 2009
Page 34 of 34