MC9S12XEP100
Reference Manual
Covers MC9S12XE Family
HCS12
Microcontrollers
MC9S12XEP100
Rev. 1.07
05/2007
freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to: http://freescale.com/
A full list of family members and options is included in the appendices.
The following revision history table summarizes changes contained in this document.
This document contains information for all constituent modules, with the exception of the S12X CPU. For
S12X CPU information please refer to the CPU S12 Reference Manual Version 2 .
Revision History
Date
Revision
Level
Oct, 2006
1.01
VREG, NVM electrical parameter updates
Use of external regulator now prohibited
Nov, 2006
1.02
Corrected package option code. Added dataflash to derivative table.
Included revision history in module sections
Removed internal text
Dec, 2006
1.03
NVM timing parameters, PLL parameters. Minor typo corrections.
Jan, 2007
1.04
NVM timing parameters and EEE description updated.
Feb, 2007
1.05
EBI/NVM/IDD parameter updates
Partnumber coding explanation updated in Appendix F
Ex256 memory map correction
Mar, 2007
1.06
ATD/PLL electricals updated
Revised FTM section
Version ID added to Part ID section
1.07
EPROT/FPROT configuration field locations changed !!
Various electricals updated following characterization
Revised PIM section : corrected ATD pin mapping
Revised INT section : software interrupt priorities changed
Revised DBG section: NDB functionality, simultaneous arm and disarm
Revised SEC section : added disclaimer, corrected backdoor key text
Revised SPI section: typo fixes only
Revised TIM section : removed redundant table, corrected bit name
Revised FTM section: Updated security description.
May, 2007
Description
Chapter 1
Device Overview MC9S12XE-Family. . . . . . . . . . . . . . . . . . . . . 21
Chapter 2
Port Integration Module (S12XEPIMV1) . . . . . . . . . . . . . . . . . . 77
Chapter 3
Memory Mapping Control (S12XMMCV4) . . . . . . . . . . . . . . . 177
Chapter 4
Memory Protection Unit (S12XMPUV1) . . . . . . . . . . . . . . . . . 219
Chapter 5
External Bus Interface (S12XEBIV4) . . . . . . . . . . . . . . . . . . . . 233
Chapter 6
Interrupt (S12XINTV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Chapter 7
Background Debug Module (S12XBDMV2) . . . . . . . . . . . . . . 271
Chapter 8
S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . 297
Chapter 9
Security (S12XE9SECV2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
Chapter 10
XGATE (S12XGATEV3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Chapter 11
S12XE Clocks and Reset Generator (S12XECRGV1) . . . . . . 469
Chapter 12
Pierce Oscillator (S12XOSCLCPV2) . . . . . . . . . . . . . . . . . . . . 503
Chapter 13
Analog-to-Digital Converter (ADC12B16CV1) . . . . . . . . . . . 507
Chapter 14
Enhanced Capture Timer (ECT16B8CV3). . . . . . . . . . . . . . . . 533
Chapter 15
Inter-Integrated Circuit (IICV3) . . . . . . . . . . . . . . . . . . . . . . . . 587
Chapter 16
Scalable Controller Area Network (S12MSCANV3) . . . . . . . . 615
Chapter 17
Periodic Interrupt Timer (S12PIT24B8CV1) . . . . . . . . . . . . . . 673
Chapter 18
Pulse-Width Modulator (S12PWM8B8CV1) . . . . . . . . . . . . . . 693
Chapter 19
Serial Communication Interface (S12SCIV5) . . . . . . . . . . . . . 725
Chapter 20
Serial Peripheral Interface (S12SPIV5) . . . . . . . . . . . . . . . . . . 763
Chapter 21
Timer Module (TIM16B8CV2) . . . . . . . . . . . . . . . . . . . . . . . . . 793
Chapter 22
Voltage Regulator (S12VREGL3V3V1) . . . . . . . . . . . . . . . . . . 821
Chapter 23
1024 KByte Flash Module (S12XFTM1024K5V2) . . . . . . . . . . 837
Appendix A Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
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Appendix C PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Appendix D Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Appendix E Detailed Register Address Map. . . . . . . . . . . . . . . . . . . . . . . . 978
Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
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Chapter 1Device Overview MC9S12XE-Family
1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.1.4 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.1.5 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.1.6 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1.7 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2.2 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.2.3 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
1.2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
1.3 System Clock Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.4.1 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.4.2 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
1.4.3 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.4.4 System States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
1.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
1.6 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
1.6.1 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
1.6.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
1.6.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
1.7 ATD0 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
1.8 ATD1 External Trigger Input Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.9 MPU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.10 VREG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.11 S12XEPIM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
1.12 Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 2
Port Integration Module (S12XEPIMV1)
2.1
2.2
2.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
2.3.10
2.3.11
2.3.12
2.3.13
2.3.14
2.3.15
2.3.16
2.3.17
2.3.18
2.3.19
2.3.20
2.3.21
2.3.22
2.3.23
2.3.24
2.3.25
2.3.26
2.3.27
2.3.28
2.3.29
2.3.30
2.3.31
2.3.32
2.3.33
2.3.34
2.3.35
2.3.36
2.3.37
2.3.38
2.3.39
2.3.40
2.3.41
2.3.42
2.3.43
2.3.44
2.3.45
2.3.46
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Port A Data Register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Port B Data Register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Port B Data Direction Register (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Port C Data Register (PORTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Port D Data Register (PORTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Port C Data Direction Register (DDRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Port E Data Register (PORTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Port E Data Direction Register (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR) . . . . . . . . . . . . . . . . . . 102
S12X_EBI ports Reduced Drive Register (RDRIV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ECLK Control Register (ECLKCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
IRQ Control Register (IRQCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Port K Data Register (PORTK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Port K Data Direction Register (DDRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Port T Data Register (PTT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Port T Input Register (PTIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Port T Data Direction Register (DDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Port T Reduced Drive Register (RDRT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Port T Pull Device Enable Register (PERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Port T Polarity Select Register (PPST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Port S Data Register (PTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Port S Input Register (PTIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Port S Data Direction Register (DDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Port S Reduced Drive Register (RDRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Port S Pull Device Enable Register (PERS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Port S Polarity Select Register (PPSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Port S Wired-Or Mode Register (WOMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Port M Data Register (PTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Port M Input Register (PTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Port M Data Direction Register (DDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Port M Reduced Drive Register (RDRM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Port M Pull Device Enable Register (PERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Port M Polarity Select Register (PPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Port M Wired-Or Mode Register (WOMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Module Routing Register (MODRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Port P Data Register (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Port P Input Register (PTIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
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2.3.48
2.3.49
2.3.50
2.3.51
2.3.52
2.3.53
2.3.54
2.3.55
2.3.56
2.3.57
2.3.58
2.3.59
2.3.60
2.3.61
2.3.62
2.3.63
2.3.64
2.3.65
2.3.66
2.3.67
2.3.68
2.3.69
2.3.70
2.3.71
2.3.72
2.3.73
2.3.74
2.3.75
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2.3.77
2.3.78
2.3.79
2.3.80
2.3.81
2.3.82
2.3.83
2.3.84
2.3.85
2.3.86
2.3.87
2.3.88
2.3.89
2.3.90
2.3.91
Port P Data Direction Register (DDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Port P Reduced Drive Register (RDRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Port P Pull Device Enable Register (PERP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Port P Polarity Select Register (PPSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Port P Interrupt Enable Register (PIEP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Port P Interrupt Flag Register (PIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Port H Data Register (PTH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Port H Input Register (PTIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Port H Data Direction Register (DDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Port H Reduced Drive Register (RDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Port H Pull Device Enable Register (PERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Port H Polarity Select Register (PPSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Port H Interrupt Enable Register (PIEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Port H Interrupt Flag Register (PIFH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Port J Data Register (PTJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Port J Input Register (PTIJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Port J Data Direction Register (DDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Port J Reduced Drive Register (RDRJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Port J Pull Device Enable Register (PERJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Port J Polarity Select Register (PPSJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Port J Interrupt Enable Register (PIEJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Port J Interrupt Flag Register (PIFJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Port AD0 Data Register 0 (PT0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Port AD0 Data Register 1 (PT1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Port AD0 Data Direction Register 0 (DDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Port AD0 Data Direction Register 1 (DDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Port AD0 Reduced Drive Register 0 (RDR0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Port AD0 Reduced Drive Register 1 (RDR1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Port AD0 Pull Up Enable Register 0 (PER0AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Port AD0 Pull Up Enable Register 1 (PER1AD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Port AD1 Data Register 0 (PT0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Port AD1 Data Register 1 (PT1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Port AD1 Data Direction Register 0 (DDR0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Port AD1 Data Direction Register 1 (DDR1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Port AD1 Reduced Drive Register 0 (RDR0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Port AD1 Reduced Drive Register 1 (RDR1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Port AD1 Pull Up Enable Register 0 (PER0AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Port AD1 Pull Up Enable Register 1 (PER1AD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Port R Data Register (PTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Port R Input Register (PTIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Port R Data Direction Register (DDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Port R Reduced Drive Register (RDRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Port R Pull Device Enable Register (PERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Port R Polarity Select Register (PPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
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2.5
2.3.92 Port R Routing Register (PTRRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
2.3.93 Port L Data Register (PTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
2.3.94 Port L Input Register (PTIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.3.95 Port L Data Direction Register (DDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
2.3.96 Port L Reduced Drive Register (RDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2.3.97 Port L Pull Device Enable Register (PERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
2.3.98 Port L Polarity Select Register (PPSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
2.3.99 Port L Wired-Or Mode Register (WOML) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
2.3.100Port L Routing Register (PTLRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
2.3.101Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
2.3.102Port F Input Register (PTIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
2.3.103Port F Data Direction Register (DDRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
2.3.104Port F Reduced Drive Register (RDRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
2.3.105Port F Pull Device Enable Register (PERF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
2.3.106Port F Polarity Select Register (PPSF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
2.3.107PIM Reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
2.3.108Port F Routing Register (PTFRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
2.4.3 Pins and Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
2.4.4 Pin interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Chapter 3
Memory Mapping Control (S12XMMCV4)
3.1
3.2
3.3
3.4
3.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
3.1.1 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
3.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
3.1.3 S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
3.4.1 MCU Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
3.4.2 Memory Map Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
3.4.3 Chip Access Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
3.4.4 Chip Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
3.5.1 CALL and RTC Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
3.5.2 Port Replacement Registers (PRRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
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3.5.3 On-Chip ROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Chapter 4
Memory Protection Unit (S12XMPUV1)
4.1
4.2
4.3
4.4
4.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
4.1.1 Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
4.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
4.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
4.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
4.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
4.4.1 Protection Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
4.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Chapter 5
External Bus Interface (S12XEBIV4)
5.1
5.2
5.3
5.4
5.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.1.1 Glossary or Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
5.4.1 Operating Modes and External Bus Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
5.4.2 Internal Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
5.4.3 Accesses to Port Replacement Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
5.4.4 Stretched External Bus Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
5.4.5 Data Select and Data Direction Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
5.4.6 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.5.1 Normal Expanded Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.5.2 Emulation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Chapter 6
Interrupt (S12XINTV2)
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
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6.2
6.3
6.4
6.5
6.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
6.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
6.4.3 XGATE Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.4.4 Priority Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.4.5 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.4.6 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Chapter 7
Background Debug Module (S12XBDMV2)
7.1
7.2
7.3
7.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
7.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
7.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
7.3.3 Family ID Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.4.2 Enabling and Activating BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
7.4.3 BDM Hardware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
7.4.4 Standard BDM Firmware Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.4.5 BDM Command Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
7.4.6 BDM Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
7.4.7 Serial Interface Hardware Handshake Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
7.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
7.4.9 SYNC — Request Timed Reference Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
7.4.10 Instruction Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
7.4.11 Serial Communication Time Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
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Chapter 8
S12X Debug (S12XDBGV3) Module
8.1
8.2
8.3
8.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
8.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
8.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
8.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
8.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
8.4.1 S12XDBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
8.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
8.4.3 Trigger Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
8.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
8.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
8.4.6 Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
8.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Chapter 9
Security (S12XE9SECV2)
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
9.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
9.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
9.1.3 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
9.1.4 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
9.1.5 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
9.1.6 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
9.1.7 Complete Memory Erase (Special Modes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Chapter 10
XGATE (S12XGATEV3)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
10.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
10.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
10.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
10.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
10.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
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10.5
10.6
10.7
10.8
10.9
10.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
10.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
10.4.4 Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
10.4.5 Software Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
10.5.1 Incoming Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
10.5.2 Outgoing Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
10.6.1 Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
10.6.2 Leaving Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
10.8.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
10.8.2 Instruction Summary and Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
10.8.3 Cycle Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
10.8.4 Thread Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
10.8.5 Instruction Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
10.8.6 Instruction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
10.9.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
10.9.2 Code Example (Transmit "Hello World!" on SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
10.9.3 Stack Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Chapter 11
S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
11.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
11.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
11.2.1 VDDPLL, VSSPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
11.2.2 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
11.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
11.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
11.4.2 Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
11.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
11.5.1 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
11.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
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Chapter 12
Pierce Oscillator (S12XOSCLCPV2)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
12.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
12.2.1 VDDPLL and VSSPLL — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 504
12.2.2 EXTAL and XTAL — Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
12.4.1 Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
12.4.2 Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
12.4.3 Wait Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
12.4.4 Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
Chapter 13
Analog-to-Digital Converter (ADC12B16CV1)
Block Description
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
13.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
13.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
13.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
13.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
13.2.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
13.4.1 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
13.4.2 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
13.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
13.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Chapter 14
Enhanced Capture Timer (ECT16B8CV3)
14.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
14.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
14.2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
14.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
14.3.1 IOC7 — Input Capture and Output Compare Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . 535
14.3.2 IOC6 — Input Capture and Output Compare Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . 535
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14.3.3 IOC5 — Input Capture and Output Compare Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . 535
14.3.4 IOC4 — Input Capture and Output Compare Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . 535
14.3.5 IOC3 — Input Capture and Output Compare Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . 535
14.3.6 IOC2 — Input Capture and Output Compare Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . 535
14.3.7 IOC1 — Input Capture and Output Compare Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . 535
14.3.8 IOC0 — Input Capture and Output Compare Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . 535
14.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
14.4.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
14.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
14.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
14.5.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
14.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
14.5.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Chapter 15
Inter-Integrated Circuit (IICV3) Block Description
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
15.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
15.2.1 IIC_SCL — Serial Clock Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
15.2.2 IIC_SDA — Serial Data Line Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
15.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
15.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
15.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
15.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
15.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
15.4.4 Operation in Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
15.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
15.7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
15.7.1 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Chapter 16
Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
16.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
16.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
16.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
16.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
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16.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
16.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
16.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
16.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
16.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
16.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
16.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
16.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
16.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
16.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
16.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
16.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
16.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
16.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
Chapter 17
Periodic Interrupt Timer (S12PIT24B8CV1)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
17.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
17.3 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
17.4.1 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
17.4.2 Interrupt Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
17.4.3 Hardware Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
17.5 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
17.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
17.5.2 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
17.5.3 Flag Clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
17.6 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Chapter 18
Pulse-Width Modulator (S12PWM8B8CV1)
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
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18.4
18.5
18.6
18.2.1 PWM7 — PWM Channel 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
18.2.2 PWM6 — PWM Channel 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
18.2.3 PWM5 — PWM Channel 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
18.2.4 PWM4 — PWM Channel 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
18.2.5 PWM3 — PWM Channel 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
18.2.6 PWM3 — PWM Channel 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
18.2.7 PWM3 — PWM Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
18.2.8 PWM3 — PWM Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
18.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
18.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Chapter 19
Serial Communication Interface (S12SCIV5)
19.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
19.2.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
19.2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
19.2.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
19.2.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
19.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
19.3.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
19.3.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
19.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
19.4.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
19.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
19.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
19.5.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
19.5.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
19.5.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
19.5.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
19.5.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
19.5.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
19.5.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
19.5.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.6.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.6.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
19.6.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
19.6.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
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19.6.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
Chapter 20
Serial Peripheral Interface (S12SPIV5)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
20.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
20.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
20.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
20.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
20.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
20.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
20.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
20.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
20.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
20.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
20.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
20.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
20.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787
20.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
20.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Chapter 21
Timer Module (TIM16B8CV2) Block Description
21.1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
21.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
21.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
21.2.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
21.2.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
21.3 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
21.3.1 IOC7 — Input Capture and Output Compare Channel 7 Pin . . . . . . . . . . . . . . . . . . . . 796
21.3.2 IOC6 — Input Capture and Output Compare Channel 6 Pin . . . . . . . . . . . . . . . . . . . . 796
21.3.3 IOC5 — Input Capture and Output Compare Channel 5 Pin . . . . . . . . . . . . . . . . . . . . 796
21.3.4 IOC4 — Input Capture and Output Compare Channel 4 Pin . . . . . . . . . . . . . . . . . . . . 796
21.3.5 IOC3 — Input Capture and Output Compare Channel 3 Pin . . . . . . . . . . . . . . . . . . . . 796
21.3.6 IOC2 — Input Capture and Output Compare Channel 2 Pin . . . . . . . . . . . . . . . . . . . . 796
21.3.7 IOC1 — Input Capture and Output Compare Channel 1 Pin . . . . . . . . . . . . . . . . . . . . 797
21.3.8 IOC0 — Input Capture and Output Compare Channel 0 Pin . . . . . . . . . . . . . . . . . . . . 797
21.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
21.4.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
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21.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
21.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
21.5.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
21.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
21.5.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
21.5.4 Pulse Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
21.5.5 Event Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
21.5.6 Gated Time Accumulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
21.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
21.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
21.7.1 Channel [7:0] Interrupt (C[7:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
21.7.2 Pulse Accumulator Input Interrupt (PAOVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
21.7.3 Pulse Accumulator Overflow Interrupt (PAOVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
21.7.4 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
Chapter 22
Voltage Regulator (S12VREGL3V3V1)
22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.2.1 VDDR — Regulator Power Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.2.2 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.2.3 VDD, VSS — Regulator Output1 (Core Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.2.4 VDDF — Regulator Output2 (NVM Logic) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
22.2.5 VDDPLL, VSSPLL — Regulator Output3 (PLL) Pins . . . . . . . . . . . . . . . . . . . . . . . . . 825
22.2.6 VDDX — Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
22.2.7 VREGEN — Optional Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
22.2.8 VREG_API — Optional Autonomous Periodical Interrupt Output Pin . . . . . . . . . . . . . . 825
22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
22.4.2 Regulator Core (REG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
22.4.3 Low-Voltage Detect (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
22.4.4 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
22.4.5 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
22.4.6 Regulator Control (CTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
22.4.7 Autonomous Periodical Interrupt (API) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
22.4.8 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
22.4.9 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
22.4.10Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
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1024 KByte Flash Module (S12XFTM1024K5V2)
23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
23.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
23.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
23.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
23.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
23.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
23.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
23.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
23.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
23.4.2 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
23.4.3 .....Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 903
23.4.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
23.4.5 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
23.4.6 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
23.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
23.5.1 Flash Module Operation while Unsecure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 905
23.5.2 Flash Module Operation while Secure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
23.5.3 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
23.5.4 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 908
23.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
23.6.1 Flash Reset Sequence - Core Hold Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
23.6.2 Flash Reset Sequence - Core Active Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
23.6.3 Error Handling during Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
23.6.4 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
Appendix A
Electrical Characteristics
A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
A.1.4 Current Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
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A.4
A.5
A.6
A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
NVM, Flash and Emulated EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
A.3.1 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 934
A.3.2 NVM Reliability Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Output Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
A.5.1 Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
A.5.2 Capacitive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
A.5.3 Chip Power-up and Voltage Drops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Reset, Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
A.6.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
A.6.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 944
A.6.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
A.6.4 MSCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
A.6.5 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
A.6.6 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
Appendix B
Package Information
B.1
B.2
B.3
B.4
208 MAPBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
144-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
112-Pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
80-Pin QFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Appendix C
PCB Layout Guidelines
Appendix D Derivative Differences
D.1 Memory Sizes and Package Options S12XE - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
D.2 Pinout explanations: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Appendix E
Detailed Register Address Map
23.6.5 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
Appendix F
Ordering Information
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Chapter 1 Device Overview MC9S12XE-Family
1.1
Introduction
The MC9S12XE-Family of micro controllers is a further development of the S12XD-Family including
new features for enhanced system integrity and greater functionality. These new features include a
Memory Protection Unit (MPU) and Error Correction Code (ECC) on the Flash memory together with
enhanced EEPROM functionality (EEE), an enhanced XGATE, an Internally filtered, frequency
modulated Phase Locked Loop (IPLL) and an enhanced ATD. The E-Family extends the S12X product
range up to 1MB of Flash memory with increased I/O capability in the 208-pin version of the flagship
MC9S12XE100.
The MC9S12XE-Family delivers 32-bit performance with all the advantages and efficiencies of a 16 bit
MCU. It retains the low cost, power consumption, EMC and code-size efficiency advantages currently
enjoyed by users of Freescale’s existing 16-Bit MC9S12 and S12X MCU families. There is a high level of
compatibility between the S12XE and S12XD families.
The MC9S12XE-Family features an enhanced version of the performance-boosting XGATE co-processor
which is programmable in “C” language and runs at twice the bus frequency of the S12X with an
instruction set optimized for data movement, logic and bit manipulation instructions and which can service
any peripheral module on the device. The new enhanced version has improved interrupt handling
capability and is fully compatible with the existing XGATE module.
The MC9S12XE-Family is composed of standard on-chip peripherals including up to 64Kbytes of RAM,
eight asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an
8-channel IC/OC enhanced capture timer (ECT), two 16-channel, 12-bit analog-to-digital converters, an
8-channel pulse-width modulator (PWM), five CAN 2.0 A, B software compatible modules (MSCAN12),
two inter-IC bus blocks (IIC), an 8-channel 24-bit periodic interrupt timer (PIT) and an 8-channel 16-bit
standard timer module (TIM).
The MC9S12XE-Family uses 16-bit wide accesses without wait states for all peripherals and memories.
The non-multiplexed expanded bus interface available on the 144/208-Pin versions allows an easy
interface to external memories.
In addition to the I/O ports available in each module, up to 26 further I/O ports are available with interrupt
capability allowing Wake-Up from STOP or WAIT modes. The MC9S12XE-Family is available in
208-Pin MAPBGA, 144-Pin LQFP, 112-Pin LQFP or 80-Pin QFP options.
1.1.1
Features
Features of the MC9S12XE-Family are listed here. Please see Table D-1.for memory options and
Table D-2. for the peripheral features that are available on the different family members.
• 16-Bit CPU12X
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Chapter 1 Device Overview MC9S12XE-Family
•
•
•
•
•
•
•
•
•
— Upward compatible with MC9S12 instruction set with the exception of five Fuzzy instructions
(MEM, WAV, WAVR, REV, REVW) which have been removed
— Enhanced indexed addressing
— Access to large data segments independent of PPAGE
INT (interrupt module)
— Eight levels of nested interrupts
— Flexible assignment of interrupt sources to each interrupt level.
— External non-maskable high priority interrupt (XIRQ)
— Internal non-maskable high priority Memory Protection Unit interrupt
— Up to 24 pins on ports J, H and P configurable as rising or falling edge sensitive interrupts
EBI (external bus interface)(available in 208-Pin and 144-Pin packages only)
— Up to four chip select outputs to select 16K, 1M, 2M and up to 4MByte address spaces
— Each chip select output can be configured to complete transaction on either the time-out of one
of the two wait state generators or the deassertion of EWAIT signal
MMC (module mapping control)
DBG (debug module)
— Monitoring of CPU and/or XGATE busses with tag-type or force-type breakpoint requests
— 64 x 64-bit circular trace buffer captures change-of-flow or memory access information
BDM (background debug mode)
MPU (memory protection unit)
— 8 address regions definable per active program task
— Address range granularity as low as 8-bytes
— No write / No execute Protection Attributes
— Non-maskable interrupt on access violation
XGATE
— Programmable, high performance I/O coprocessor module
— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states
— Performs logical, shifts, arithmetic, and bit operations on data
— Can interrupt the HCS12X CPU signalling transfer completion
— Triggers from any hardware module as well as from the CPU possible
— Two interrupt levels to service high priority tasks
— Hardware support for stack pointer initialisation
OSC_LCP (oscillator)
— Low power loop control Pierce oscillator utilizing a 4MHz to 16MHz crystal
— Good noise immunity
— Full-swing Pierce option utilizing a 2MHz to 40MHz crystal
— Transconductance sized for optimum start-up margin for typical crystals
IPLL (Internally filtered, frequency modulated phase-locked-loop clock generation)
— No external components required
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•
•
•
•
•
•
•
— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)
CRG (clock and reset generation)
— COP watchdog
— Real time interrupt
— Clock monitor
— Fast wake up from STOP in self clock mode
Memory Options
— 128K, 256k, 384K, 512K, 768K and 1M byte Flash
— 2K, 4K byte emulated EEPROM
— 12K, 16K, 24K, 32K, 48K and 64K Byte RAM
Flash General Features
— 64 data bits plus 8 syndrome ECC (Error Correction Code) bits allow single bit failure
correction and double fault detection
— Erase sector size 1024 bytes
— Automated program and erase algorithm
D-Flash Features
— Up to 32 Kbytes of D-Flash memory with 256 byte sectors for user access.
— Dedicated commands to control access to the D-Flash memory over EEE operation.
— Single bit fault correction and double bit fault detection within a word during read operations.
— Automated program and erase algorithm with verify and generation of ECC parity bits.
— Fast sector erase and word program operation.
— Ability to program up to four words in a burst sequence
Emulated EEPROM Features
— Automatic EEE file handling using an internal Memory Controller.
— Automatic transfer of valid EEE data from D-Flash memory to buffer RAM on reset.
— Ability to monitor the number of outstanding EEE related buffer RAM words left to be
programmed into D-Flash memory.
— Ability to disable EEE operation and allow priority access to the D-Flash memory.
— Ability to cancel all pending EEE operations and allow priority access to the D-Flash memory.
Two 16-channel, 12-bit Analog-to-Digital Converters
— 8/10/12 Bit resolution
— 3µs, 10-bit single conversion time
— Left/right, signed/unsigned result data
— External and internal conversion trigger capability
— Internal oscillator for conversion in Stop modes
— Wake from low power modes on analog comparison > or <= match
Five MSCAN (1 M bit per second, CAN 2.0 A, B software compatible modules)
— Five receive and three transmit buffers
— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit, or 8 x 8 bit
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Chapter 1 Device Overview MC9S12XE-Family
•
•
•
•
•
•
•
•
•
— Four separate interrupt channels for Rx, Tx, error, and wake-up
— Low-pass filter wake-up function
— Loop-back for self-test operation
ECT (enhanced capture timer)
— 8 x 16-bit channels for input capture or output compare
— 16-bit free-running counter with 8-bit precision prescaler
— 16-bit modulus down counter with 8-bit precision prescaler
— Four 8-bit or two 16-bit pulse accumulators
TIM (standard timer module)
— 8 x 16-bit channels for input capture or output compare
— 16-bit free-running counter with 8-bit precision prescaler
— 1 x 16-bit pulse accumulator
PIT (periodic interrupt timer)
— Up to eight timers with independent time-out periods
— Time-out periods selectable between 1 and 224 bus clock cycles
— Time-out interrupt and peripheral triggers
8 PWM (pulse-width modulator) channels
— 8 channel x 8-bit or 4 channel x 16-bit Pulse Width Modulator
— programmable period and duty cycle per channel
— Center- or left-aligned outputs
— Programmable clock select logic with a wide range of frequencies
— Fast emergency shutdown input
Three Serial Peripheral Interface Modules (SPI)
— Configurable for 8 or 16-bit data size
Eight Serial Communication Interfaces (SCI)
— Standard mark/space non-return-to-zero (NRZ) format
— Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
Two Inter-IC bus (IIC) Modules
— Multi-master operation
— Software programmable for one of 256 different serial clock frequencies
— Broadcast mode support
— 10-bit address support
On-Chip Voltage Regulator
— Two parallel, linear voltage regulators with bandgap reference
— Low-voltage detect (LVD) with low-voltage interrupt (LVI)
— Power-on reset (POR) circuit
— 3.3V and 5V range operation
— Low-voltage reset (LVR)
Low-power wake-up timer (API)
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•
•
•
1.1.2
— Available in all modes including Full Stop Mode
— Trimmable to +-10% accuracy
— Time-out periods range from 0.2ms to ~13s with a 0.2ms resolution
Input/Output
— Up to 152 general-purpose input/output (I/O) pins plus 2 input-only pins
— Hysteresis and configurable pull up/pull down device on all input pins
— Configurable drive strength on all output pins
Package Options
— 208-pin MAPBGA
— 144-pin low-profile quad flat-pack (LQFP)
— 112-pin low-profile quad flat-pack (LQFP)
— 80-pin quad flat-pack (QFP)
50MHz maximum CPU bus frequency, 100MHz maximum XGATE bus frequency
Modes of Operation
Memory map and bus interface modes:
• Normal and emulation operating modes
— Normal single-chip mode
— Normal expanded mode
— Emulation of single-chip mode
— Emulation of expanded mode
• Special Operating Modes
— Special single-chip mode with active background debug mode
— Special test mode (Freescale use only)
Low-power modes:
• System stop modes
— Pseudo stop mode
— Full stop mode with fast wake-up option
• System wait mode
Operating system states
• Supervisor state
• User state
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Chapter 1 Device Overview MC9S12XE-Family
1.1.3
Block Diagram
Reset Generation
and Test Entry
EWAIT
PA[7:0]
PTA
ADDR[15:8]
PB[7:0]
PTB
ADDR[7:0]
PC[7:0]
PTC
ADDR[22:16]
DATA[15:8]
PD[7:0]
DATA[7:0]
PTF
CS0
CS1
CS2
CS3
SDA
SCL
RXD
TXD
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
INT
Enhanced Multilevel
Interrupt Module
MPU
XIRQ
IRQ
RW/WE
LSTRB/LDS
ECLK
MODA/TAGLO/RE
MODB/TAGHI
XCLKS/ECLKX2
PTD
PK[7:0]
PTK
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PTE
TEST
Memory Protection
8 regions
Non-Multiplexed External Bus Interface
RESET
PWM
PIT
PWM[7:0]
8-bit 8 channel
Pulse Width Modulator
RXD
SCI0
TXD
Asynchronous Serial IF
RXD
SCI1
TXD
Asynchronous Serial IF
SPI0
MISO
Synchronous Serial IF
CAN0
msCAN 2.0B
CAN1
msCAN 2.0B
CAN2
msCAN 2.0B
CAN3
msCAN 2.0B
SCI4
Asynchronous Serial IF
SCI5
Asynchronous Serial IF
SCI6
Asynchronous Serial IF
SCI7
Asynchronous Serial IF
SCI2
Asynchronous Serial IF
MOSI
SCK
SS
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXCAN
TXCAN
RXD
TXD
RXD
TXD
RXD
TXD
RXD
TXD
RXD
TXD
IIC1
Inter IC Module
CAN4
msCAN 2.0B
SDA
SCL
RXCAN
TXCAN
Synchronous Serial IF
SPI1
Synchronous Serial IF
SPI2
8ch 16-bit Timer
IIC0
Inter IC Module
SCI3
Asynchronous Serial IF
Figure 1-1. MC9S12XE-Family
PTAD0
IPLL with Frequency
Modulation option
Clock Monitor
COP Watchdog
Periodic Interrupt
Async. Periodic Int.
IOC[7:0]
PTAD1
XTAL
Amplitude Controlled
Low Power Pierce or
Full drive Pierce
Oscillator
X
EXTAL
16-bit 8 channel
Timer
XGATE
BKGD
Debug Module
Single-wire Background 4 address breakpoints
Debug Module
2 data breakpoints
512 Byte Trace Buffer
PTT
CPU12X
PT[7:0]
PTR
IOC[7:0]
16-bit 8 channel
Enhanced Capture Timer
TIM
PR[7:0]
PP[7:0]
PTS
Voltage Regulator
PAD[31:16]
PTH (Wake-up Int)
8/10/12-bit 16-channel AN[15:0]
Analog-Digital Converter
ECT
PTM
2K … 4K bytes EEPROM
VDDR
VDD
VDDF
VDDPLL
PAD[15:0]
PTL
8/10/12-bit 16-channel AN[15:0]
Analog-Digital Converter
ATD1
12K … 64K bytes RAM
PTJ (Wake-up Int.)
ATD0
128K … 1M bytes Flash
PTP (Int)
Figure 1-1 shows a block diagram of the MC9S12XE-Family devices
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
PL0
PL1
PL2
PL3
PL4
PL5
PL6
PL7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
Block Diagram
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1.1.4
Device Memory Map
Table 1-1 shows the device register memory map.
Table 1-1. Device Register Memory Map
Address
Module
Size
(Bytes)
0x0000–0x0009
PIM (port integration module)
10
0x000A–0x000B
MMC (memory map control)
2
0x000C–0x000D
PIM (port integration module)
2
0x000E–0x000F
EBI (external bus interface)
2
0x0010–0x0017
MMC (memory map control)
8
0x0018–0x0019
Reserved
2
0x001A–0x001B
Device ID register
2
0x001C–0x001F
PIM (port integration module)
4
0x0020–0x002F
DBG (debug module)
16
0x0030–0x0031
Reserved
2
0x0032–0x0033
PIM (port integration module)
2
0x0034–0x003F
ECRG (clock and reset generator)
12
0x0040–0x007F
ECT (enhanced capture timer 16-bit 8-channel)s
64
0x0080–0x00AF
ATD1 (analog-to-digital converter 12-bit 16-channel)
48
0x00B0–0x00B7
IIC1 (inter IC bus)
8
0x00B8–0x00BF
SCI2 (serial communications interface)
8
0x00C0–0x00C7
SCI3 (serial communications interface)
8
0x00C8–0x00CF
SCI0 (serial communications interface)
8
0x00D0–0x00D7
SCI1 (serial communications interface)
8
0x00D8–0x00DF
SPI0 (serial peripheral interface)
8
0x00E0–0x00E7
IIC0 (inter IC bus)
8
0x00E8–0x00EF
Reserved
8
0x00F0–0x00F7
SPI1 (serial peripheral interface)
8
0x00F8–0x00FF
SPI2 (serial peripheral interface)
8
0x0100–0x0113
FTM control registers
20
0x0114–0x011F
MPU (memory protection unit)
12
0x0120–0x012F
INT (interrupt module)
16
0x0130–0x0137
SCI4 (serial communications interface)
8
0x0138–0x013F
SCI5 (serial communications interface)
8
0x0140–0x017F
CAN0
64
0x0180–0x01BF
CAN1
64
0x01C0–0x01FF
CAN2
64
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Chapter 1 Device Overview MC9S12XE-Family
Table 1-1. Device Register Memory Map (continued)
Address
Size
(Bytes)
Module
0x0200–0x023F
CAN3
64
0x0240–0x027F
PIM (port integration module)
64
0x0280–0x02BF
CAN4
64
0x02C0–0x02EF
ATD0 (analog-to-digital converter 12 bit 16-channel)
48
0x02F0–0x02F7
Voltage regulator
8
0x02F8–0x02FF
Reserved
8
0x0300–0x0327
PWM (pulse-width modulator 8 channels)
40
0x0328–0x032F
Reserved
8
0x0330–0x0337
SCI6 (serial communications interface)
8
0x0338–0x033F
SCI7 (serial communications interface)
8
0x0340–0x0367
PIT (periodic interrupt timer)
40
0x0368–0x037F
PIM (port integration module)
24
0x0380–0x03BF
XGATE
64
0x03C0–0x03CF
Reserved
16
0x03D0–0x03FF
TIM (timer module)
48
0x0400–0x07FF
Reserved
1024
NOTE
Reserved register space shown in Table 1-1 is not allocated to any module.
This register space is reserved for future use. Writing to these locations have
no effect. Read access to these locations returns zero.
1.1.5
Address Mapping
Figure 1-2 shows S12XE CPU & BDM local address translation to the global memory map. It indicates
also the location of the internal resources in the memory map.
EEEPROM size is presented like a fixed 256 KByte in the memory map.
Table 1-2. Device Internal Resources
Internal Resource
Size /KByte
$Address
System RAM
64K
RAM_LOW = 0x0F_0000
FLASH
1M
FLASH_LOW = 0x70_0000
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CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_07FF
2K REGISTERS
CS3
Unimplemented
RAM
0x0000
0x0800
0x0C00
0x1000
RAM
2K REGISTERS
1K EEPROM window
EPAGE
RAMSIZE
RAM_LOW
0x0F_FFFF
1K EEPROM
4K RAM window
RPAGE
0x2000
256 K EEEPROM
RESOURCES
8K RAM
0x4000
0x13_FFFF
CS2
Unpaged
16K FLASH
0x1F_FFFF
External
Space
CS1
0x8000
PPAGE
0x3F_FFFF
0xC000
CS0
16K FLASH window
Unimplemented
FLASH
Unpaged
16K FLASH
Reset Vectors
FLASH_LOW
FLASH
FLASHSIZE
0xFFFF
0x7F_FFFF
Figure 1-2. MC9S12XE100 Global Memory Map
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Chapter 1 Device Overview MC9S12XE-Family
Unimplemented RAM pages are mapped externally in expanded modes. Accessing unimplemented RAM
pages in single chip modes causes an illegal address reset.
Accessing unimplemented FLASH pages in single chip modes causes an illegal address reset.
The range between 0x10_0000 and 0x13_FFFF is mapped to EEPROM resources. The actual EEPROM
and dataflash block sizes are listed in Table 1-4. Within EEPROM resource range an address range exists
which is neither used by EEPROM resources nor remapped to external resources via chip selects (see the
FTM/MMC descriptions for details).
The fixed 8K RAM default location in the global map is 0x0F_E000- 0x0F_FFFF. This is subject to
remapping when configuring the local address map for a larger RAM access range.
Figure 1-3 shows XGATE local address translation to the global memory map. It indicates also the location
of used internal resources in the memory map.
Table 1-3. XGATE Resources
1
Internal Resource
Size /KByte
$Address
XGATE RAM
32K
XGRAM_LOW = 0x0F_8000
FLASH
30K1
XGFLASH_HIGH = 0x78_8000
This value is calculated by the following formula: (64K -2K- XGRAMSIZE)
Table 1-4. Derivative Dependent Memory Parameters
Device
FLASH_LOW
PPAGE1
RAM_LOW
RPAGE
2
EE_LOW
DF_HIGH
EPAGE
9S12XEx100
0x70_0000
64
0x0F_0000
16
0x13_F000
0x10_7FFF
43 + 324
9S12XEx768
0x74_0000
48
0x0F_4000
12
0x13_F000
0x10_7FFF
4 + 32
9S12XEx512
0x78_0000
32
0x0F_8000
8
0x13_F000
0x10_7FFF
4 + 32
9S12XEx384
0x78_00005
24
0x0F_A000
6
0x13_F000
0x10_7FFF
4 + 32
9S12XEx256
0x78_00006
16
0x0F_C000
4
0x13_F000
0x10_7FFF
4 + 32
9S12XEx128
0x7E_0000
8
0x0F_D000
3
0x13_7F00
0x10_3FFF
2 + 16
1Number of 16K pages addressable via PPAGE register
2Number of 4K pages addressing the RAM. RAM can also be mapped to 0x4000 - 0x7FFF
3Number of 1K pages addressing the Cache RAM via the EPAGE register counting downwards from 0xFF
4Number of 1K pages addressing the Data flash via the EPAGE register starting upwards from 0x00
5The 384K memory map is split into a 128K block from 0x78_0000 to 0x79_FFFF and a 256K block from 0x7C_0000
to
0x7F_FFFF
6The 256K memory map is split into a 128K block from 0x78_0000 to 0x79_FFFF and a 128K block from 0x7E_0000 to
0x7F_FFFF
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Table 1-5. Derivative Dependent Flash Block Mapping
Device
0x70_0000
0x74_0000
0x78_0000
0x7A_0000
0x7C_0000
0x7E_0000
9S12XEx100
B3
B2
B1S
B1N
B0
9S12XEx768
—
B2
B1S
B1N
B0
9S12XEx512
—
—
B1S
B1N
B0
9S12XEx384
—
—
B1S
—
B0
9S12XEx256
—
—
B1S
—
—
B0(128K)
9S12XEx128
—
—
—
—
—
B0 (128K)
Block B1 is divided into two 128K blocks. The XGATE is always mapped to block B1S. Since block B1S
does not exist on the 9S12XEx128, XGATE code can only be run from RAM.
The block B0 is a reduced size 128K block on the 128K and 256K derivatives. On the larger derivatives
B0 is a 256K block.
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Chapter 1 Device Overview MC9S12XE-Family
XGATE
Local Memory Map
Global Memory Map
0x00_0000
Registers
0x00_07FF
XGRAM_LOW
0x0800
RAM
0x0F_FFFF
RAMSIZE
Registers
XGRAMSIZE
0x0000
FLASH
RAM
0x78_0800
0xFFFF
FLASHSIZE
FLASH
XGFLASH_HIGH
0x7F_FFFF
Figure 1-3. XGATE Global Address Mapping
MC9S12XE-Family Reference Manual , Rev. 1.07
32
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Chapter 1 Device Overview MC9S12XE-Family
1.1.6
Detailed Register Map
The detailed register map is listed in Appendix A.
1.1.7
Part ID Assignments
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B).
The read-only value is a unique part ID for each revision of the chip. Table 1-6 shows the assigned part ID
number and Mask Set number.
The Version ID is a word located in a flash information row at 0x40_00E8. The version ID number
indicates a specific version of internal NVM variables used to patch NVM errata.
The default is no patch (0xFFFF).
Table 1-6. Assigned Part ID Numbers
1
1.2
Device
Mask Set Number
Part ID1
Version ID
MC9S12XEP100
0M22E
$CC80
0xFFFF
MC9S12XEP100
1M22E
$CC80
0xFFFF
MC9S12XEP100
2M22E
$CC82
0xFFFF
MC9S12XEP100
0M48H
$CC90
0xFFFF
MC9S12XEP100
1M48H
$CC91
0xFFFF
MC9S12XEP100
2M48H
$CC92
0xFFFF
MC9S12XEQ512
0M25J
$C480
0xFFFF
MC9S12XET256
0M53J
$C080
0xFFFF
The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
Signal Description
This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal
properties, and detailed discussion of signals. It is built from the signal description sections of the Block
User Guides of the individual IP blocks on the device.
1.2.1
Device Pinout
The XE-Family of devices offers pin-compatible packaged devices to assist with system development and
accommodate expansion of the application.
The MC9S12XE-Family devices are offered in the following package options:
• 208-pin MAPBGA package with an external bus interface (address/data bus)
• 144-pin LQFP package with an external bus interface (address/data bus)
• 112-pin LQFP without external bus interface
• 80-pin QFP without external bus interface
MC9S12XE-Family Reference Manual Rev. 1.07
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33
Chapter 1 Device Overview MC9S12XE-Family
1
2
3
4
5
6
7
8
9
10
11
12
A
N.C.
N.C.
PP7
PM0
PM1
PF5
PF3
PF1
PJ6
PS6
PS5
PS3
B
N.C.
PP2
PP6
PF7
PF6
PF4
PF2
PF0
C
PJ2
PP1
PP4
PP5
PK7
PM2
PM4
PJ5
PS7
D
PK1
PJ3
PP0
PP3
VDDX
PM3
PM5
PJ4
PJ7 VDDX PS0 PAD22 VRH PAD17 PAD30 PAD29
E
PK0
PK3
PK2
PK6
VSSA PAD15 PAD06 PAD28
F
PR1
PR0
PT0
VDDX
VDDA PAD05 PAD13 PAD27
G
PT2
PT3
PR2
PT1
VSSX VSSX VSSX VSSX
VDDA PAD12 PAD04 PAD11
H
PR3
PR4
PT4
VDDF
VSSX VSSX VSSX VSSX
VSSA PAD26 PAD03 PAD10
J
PT5
PR5
PT6
VSS1
VSSX VSSX VSSX VSSX
VSS2 PAD09 PAD25 PAD02
K
PR6
PT7
PK4
PR7
VSSX VSSX VSSX VSSX
L
PK5
PJ1
M
PJ0
PC0
PB1
PC1
N
PC2
PC3
PB2
PC7
PL1
PE6
P
PB0
PB3
PB4
PC4
PL2
R
N.C.
PB5
PB6
PB7
T
N.C.
N.C.
PC5
PL3
TEST PS4
PS2
14
15
PM6 PAD19 N.C.
16
N.C.
PS1 PAD23 PAD21 PAD18 PAD31 N.C.
PM7 PAD20 VRL PAD16 PAD07 PAD14
BKGD VDDX
VDDX VDDR
13
VDD
PD7 PAD24 PAD01
VDDX
PD4 PAD00 PAD08
PA6
PA2
PD5
PD6
VSS3
PH3
PH1
VDDX
PE1
PA1
PA5
PA7
PL0
PE4 RESET PL7
PL6
PH0
PE2
PE0
PA0
PA3
PA4
PC6
PH6
PH4
PE5
VSS
PLL
VDD
PLL
PH2
PL4
PD1
PD3
PE3
N.C.
PH7
PH5
PE7
VSS
EXTAL XTAL
PLL
VDD
PLL
PL5
PD0
PD2
N.C.
N.C.
Figure 1-4. - Pin Assignments, 208 MAPBGA Package
MC9S12XE-Family Reference Manual , Rev. 1.07
34
Freescale Semiconductor
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PP4/KWP4/PWM4/MISO2/TIMIOC4
PP5/KPW5/PWM5/MOSI2/TIMIOC5
PP6/KWP6/PWM6/SS2/TIMIOC6
PP7/KWP7/PWM7/SCK2/TIMIOC7
PK7/ROMCTL/EWAIT
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN2/TXCAN0/TXCAN4/SCK0
PJ4/KWJ4/SDA1/CS0
PJ5/KWJ5/SCL1/CS2
PJ6/KWJ6/RXCAN4/SDA0/RXCAN0
PJ7/KWJ7/TXCAN4/SCL0/TXACAN0
TEST
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6/RXCAN3/RXCAN4/RXD3
PM7/TXCAN3/TXCAN4/TXD3
PAD23/AN23
PAD22/AN22
PAD21/AN21
PAD20/AN20
PAD19/AN19
PAD18/AN18
VSSA1
VRL
Chapter 1 Device Overview MC9S12XE-Family
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MC9S12XE-Family
144 LQFP
Pins shown in BOLD-ITALICS neither available on the 112 LQFP
nor on the 80 QFP Package Option
Pins shown in BOLD are not available on the 80 QFP package
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VRH
VDDA1
PAD17/AN17
PAD16/AN16
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD
PD7/DATA7
PD6/DATA6
PD5/DATA5
PD4/DATA4
VDDX3
VSSX3
PA7/ADDR15
PA6/ADDR14
PA5/ADDR13
PA4/ADDR12
PA3/ADDR11
PA2/ADDR10
PA1/ADDR9
PA0/ADDR8
ADDR5/PB5
ADDR6/PB6
ADDR7/PB7
DATA12/PC4
DATA13/PC5
DATA14/PC6
DATA15/PC7
TXD5/SS2/KWH7/PH7
RXD5/SCK2/KWH6/PH6
TXD4/MOSI2/KWH5/PH5
RXD4/MISO2/KWH4/PH4
XCLKS/ECLK2X/PE7
TAGHI/MODB/PE6
RE/TAGLO/MODA/PE5
ECLK/PE4
VSSX2
VDDX2
RESET
VDDR
VSS3
VSSPLL
EXTAL
XTAL
VDDPLL
TXD7/SS1/KWH3/PH3
RXD7/SCK1/KWH2/PH2
TXD6/MOSI1/KWH1/PH1
RXD6/MISO1/KWH0/PH0
DATA0/PD0
DATA1/PD1
DATA2/PD2
DATA3/PD3
EROMCTL/LDS/LSTRB/PE3
WE/RW/PE2
IRQ/PE1
XIRQ/PE0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TIMIOC3/SS1/PWM3/KWP3/PP3
TIMIOC2/SCK1/PWM2/KWP2/PP2
TIMIOC1/MOSI1/PWM1/KWP1/PP1
TIMIOC0/MISO1/PWM0/KWP0/PP0
CS1/KWJ2/PJ2
NOACC/ADDR22/PK6
ADDR19/PK3
IQSTAT2/ADDR18/PK2
IQSTAT1/ADDR17/PK1
IQSTAT0/ADDR16/PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDDF
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
ADDR21/PK5
ADDR20/PK4
TXD2/KWJ1/PJ1
RXD2/KWJ0/PJ0
MODC/BKGD
VDDX4
VSSX4
DATA8/PC0
DATA9/PC1
DATA10/PC2
DATA11/PC3
UDS/ADDR0/PB0
ADDR1/PB1
ADDR2/PB2
ADDR3/PB3
ADDR4/PB4
Figure 1-5. MC9S12XE-Family Pin Assignments 144-pin LQFP Package
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
35
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
Pins shown in BOLD are not available on the 80 QFP package 67
66
65
64
63
62
61
60
59
58
57
MC9S12XE-Family
112LQFP
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VRH
VDDA1
PAD15/AN15
PAD07/AN07
PAD14/AN14
PAD06/AN06
PAD13/AN13
PAD05/AN05
PAD12/AN12
PAD04/AN04
PAD11/AN11
PAD03/AN03
PAD10/AN10
PAD02/AN02
PAD09/AN09
PAD01/AN01
PAD08/AN08
PAD00/AN00
VSS2
VDD
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB5
PB6
PB7
TXD5/SS2/KWH7/PH7
RXD5/SCK2/KWH6/PH6
TXD4/MOSI2/KWH5/PH5
RXD4/MISO2/KWH4/PH4
ECLK2X/XCLKS/PE7
MODB/PE6
MODA/PE5
ECLK/PE4
VSSX2
VDDX2
RESET
VDDR
VSS3
VSSPLL
EXTAL
XTAL
VDDPLL
TXD7/SS1/KWH3/PH3
RXD7/SCK1/KWH2/PH2
TXD6/MOSI1/KWH1/PH1
RXD6/MISO1/KWH0/PH0
PE3
PE2
IRQ/PE1
XIRQ/PE0
TIMIOC3/SS1/PWM3/KWP3/PP3
TIMIOC2/SCK1/PWM2/KWP2/PP2
TIMIOC1/MOSI1/PWM1/KWP1/PP1
TIMIOC0/MISO1/PWM0/KWP0/PP0
PK3
PK2
PK1
PK0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDDF
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
PK5
PK4
TXD2/KWJ1/PJ1
RXD2/KWJ0/PJ0
MODC/BKGD
PB0
PB1
PB2
PB3
PB4
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PP4/KWP4/PWM4/MISO2/TIMIOC4
PP5/KPW5/PWM5/MOSI2/TIMIOC5
PP6/KWP6/PWM6/SS2/TIMIOC6
PP7/KWP7/PWM7/SCK2/TIMIOC7
PK7
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN2/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA0/RXCAN0
PJ7/KWJ7/TXCAN4/SCL0/TXCAN0
TEST
PS7/SS0
PS6/SCK0
PS5/MOSI0
PS4/MISO0
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
PM6/RXCAN3/RXCAN4/RXD3
PM7/TXCAN3/TXCAN4/TXD3
VSSA1
VRL
Chapter 1 Device Overview MC9S12XE-Family
Figure 1-6. . MC9S12XE-Family Pin Assignments 112-pin LQFP Package
MC9S12XE-Family Reference Manual , Rev. 1.07
36
Freescale Semiconductor
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PP4/KWP4/PWM4/MISO2/TIMIOC4
PP5/KWP5/PWM5/MOSI2/TIMIOC5
PP7/KWP7/PWM7/SCK2/TIMIOC7
VDDX1
VSSX1
PM0/RXCAN0
PM1/TXCAN0
PM2/RXCAN1/RXCAN0/MISO0
PM3/TXCAN1/TXCAN0/SS0
PM4/RXCAN2/RXCAN0/RXCAN4/MOSI0
PM5/TXCAN2/TXCAN0/TXCAN4/SCK0
PJ6/KWJ6/RXCAN4/SDA0/RXCAN0
PJ7/KWJ7/TXCAN4/SCL0/TXCAN0
TEST
PS3/TXD1
PS2/RXD1
PS1/TXD0
PS0/RXD0
VSSA1
VRL
Chapter 1 Device Overview MC9S12XE-Family
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MC9S12XE-Family
80QFP
VRH
VDDA1
PAD07/AN07/
PAD06/AN06
PAD05/AN05
PAD04/AN04
PAD03/AN03
PAD02/AN02
PAD01/AN01
PAD00/AN00
VSS2
VDD
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
XIRQ/PE0
IRQ/PE1
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PB5
PB6
PB7
ECLK2X/XCLKS/PE7
MODB/PE6
MODA/PE5
ECLK/PE4
VSSX2
VDDX2
RESET
VDDR
VSS3
VSSPLL
EXTAL
XTAL
VDDPLL
PE3
PE2
TIMIOC3/SS1/PWM3/KWP3/PP3
TIMIOC2/SCK1/PWM2/KWP2/PP2
TIMIOC1/MOSI1/PWM1/KWP1/PP1
TIMIOC0/MISO1/PWM0/KWP0/PP0
IOC0/PT0
IOC1/PT1
IOC2/PT2
IOC3/PT3
VDDF
VSS1
IOC4/PT4
IOC5/PT5
IOC6/PT6
IOC7/PT7
MODC/BKGD
PB0
PB1
PB2
PB3
PB4
Figure 1-7. . MC9S12XE-Family Pin Assignments 80-pin QFP Package
MC9S12XE-Family Reference Manual Rev. 1.07
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37
Chapter 1 Device Overview MC9S12XE-Family
1.2.2
Pin Assignment Overview
Table 1-7 provides a summary of which Ports are available for each package option.
Routing of pin functions is summarized in Table 1-8.
Table 1-9 provides a pin out summary listing the availability of individual pins for each package option.
Table 1-10 provides a list of individual pin functionality
Table 1-7. Port Availability by Package Option
Port
208
MAPBGA
144 LQFP
112 LQFP
80 QFP
Port AD/ADC Channels
32/32
24/24
16/16
8/8
Port A pins
8
8
8
8
Port B pins
8
8
8
8
Port C pins
8
8
0
0
Port D pins
8
8
0
0
Port E pins inc. IRQ/XIRQ input only
8
8
8
8
Port F
8
0
0
0
Port H
8
8
8
0
Port J
8
7
4
2
Port K
8
8
7
0
Port L
8
0
0
0
Port M
8
8
8
6
Port P
8
8
8
7
Port R
8
0
0
0
Port S
8
8
8
4
Port T
8
8
8
8
Sum of Ports
152
119
91
59
I/O Power Pairs VDDX/VSSX
7/7
4/4
2/2
2/2
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Chapter 1 Device Overview MC9S12XE-Family
PF[0]
TIM
CS3
CS2
CS1
CS0
IIC1
IIC0
SPI2
SPI1
SPI0
SCI7
SCI6
SCI5
SCI4
SCI3
SCI2
SCI1
SCI0
CAN4
CAN3
CAN2
CAN1
CAN0
Table 1-8. Peripheral - Port Routing Options1
X
PF[1]
X
PF[2]
X
PF[3]
X
PF[5:4]
X
PF[7:6]
X
PH[1:0]
O
PH[3:2]
X
O
PH[5:4]
X
O
PH[7:6]
X
O
PJ[0]
O
PJ[1]
O
X
O
PJ[2]
O
PJ[3]
PJ[4]
O
PJ[5]
O
PJ[7:6]
X
O
O
O
O
PL[1:0]
X
PL[3:2]
X
PL[5:4]
X
PL[7:6]
X
PM[1:0]
O
PM[3:2]
X
PM[5:4]
X
O
PM[7:6]
PP[3:0]
X
O
X
O
X
X
O
O
X
MC9S12XE-Family Reference Manual Rev. 1.07
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39
Chapter 1 Device Overview MC9S12XE-Family
PP[7:4]
O
PR[7:0]
PS[1:0]
PS[3:2]
PS[7:4]
1
TIM
CS3
CS2
CS1
CS0
IIC1
IIC0
SPI2
SPI1
SPI0
SCI7
SCI6
SCI5
SCI4
SCI3
SCI2
SCI1
SCI0
CAN4
CAN3
CAN2
CAN1
CAN0
Table 1-8. Peripheral - Port Routing Options1
X
O
O
O
O
“O” denotes reset condition, “X” denotes a possible rerouting under software control
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Chapter 1 Device Overview MC9S12XE-Family
Table 1-9. Pin-Out Summary
208 1
MAPBGA
LQFP
144
LQFP
112
QFP
80
D4
1
1
1
PP3
KWP3
PWM3
SS1
TIMIOC3
B2
2
2
2
PP2
KWP2
PWM2
SCK1
TIMIOC2
C2
3
3
3
PP1
KWP1
PWM1
MOSI1
TIMIOC1
D3
4
4
4
PP0
KWP0
PWM0
MISO1
TIMIOC0
PJ3
KWJ3
D2
Pin
2nd
Func.
3rd
Func.
C1
5
PJ2
KWJ2
CS1
E4
6
PK6
ADDR22
ACC2
E2
7
5
PK3
ADDR19
IQSTAT3
E3
8
6
PK2
ADDR18
IQSTAT2
D1
9
7
PK1
ADDR17
IQSTAT1
E1
10
8
PK0
ADDR16
IQSTAT0
VDDX
VDDX7
VSSX
VSSX7
F3
11
9
5
F2
G4
12
10
6
F1
G1
13
11
7
G3
G2
14
12
8
H1
PT0
IOC0
PR0
TIMIOC0
PT1
IOC1
PR1
TIMIOC1
PT2
IOC2
PR2
TIMIOC2
PT3
IOC3
PR3
TIMIOC3
H4
15
13
9
VDDF
J4
16
14
10
VSS1
H3
17
15
11
PT4
IOC4
PR4
TIMIOC4
PT5
IOC5
PR5
TIMIOC5
H2
J1
18
J2
16
12
4th
Func.
5th
Func.
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Chapter 1 Device Overview MC9S12XE-Family
Table 1-9. Pin-Out Summary
208 1
MAPBGA
J3
LQFP
144
LQFP
112
QFP
80
19
17
13
K1
K2
20
18
14
K4
Pin
2nd
Func.
PT6
IOC6
PR6
TIMIOC6
PT7
IOC7
PR7
TIMIOC7
3rd
Func.
4th
Func.
L1
21
19
PK5
ADDR21
ACC1
K3
22
20
PK4
ADDR20
ACC0
L2
23
21
PJ1
KWJ1
TXD2
M1
24
22
PJ0
KWJ0
RXD2
CS3
L3
25
23
BKGD
MODC
VDDX
26
VDDX4
VSSX
27
VSSX4
M2
28
PC0
DATA8
M4
29
PC1
DATA9
N1
30
PC2
DATA10
N2
31
PC3
DATA11
P1
32
24
16
PB0
ADDR0
IVD0
UDS
M3
33
25
17
PB1
ADDR1
IVD1
N3
34
26
18
PB2
ADDR2
IVD2
P2
35
27
19
PB3
ADDR3
IVD3
P3
36
28
20
PB4
ADDR4
IVD4
R2
37
29
21
PB5
ADDR5
IVD5
R3
38
30
22
PB6
ADDR6
IVD6
R4
39
31
23
PB7
ADDR7
IVD7
P4
40
PC4
DATA12
T3
41
PC5
DATA13
R5
42
PC6
DATA14
N4
43
PC7
DATA15
PL3
TXD5
PH7
KWH7
T4
T5
44
32
15
SS2
5th
Func.
TXD5
MC9S12XE-Family Reference Manual , Rev. 1.07
42
Freescale Semiconductor
Chapter 1 Device Overview MC9S12XE-Family
Table 1-9. Pin-Out Summary
208 1
MAPBGA
LQFP
144
LQFP
112
QFP
80
P5
R6
45
33
N5
T6
46
34
P6
Pin
2nd
Func.
PL2
RXD5
PH6
KWH6
PL1
TXD4
PH5
KWH5
PL0
RXD4
PH4
3rd
Func.
4th
Func.
SCK2
RXD5
MOSI2
TXD4
KWH4
MISO2
RXD4
R7
47
35
T7
48
36
24
PE7
XCLKS
ECLKX2
N6
49
37
25
PE6
MODB
TAGHI
R8
50
38
26
PE5
MODA
TAGLO
RE
P7
51
39
27
PE4
ECLK
VSSX
52
40
28
VSSX2
VDDX
53
41
29
VDDX2
P8
54
42
30
RESET
N8
55
43
31
VDDR
N9
56
44
32
VSS3
T8
57
45
33
VSSPLL
T9
58
46
34
EXTAL
T10
59
47
35
XTAL
R10
60
48
36
VDDPLL
SS1
TXD7
SCK1
RXD7
MOSI1
TXD6
MISO1
RXD6
P9
N10
61
49
P10
R11
62
50
T12
N11
63
51
R12
52
PL7
TXD7
PH3
KWH3
PL6
RXD7
PH2
KWH2
PL5
TXD6
PH1
KWH1
PL4
RXD6
PH0
KWH0
P11
64
T13
65
PD0
DATA0
R13
66
PD1
DATA1
5th
Func.
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
43
Chapter 1 Device Overview MC9S12XE-Family
Table 1-9. Pin-Out Summary
208 1
MAPBGA
LQFP
144
LQFP
112
QFP
80
Pin
2nd
Func.
T14
67
PD2
DATA2
R14
68
PD3
DATA3
VDDX
VDDX5
VSSX
VSSX5
3rd
Func.
R15
69
53
37
PE3
LSTRB
LDS
P12
70
54
38
PE2
RW
WE
N13
71
55
39
PE1
IRQ
P13
72
56
40
PE0
XIRQ
P14
73
57
41
PA0
ADDR8
IVD8
N14
74
58
42
PA1
ADDR9
IVD9
M14
75
59
43
PA2
ADDR10
IVD10
P15
76
60
44
PA3
ADDR11
IVD11
P16
77
61
45
PA4
ADDR12
IVD12
N15
78
62
46
PA5
ADDR13
IVD13
M13
79
63
47
PA6
ADDR14
IVD14
N16
80
64
48
PA7
ADDR15
IVD15
VSSX
81
VSSX3
VDDX
82
VDDX3
L14
83
PD4
DATA4
M15
84
PD5
DATA5
M16
85
PD6
DATA6
K14
86
PD7
DATA7
K13
87
65
49
VDD
J13
88
66
50
VSS2
L15
89
67
51
PAD00
AN00
L16
90
68
PAD08
AN08
PAD24
AN24
PAD01
AN01
PAD09
AN09
K15
K16
91
69
J14
92
70
52
4th
Func.
5th
Func.
EROMCTL
MC9S12XE-Family Reference Manual , Rev. 1.07
44
Freescale Semiconductor
Chapter 1 Device Overview MC9S12XE-Family
Table 1-9. Pin-Out Summary
208 1
MAPBGA
LQFP
144
LQFP
112
QFP
80
J15
Pin
2nd
Func.
PAD25
AN25
PAD02
AN02
PAD10
AN10
H14
PAD26
AN26
H13
VSSA2
G13
VDDA2
J16
93
71
H16
94
72
H15
95
73
G16
96
74
53
54
F16
G15
97
75
G14
98
76
55
E16
F14
99
77
F15
100
78
56
D16
E15
101
79
C16
102
80
57
D15
C15
103
81
E14
104
82
58
B15
PAD03
AN03
PAD11
AN11
PAD27
AN27
PAD04
AN04
PAD12
AN12
PAD28
AN28
PAD05
AN05
PAD13
AN13
PAD29
AN29
PAD06
AN06
PAD14
AN14
PAD30
AN30
PAD07
AN07
PAD15
AN15
PAD31
AN31
C14
105
PAD16
AN16
D14
106
PAD17
AN17
F13
107
83
59
VDDA1
D13
108
84
60
VRH
C13
109
85
61
VRL
E13
110
86
62
VSSA1
B14
111
PAD18
AN18
A14
112
PAD19
AN19
3rd
Func.
4th
Func.
5th
Func.
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
45
Table 1-9. Pin-Out Summary
208 1
MAPBGA
LQFP
144
LQFP
112
QFP
80
Pin
2nd
Func.
3rd
Func.
4th
Func.
C12
113
PAD20
AN20
B13
114
PAD21
AN21
D12
115
PAD22
AN22
B12
116
PAD23
AN23
C11
117
87
PM7
TXCAN3
TXCAN4
TXD3
A13
118
88
PM6
RXCAN3
RXCAN4
RXD3
D11
119
89
63
PS0
RXD0
B11
120
90
64
PS1
TXD0
C10
121
91
65
PS2
RXD1
A12
122
92
66
PS3
TXD1
VSSX
VSSX6
VDDX
VDDX6
5th
Func.
B10
123
93
PS4
MISO0
A11
124
94
PS5
MOSI0
A10
125
95
PS6
SCK0
C9
126
96
PS7
SS0
B9
127
97
67
TEST
D9
128
98
68
PJ7
KWJ7
TXCAN4
SCL0
TXCAN0
A9
129
99
69
PJ6
KWJ6
RXCAN4
SDA0
RXCAN0
C8
130
PJ5
KWJ5
SCL1
CS2
PF0
CS0
PJ4
KWJ4
SDA1
CS0
PF1
CS1
PM5
TXCAN2
TXCAN0
TXCAN4
SCK0
PF2
CS2
PM4
RXCAN2
RXCAN0
RXCAN4
MOSI0
PF3
CS3
PM3
TXCAN1
TXCAN0
SS0
PF4
SDA0
B8
D8
131
A8
D7
132
100
70
B7
C7
133
101
71
A7
D6
B6
134
102
72
Chapter 1 Device Overview MC9S12XE-Family
Table 1-9. Pin-Out Summary
208 1
MAPBGA
C6
LQFP
144
LQFP
112
QFP
80
135
103
73
A6
A5
136
104
74
B5
A4
137
105
75
B4
2nd
Func.
3rd
Func.
PM2
RXCAN1
RXCAN0
PF5
SCL0
PM1
TXCAN0
PF6
RXD3
PM0
RXCAN0
PF7
TXD3
Pin
VSSX
138
106
76
VSSX1
VDDX
139
107
77
VDDX1
C5
140
108
A3
141
109
B3
142
110
C4
143
111
C3
144
112
1Not
4th
Func.
5th
Func.
MISO0
PK7
ROMCTL
EWAIT
PP7
KWP7
PWM7
SCK2
TIMIOC7
PP6
KWP6
PWM6
SS2
TIMIOC6
79
PP5
KWP5
PWM5
MOSI2
TIMIOC5
80
PP4
KWP4
PWM4
MISO2
TIMIOC4
78
the final MAPBGA pin assignment. Numbers are for reference only.
MC9S12XE-Family Reference Manual Rev. 1.07
Freescale Semiconductor
47
Chapter 1 Device Overview MC9S12XE-Family
Table 1-10. Signal Properties Summary (Sheet 1 of 4)
Pin
Pin
Pin
Pin
Pin
Power
Name
Name
Name
Name
Name
Supply
Function 1 Function 2 Function 3 Function 4 Function 5
Internal Pull
Resistor
Description
CTRL
Reset
State
EXTAL
—
—
—
—
VDDPLL
NA
NA
NA
NA
Oscillator pins
XTAL
—
—
—
—
VDDPLL
RESET
—
—
—
—
VDDX
TEST
—
—
—
—
N.A.
RESET pin
BKGD
MODC
—
—
—
VDDX
Always on
PAD[31:16]
AN[31:16]
—
—
—
VDDA
PER0AD1
PER1AD1
Disabled Port AD inputs of ATD1,
analog inputs of ATD1
PAD[15:0]
AN[15:0]
—
—
—
VDDA
PER0AD0
PER1AD0
Disabled Port AD inputs of ATD0,
analog inputs of ATD0
PULLUP
External reset
DOWN Test input
Up
Background debug
PA[7:0]
ADDR[15:8] IVD[15:8]
—
—
VDDX
PUCR
Disabled Port A I/O, address bus,
internal visibility data
PB[7:1]
ADDR[7:1]
IVD[7:0]
—
—
VDDX
PUCR
Disabled Port B I/O, address bus,
internal visibility data
PB0
ADDR0
UDS
VDDX
PUCR
Disabled Port B I/O, address bus,
upper data strobe
PC[7:0]
DATA[15:8]
—
—
—
VDDX
PUCR
Disabled Port C I/O, data bus
PD[7:0]
DATA[7:0]
—
—
—
VDDX
PUCR
Disabled Port D I/O, data bus
PE7
ECLKX2
XCLKS
—
—
VDDX
PUCR
PE6
TAGHI
MODB
—
—
VDDX
While RESET
pin is low: down
Port E I/O, tag high, mode
input
PE5
RE
MODA
TAGLO
—
VDDX
While RESET
pin is low: down
Port E I/O, read enable,
mode input, tag low input
PE4
ECLK
—
—
—
VDDX
PUCR
Up
Port E I/O, bus clock output
PE3
LSTRB
LDS
EROMCTL
—
VDDX
PUCR
Up
Port E I/O, low byte data
strobe, EROMON control
PE2
R/W
WE
—
—
VDDX
PUCR
Up
Port E I/O, read/write
PE1
IRQ
—
—
—
VDDX
PUCR
Up
Port E Input, maskable
interrupt
PE0
XIRQ
—
—
—
VDDX
PUCR
Up
Port E input, non-maskable
interrupt
PF7
TXD3
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, TXD of
SCI3
PF6
RXD3
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, RXD of
SCI3
PF5
SCL0
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, SCL of
IIC0
PF4
SDA0
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, SDA of
IIC0
Up
Port E I/O, system clock
output, clock select
MC9S12XE-Family Reference Manual , Rev. 1.07
48
Freescale Semiconductor
Chapter 1 Device Overview MC9S12XE-Family
Table 1-10. Signal Properties Summary (Sheet 2 of 4)
Pin
Pin
Pin
Pin
Pin
Power
Name
Name
Name
Name
Name
Supply
Function 1 Function 2 Function 3 Function 4 Function 5
Internal Pull
Resistor
Description
Reset
State
CTRL
PF3
CS3
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, chip
select 3
PF2
CS2
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, chip
select 2
PF1
CS1
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, chip
select 1
PF0
CS0
—
—
—
VDDX
PERF/
PPSF
Up
Port F I/O, interrupt, chip
select 0
PH7
KWH7
SS2
TXD5
—
VDDX
PERH/
PPSH
Disabled Port H I/O, interrupt, SS of
SPI2, TXD of SCI5
PH6
KWH6
SCK2
RXD5
—
VDDX
PERH/
PPSH
Disabled Port H I/O, interrupt, SCK of
SPI2, RXD of SCI5
PH5
KWH5
MOSI2
TXD4
—
VDDX
PERH/
PPSH
Disabled Port H I/O, interrupt, MOSI
of SPI2, TXD of SCI4
PH4
KWH4
MISO2
RXD4
—
VDDX
PERH/PPSH Disabled Port H I/O, interrupt, MISO
of SPI2, RXD of SCI4
PH3
KWH3
SS1
TXD7
—
VDDX
PERH/PPSH Disabled Port H I/O, interrupt, SS of
SPI1
PH2
KWH2
SCK1
RXD7
—
VDDX
PERH/PPSH Disabled Port H I/O, interrupt, SCK of
SPI1
PH1
KWH1
MOSI1
TXD6
—
VDDX
PERH/PPSH Disabled Port H I/O, interrupt, MOSI
of SPI1
PH0
KWH0
MISO1
RXD6
—
VDDX
PERH/PPSH Disabled Port H I/O, interrupt, MISO
of SPI1
PJ7
KWJ7
TXCAN4
SCL0
TXCAN0
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt, TX of
CAN4, SCL of IIC0, TX of
CAN0
PJ6
KWJ6
RXCAN4
SDA0
RXCAN0
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt, RX of
CAN4, SDA of IIC0, RX of
CAN0
PJ5
KWJ5
SCL1
CS2
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt, SCL of
IIC1, chip select 2
PJ4
KWJ4
SDA1
CS0
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt, SDA of
IIC1, chip select 0
PJ3
KWJ3
—
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt,
PJ2
KWJ2
CS1
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt, chip
select 1
PJ1
KWJ1
TXD2
—
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt, TXD of
SCI2
PJ0
KWJ0
RXD2
CS3
—
VDDX
PERJ/
PPSJ
Up
Port J I/O, interrupt, RXD of
SCI2
MC9S12XE-Family Reference Manual , Rev. 1.07
49
Freescale Semiconductor
Chapter 1 Device Overview MC9S12XE-Family
Table 1-10. Signal Properties Summary (Sheet 3 of 4)
Pin
Pin
Pin
Pin
Pin
Power
Name
Name
Name
Name
Name
Supply
Function 1 Function 2 Function 3 Function 4 Function 5
Internal Pull
Resistor
Description
CTRL
Reset
State
PK7
EWAIT
ROMCTL
—
—
VDDX
PUCR
Up
Port K I/O, EWAIT input,
ROM on control
PK[6:4]
ADDR
[22:20]
ACC[2:0]
—
—
VDDX
PUCR
Up
Port K I/O, extended
addresses, access source
for external access
PK[3:0]
ADDR
[19:16]
IQSTAT
[3:0]
—
—
VDDX
PUCR
Up
Extended address, PIPE
status
PL7
TXD7
—
—
—
VDDX
PERL/
PPSL
Up
Port L I/O, TXD of SCI7
PL6
RXD7
—
—
—
VDDX
PERL/
PPSL
Up
Port LI/O, RXD of SCI7
PL5
TXD6
—
—
—
VDDX
PERL/
PPSL
Up
Port L I/O, TXD of SCI6
PL4
RXD6
—
—
—
VDDX
PERL/
PPSL
Up
Port LI/O, RXD of SCI6
PL3
TXD5
—
—
—
VDDX
PERL/
PPSL
Up
Port L I/O, TXD of SCI5
PL2
RXD5
—
—
—
VDDX
PERL/
PPSL
Up
Port LI/O, RXD of SCI5
PL1
TXD4
—
—
—
VDDX
PERL/
PPSL
Up
Port L I/O, TXD of SCI4
PL0
RXD4
—
—
—
VDDX
PERL/
PPSL
Up
Port LI/O, RXD of SCI4
PM7
TXCAN3
TXD3
TXCAN4
—
VDDX
PERM/
PPSM
PM6
RXCAN3
RXD3
RXCAN4
—
VDDX PERM/PPSM Disabled Port M I/O RX of CAN3 and
CAN4, RXD of SCI3
PM5
TXCAN2
TXCAN0
TXCAN4
SCK0
VDDX PERM/PPSM Disabled Port M I/OCAN0, CAN2,
CAN4, SCK of SPI0
PM4
RXCAN2
RXCAN0
RXCAN4
MOSI0
VDDX PERM/PPSM Disabled Port M I/O, CAN0, CAN2,
CAN4, MOSI of SPI0
PM3
TXCAN1
TXCAN0
SS0
—
VDDX PERM/PPSM Disabled Port M I/O TX of CAN1,
CAN0, SS of SPI0
PM2
RXCAN1
RXCAN0
MISO0
—
VDDX PERM/PPSM Disabled Port M I/O, RX of CAN1,
CAN0, MISO of SPI0
PM1
TXCAN0
—
—
VDDX PERM/PPSM Disabled Port M I/O, TX of CAN0
PM0
RXCAN0
—
—
VDDX PERM/PPSM Disabled Port M I/O, RX of CAN0
PP7
KWP7
PWM7
SCK2
TIMIOC7
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
7 of PWM/TIM , SCK of SPI2
PP6
KWP6
PWM6
SS2
TIMIOC6
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
6 of PWM/TIM, SS of SPI2
Disabled Port M I/O, TX of CAN3 and
CAN4, TXD of SCI3
MC9S12XE-Family Reference Manual , Rev. 1.07
50
Freescale Semiconductor
Chapter 1 Device Overview MC9S12XE-Family
Table 1-10. Signal Properties Summary (Sheet 4 of 4)
Pin
Pin
Pin
Pin
Pin
Power
Name
Name
Name
Name
Name
Supply
Function 1 Function 2 Function 3 Function 4 Function 5
Internal Pull
Resistor
Description
Reset
State
CTRL
PP5
KWP5
PWM5
MOSI2
TIMIOC5
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
5 of PWM/TIM, MOSI of
SPI2
PP4
KWP4
PWM4
MISO2
TIMIOC4
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
4 of PWM/TIM, MISO2 of
SPI2
PP3
KWP3
PWM3
SS1
TIMIOC3
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
3 of PWM/TIM, SS of SPI1
PP2
KWP2
PWM2
SCK1
TIMIOC2
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
2 of PWM/TIM, SCK of SPI1
PP1
KWP1
PWM1
MOSI1
TIMIOC1
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
1 of PWM/TIM, MOSI of
SPI1
PP0
KWP0
PWM0
MISO1
TIMIOC0
VDDX
PERP/
PPSP
Disabled Port P I/O, interrupt, channel
0 of PWM/TIM, MISO2 of
SPI1
PR[7:0]
TIMIOC
[7:0]
—
—
—
VDDX
PERR/
PPSR
Disabled Port RI/O, TIM channels
PS7
SS0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SS of SPI0
PS6
SCK0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, SCK of SPI0
PS5
MOSI0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, MOSI of SPI0
PS4
MISO0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, MISO of SPI0
PS3
TXD1
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, TXD of SCI1
PS2
RXD1
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, RXD of SCI1
PS1
TXD0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, TXD of SCI0
PS0
RXD0
—
—
—
VDDX
PERS/
PPSS
Up
Port S I/O, RXD of SCI0
PT[7:6]
IOC[7:6]
—
—
—
VDDX
PERT/
PPST
Disabled Port T I/O, ECT channels
PT[5]
IOC[5]
VREGAPI
—
—
VDDX
PERT/
PPST
Disabled Port T I/O, ECT channels
PT[4:0]
IOC[4:0]
—
—
—
VDDX
PERT/
PPST
Disabled Port T I/O, ECT channels
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1.2.3
Detailed Signal Descriptions
NOTE
For devices assembled in 80-pin ,112-pin and 144-pin packages all
non-bonded out pins should be configured as outputs after reset in order to
avoid current drawn from floating inputs. Refer to Table 1-10 for affected
pins.
1.2.3.1
EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the oscillator output.
1.2.3.2
RESET — External Reset Pin
The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a
known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has an
internal pull-up device.
1.2.3.3
TEST — Test Pin
This input only pin is reserved for test. This pin has a pull-down device.
NOTE
The TEST pin must be tied to VSS in all applications.
1.2.3.4
BKGD / MODC — Background Debug and Mode Pin
The BKGD/MODC pin is used as a pseudo-open-drain pin for the background debug communication. It
is used as a MCU operating mode select pin during reset. The state of this pin is latched to the MODC bit
at the rising edge of RESET. The BKGD pin has a pull-up device.
1.2.3.5
PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD0
PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital
converter ATD0.
1.2.3.6
PAD[31:16] / AN[31:16] — Port AD Input Pins of ATD1
PAD[31:16] are general-purpose input or output pins and analog inputs AN[31:16] of the analog-to-digital
converter ATD1.
1.2.3.7
PA[7:0] / ADDR[15:8] / IVD[15:8] — Port A I/O Pins
PA[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
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1.2.3.8
PB[7:1] / ADDR[7:1] / IVD[7:1] — Port B I/O Pins
PB[7:1] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external address bus. In MCU emulation modes of operation, these pins are used for external
address bus and internal visibility read data.
1.2.3.9
PB0 / ADDR0 / UDS / IVD[0] — Port B I/O Pin 0
PB0 is a general-purpose input or output pin. In MCU expanded modes of operation, this pin is used for
the external address bus ADDR0 or as upper data strobe signal. In MCU emulation modes of operation,
this pin is used for external address bus ADDR0 and internal visibility read data IVD0.
1.2.3.10
PC[7:0] / DATA [15:8] — Port C I/O Pins
PC[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PC[7:0] can be configured to reduced levels, to allow data from an external
3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for PC[7:0] are
configured to reduced levels out of reset in expanded and emulation modes. The input voltage thresholds
for PC[7:0] are configured to 5-V levels out of reset in normal modes.
1.2.3.11
PD[7:0] / DATA [7:0] — Port D I/O Pins
PD[7:0] are general-purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the external data bus.
The input voltage thresholds for PD[7:0] can be configured to reduced levels, to allow data from an
external 3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage thresholds for
PD[7:0] are configured to reduced levels out of reset in expanded and emulation modes. The input voltage
thresholds for PC[7:0] are configured to 5-V levels out of reset in normal modes.
1.2.3.12
PE7 / ECLKX2 / XCLKS — Port E I/O Pin 7
PE7 is a general-purpose input or output pin. ECLKX2 is a free running clock of twice the internal bus
frequency, available by default in emulation modes and when enabled in other modes. The XCLKS is an
input signal which controls whether a crystal in combination with the internal loop controlled Pierce
oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used (refer to Oscillator
Configuration). An internal pullup is enabled during reset.
1.2.3.13
PE6 / MODB / TAGHI — Port E I/O Pin 6
PE6 is a general-purpose input or output pin. It is used as a MCU operating mode select pin during reset.
The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a
pull-down device which is only active when RESET is low. TAGHI is used to tag the high half of the
instruction word being read into the instruction queue.
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The input voltage threshold for PE6 can be configured to reduced levels, to allow data from an external
3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE6 is
configured to reduced levels out of reset in expanded and emulation modes.
1.2.3.14
PE5 / MODA / TAGLO / RE — Port E I/O Pin 5
PE5 is a general-purpose input or output pin. It is used as an MCU operating mode select pin during reset.
The state of this pin is latched to the MODA bit at the rising edge of RESET. This pin is shared with the
read enable RE output. This pin is an input with a pull-down device which is only active when RESET is
low. TAGLO is used to tag the low half of the instruction word being read into the instruction queue.
The input voltage threshold for PE5 can be configured to reduced levels, to allow data from an external
3.3-V peripheral to be read by the MCU operating at 5.0 V. The input voltage threshold for PE5 is
configured to reduced levels out of reset in expanded and emulation modes.
1.2.3.15
PE4 / ECLK — Port E I/O Pin 4
PE4 is a general-purpose input or output pin. It can be configured to drive the internal bus clock ECLK.
ECLK can be used as a timing reference. The ECLK output has a programmable prescaler.
1.2.3.16
PE3 / LSTRB / LDS / EROMCTL— Port E I/O Pin 3
PE3 is a general-purpose input or output pin. In MCU expanded modes of operation, LSTRB or LDS can
be used for the low byte strobe function to indicate the type of bus access. At the rising edge of RESET
the state of this pin is latched to the EROMON bit.
1.2.3.17
PE2 / R/W / WE— Port E I/O Pin 2
PE2 is a general-purpose input or output pin. In MCU expanded modes of operations, this pin drives the
read/write output signal or write enable output signal for the external bus. It indicates the direction of data
on the external bus.
1.2.3.18
PE1 / IRQ — Port E Input Pin 1
PE1 is a general-purpose input pin and the maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode.
1.2.3.19
PE0 / XIRQ — Port E Input Pin 0
PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of
applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. The XIRQ
interrupt is level sensitive and active low. As XIRQ is level sensitive, while this pin is low the MCU will
not enter STOP mode.
1.2.3.20
PF7 / TXD3 — Port F I/O Pin 7
PF7 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 3 (SCI3).
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1.2.3.21
PF6 / RXD3 — Port F I/O Pin 6
PF6 is a general-purpose input or output pin. It can be configured as the transmit pin RXD of serial
communication interface 3 (SCI3).
1.2.3.22
PF5 / SCL0 — Port F I/O Pin 5
PF5 is a general-purpose input or output pin. It can be configured as the serial clock pin SCL of the IIC0
module.
1.2.3.23
PF4 / SDA0 — Port F I/O Pin 4
PF4 is a general-purpose input or output pin. It can be configured as the serial data pin SDA of the IIC0
module.
1.2.3.24
PF[3:0] / CS[3:0] — Port F I/O Pins 3 to 0
PF[3:0] are a general-purpose input or output pins. They can be configured as chip select outputs [3:0].
1.2.3.25
PH7 / KWH7 / SS2 / TXD5 — Port H I/O Pin 7
PH7 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as slave select pin SS of the serial peripheral interface 2 (SPI2). It can be configured as the
transmit pin TXD of serial communication interface 5 (SCI5).
1.2.3.26
PH6 / KWH6 / SCK2 / RXD5 — Port H I/O Pin 6
PH6 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as serial clock pin SCK of the serial peripheral interface 2 (SPI2). It can be configured as the
receive pin (RXD) of serial communication interface 5 (SCI5).
1.2.3.27
PH5 / KWH5 / MOSI2 / TXD4 — Port H I/O Pin 5
PH5 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the
serial peripheral interface 2 (SPI2). It can be configured as the transmit pin TXD of serial communication
interface 4 (SCI4).
1.2.3.28
PH4 / KWH4 / MISO2 / RXD4 — Port H I/O Pin 4
PH4 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as master input (during master mode) or slave output (during slave mode) pin MISO of the
serial peripheral interface 2 (SPI2). It can be configured as the receive pin RXD of serial communication
interface 4 (SCI4).
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1.2.3.29
PH3 / KWH3 / SS1 — Port H I/O Pin 3
PH3 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as slave select pin SS of the serial peripheral interface 1 (SPI1). It can also be configured as the
transmit pin TXD of serial communication interface 7 (SCI7).
1.2.3.30
PH2 / KWH2 / SCK1 — Port H I/O Pin 2
PH2 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as serial clock pin SCK of the serial peripheral interface 1 (SPI1). It can be configured as the
receive pin RXD of serial communication interface 7 (SCI7).
1.2.3.31
PH1 / KWH1 / MOSI1 — Port H I/O Pin 1
PH1 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the
serial peripheral interface 1 (SPI1). It can also be configured as the transmit pin TXD of serial
communication interface 6 (SCI6).
1.2.3.32
PH0 / KWH0 / MISO1 — Port H I/O Pin 0
PH0 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as master input (during master mode) or slave output (during slave mode) pin MISO of the
serial peripheral interface 1 (SPI1). It can be configured as the receive pin RXD of serial communication
interface 6 (SCI6).
1.2.3.33
PJ7 / KWJ7 / TXCAN4 / SCL0 / TXCAN0— PORT J I/O Pin 7
PJ7 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as the transmit pin TXCAN for the scalable controller area network controller 0 or 4 (CAN0 or
CAN4) or as the serial clock pin SCL of the IIC0 module.
1.2.3.34
PJ6 / KWJ6 / RXCAN4 / SDA0 / RXCAN0 — PORT J I/O Pin 6
PJ6 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as the receive pin RXCAN for the scalable controller area network controller 0 or 4 (CAN0 or
CAN4) or as the serial data pin SDA of the IIC0 module.
1.2.3.35
PJ5 / KWJ5 / SCL1 / CS2 — PORT J I/O Pin 5
PJ5 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as the serial clock pin SCL of the IIC1 module. It can be also configured as chip-select output 2.
1.2.3.36
PJ4 / KWJ4 / SDA1 / CS0 — PORT J I/O Pin 4
PJ4 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as the serial data pin SDA of the IIC1 module. It can also be configured as chip-select output.
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1.2.3.37
PJ3 / KWJ3 — PORT J I/O Pin 3
PJ2 is a general-purpose input or output pins. It can be configured as a keypad wakeup input.
1.2.3.38
PJ2 / KWJ2 / CS1 — PORT J I/O Pin 2
PJ2 is a general-purpose input or output pins. It can be configured as a keypad wakeup input. It can also
be configured as chip-select output.
1.2.3.39
PJ1 / KWJ1 / TXD2 — PORT J I/O Pin 1
PJ1 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as the transmit pin TXD of the serial communication interface 2 (SCI2).
1.2.3.40
PJ0 / KWJ0 / RXD2 / CS3 — PORT J I/O Pin 0
PJ0 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as the receive pin RXD of the serial communication interface 2 (SCI2).It can also be configured
as chip-select output 3.
1.2.3.41
PK7 / EWAIT / ROMCTL — Port K I/O Pin 7
PK7 is a general-purpose input or output pin. During MCU emulation modes and normal expanded modes
of operation, this pin is used to enable the Flash EEPROM memory in the memory map (ROMCTL). At
the rising edge of RESET, the state of this pin is latched to the ROMON bit. The EWAIT input signal
maintains the external bus access until the external device is ready to capture data (write) or provide data
(read).
The input voltage threshold for PK7 can be configured to reduced levels, to allow data from an external
3.3-V peripheral to be read by the MCU operating at 5.0 V.
1.2.3.42
PK[6:4] / ADDR[22:20] / ACC[2:0] — Port K I/O Pin [6:4]
PK[6:4] are general-purpose input or output pins. During MCU expanded modes of operation, the
ACC[2:0] signals are used to indicate the access source of the bus cycle. This pins also provide the
expanded addresses ADDR[22:20] for the external bus. In Emulation modes ACC[2:0] is available and is
time multiplexed with the high addresses
1.2.3.43
PK[3:0] / ADDR[19:16] / IQSTAT[3:0] — Port K I/O Pins [3:0]
PK3-PK0 are general-purpose input or output pins. In MCU expanded modes of operation, these pins
provide the expanded address ADDR[19:16] for the external bus and carry instruction pipe information.
1.2.3.44
PL7 / TXD7 — Port L I/O Pin 7
PL7 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 7 (SCI7).
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1.2.3.45
PL6 / RXD7 — Port L I/O Pin 6
PL6 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 7 (SCI7).
1.2.3.46
PL5 / TXD6 — Port L I/O Pin 5
PL5 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 6 (SCI6).
1.2.3.47
PL4 / RXD6 — Port L I/O Pin 4
PL4 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 6 (SCI6).
1.2.3.48
PL3 / TXD5 — Port L I/O Pin 3
PL3 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 5 (SCI5).
1.2.3.49
PL2 / RXD5 — Port L I/O Pin 2
PL2 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 5 (SCI5).
1.2.3.50
PL1 / TXD4 — Port L I/O Pin 1
PL1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 4 (SCI4).
1.2.3.51
PL0 / RXD4 — Port L I/O Pin 0
PL0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 4 (SCI4).
1.2.3.52
PM7 / TXCAN3 / TXCAN4 / TXD3 — Port M I/O Pin 7
PM7 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the
scalable controller area network controller 3 or 4 (CAN3 or CAN4). PM7 can be configured as the transmit
pin TXD3 of the serial communication interface 3 (SCI3).
1.2.3.53
PM6 / RXCAN3 / RXCAN4 / RXD3 — Port M I/O Pin 6
PM6 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the
scalable controller area network controller 3 or 4 (CAN3 or CAN4). PM6 can be configured as the receive
pin RXD3 of the serial communication interface 3 (SCI3).
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1.2.3.54
PM5 / TXCAN0 / TXCAN2 / TXCAN4 / SCK0 — Port M I/O Pin 5
PM5 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the
scalable controller area network controllers 0, 2 or 4 (CAN0, CAN2, or CAN4). It can be configured as
the serial clock pin SCK of the serial peripheral interface 0 (SPI0).
1.2.3.55
PM4 / RXCAN0 / RXCAN2 / RXCAN4 / MOSI0 — Port M I/O Pin 4
PM4 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the
scalable controller area network controllers 0, 2, or 4 (CAN0, CAN2, or CAN4). It can be configured as
the master output (during master mode) or slave input pin (during slave mode) MOSI for the serial
peripheral interface 0 (SPI0).
1.2.3.56
PM3 / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3
PM3 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the
scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the slave
select pin SS of the serial peripheral interface 0 (SPI0).
1.2.3.57
PM2 / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2
PM2 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the
scalable controller area network controllers 1 or 0 (CAN1 or CAN0). It can be configured as the master
input (during master mode) or slave output pin (during slave mode) MISO for the serial peripheral
interface 0 (SPI0).
1.2.3.58
PM1 / TXCAN0 — Port M I/O Pin 1
PM1 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the
scalable controller area network controller 0 (CAN0).
1.2.3.59
PM0 / RXCAN0 — Port M I/O Pin 0
PM0 is a general-purpose input or output pin. It can be configured as the receive pin RXCAN of the
scalable controller area network controller 0 (CAN0).
1.2.3.60
PP7 / KWP7 / PWM7 / SCK2 / TIMIOC7— Port P I/O Pin 7
PP7 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 7 output, TIM channel 7, or as serial clock pin SCK
of the serial peripheral interface 2 (SPI2).
1.2.3.61
PP6 / KWP6 / PWM6 / SS2 / TIMIOC6— Port P I/O Pin 6
PP6 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 6 output, TIM channel 6 or as the slave select pin SS
of the serial peripheral interface 2 (SPI2).
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1.2.3.62
PP5 / KWP5 / PWM5 / MOSI2 / TIMIOC5— Port P I/O Pin 5
PP5 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 5 output, TIM channel 5 or as the master output
(during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 2
(SPI2).
1.2.3.63
PP4 / KWP4 / PWM4 / MISO2 / TIMIOC4— Port P I/O Pin 4
PP4 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 4 output, TIM channel 4 or as the master input
(during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 2
(SPI2).
1.2.3.64
PP3 / KWP3 / PWM3 / SS1 / TIMIOC3— Port P I/O Pin 3
PP3 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 3 output, TIM channel 3, or as the slave select pin
SS of the serial peripheral interface 1 (SPI1).
1.2.3.65
PP2 / KWP2 / PWM2 / SCK1 / TIMIOC2— Port P I/O Pin 2
PP2 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 2 output, TIM channel 2, or as the serial clock pin
SCK of the serial peripheral interface 1 (SPI1).
1.2.3.66
PP1 / KWP1 / PWM1 / MOSI1 / TIMIOC1— Port P I/O Pin 1
PP1 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 1 output, TIM channel 1, or master output (during
master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1).
1.2.3.67
PP0 / KWP0 / PWM0 / MISO1 / TIMIOC0— Port P I/O Pin 0
PP0 is a general-purpose input or output pin. It can be configured as a keypad wakeup input. It can be
configured as pulse width modulator (PWM) channel 0 output, TIM channel 0 or as the master input
(during master mode) or slave output (during slave mode) pin MISO of the serial peripheral interface 1
(SPI1).
1.2.3.68
PR[7:0] / TIMIOC[7:0] — Port R I/O Pins [7:0]
PR[7:0] are general-purpose input or output pins. They can be configured as input capture or output
compare pins IOC[7:0] of the standard timer (TIM).
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1.2.3.69
PS7 / SS0 — Port S I/O Pin 7
PS7 is a general-purpose input or output pin. It can be configured as the slave select pin SS of the serial
peripheral interface 0 (SPI0).
1.2.3.70
PS6 / SCK0 — Port S I/O Pin 6
PS6 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial
peripheral interface 0 (SPI0).
1.2.3.71
PS5 / MOSI0 — Port S I/O Pin 5
PS5 is a general-purpose input or output pin. It can be configured as master output (during master mode)
or slave input pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).
1.2.3.72
PS4 / MISO0 — Port S I/O Pin 4
PS4 is a general-purpose input or output pin. It can be configured as master input (during master mode) or
slave output pin (during slave mode) MOSI of the serial peripheral interface 0 (SPI0).
1.2.3.73
PS3 / TXD1 — Port S I/O Pin 3
PS3 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 1 (SCI1).
1.2.3.74
PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 1 (SCI1).
1.2.3.75
PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general-purpose input or output pin. It can be configured as the transmit pin TXD of serial
communication interface 0 (SCI0).
1.2.3.76
PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general-purpose input or output pin. It can be configured as the receive pin RXD of serial
communication interface 0 (SCI0).
1.2.3.77
PT[7:6] / IOC[7:6] — Port T I/O Pins [7:6]
PT[7:6] are general-purpose input or output pins. They can be configured as input capture or output
compare pins IOC[7:6] of the enhanced capture timer (ECT).
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1.2.3.78
PT[5] / IOC[5] / VREG_API— Port T I/O Pins [5]
PT[5] is a general-purpose input or output pin. It can be configured as input capture or output compare pin
IOC[5] of the enhanced capture timer (ECT) or can be configured to output the VREG_API signal.
1.2.3.79
PT[4:0] / IOC[4:0] — Port T I/O Pins [4:0]
PT[4:0] are general-purpose input or output pins. They can be configured as input capture or output
compare pins IOC[4:0] of the enhanced capture timer (ECT).
1.2.4
Power Supply Pins
MC9S12XE-Family power and ground pins are described below.
Because fast signal transitions place high, short-duration current demands on the power supply, use bypass
capacitors with high-frequency characteristics and place them as close to the MCU as possible.
NOTE
All VSS pins must be connected together in the application.
1.2.4.1
VDDX[7:1], VSSX[7:1] — Power and Ground Pins for I/O Drivers
External power and ground for I/O drivers. Bypass requirements depend on how heavily the MCU pins are
loaded. All VDDX pins are connected together internally. All VSSX pins are connected together internally.
1.2.4.2
VDDR — Power Pin for Internal Voltage Regulator
Input to the internal voltage regulator. The internal voltage regulator is turned off, if VDDR is tied to ground
1.2.4.3
VDD, VSS1,VSS2,VSS3 — Core Power Pins
Power is supplied to the MCU core from the internal voltage regulator, whose load capacitor must be
connected to VDD. The voltage supply of nominally 1.8V is derived from the internal voltage regulator.
The return current path is through the VSS1,VSS2 and VSS3 pins. No static external loading of these pins
is permitted.
1.2.4.4
VDDF — NVM Power Pin
Power is supplied to the MCU NVM through VDDF . The voltage supply of nominally 2.8V is derived
from the internal voltage regulator. No static external loading of these pins is permitted.
1.2.4.5
VDDA2, VDDA1, VSSA2, VSSA1 — Power Supply Pins for ATD and
Voltage Regulator
These are the power supply and ground input pins for the analog-to-digital converters and the voltage
regulator. Internally the VDDA pins are connected together. Internally the VSSA pins are connected
together.
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1.2.4.6
VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog-to-digital converter.
1.2.4.7
VDDPLL, VSSPL — Power Supply Pins for PLL
These pins provide operating voltage and ground for the oscillator and the phased-locked loop. The voltage
supply of nominally 1.8V is derived from the internal voltage regulator. This allows the supply voltage to
the oscillator and PLL to be bypassed independently. This voltage is generated by the internal voltage
regulator. No static external loading of these pins is permitted.
Table 1-11. Power and Ground Connection Summary
Mnemonic
Nominal
Voltage
VDDR
5.0 V
External power supply to internal voltage
regulator
VDDX[7:1]
5.0 V
VSSX[7:1]
0V
External power and ground, supply to pin
drivers
VDDA2,
VDDA1
5.0 V
VSSA2,
VSSA1
0V
VRL
0V
VRH
5.0 V
VDD
1.8 V
VSS1, VSS2,
VSS3
0V
VDDF
2.8 V
Internal power and ground generated by
internal regulator for the internal NVM.
VDDPLL
1.8 V
VSSPLL
0V
Provides operating voltage and ground for
the phased-locked loop. This allows the
supply voltage to the PLL to be bypassed
independently. Internal power and ground
generated by internal regulator.
Description
Operating voltage and ground for the
analog-to-digital converters and the
reference for the internal voltage regulator,
allows the supply voltage to the A/D to be
bypassed independently.
Reference voltages for the analog-to-digital
converter.
Internal power and ground generated by
internal regulator for the internal core.
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1.3
System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 1-8 shows the clock connections from the CRG to all modules.
Consult the CRG specification for details on clock generation.
SCI0 . . SCI 7
CAN0 . . CAN4
SPI0 . . SPI2
IIC0 & IIC1
ATD0 & ATD1
Bus Clock
PIT
EXTAL
Oscillator Clock
ECT
CRG
PIM
XTAL
Core Clock
PWM
RAM
S12X
XGATE
FLASH &
EEE
TIM
Figure 1-8. Clock Connections
The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:
• The on-chip phase locked loop (PLL)
• the PLL self clocking
• the oscillator
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-8, these system clocks are used throughout the MCU to drive the core,
the memories, and the peripherals.
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The program Flash memory and the EEPROM are supplied by the bus clock and the oscillator clock. The
oscillator clock is used as a time base to derive the program and erase times for the NVM’s.
The CAN modules may be configured to have their clock sources derived either from the bus clock or
directly from the oscillator clock. This allows the user to select its clock based on the required jitter
performance.
In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the
output of the oscillator. The clock monitor can be configured to invoke the PLL self-clocking mode or to
generate a system reset if it is allowed to time out as a result of no oscillator clock being present.
In addition to the clock monitor, the MCU also provides a clock quality checker which performs a more
accurate check of the clock. The clock quality checker counts a predetermined number of clock edges
within a defined time window to insure that the clock is running. The checker can be invoked following
specific events such as on wake-up or clock monitor failure.
1.4
Modes of Operation
The MCU can operate in different modes associated with MCU resource mapping and bus interface
configuration. These are described in 1.4.1 Chip Configuration Summary.
The MCU can operate in different power modes to facilitate power saving when full system performance
is not required. These are described in 1.4.2 Power Modes.
Some modules feature a software programmable option to freeze the module status whilst the background
debug module is active to facilitate debugging. This is described in 1.4.3 Freeze Mode.
For system integrity support separate system states are featured as explained in 1.4.4 System States.
1.4.1
Chip Configuration Summary
The MCU can operate in six different modes associated with resource configuration. The different modes,
the state of ROMCTL and EROMCTL signal on rising edge of RESET and the security state of the MCU
affect the following device characteristics:
• External bus interface configuration
• Flash in memory map, or not
• Debug features enabled or disabled
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA signals
during reset (see Table 1-12). The MODC, MODB, and MODA bits in the MODE register show the current
operating mode and provide limited mode switching during operation. The states of the MODC, MODB,
and MODA signals are latched into these bits on the rising edge of RESET.
In normal expanded mode and in emulation modes the ROMON bit and the EROMON bit in the
MMCCTL1 register defines if the on chip flash memory is the memory map, or not. (See Table 1-12.) For
a detailed explanation of the ROMON and EROMON bits refer to the MMC description.
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The state of the ROMCTL signal is latched into the ROMON bit in the MMCCTL1 register on the rising
edge of RESET. The state of the EROMCTL signal is latched into the EROMON bit in the MMCCTL1
register on the rising edge of RESET.
Table 1-12. Chip Modes and Data Sources
Chip Modes
Data Source1
MODC
MODB
MODA
ROMCTL
EROMCTL
Normal single chip
1
0
0
X
X
Internal
Special single chip
0
0
0
Emulation single chip
0
0
1
X
0
Emulation memory
X
1
Internal Flash
Normal expanded
Emulation expanded
Special test
1
1
0
0
0
1
1
1
1
0
0
X
External application
1
X
Internal Flash
0
X
External application
1
0
Emulation memory
1
1
Internal Flash
0
X
External application
1
X
Internal Flash
Internal means resources inside the MCU are read/written.
Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, Flash replacement, RAM, EEPROM,
and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
1.4.1.1
Normal Expanded Mode
Ports K, A, and B are configured as a 23-bit address bus, ports C and D are configured as a 16-bit data bus,
and port E provides bus control and status signals. This mode allows 16-bit external memory and
peripheral devices to be interfaced to the system. The fastest external bus rate is divide by 2 from the
internal bus rate.
1.4.1.2
Normal Single-Chip Mode
There is no external bus in this mode. The processor program is executed from internal memory. Ports A,
B,C,D, K, and most pins of port E are available as general-purpose I/O.
1.4.1.3
Special Single-Chip Mode
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin. There is
no external bus after reset in this mode.
1.4.1.4
Emulation of Expanded Mode
Developers use this mode for emulation systems in which the users target application is normal expanded
mode. Code is executed from external memory or from internal memory depending on the state of
ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
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1.4.1.5
Emulation of Single-Chip Mode
Developers use this mode for emulation systems in which the user’s target application is normal
single-chip mode. Code is executed from external memory or from internal memory depending on the state
of ROMON and EROMON bit. In this mode the internal operation is visible on external bus interface.
1.4.1.6
Special Test Mode
Freescale internal use only.
1.4.2
Power Modes
The MCU features two main low-power modes. Consult the respective module description for module
specific behavior in system stop, system pseudo stop, and system wait mode. An important source of
information about the clock system is the Clock and Reset Generator description (CRG).
1.4.2.1
System Stop Modes
The system stop modes are entered if the CPU executes the STOP instruction unless either the XGATE is
active or an NVM command is active. The XGATE is active if it executes a thread or the XGFACT bit in
the XGMCTL register is set. Depending on the state of the PSTP bit in the CLKSEL register the MCU
goes into pseudo stop mode or full stop mode. Please refer to CRG description. Asserting RESET, XIRQ,
IRQ or any other interrupt that is not masked exits system stop modes. System stop modes can be exited
by XGATE or CPU activity independently, depending on the configuration of the interrupt request. If
System-Stop is exited on an XGATE request then, as long as the XGATE does not set an interrupt flag on
the CPU and the XGATE fake activity bit (FACT) remains cleared, once XGATE activity is completed
System Stop mode will automatically be re-entered.
If the CPU executes the STOP instruction whilst XGATE is active or an NVM command is being
processed, then the system clocks continue running until XGATE/NVM activity is completed. If a
non-masked interrupt occurs within this time then the system does not effectively enter stop mode although
the STOP instruction has been executed.
1.4.2.2
Full Stop Mode
The oscillator is stopped in this mode. By default all clocks are switched off and all counters and dividers
remain frozen. The Autonomous Periodic Interrupt (API) and ATD modules may be enabled to self wake
the device. A Fast wake up mode is available to allow the device to wake from Full Stop mode immediately
on the PLL internal clock without starting the oscillator clock.
1.4.2.3
Pseudo Stop Mode
In this mode the system clocks are stopped but the oscillator is still running and the real time interrupt
(RTI) and watchdog (COP), API and ATD modules may be enabled. Other peripherals are turned off. This
mode consumes more current than system stop mode but, as the oscillator continues to run, the full speed
wake up time from this mode is significantly shorter.
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1.4.2.4
XGATE Fake Activity Mode
This mode is entered if the CPU executes the STOP instruction when the XGATE is not executing a thread
and the XGFACT bit in the XGMCTL register is set. The oscillator remains active and any enabled
peripherals continue to function.
1.4.2.5
Wait Mode
This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute
instructions. The internal CPU clock is switched off. All peripherals and the XGATE can be active in
system wait mode. For further power consumption the peripherals can individually turn off their local
clocks. Asserting RESET, XIRQ, IRQ or any other interrupt that is not masked and is not routed to XGATE
ends system wait mode.
1.4.2.6
Run Mode
Although this is not a low-power mode, unused peripheral modules should not be enabled in order to save
power.
1.4.3
Freeze Mode
The enhanced capture timer, pulse width modulator, analog-to-digital converters, and the periodic interrupt
timer provide a software programmable option to freeze the module status when the background debug
module is active. This is useful when debugging application software. For detailed description of the
behavior of the ATD0, ATD1, ECT, PWM, and PIT when the background debug module is active consult
the corresponding Block Guides.
1.4.4
System States
To facilitate system integrity the MCU can run in Supervisor state or User state. The System States strategy
is implemented by additional features on the S12X CPU and a Memory Protection Unit. This is designed
to support restricted access for code modules executed by kernels or operating systems supporting access
control to system resources.
The current system state is indicated by the U bit in the CPU condition code register. In User state certain
CPU instructions are restricted. See the CPU reference guide for details of the U bit and of those
instructions affected by User state.
In the case that software task accesses resources outside those defined for it in the MPU a non-maskable
interrupt is generated.
1.4.4.1
Supervisor State
This state is intended for configuring the MPU for different tasks that are then executed in User state,
returning to Supervisor state on completion of each task. This is the default ’state’ following reset and can
be re-entered from User state by an exception (interrupt). If the SVSEN bit in the MPUSEL register of the
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MPU is set, access to system resources is only allowed if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.4.4.2
User State
This state is intended for carrying out system tasks and is entered by setting the U bit of the condition codes
register while in Supervisor state. Restrictions apply for the execution of several CPU instructions in User
state and access to system resources is only allowed in if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.5
Security
The MCU security feature allows the protection of the on chip Flash and emulated EEPROM memory. For
a detailed description of the security features refer to the S12X9SEC description.
1.6
Resets and Interrupts
Consult the S12XCPU manual and the S12XINT description for information on exception processing.
1.6.1
Resets
Resets are explained in detail in the Clock Reset Generator (CRG) description.
1.6.2
Vectors
Table 1-13 lists all interrupt sources and vectors in the default order of priority. The interrupt module
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
I-bit maskable service request is a configuration register. It selects if the service request is enabled, the
service request priority level and whether the service request is handled either by the S12X CPU or by the
XGATE module.
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Table 1-13. Interrupt Vector Locations (Sheet 1 of 4)
Vector Address1
XGATE
Channel ID2
Interrupt Source
CCR
Mask
Local Enable
$FFFE
—
System reset or illegal access reset
None
None
$FFFC
—
Clock monitor reset
None
PLLCTL (CME, SCME)
$FFFA
—
COP watchdog reset
None
COP rate select
Vector base + $F8
—
Unimplemented instruction trap
None
None
Vector base+ $F6
—
SWI
None
None
Vector base+ $F4
—
XIRQ
X Bit
None
Vector base+ $F2
—
IRQ
I bit
IRQCR (IRQEN)
Vector base+ $F0
$78
Real time interrupt
I bit
CRGINT (RTIE)
Vector base+ $EE
$77
Enhanced capture timer channel 0
I bit
TIE (C0I)
Vector base + $EC
$76
Enhanced capture timer channel 1
I bit
TIE (C1I)
Vector base+ $EA
$75
Enhanced capture timer channel 2
I bit
TIE (C2I)
Vector base+ $E8
$74
Enhanced capture timer channel 3
I bit
TIE (C3I)
Vector base+ $E6
$73
Enhanced capture timer channel 4
I bit
TIE (C4I)
Vector base+ $E4
$72
Enhanced capture timer channel 5
I bit
TIE (C5I)
Vector base + $E2
$71
Enhanced capture timer channel 6
I bit
TIE (C6I)
Vector base+ $E0
$70
Enhanced capture timer channel 7
I bit
TIE (C7I)
Vector base+ $DE
$6F
Enhanced capture timer overflow
I bit
TSRC2 (TOF)
Vector base+ $DC
$6E
Pulse accumulator A overflow
I bit
PACTL (PAOVI)
Vector base + $DA
$6D
Pulse accumulator input edge
I bit
PACTL (PAI)
Vector base + $D8
$6C
SPI0
I bit
SPI0CR1 (SPIE, SPTIE)
Vector base+ $D6
$6B
SCI0
I bit
SCI0CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $D4
$6A
SCI1
I bit
SCI1CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $D2
$69
ATD0
I bit
ATD0CTL2 (ASCIE)
Vector base + $D0
$68
ATD1
I bit
ATD1CTL2 (ASCIE)
Vector base + $CE
$67
Port J
I bit
PIEJ (PIEJ7-PIEJ0)
Vector base + $CC
$66
Port H
I bit
PIEH (PIEH7-PIEH0)
Vector base + $CA
$65
Modulus down counter underflow
I bit
MCCTL(MCZI)
Vector base + $C8
$64
Pulse accumulator B overflow
I bit
PBCTL(PBOVI)
Vector base + $C6
$63
CRG PLL lock
I bit
CRGINT(LOCKIE)
Vector base + $C4
$62
CRG self-clock mode
I bit
CRGINT (SCMIE)
Vector base + $C2
$61
SCI6
I bit
SCI6CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $C0
$60
IIC0 bus
I bit
IBCR0 (IBIE)
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Table 1-13. Interrupt Vector Locations (Sheet 2 of 4)
Vector Address1
XGATE
Channel ID2
Interrupt Source
CCR
Mask
Local Enable
Vector base + $BE
$5F
SPI1
I bit
SPI1CR1 (SPIE, SPTIE)
Vector base + $BC
$5E
SPI2
I bit
SPI2CR1 (SPIE, SPTIE)
Vector base + $BA
$5D
FLASH Fault Detect
I bit
FCNFG2 (FDIE)
Vector base + $B8
$5C
FLASH
I bit
FCNFG (CCIE, CBEIE)
Vector base + $B6
$5B
CAN0 wake-up
I bit
CAN0RIER (WUPIE)
Vector base + $B4
$5A
CAN0 errors
I bit
CAN0RIER (CSCIE, OVRIE)
Vector base + $B2
$59
CAN0 receive
I bit
CAN0RIER (RXFIE)
Vector base + $B0
$58
CAN0 transmit
I bit
CAN0TIER (TXEIE[2:0])
Vector base + $AE
$57
CAN1 wake-up
I bit
CAN1RIER (WUPIE)
Vector base + $AC
$56
CAN1 errors
I bit
CAN1RIER (CSCIE, OVRIE)
Vector base + $AA
$55
CAN1 receive
I bit
CAN1RIER (RXFIE)
Vector base + $A8
$54
CAN1 transmit
I bit
CAN1TIER (TXEIE[2:0])
Vector base + $A6
$53
CAN2 wake-up
I bit
CAN2RIER (WUPIE)
Vector base + $A4
$52
CAN2 errors
I bit
CAN2RIER (CSCIE, OVRIE)
Vector base + $A2
$51
CAN2 receive
I bit
CAN2RIER (RXFIE)
Vector base + $A0
$50
CAN2 transmit
I bit
CAN2TIER (TXEIE[2:0])
Vector base + $9E
$4F
CAN3 wake-up
I bit
CAN3RIER (WUPIE)
Vector base+ $9C
$4E
CAN3 errors
I bit
CAN3RIER (CSCIE, OVRIE)
Vector base+ $9A
$4D
CAN3 receive
I bit
CAN3RIER (RXFIE)
Vector base + $98
$4C
CAN3 transmit
I bit
CAN3TIER (TXEIE[2:0])
Vector base + $96
$4B
CAN4 wake-up
I bit
CAN4RIER (WUPIE)
Vector base + $94
$4A
CAN4 errors
I bit
CAN4RIER (CSCIE, OVRIE)
Vector base + $92
$49
CAN4 receive
I bit
CAN4RIER (RXFIE)
Vector base + $90
$48
CAN4 transmit
I bit
CAN4TIER (TXEIE[2:0])
Vector base + $8E
$47
Port P Interrupt
I bit
PIEP (PIEP7-PIEP0)
Vector base+ $8C
$46
PWM emergency shutdown
I bit
PWMSDN (PWMIE)
Vector base + $8A
$45
SCI2
I bit
SCI2CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $88
$44
SCI3
I bit
SCI3CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $86
$43
SCI4
I bit
SCI4CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $84
$42
SCI5
I bit
SCI5CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $82
$41
IIC1 Bus
I bit
IBCR (IBIE)
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Table 1-13. Interrupt Vector Locations (Sheet 3 of 4)
Vector Address1
XGATE
Channel ID2
Interrupt Source
CCR
Mask
Local Enable
Vector base + $80
$40
Low-voltage interrupt (LVI)
I bit
VREGCTRL (LVIE)
Vector base + $7E
$3F
Autonomous periodical interrupt (API)
I bit
VREGAPICTRL (APIE)
Vector base + $7C
Reserved
Vector base + $7A
$3D
Periodic interrupt timer channel 0
I bit
PITINTE (PINTE0)
Vector base + $78
$3C
Periodic interrupt timer channel 1
I bit
PITINTE (PINTE1)
Vector base + $76
$3B
Periodic interrupt timer channel 2
I bit
PITINTE (PINTE2)
Vector base + $74
$3A
Periodic interrupt timer channel 3
I bit
PITINTE (PINTE3)
Vector base + $72
$39
XGATE software trigger 0
I bit
XGMCTL (XGIE)
Vector base + $70
$38
XGATE software trigger 1
I bit
XGMCTL (XGIE)
Vector base + $6E
$37
XGATE software trigger 2
I bit
XGMCTL (XGIE)
Vector base + $6C
$36
XGATE software trigger 3
I bit
XGMCTL (XGIE)
Vector base + $6A
$35
XGATE software trigger 4
I bit
XGMCTL (XGIE)
Vector base + $68
$34
XGATE software trigger 5
I bit
XGMCTL (XGIE)
Vector base + $66
$33
XGATE software trigger 6
I bit
XGMCTL (XGIE)
Vector base + $64
$32
XGATE software trigger 7
I bit
XGMCTL (XGIE)
Vector base + $62
Reserved
Vector base + $60
Reserved
Vector base + $5E
$2F
Periodic interrupt timer channel 4
I bit
PITINTE (PINTE4)
Vector base + $5C
$2E
Periodic interrupt timer channel 5
I bit
PITINTE (PINTE5)
Vector base + $5A
$2D
Periodic interrupt timer channel 6
I bit
PITINTE (PINTE6)
Vector base + $58
$2C
Periodic interrupt timer channel 7
I bit
PITINTE (PINTE7)
Vector base + $56
$2B
SCI7
I bit
SCI7CR2
(TIE, TCIE, RIE, ILIE)
Vector base + $54
$2A
TIM timer channel 0
I bit
TIE (C0I)
Vector base + $52
$29
TIM timer channel 1
I bit
TIE (C1I)
Vector base + $50
$28
TIM timer channel 2
I bit
TIE (C2I)
Vector base+ $4E
$27
TIM timer channel 3
I bit
TIE (C3I)
Vector base + $4C
$26
TIM timer channel 4
I bit
TIE (C4I)
Vector base+ $4A
$25
TIM timer channel 5
I bit
TIE (C5I)
Vector base+ $48
$24
TIM timer channel 6
I bit
TIE (C6I)
Vector base+ $46
$23
TIM timer channel 7
I bit
TIE (C7I)
Vector base+ $44
$22
TIM timer overflow
I bit
TSRC2 (TOF)
Vector base + $42
$21
TIM Pulse accumulator A overflow
I bit
PACTL (PAOVI)
Vector base+ $40
$20
TIM Pulse accumulator input edge
I bit
PACTL (PAI)
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Table 1-13. Interrupt Vector Locations (Sheet 4 of 4)
Vector Address1
XGATE
Channel ID2
Interrupt Source
CCR
Mask
Local Enable
Vector base + $3E
$1F
ATD0 Compare Interrupt
I bit
ATD0CTL2 (ACMPIE)
Vector base + $3C
$1E
ATD1 Compare Interrupt
I bit
ATD1CTL2 (ACMPIE)
Vector base+ $18
to
Vector base + $3A
1
2
Reserved
Vector base + $16
—
XGATE software error interrupt
None
None
Vector base + $14
—
MPU Access Error
None
None
Vector base + $12
—
System Call Interrupt (SYS)
—
None
Vector base + $10
—
Spurious interrupt
—
None
16 bits vector address based
For detailed description of XGATE channel ID refer to XGATE Block Guide
1.6.3
Effects of Reset
When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block
descriptions for register reset states.
On each reset, the Flash module executes a reset sequence to load Flash configuration registers and
initialize the buffer RAM EEE partition, if required.
1.6.3.1
Flash Configuration Reset Sequence Phase
On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section.
1.6.3.2
EEE Reset Sequence Phase
During the reset phase the EEE buffer array is loaded with valid data from the D-Flash EEE partition. In
this reset phase CPU activity is held so device accesses to the EEE before the Flash memory controller
reset is completed are stalled.
If configured for EEE operation (ERPART > 0), all valid EEE records from the D-Flash EEE partition will
be copied to the buffer RAM EEE partition.
1.6.3.3
Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.4
I/O Pins
Refer to the PIM block description for reset configurations of all peripheral module ports.
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1.6.3.5
Memory
The RAM arrays are not initialized out of reset.
1.6.3.6
COP Configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash register FOPT. See Table 1-14 and Table 1-15 for coding. The FOPT register is
loaded from the Flash configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP
reset.
Table 1-14. Initial COP Rate Configuration
NV[2:0] in
FCTL Register
CR[2:0] in
COPCTL Register
000
111
001
110
010
101
011
100
100
011
101
010
110
001
111
000
Table 1-15. Initial WCOP Configuration
1.7
NV[3] in
FCTL Register
WCOP in
COPCTL Register
1
0
0
1
ATD0 External Trigger Input Connection
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The
external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-16
shows the connection of the external trigger inputs.
Table 1-16. ATD0 External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
Pulse width modulator channel 1
ETRIG1
Pulse width modulator channel 3
ETRIG2
Periodic interrupt timer hardware trigger 0
ETRIG3
Periodic interrupt timer hardware trigger 1
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Consult the ATD block description for information about the analog-to-digital converter module. ATD
block description refererences to freeze mode are equivalent to active BDM mode.
1.8
ATD1 External Trigger Input Connection
The ATD module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG2, and ETRIG3. The
external trigger feature allows the user to synchronize ATD conversion to external trigger events.
Table 1-17 shows the connection of the external trigger inputs.
Table 1-17. ATD1 External Trigger Sources
External Trigger
Input
Connectivity
ETRIG0
Pulse width modulator channel 1
ETRIG1
Pulse width modulator channel 3
ETRIG2
Periodic interrupt timer hardware trigger 0
ETRIG3
Periodic interrupt timer hardware trigger 1
Consult the ATD block description for information about the analog-to-digital converter module. ATD
block description refererences to freeze mode are equivalent to active BDM mode.
1.9
MPU Configuration
The MPU has the option of a third bus master (CPU + XGATE + other) which is not present on this device
family but may be on other parts.
1.10
VREG Configuration
The VREGEN connection of the voltage regulator is tied internally to VDDR such that the voltage
regulator is always enabled with VDDR connected to a positive supply voltage. The device must be
configured with the internal voltage regulator enabled. Operation in conjunction with an external voltage
regulator is not supported.
The internal bandgap reference voltage is mapped to ATD0 analog input channel 17.
The autonomus periodic interrupt clock output is mapped to PortT[5].
The API trimming register APITR is loaded on rising edge of RESET from the Flash IFR option field at
global address 0x40_00F0 bits[5:0] during the reset sequence. Currently factory programming of this IFR
range is not supported.
Read access to reserved VREG register space returns “0”. Wtite accesses have no effect. This device does
not support access abort of reserved VREG register space.
1.11
S12XEPIM Configuration
On smaller derivatives the S12XEPIM module is a subset of the XEP100. The registers of the unavailable
ports are unimplemented.
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1.12
Oscillator Configuration
The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used. For this device XCLKS is mapped to PE7.
The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:
• Power on reset or low-voltage reset
• Clock monitor reset
• Any reset while in self-clock mode or full stop mode
The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above
described reset cases.
EXTAL
C1
MCU
Crystal or
Ceramic Resonator
XTAL
C2
VSSPLL
Figure 1-9. Loop Controlled Pierce Oscillator Connections (XCLKS = 1)
EXTAL
C1
MCU
RB
RS
Crystal or
Ceramic Resonator
XTAL
C2
RB=1MΩ ; RS specified by crystal vendor
VSSPLL
Figure 1-10. Full Swing Pierce Oscillator Connections (XCLKS = 0)
EXTAL
CMOS-Compatible
External Oscillator
MCU
XTAL
Not Connected
Figure 1-11. External Clock Connections (XCLKS = 0)
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Chapter 2
Port Integration Module (S12XEPIMV1)
Revision History
Rev. No.
Date
(Item No.) (Submitted By)
Sections
Affected
V01.13
18 Jul 2006
2.3.5/2-103
2.3.17/2-112
V01.14
01 Aug 2006
2.3.1/2-93
V01.15
16 Apr 2007
2.3.69/2-149
2.3.70/2-149
2.3.77/2-153
2.3.78/2-154
2.4.3.12/2-179
2.4.3.13/2-179
2.1
2.1.1
Substantial Change(s)
Corrected DDRA address.
Removed ‘PRR’ from IRQCR register.
Revised PAD0 and PAD1 register bit names.
Corrected ATD pin mappings
Introduction
Overview
The S12XE Family Port Integration Module establishes the interface between the peripheral modules
including the non-multiplexed External Bus Interface module (S12X_EBI) and the I/O pins for all ports.
It controls the electrical pin properties as well as the signal prioritization and multiplexing on shared pins.
This document covers:
• Port A and B used as address output of the S12X_EBI
• Port C and D used as data I/O of the S12X_EBI
• Port E associated with the S12X_EBI control signals and the IRQ, XIRQ interrupt inputs
• Port K associated with address output and control signals of the S12X_EBI
• Port T associated with 1 ECT module
• Port S associated with 2 SCI and 1 SPI modules
• Port M associated with 4 MSCAN and 1 SCI module
• Port P connected to the PWM and 2 SPI modules - inputs can be used as an external interrupt source
• Port H associated with 4 SCI modules - inputs can be used as an external interrupt source
• Port J associated with 1 MSCAN, 1 SCI, 2 IIC modules and chip select outputs - inputs can be used
as an external interrupt source
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Chapter 2 Port Integration Module (S12XEPIMV1)
•
•
•
•
Port AD0 and AD1 associated with two 16-channel ATD modules
Port R associated with 1 stardard timer (TIM) module
Port L associated with 4 SCI modules
Port F associated with IIC, SCI and chip select outputs
Most I/O pins can be configured by register bits to select data direction and drive strength, to enable and
select pull-up or pull-down devices.
NOTE
This document assumes the availabitity of all features (208-pin package
option). Some functions are not available on lower pin count package
options. Refer to the pin-out summary in the SOC Guide.
2.1.2
Features
The Port Integration Module includes these distinctive registers:
• Data and data direction registers for Ports A, B, C, D, E, K, T, S, M, P, H, J, AD0, AD1, R, L, and
F when used as general-purpose I/O
• Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,
H, J, R, L, and F on per-pin basis
• Control registers to enable/disable pull-up devices on Ports AD0 and AD1 on per-pin basis
• Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis
and on BKGD pin
• Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, AD1, R, L,
and F on per-pin basis
• Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on
per-port basis
• Control registers to enable/disable open-drain (wired-or) mode on Ports S, M, and L
• Interrupt flag register for pin interrupts on Ports P, H, and J
• Control register to configure IRQ pin operation
• Free-running clock outputs
A standard port pin has the following minimum features:
• Input/output selection
• 5V output drive with two selectable drive strengths
• 5V digital and analog input
• Input with selectable pull-up or pull-down device
Optional features supported on dedicated pins:
•
Open drain for wired-or connections
•
Interrupt inputs with glitch filtering
•
Reduced input threshold to support low voltage applications
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2.2
External Signal Description
This section lists and describes the signals that do connect off-chip.
Table 2-1 shows all the pins and their functions that are controlled by the Port Integration Module. Refer
to the SOC Guide for the availability of the individual pins in the different package options.
NOTE
If there is more than one function associated with a pin, the priority is
indicated by the position in the table from top (highest priority) to bottom
(lowest priority).
Table 2-1. Pin Functions and Priorities
Port
Pin Name
Pin Function
& Priority1
I/O
-
BKGD
MODC 2
I
BKGD
A
PA[7:0]
ADDR[15:8]
mux
IVD[15:8] 3
GPIO
B
PB[7:1]
ADDR[7:1]
mux
IVD[7:1] 3
GPIO
PB[0]
C
PC[7:0]
PD[7:0]
MODC input during RESET
O
High-order external bus address output
(multiplexed with IVIS data)
O
Low-order external bus address output
(multiplexed with IVIS data)
UDS
O
Upper data strobe
GPIO
I/O General-purpose I/O
GPIO
Mode
dependent 4
Mode
dependent 4
I/O General-purpose I/O
Low-order external bus address output
(multiplexed with IVIS data)
DATA[7:0]
BKGD
I/O General-purpose I/O
O
DATA[15:8]
Pin Function
after Reset
I/O S12X_BDM communication pin
ADDR[0]
mux
IVD0 3
GPIO
D
Description
I/O High-order bidirectional data input/output
Configurable for reduced input threshold
Mode
dependent 4
I/O General-purpose I/O
I/O Low-order bidirectional data input/output
Configurable for reduced input threshold
Mode
dependent 4
I/O General-purpose I/O
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port
Pin Name
Pin Function
& Priority1
I/O
E
PE[7]
XCLKS 2
I
External clock selection input during RESET
ECLKX2
I
Free-running clock output at Core Clock rate (ECLK x 2)
GPIO
PE[6]
MODB
GPIO
PE[4]
PE[2]
Instruction tagging low pin
Configurable for reduced input threshold
I
MODA input during RESET
O
Read enable signal
TAGLO
I
Instruction tagging low pin
Configurable for reduced input threshold
GPIO
I/O General-purpose I/O
ECLK
O
Free-running clock output at the Bus Clock rate or programmable
divided in normal modes
I/O General-purpose I/O
2
I
EROMON bit control input during RESET
LSTRB
O
Low strobe bar output
LDS
O
Lower data strobe
GPIO
I/O General-purpose I/O
EROMCTL
RW
O
Read/write output for external bus
WE
O
Write enable signal
GPIO
I/O General-purpose I/O
PE[1]
IRQ
I
GPI
I
General-purpose input
PE[0]
XIRQ
I
Non-maskable level-sensitive interrupt input
I
General-purpose input
I
ROMON bit control input during RESET
I
External Wait signal
Configurable for reduced input threshold
GPI
K
MODB input during RESET
I
I/O General-purpose I/O
2
GPIO
PE[3]
I
RE
MODA
PK[7]
ROMCTL
2
EWAIT
GPIO
PK[6:4]
ADDR[22:20]
mux
ACC[2:0] 3
GPIO
PK[3:0]
ADDR[19:16]
mux
IQSTAT[3:0] 3
GPIO
Mode
dependent 4
I/O General-purpose I/O
2
TAGHI
PE[5]
Pin Function
after Reset
Description
Maskable level- or falling edge-sensitive interrupt input
Mode
dependent 3
I/O General-purpose I/O
O
Extended external bus address output
(multiplexed with access master output)
I/O General-purpose I/O
O
Extended external bus address output
(multiplexed with instruction pipe status bits)
I/O General-purpose I/O
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Port
Pin Name
Pin Function
& Priority1
T
PT[7]
IOC[7]
I/O Enhanced Capture Timer Channels 7 input/output
GPIO
I/O General-purpose I/O
IOC[5]
I/O Enhanced Capture Timer Channel 5 input/output
PT[5]
VREG_API
GPIO
PT[4:0]
IOC[4:0]
GPIO
S
PS7
SS0
I/O
O
Description
VREG Autonomous Periodical Interrupt output
I/O Enhanced Capture Timer Channels 4 - 0 input/output
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 slave select output in master mode,
input in slave mode or master mode.
I/O General-purpose I/O
PS6
SCK0
I/O Serial Peripheral Interface 0 serial clock pin
GPIO
I/O General-purpose I/O
PS5
MOSI0
I/O General-purpose I/O
MISO0
GPIO
I/O General-purpose I/O
PS3
TXD1
O
GPIO
I/O General-purpose I/O
I/O Serial Peripheral Interface 0 master in/slave out pin
RXD1
GPIO
I/O General-purpose I/O
PS1
TXD0
O
GPIO
I/O General-purpose I/O
GPIO
I
Serial Communication Interface 1 transmit pin
PS2
RXD0
GPIO
I/O Serial Peripheral Interface 0 master out/slave in pin
PS4
PS0
GPIO
I/O General-purpose I/O
GPIO
GPIO
Pin Function
after Reset
I
Serial Communication Interface 1 receive pin
Serial Communication Interface 0 transmit pin
Serial Communication Interface 0 receive pin
I/O General-purpose I/O
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Chapter 2 Port Integration Module (S12XEPIMV1)
Port
Pin Name
Pin Function
& Priority1
I/O
M
PM7
TXCAN3
O
MSCAN3 transmit pin
(TXCAN4)
O
MSCAN4 transmit pin
TXD3
O
Serial Communication Interface 3 transmit pin
GPIO
I/O General-purpose I/O
PM6
RXCAN3
I
MSCAN3 receive pin
(RXCAN4)
I
MSCAN4 receive pin
RXD3
I
Serial Communication Interface 3 receive pin
GPIO
PM5
O
MSCAN2 transmit pin
(TXCAN0)
O
MSCAN0 transmit pin
(TXCAN4)
O
MSCAN4 transmit pin
GPIO
PM4
I
MSCAN2 receive pin
I
MSCAN0 receive pin
(RXCAN4)
I
MSCAN4 receive pin
TXCAN1
(TXCAN0)
PM2
I/O General-purpose I/O
O
MSCAN1 transmit pin
O
MSCAN0 transmit pin
I/O Serial Peripheral Interface 0 slave select output in master mode,
input for slave mode or master mode.
GPIO
I/O General-purpose I/O
RXCAN1
I
MSCAN1 receive pin
(RXCAN0)
I
MSCAN0 receive pin
GPIO
TXCAN0
GPIO
PM0
I/O Serial Peripheral Interface 0 master out/slave in pin
If CAN0 is routed to PM[3:2] the SPI0 can still be used in
bidirectional master mode.
(SS0)
(MISO0)
PM1
I/O General-purpose I/O
RXCAN2
GPIO
PM3
I/O Serial Peripheral Interface 0 serial clock pin
If CAN0 is routed to PM[3:2] the SPI0 can still be used in
bidirectional master mode.
(RXCAN0)
(MOSI0)
GPIO
I/O General-purpose I/O
TXCAN2
(SCK0)
Pin Function
after Reset
Description
RXCAN0
GPIO
I/O Serial Peripheral Interface 0 master in/slave out pin
I/O General-purpose I/O
O
MSCAN0 transmit pin
I/O General-purpose I/O
I
MSCAN0 receive pin
I/O General-purpose I/O
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Port
Pin Name
Pin Function
& Priority1
P
PP7
PWM7
I/O Pulse Width Modulator input/output channel 7
SCK2
I/O Serial Peripheral Interface 2 serial clock pin
(TIMIOC7)
GPIO/KWP7
PP6
PWM6
SS2
(TIMIOC6)
GPIO/KWP6
PP5
I/O Timer Channel 6 input/output
I/O General-purpose I/O with interrupt
Pulse Width Modulator output channel 5
I/O Timer Channel 5 input/output
I/O General-purpose I/O with interrupt
MISO2
I/O Serial Peripheral Interface 2 master in/slave out pin
(TIMIOC3)
GPIO/KWP3
Pulse Width Modulator output channel 4
I/O Timer Channel 4 input/output
I/O General-purpose I/O with interrupt
O
Pulse Width Modulator output channel 3
I/O Serial Peripheral Interface 1 slave select output in master mode,
input for slave mode or master mode.
I/O Timer Channel 3 input/output
I/O General-purpose I/O with interrupt
PWM2
O
SCK1
I/O Serial Peripheral Interface 1 serial clock pin
(TIMIOC2)
GPIO/KWP2
Pulse Width Modulator output channel 2
I/O Timer Channel 2 input/output
I/O General-purpose I/O with interrupt
PWM1
O
MOSI1
I/O Serial Peripheral Interface 1 master out/slave in pin
(TIMIOC1)
GPIO/KWP1
PP0
I/O Serial Peripheral Interface 2 slave select output in master mode,
input for slave mode or master mode.
O
SS1
PP1
Pulse Width Modulator output channel 6
PWM4
PWM3
PP2
O
I/O Serial Peripheral Interface 2 master out/slave in pin
(TIMIOC4)
Pulse Width Modulator output channel 1
I/O Timer Channel 1 input/output
I/O General-purpose I/O with interrupt
PWM0
O
MISO1
I/O Serial Peripheral Interface 1 master in/slave out pin
(TIMIOC0)
GPIO/KWP0
GPIO
I/O General-purpose I/O with interrupt
MOSI2
GPIO/KWP4
Pin Function
after Reset
I/O Timer Channel 7 input/output
O
(TIMIOC5)
PP3
Description
PWM5
GPIO/KWP5
PP4
I/O
Pulse Width Modulator output channel 0
I/O Timer Channel 0 input/output
I/O General-purpose I/O with interrupt
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Chapter 2 Port Integration Module (S12XEPIMV1)
Pin Function
after Reset
Port
Pin Name
Pin Function
& Priority1
H
PH7
(SS2)
I/O Serial Peripheral Interface 2 slave select output in master mode,
input for slave mode or master mode
TXD5
O
GPIO/KWH7
PH6
(SCK2)
RXD5
GPIO/KWH6
PH5
(MOSI2)
TXD4
GPIO/KWH5
PH4
(MISO2)
RXD4
GPIO/KWH4
PH3
(SS1)
TXD7
GPIO/KWH3
PH2
(SCK1)
RXD7
GPIO/KWH2
PH1
(MOSI1)
TXD6
GPIO/KWH1
PH0
(MISO1)
TXD6
GPIO/KWH0
I/O
Description
GPIO
Serial Communication Interface 5 transmit pin
I/O General-purpose I/O with interrupt
I/O Serial Peripheral Interface 2 serial clock pin
I
Serial Communication Interface 5 receive pin
I/O General-purpose I/O with interrupt
I/O Serial Peripheral Interface 2 master out/slave in pin
O
Serial Communication Interface 4 transmit pin
I/O General-purpose I/O with interrupt
I/O Serial Peripheral Interface 2 master in/slave out pin
I
Serial Communication Interface 4 receive pin
I/O General-purpose I/O with interrupt
I/O Serial Peripheral Interface 1 slave select output in master mode,
input for slave mode or master mode.
O
Serial Communication Interface 7 transmit pin
I/O General-purpose I/O with interrupt
I/O Serial Peripheral Interface 1 serial clock pin
I
Serial Communication Interface 7 receive pin
I/O General-purpose I/O with interrupt
I/O Serial Peripheral Interface 1 master out/slave in pin
O
Serial Communication Interface 6 transmit pin
I/O General-purpose I/O with interrupt
I/O Serial Peripheral Interface 1 master in/slave out pin
O
Serial Communication Interface 6 transmit pin
I/O General-purpose I/O with interrupt
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Port
Pin Name
Pin Function
& Priority1
I/O
J
PJ7
TXCAN4
O
MSCAN4 transmit pin
SCL0
O
Inter Integrated Circuit 0 serial clock line
(TXCAN0)
O
MSCAN0 transmit pin
GPIO/KWJ7
PJ6
RXCAN4
SDA0
(RXCAN0)
GPIO/KWJ6
PJ5
I/O General-purpose I/O with interrupt
O
Chip select 2
I/O General-purpose I/O with interrupt
I/O Inter Integrated Circuit 1 serial data line
O
Chip select 0
GPIO/KWJ3
I/O General-purpose I/O with interrupt
CS1
TXD2
GPIO/KWJ1
PJ0
PAD[15:0]
Chip select 1
O
Serial Communication Interface 2 transmit pin
I/O General-purpose I/O with interrupt
I
Serial Communication Interface 2 receive pin
CS3
O
Chip select 3
GPIO
AN[15:0]
AD1 PAD[31:16]
O
I/O General-purpose I/O with interrupt
RXD2
GPIO/KWJ0
GPIO
AN[15:0]
PR[7:0]
MSCAN0 receive pin
I/O General-purpose I/O with interrupt
PJ1
R
I
CS2
GPIO/KWJ2
AD0
I/O Inter Integrated Circuit 0 serial data line
GPIO/KWJ4
PJ2
TIMIOC[7:0]
GPIO
GPIO
MSCAN4 receive pin
Inter Integrated Circuit 1 serial clock line
CS0
PJ3
I
O
SDA1
Pin Function
after Reset
I/O General-purpose I/O with interrupt
SCL1
GPIO/KWJ5
PJ4
Description
I/O General-purpose I/O with interrupt
I/O General-purpose I/O
I
ATD0 analog inputs
I/O General-purpose I/O
I
GPIO
GPIO
ATD1 analog inputs
I/O Timer Channels 7- 0 input/output
GPIO
I/O General-purpose I/O
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Port
Pin Name
Pin Function
& Priority1
I/O
L
PL7
(TXD7)
O
GPIO
PL6
(RXD7)
PL5
(TXD6)
GPIO
GPIO
PL4
(RXD6)
PL3
(TXD5)
GPIO
GPIO
PL2
(RXD5)
PL1
(TXD4)
GPIO
GPIO
PL0
(RXD4)
PF7
(TXD3)
GPIO
F
GPIO
PF6
(RXD3)
PF5
(SCL0)
GPIO
GPIO
Description
Serial Communication Interface 7 transmit pin
GPIO
I/O General-purpose I/O
I
Serial Communication Interface 7 receive pin
I/O General-purpose I/O
O
Serial Communication Interface 6 transmit pin
I/O General-purpose I/O
I
Serial Communication Interface 6 receive pin
I/O General-purpose I/O
O
Serial Communication Interface 5 transmit pin
I/O General-purpose I/O
I
Serial Communication Interface 5 receive pin
I/O General-purpose I/O
O
Serial Communication Interface 4 transmit pin
I/O General-purpose I/O
I
Serial Communication Interface 4 receive pin
I/O General-purpose I/O
O
Serial Communication Interface 3 transmit pin
GPIO
I/O General-purpose I/O
I
Serial Communication Interface 3 receive pin
I/O General-purpose I/O
O
Inter Integrated Circuit 0 serial clock line
I/O General-purpose I/O
PF4
(SDA0)
GPIO
I/O General-purpose I/O
PF3
(CS3)
O
GPIO
I/O General-purpose I/O
PF2
(CS2)
O
GPIO
I/O General-purpose I/O
PF1
(CS1)
O
GPIO
I/O General-purpose I/O
(CS0)
O
GPIO
I/O General-purpose I/O
PF0
Pin Function
after Reset
I/O Inter Integrated Circuit 0 serial data line
Chip select 3
Chip select 2
Chip select 1
Chip select 0
1
Signals in brackets denote alternative module routing pins.
Function active when RESET asserted.
3 Only available in emulation modes or in Special Test Mode with IVIS on.
4 Refer to S12X_EBI section.
2
2.3
Memory Map and Register Definition
This section provides a detailed description of all Port Integration Module registers.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.1
Memory Map
Register
Name
0x0000
PORTA
R
W
0x0001
PORTB
W
0x0002
DDRA
W
0x0003
DDRB
R
R
R
W
0x0004
PORTC
W
0x0005
PORTD
W
0x0006
DDRC
R
R
R
W
0x0007
DDRD
W
0x0008
PORTE
W
0x0009
DDRE
R
R
R
W
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
0
0
0x000A R
0x000B W
Non-PIM
Address
Range
0x000C
PUCR
0x000D
RDRIV
R
W
R
W
Non-PIM Address Range
PUPKE
RDPK
BKPUE
0
0
PUPEE
PUPDE
PUPCE
PUPBE
PUPAE
RDPE
RDPD
RDPC
RDPB
RDPA
0
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
Bit 7
6
5
0x000E– R
0x001B W
Non-PIM
Address
Range
0x001C R
ECLKCTL W
0x001D R
Reserved W
0x001E
IRQCR
W
0x001F
R
Reserved
R
0x0033
DDRK
0x0241
PTIT
2
1
Bit 0
NECLK
NCLKX2
DIV16
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
0
0
0
0
0
0
0
0
IRQE
IRQEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
R
W
R
W
Non-PIM Address Range
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
DDRK7
DDRK6
DDRK5
DDRK4
DDRK3
DDRK2
DDRK1
DDRK0
0x0034– R
0x023F W
Non-PIM
Address
Range
0x0240
PTT
3
Non-PIM Address Range
0x0020– R
0x0031 W
Non-PIM
Address
Range
0x0032
PORTK
4
R
W
R
Non-PIM Address Range
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
W
0x0242
DDRT
R
W
0x0243
RDRT
W
R
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0x0246
R
Reserved W
0
0
0
0
0
0
0
0
0x0247
R
Reserved W
0
0
0
0
0
0
0
0
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0
0
0
0
0
0
0
0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
DDRM7
DDRM6
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
0x0244
PERT
W
0x0245
PPST
W
0x0248
PTS
R
R
R
W
0x0249
PTIS
W
0x024A
DDRS
W
0x024B
RDRS
R
R
R
W
0x024C
PERS
W
0x024D
PPSS
W
0x024E
WOMS
R
R
R
W
0x024F
R
Reserved W
0x0250
PTM
0x0251
PTIM
0x0252
DDRM
R
W
R
W
R
W
= Unimplemented or Reserved
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95
Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
0x0253
RDRM
W
0x0254
PERM
W
0x0255
PPSM
R
R
R
W
0x0256
WOMM
W
0x0257
MODRR
W
0x0258
PTP
0x0259
PTIP
0x025A
DDRP
0x025B
RDRP
0x025C
PERP
R
R
R
W
R
R
W
R
W
R
W
W
0x025E
PIEP
W
R
R
R
W
0x0260
PTH
W
0x0261
PTIH
W
0x0262
DDRH
6
5
4
3
2
1
Bit 0
RDRM7
RDRM6
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
RDRM0
PERM7
PERM6
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
PPSM7
PPSM6
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
WOMM7
WOMM6
WOMM5
WOMM4
WOMM3
WOMM2
WOMM1
WOMM0
MODRR6
MODRR5
MODRR4
MODRR3
MODRR2
MODRR1
MODRR0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
DDRP7
DDRP6
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSP0
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
DDRH7
DDRH6
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
0
W
0x025D
PPSP
0x025F
PIFP
Bit 7
R
R
R
W
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
0x0263
RDRH
0x0264
PERH
0x0265
PPSH
0x0266
PIEH
R
W
R
W
R
W
R
W
0x0267
PIFH
W
0x0268
PTJ
W
0x0269
PTIJ
R
R
R
W
0x026B
RDRJ
W
0x026D
PPSJ
0x026E
PIEJ
0x026F
PIFJ
0x0270
PT0AD0
0x0271
PT1AD0
6
5
4
3
2
1
Bit 0
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
PIEH7
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
PIFH7
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
PTIJ7
PTIJ6
PTIJ5
PTIJ4
PTIJ3
PTIJ2
PTIJ1
PTIJ0
DDRJ7
DDRJ6
DDRJ5
DDRJ4
DDRJ3
DDRJ2
DDRJ1
DDRJ0
RDRJ7
RDRJ6
RDRJ5
RDRJ4
RDRJ3
RDRJ2
RDRJ1
RDRJ0
PERJ7
PERJ6
PERJ5
PERJ4
PERJ3
PERJ2
PERJ1
PERJ0
PPSJ7
PPSJ6
PPSJ5
PPSJ4
PPSJ3
PPSJ2
PPSJ1
PPSJ0
PIEJ7
PIEJ6
PIEJ5
PIEJ4
PIEJ3
PIEJ2
PIEJ1
PIEJ0
PIFJ7
PIFJ6
PIFJ5
PIFJ4
PIFJ3
PIFJ2
PIFJ1
PIFJ0
PT0AD07
PT0AD06
PT0AD05
PT0AD04
PT0AD03
PT0AD02
PT0AD01
PT0AD00
PT1AD07
PT1AD06
PT1AD05
PT1AD04
PT1AD03
PT1AD02
PT1AD01
PT1AD00
W
0x026A
DDRJ
0x026C
PERJ
Bit 7
R
R
R
W
R
W
R
W
R
W
R
W
R
W
= Unimplemented or Reserved
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Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0272
R
DDR0AD0 W DDR0AD07 DDR0AD06 DDR0AD05 DDR0AD04 DDR0AD03 DDR0AD02 DDR0AD01 DDR0AD00
0x0273
R
DDR1AD0 W DDR1AD07 DDR1AD06 DDR1AD05 DDR1AD04 DDR1AD03 DDR1AD02 DDR1AD01 DDR1AD00
0x0274
R
RDR0AD0 W RDR0AD07 RDR0AD06 RDR0AD05 RDR0AD04 RDR0AD03 RDR0AD02 RDR0AD01 RDR0AD00
0x0275
R
RDR1AD0 W RDR1AD07 RDR1AD06 RDR1AD05 RDR1AD04 RDR1AD03 RDR1AD02 RDR1AD01 RDR1AD00
0x0276
R
PER0AD0 W PER0AD07
PER0AD06
PER0AD05
PER0AD04
PER0AD03
PER0AD02
PER0AD01
PER0AD00
0x0277
R
PER1AD0 W PER1AD07
PER1AD06
PER1AD05
PER1AD04
PER1AD03
PER1AD02
PER1AD01
PER1AD00
PT0AD17
PT0AD16
PT0AD15
PT0AD14
PT0AD13
PT0AD12
PT0AD11
PT0AD10
PT1AD17
PT1AD16
PT1AD15
PT1AD14
PT1AD13
PT1AD12
PT1AD11
PT1AD10
0x0278
PT0AD1
0x0279
PT1AD1
R
W
R
W
0x027A R
DDR0AD1 W DDR0AD17 DDR0AD16 DDR0AD15 DDR0AD14 DDR0AD13 DDR0AD12 DDR0AD11 DDR0AD10
0x027B R
DDR1AD1 W DDR1AD17 DDR1AD16 DDR1AD15 DDR1AD14 DDR1AD13 DDR1AD12 DDR1AD11 DDR1AD10
0x027C R
RDR0AD1 W RDR0AD17 RDR0AD16 RDR0AD15 RDR0AD14 RDR0AD13 RDR0AD12 RDR0AD11 RDR0AD10
0x027D R
RDR1AD1 W RDR1AD17 RDR1AD16 RDR1AD15 RDR1AD14 RDR1AD13 RDR1AD12 RDR1AD11 RDR1AD10
0x027E R
PER0AD1 W PER0AD17
PER0AD16
PER0AD15
PER0AD14
PER0AD13
PER0AD12
PER0AD1‘
PER0AD10
0x027F
R
PER1AD1 W PER1AD17
PER1AD16
PER1AD15
PER1AD14
PER1AD13
PER1AD12
PER1AD11
PER1AD10
0x0280– R
0x0267 W
Non-PIM
Address
Range
Non-PIM Address Range
= Unimplemented or Reserved
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Freescale Semiconductor
Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
0x0368
PTR
W
0x0369
PTIR
W
0x036A
DDRR
R
R
R
W
0x036B
RDRR
W
0x036C
PERR
W
0x036D
PPSR
R
R
R
W
0x036E R
Reserved W
0x036F
PTRRR
0x0370
PTL
R
W
R
W
0x0371
PTIL
W
0x0372
DDRL
W
0x0373
RDRL
R
R
R
W
0x0374
PERL
W
0x0375
PPSL
W
0x0376
WOML
0x0377
PTLRR
R
R
R
W
R
W
Bit 7
6
5
4
3
2
1
Bit 0
PTR7
PTR6
PTR5
PTR4
PTR3
PTR2
PTR1
PTR0
PTIR7
PTIR6
PTIR5
PTIR4
PTIR3
PTIR2
PTIR1
PTIR0
DDRR7
DDRR6
DDRR5
DDRR4
DDRR3
DDRR2
DDRR1
DDRR0
RDRR7
RDRR6
RDRR5
RDRR4
RDRR3
RDRR2
RDRR1
RDRR0
PERR7
PERR6
PERR5
PERR4
PERR3
PERR2
PERR1
PERR0
PPSR7
PPSR6
PPSR5
PPSR4
PPSR3
PPSR2
PPSR1
PPSR0
0
0
0
0
0
0
0
0
PTRRR7
PTRRR6
PTRRR5
PTRRR4
PTRRR3
PTRRR2
PTRRR1
PTRRR0
PTL7
PTL6
PTL5
PTL4
PTL3
PTL2
PTL1
PTL0
PTIL7
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
DDRL7
DDRL6
DDRL5
DDRL4
DDRL3
DDRL2
DDRL1
DDRL0
RDRL7
RDRL6
RDRL5
RDRL4
RDRL3
RDRL2
RDRL1
RDRL0
PERL7
PERL6
PERL5
PERL4
PERL3
PERL2
PERL1
PERL0
PPSL7
PPSL6
PPSL5
PPSL4
PPSL3
PPSL2
PPSL1
PPSL0
WOML7
WOML6
WOML5
WOML4
WOML3
WOML2
WOML1
WOML0
PTLRR7
PTLRR6
PTLRR5
PTLRR4
0
0
0
0
= Unimplemented or Reserved
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99
Chapter 2 Port Integration Module (S12XEPIMV1)
Register
Name
0x0378
PTF
0x0379
PTIF
0x037A
DDRF
0x037B
RDRF
R
W
R
6
5
4
3
2
1
Bit 0
PTF7
PTF6
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
PTIF7
PTIF6
PTIF5
PTIF4
PTIF3
PTIF2
PTIF1
PTIF0
DDRF7
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
RDRF7
RDRF6
RDRF5
RDRF4
RDRF3
RDRF2
RDRF1
RDRF0
PERF7
PERF6
PERF5
PERF4
PERF3
PERF2
PERF1
PERF0
PPSF7
PPSF6
PPSF5
PPSF4
PPSF3
PPSF2
PPSF1
PPSF0
0
0
0
0
0
0
0
0
0
0
PTFRR5
PTFRR4
PTFRR3
PTFRR2
PTFRR1
PTFRR0
W
R
W
R
W
0x037C
PERF
W
0x037D
PPSF
W
R
R
0x037E R
Reserved W
0x037F
PTFRR
Bit 7
R
W
= Unimplemented or Reserved
2.3.2
Register Descriptions
The following table summarizes the effect of the various configuration bits, i.e. data direction (DDR),
output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull
device activity.
The configuration bit PS is used for two purposes:
1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pull-up or pull-down device if PE is active.
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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-2. Pin Configuration Summary
1
2
DDR
IO
RDR
PE
PS1
IE2
0
x
x
0
x
0
Input
Disabled
Disabled
0
x
x
1
0
0
Input
Pull Up
Disabled
0
x
x
1
1
0
Input
Pull Down
Disabled
0
x
x
0
0
1
Input
Disabled
Falling edge
0
x
x
0
1
1
Input
Disabled
Rising edge
0
x
x
1
0
1
Input
Pull Up
Falling edge
0
x
x
1
1
1
Input
Pull Down
Rising edge
1
0
0
x
x
0
Output, full drive to 0
Disabled
Disabled
1
1
0
x
x
0
Output, full drive to 1
Disabled
Disabled
1
0
1
x
x
0
Output, reduced drive to 0
Disabled
Disabled
1
1
1
x
x
0
Output, reduced drive to 1
Disabled
Disabled
1
0
0
x
0
1
Output, full drive to 0
Disabled
Falling edge
1
1
0
x
1
1
Output, full drive to 1
Disabled
Rising edge
1
0
1
x
0
1
Output, reduced drive to 0
Disabled
Falling edge
1
1
1
x
1
1
Output, reduced drive to 1
Disabled
Rising edge
Function
Pull Device
Interrupt
Always “0” on Port A, B, C, D, E, K, AD0, and AD1.
Applicable only on Port P, H, and J.
NOTE
All register bits in this module are completely synchronous to internal
clocks during a register read.
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2.3.3
Port A Data Register (PORTA)
Access: User read/write1
Address 0x0000 (PRR)
7
6
5
4
3
2
1
0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
ADDR15
mux
IVD15
ADDR14
mux
IVD14
ADDR13
mux
IVD13
ADDR12
mux
IVD12
ADDR11
mux
IVD11
ADDR10
mux
IVD10
ADDR9
mux
IVD9
ADDR8
mux
IVD8
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-1. Port A Data Register (PORTA)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-3. PORTA Register Field Descriptions
Field
Description
7-0
PA
Port A general purpose input/output data—Data Register
Port A pins 7 through 0 are associated with address outputs ADDR[15:8] respectively in expanded modes. In
emulation modes the address is multiplexed with IVD[15:8].
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.4
Port B Data Register (PORTB)
Access: User read/write1
Address 0x0001 (PRR)
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
R
W
Altern.
Function
Reset
ADDR7
mux
IVD7
ADDR6
mux
IVD6
ADDR5
mux
IVD5
ADDR4
mux
IVD4
ADDR3
mux
IVD3
ADDR2
mux
IVD2
ADDR1
mux
IVD1
ADDR0
mux
IVD0
or
UDS
0
0
0
0
0
0
0
0
Figure 2-2. Port B Data Register (PORTB)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
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Table 2-4. PORTB Register Field Descriptions
Field
Description
7-0
PB
Port B general purpose input/output data—Data Register
Port B pins 7 through 0 are associated with address outputs ADDR[7:0] respectively in expanded modes. In
emulation modes the address is multiplexed with IVD[7:0]. In normal expanded mode pin 0 is related to the UDS
input.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.5
Port A Data Direction Register (DDRA)
Access: User read/write1
Address 0x0002 (PRR)
7
6
5
4
3
2
1
0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-3. Port A Data Direction Register (DDRA)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-5. DDRA Register Field Descriptions
Field
Description
7-0
DDRA
Port A Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits
will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
2.3.6
Port B Data Direction Register (DDRB)
Access: User read/write1
Address 0x0003 (PRR)
7
6
5
4
3
2
1
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-4. Port B Data Direction Register (DDRB)
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1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-6. DDRB Register Field Descriptions
Field
Description
7-0
DDRB
Port B Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function forces the I/O state to be outputs for all associated pins. In this case the data direction bits
will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
2.3.7
Port C Data Register (PORTC)
Access: User read/write1
Address 0x0004 (PRR)
7
6
5
4
3
2
1
0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-5. Port C Data Register (PORTC)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-7. PORTC Register Field Descriptions
Field
Description
7-0
PC
Port C general purpose input/output data—Data Register
Port C pins 7 through 0 are associated with data I/O lines DATA[15:8] respectively in expanded modes.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
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2.3.8
Port D Data Register (PORTD)
Access: User read/write1
Address 0x0005 (PRR)
7
6
5
4
3
2
1
0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-6. Port D Data Register (PORTD)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-8. PORTD Register Field Descriptions
Field
Description
7-0
PD
Port D general purpose input/output data—Data Register
Port D pins 7 through 0 are associated with data I/O lines DATA[7:0] respectively in expanded modes.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.9
Port C Data Direction Register (DDRC)
Access: User read/write1
Address 0x0006 (PRR)
7
6
5
4
3
2
1
0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-7. Port C Data Direction Register (DDRC)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
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Table 2-9. DDRC Register Field Descriptions
Field
Description
7-0
DDRC
Port C Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
2.3.10
Port D Data Direction Register (DDRD)
Access: User read/write1
Address 0x0007 (PRR)
7
6
5
4
3
2
1
0
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-8. Port D Data Direction Register (DDRD)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-10. DDRD Register Field Descriptions
Field
Description
7-0
DDRD
Port D Data Direction—
This register controls the data direction of pins 7 through 0.
When used with the external bus this function controls the data direction for the associated pins. In this case the data
direction bits will not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
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2.3.11
Port E Data Register (PORTE)
Access: User read/write1
Address 0x0008 (PRR)
7
6
5
4
3
2
1
0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
XCLKS
or
ECLKX2
MODB
or
TAGHI
MODA
or
RE
or
TAGLO
ECLK
EROMCTL
or
LSTRB
or
LDS
RW
or
WE
IRQ
XIRQ
0
0
0
0
0
0
—2
—2
R
W
Altern.
Function
Reset
= Unimplemented or Reserved
Figure 2-9. Port E Data Register (PORTE)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
2 These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
Table 2-11. PORTE Register Field Descriptions
Field
Description
7-0
PE
Port E general purpose input/output data—Data Register
Port E bits 7 through 0 are associated with external bus control signals and interrupt inputs. These include mode
select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI, TAGLO),
Read/Write (RW), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.
When not used with the alternative functions, Port E pins 7-2 can be used as general purpose I/O and pins 1-0 can
be used as general purpose inputs.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.
Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.
2.3.12
Port E Data Direction Register (DDRE)
Access: User read/write1
Address 0x0009 (PRR)
7
6
5
4
3
2
R
DDRE7
DDRE6
DDRE5
DDRE4
DDRE3
DDRE2
0
0
0
0
0
0
1
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-10. Port E Data Direction Register (DDRE)
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1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-12. DDRE Register Field Descriptions
Field
Description
7-2
DDRE
Port E Data Direction—
This register controls the data direction of pins 7 through 2.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
1-0
Reserved—
Port E bit 1 (associated with IRQ) and bit 0 (associated with XIRQ) cannot be configured as outputs. Port E, bits 1
and 0, can be read regardless of whether the alternate interrupt function is enabled.
2.3.13
S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR)
Access: User read/write1
Address 0x000C (PRR)
7
6
R
5
4
3
2
1
0
PUPEE
PUPDE
PUPCE
PUPBE
PUPAE
1
0
0
0
0
0
PUPKE
BKPUE
1
1
W
Reset
0
= Unimplemented or Reserved
Figure 2-11. S12X_EBI ports, BKGD pin Pull-up Control Register (PUCR)
1
Read:Anytime in single-chip modes.
Write:Anytime, except BKPUE which is writable in Special Test Mode only.
Table 2-13. PUCR Register Field Descriptions
Field
Description
7
PUPKE
Pull-up Port K Enable—Enable pull-up devices on all Port K input pins
This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the
pins are used as outputs. Out of reset the pull-up devices are enabled.
1 Pull-up devices enabled.
0 Pull-up devices disabled.
6
BKPUE
BKGD pin pull-up Enable—Enable pull-up devices on BKGD pin
This bit configures whether a pull-up device is activated, if the pin is used as input. This bit has no effect if the pin is
used as outputs. Out of reset the pull-up device is enabled.
1 Pull-up device enabled.
0 Pull-up device disabled.
5
Reserved—
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Table 2-13. PUCR Register Field Descriptions (continued)
Field
Description
4
PUPEE
Pull-up Port E Enable—Enable pull-up devices on all Port E input pins except on pins 5 and 6 which have pull-down
devices only enabled during reset. This bit has no effect on these pins.
This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the
pins are used as outputs. Out of reset the pull-up devices are enabled.
1 Pull-up devices enabled.
0 Pull-up devices disabled.
3
PUPDE
Pull-up Port D Enable—Enable pull-up devices on all Port D input pins
This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the
pins are used as outputs. Out of reset the pull-up devices are disabled.
1 Pull-up devices enabled.
0 Pull-up devices disabled.
2
PUPCE
Pull-up Port C Enable—Enable pull-up devices on all Port C input pins
This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the
pins are used as outputs. Out of reset the pull-up devices are disabled.
1 Pull-up devices enabled.
0 Pull-up devices disabled.
1
PUPBE
Pull-up Port B Enable—Enable pull-up devices on all Port B input pins
This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the
pins are used as outputs. Out of reset the pull-up devices are disabled.
1 Pull-up devices enabled.
0 Pull-up devices disabled.
0
PUPAE
Pull-up Port A Enable—Enable pull-up devices on all Port A input pins
This bit configures whether pull-up devices are activated, if the pins are used as inputs. This bit has no effect if the
pins are used as outputs. Out of reset the pull-up devices are disabled.
1 Pull-up devices enabled.
0 Pull-up devices disabled.
2.3.14
S12X_EBI ports Reduced Drive Register (RDRIV)
Access: User read/write1
Address 0x000D (PRR)
7
R
6
5
0
0
RDPK
4
3
2
1
0
RDPE
RDPD
RDPC
RDPB
RDPA
0
0
0
0
0
W
Reset
0
0
0
= Unimplemented or Reserved
Figure 2-12. S12X_EBI ports Reduced Drive Register (RDRIV)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register is used to select reduced drive for the pins associated with the S12X_EBI ports A, B, C, D,
E, and K. If enabled, the pins drive at about 1/6 of the full drive strength. The reduced drive function is
independent of which function is being used on a particular pin.
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The reduced drive functionality does not take effect on the pins in emulation modes.
Table 2-14. RDRIV Register Field Descriptions
Field
Description
7
RDPK
Port K reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all Port K output pins as either full or reduced. If a pin is used as input this
bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
6-5
Reserved—
4
RDPE
Port E reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all Port E output pins as either full or reduced. If a pin is used as input this
bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
3
RDPD
Port D reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has
no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2
RDPC
Port C reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has
no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
1
RDPB
Port B reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has
no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
0
RDPA
Port A reduced drive—Select reduced drive for outputs
This bit configures the drive strength of all output pins as either full or reduced. If a pin is used as input this bit has
no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
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2.3.15
ECLK Control Register (ECLKCTL)
Access: User read/write1
Address 0x001C (PRR)
7
6
5
4
3
2
1
0
NECLK
NCLKX2
DIV16
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
Reset :
Mode
Dependent
1
0
0
0
0
0
0
SS
0
1
0
0
0
0
0
0
ES
1
1
0
0
0
0
0
0
ST
0
1
0
0
0
0
0
0
EX
0
1
0
0
0
0
0
0
NS
1
1
0
0
0
0
0
0
NX
0
1
0
0
0
0
0
0
R
W
2
= Unimplemented or Reserved
Figure 2-13. ECLK Control Register (ECLKCTL)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
2 Reset values in emulation modes are identical to those of the target mode.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
Table 2-15. ECLKCTL Register Field Descriptions
Field
Description
7
NECLK
No ECLK—Disable ECLK output
This bit controls the availability of a free-running clock on the ECLK pin.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLK disabled
0 ECLK enabled
6
NCLKX2
No ECLKX2—Disable ECLKX2 output
This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed rate of twice the
internal Bus Clock.
Clock output is always active in emulation modes and if enabled in all other operating modes.
1 ECLKX2 disabled
0 ECLKX2 enabled
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Table 2-15. ECLKCTL Register Field Descriptions (continued)
Field
Description
5
DIV16
Free-running ECLK predivider—Divide by 16
This bit enables a divide-by-16 stage on the selected EDIV rate.
1 Divider enabled: ECLK rate = EDIV rate divided by 16
0 Divider disabled: ECLK rate = EDIV rate
4-0
EDIV
Free-running ECLK Divider—Configure ECLK rate
These bits determine the rate of the free-running clock on the ECLK pin. Divider is always disabled in emulation
modes and active as programmed in all other operating modes.
00000 ECLK rate = Bus Clock rate
00001 ECLK rate = Bus Clock rate divided by 2
00010 ECLK rate = Bus Clock rate divided by 3, ...
11111 ECLK rate = Bus Clock rate divided by 32
2.3.16
PIM Reserved Register
Access: User read1
Address 0x001D (PRR)
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-14. PIM Reserved Register
1
Read: Always reads 0x00
Write: Unimplemented
2.3.17
IRQ Control Register (IRQCR)
Access: User read/write1
Address 0x001E
7
6
IRQE
IRQEN
0
1
R
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-15. IRQ Control Register (IRQCR)
1
Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
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Table 2-16. IRQCR Register Field Descriptions
Field
Description
7
IRQE
IRQ select edge sensitive only—
Special modes: Read or write anytime.
Normal & emulation modes: Read anytime, write once.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime IRQE = 1
and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ configured for low level recognition.
6
IRQEN
5-0
External IRQ enable—
Read or write anytime.
1 External IRQ pin is connected to interrupt logic.
0 External IRQ pin is disconnected from interrupt logic.
Reserved—
2.3.18
PIM Reserved Register
This register is reserved for factory testing of the PIM module and is not available in normal operation.
Access: User read1
Address 0x001F
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-16. PIM Reserved Register
1
Read: Always reads 0x00
Write: Unimplemented
NOTE
Writing to this register when in special modes can alter the pin functionality.
2.3.19
Port K Data Register (PORTK)
Access: User read/write1
Address 0x0032 (PRR)
7
6
5
4
3
2
1
0
PK7
PK6
PK5
PK4
PK3
PK2
PK1
PK0
ROMCTL
or
EWAIT
ADDR22
mux
NOACC
ADDR21
ADDR20
ADDR19
mux
IQSTAT3
ADDR18
mux
IQSTAT2
ADDR17
mux
IQSTAT1
ADDR16
mux
IQSTAT0
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-17. Port K Data Register (PORTK)
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1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-17. PORTK Register Field Descriptions
Field
Description
7-0
PK
Port K general purpose input/output data—Data Register
Port K pins 7 through 0 are associated with external bus control signals and internal memory expansion emulation
pins. These include ADDR[22:16], No-Access (NOACC), External Wait (EWAIT) and instruction pipe signals
IQSTAT[3:0]. Bits 6-0 carry the external addresses in all expanded modes. In emulation modes the address is
multiplexed with the alternate functions NOACC and IQSTAT on the respective pins.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.20
Port K Data Direction Register (DDRK)
Access: User read/write1
Address 0x0033 (PRR)
7
6
5
4
3
2
1
0
DDRK7
DDRK6
DDRK5
DDRK4
DDRK3
DDRK2
DDRK1
DDRK0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-18. Port K Data Direction Register (DDRK)
1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data
source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 2-18. DDRK Register Field Descriptions
Field
Description
7-0
DDRK
Port K Data Direction—
This register controls the data direction of pins 7 through 0.
The external bus function controls the data direction for the associated pins. In this case the data direction bits will
not change.
When operating a pin as a general purpose I/O, the associated data direction bit determines whether it is an input
or output.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.21
Port T Data Register (PTT)
Access: User read/write1
Address 0x0240
7
6
5
4
3
2
1
0
PTT7
PTT6
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
—
—
VREG_API
—
—
—
—
—
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-19. Port T Data Register (PTT)
1
Read: Anytime.
Write: Anytime.
Table 2-19. PTT Register Field Descriptions
Field
Description
7-6
PTT
Port T general purpose input/output data—Data Register
Port T pins 7 through 0 are associated with ECT channels IOC7 and IOC6.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTT
Port T general purpose input/output data—Data Register
Port T pins 5 is associated with ECT channel IOC5 and the VREG_API output.
The ECT function takes precedence over the VREG_API and the general purpose I/O function if the related channel
is enabled.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
4-0
PTT
Port T general purpose input/output data—Data Register
Port T pins 4 through 0 are associated with ECT channels IOC4 through IOC0.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.22
Port T Input Register (PTIT)
Access: User read1
Address 0x0241
R
7
6
5
4
3
2
1
0
PTIT7
PTIT6
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-20. Port T Input Register (PTIT)
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1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-20. PTIT Register Field Descriptions
Field
Description
7-0
PTIT
Port T input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.23
Port T Data Direction Register (DDRT)
Access: User read/write1
Address 0x0242
7
6
5
4
3
2
1
0
DDRT7
DDRT6
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-21. Port T Data Direction Register (DDRT)
1
Read: Anytime.
Write: Anytime.
Table 2-21. DDRT Register Field Descriptions
Field
Description
7-0
DDRT
Port T data direction—
This register controls the data direction of pins 7 through 0.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTT or PTIT registers, when changing the
DDRT register.
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2.3.24
Port T Reduced Drive Register (RDRT)
Access: User read/write1
Address 0x0243
7
6
5
4
3
2
1
0
RDRT7
RDRT6
RDRT5
RDRT4
RDRT3
RDRT2
RDRT1
RDRT0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-22. Port T Reduced Drive Register (RDRT)
1
Read: Anytime.
Write: Anytime.
Table 2-22. RDRT Register Field Descriptions
Field
Description
7-0
RDRT
Port T reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.25
Port T Pull Device Enable Register (PERT)
Access: User read/write1
Address 0x0244
7
6
5
4
3
2
1
0
PERT7
PERT6
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-23. Port T Pull Device Enable Register (PERT)
1
Read: Anytime.
Write: Anytime.
Table 2-23. PERT Register Field Descriptions
Field
Description
7-0
PERT
Port T pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
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2.3.26
Port T Polarity Select Register (PPST)
Access: User read/write1
Address 0x0245
7
6
5
4
3
2
1
0
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-24. Port T Polarity Select Register (PPST)
1
Read: Anytime.
Write: Anytime.
Table 2-24. PPST Register Field Descriptions
Field
7-0
PPST
2.3.27
Description
Port T pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
PIM Reserved Register
Access: User read1
Address 0x0246
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-25. PIM Reserved Register
1
Read: Always reads 0x00
Write: Unimplemented
2.3.28
PIM Reserved Register
Access: User read1
Address 0x0247
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-26. PIM Reserved Register
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1
Read: Always reads 0x00
Write: Unimplemented
2.3.29
Port S Data Register (PTS)
Access: User read/write1
Address 0x0248
7
6
5
4
3
2
1
0
PTS7
PTST6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
SS0
SCK0
MOSI0
MISO0
TXD1
RXD1
TXD0
RXD0
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-27. Port S Data Register (PTS)
1
Read: Anytime.
Write: Anytime.
Table 2-25. PTS Register Field Descriptions
Field
Description
7
PTS
Port S general purpose input/output data—Data Register
Port S pin 7 is associated with the SS signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
6
PTS
Port S general purpose input/output data—Data Register
Port S pin 6 is associated with the SCK signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTS
Port S general purpose input/output data—Data Register
Port S pin 5 is associated with the MOSI signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
4
PTS
Port S general purpose input/output data—Data Register
Port S pin 4 is associated with the MISO signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
3
PTS
Port S general purpose input/output data—Data Register
Port S pin 3 is associated with the TXD signal of the SCI1 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
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Table 2-25. PTS Register Field Descriptions (continued)
Field
Description
2
PTS
Port S general purpose input/output data—Data Register
Port S bits 2 is associated with the RXD signal of the SCI1 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
1
PTS
Port S general purpose input/output data—Data Register
Port S pin 3 is associated with the TXD signal of the SCI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTS
Port S general purpose input/output data—Data Register
Port S bits 2 is associated with the RXD signal of the SCI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.30
Port S Input Register (PTIS)
Access: User read1
Address 0x0249
R
7
6
5
4
3
2
1
0
PTIS7
PTIS6
PTIS5
PTIS4
PTIS3
PTIS2
PTIS1
PTIS0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-28. Port S Input Register (PTIS)
1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-26. PTIS Register Field Descriptions
Field
Description
7-0
PTIS
Port S input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
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2.3.31
Port S Data Direction Register (DDRS)
Access: User read/write1
Address 0x0249
7
6
5
4
3
2
1
0
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-29. Port S Data Direction Register (DDRS)
1
Read: Anytime.
Write: Anytime.
Table 2-27. DDRS Register Field Descriptions
Field
Description
7-0
DDRS
Port S data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port S pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTS or PTIS registers, when changing the
DDRS register.
2.3.32
Port S Reduced Drive Register (RDRS)
Access: User read/write1
Address 0x024A
7
6
5
4
3
2
1
0
RDRS7
RDRS6
RDRS5
RDRS4
RDRS3
RDRS2
RDRS1
RDRS0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-30. Port S Reduced Drive Register (RDRS)
1
Read: Anytime.
Write: Anytime.
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Table 2-28. RDRS Register Field Descriptions
Field
Description
7-0
RDRS
Port S reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.33
Port S Pull Device Enable Register (PERS)
Access: User read/write1
Address 0x024B
7
6
5
4
3
2
1
0
PERS7
PERS6
PERS5
PERS4
PERS3
PERS2
PERS1
PERS0
1
1
1
1
1
1
1
1
R
W
Reset
Figure 2-31. Port S Pull Device Enable Register (PERS)
1
Read: Anytime.
Write: Anytime.
Table 2-29. PERS Register Field Descriptions
Field
Description
7-0
PERS
Port S pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.34
Port S Polarity Select Register (PPSS)
Access: User read/write1
Address 0x024C
7
6
5
4
3
2
1
0
PPSS7
PPSS6
PPSS5
PPSS4
PPSS3
PPSS2
PPSS1
PPSS0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-32. Port S Polarity Select Register (PPSS)
1
Read: Anytime.
Write: Anytime.
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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-30. PPSS Register Field Descriptions
Field
7-0
PPSS
2.3.35
Description
Port S pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
Port S Wired-Or Mode Register (WOMS)
Access: User read/write1
Address 0x024C
7
6
5
4
3
2
1
0
WOMS7
WOMS6
WOMS5
WOMS4
WOMS3
WOMS2
WOMS1
WOMS0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-33. Port S Wired-Or Mode Register (WOMS)
1
Read: Anytime.
Write: Anytime.
Table 2-31. WOMS Register Field Descriptions
Field
7-0
WOMS
2.3.36
Description
Port S wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
PIM Reserved Register
Access: User read1
Address 0x024F
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-34. PIM Reserved Register
1
Read: Always reads 0x00
Write: Unimplemented
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2.3.37
Port M Data Register (PTM)
Access: User read/write1
Address 0x0250
7
6
5
4
3
2
1
0
PTM7
PTM6
PTM5
PTM4
PTM3
PTM2
PTM1
PTM0
TXCAN3
RXCAN3
TXCAN2
RXCAN2
TXCAN1
RXCAN1
TXCAN0
RXCAN0
—
—
(TXCAN0)
(RXCAN0)
(TXCAN0)
(RXCAN0)
—
—
(TXCAN4)
(RXCAN4)
(TXCAN4)
(RXCAN4)
—
—
—
—
—
—
(SCK0)
(MOSI0)
(SS0)
(MISO0)
—
—
TXD3
RXD3
—
—
—
—
—
—
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-35. Port M Data Register (PTM)
1
Read: Anytime.
Write: Anytime.
Table 2-32. PTM Register Field Descriptions
Field
Description
7-6
PTM
Port M general purpose input/output data—Data Register
Port M pins 7 and 6 are associated with TXCAN and RXCAN signals of CAN3 and the routed CAN4, as well as with
TXD and RXD signals of SCI3, respectively.
The CAN3 function takes precedence over the CAN4, SCI3 and the general purpose I/O function if the CAN3 module
is enabled. The CAN4 function takes precedence over the SCI3 and the general purpose I/O function if the CAN4
module is enabled. The SCI3 function takes precedence over the general purpose I/O function if the SCI3 module
is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTM
Port M general purpose input/output data—Data Register
Port M pin 5 is associated with the TXCAN signal of CAN2 and the routed CAN4 and CAN0, as well as with SCK
signals of SPI0.
The CAN2 function takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose
I/O function if the CAN2 module is enabled. The routed CAN0 function takes precedence over the routed CAN4, the
routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function
takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. The
routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
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Table 2-32. PTM Register Field Descriptions (continued)
Field
Description
4
PTM
Port M general purpose input/output data—Data Register
Port M pin 4 is associated with the RXCAN signal of CAN2 and the routed CAN4 and CAN0, as well as with MOSI
signals of SPI0.
The CAN2 function takes precedence over the routed CAN0, routed CAN4, the routed SPI0 and the general purpose
I/O function if the CAN2 module is enabled. The routed CAN0 function takes precedence over the routed CAN4, the
routed SPI0 and the general purpose I/O function if the routed CAN0 module is enabled. The routed CAN4 function
takes precedence over the routed SPI0 and general purpose I/O function if the routed CAN4 module is enabled. The
routed SPI0 function takes precedence of the general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
3
PTM
Port M general purpose input/output data—Data Register
Port M pin 5 is associated with the TXCAN signal of CAN1 and the routed CAN0, as well as with SS0 signals of SPI0.
The CAN1 function takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function
if the CAN1 module is enabled. The routed CAN0 function takes precedence over the routed SPI0 and the general
purpose I/O function if the routed CAN0 module is enabled. The routed SPI0 function takes precedence of the
general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2
PTM
Port M general purpose input/output data—Data Register
Port M pin 4 is associated with the RXCAN signal of CAN1 and the routed CAN0, as well as with MISO signals of
SPI0.
The CAN1 function takes precedence over the routed CAN0, the routed SPI0 and the general purpose I/O function
if the CAN1 module is enabled. The routed CAN0 function takes precedence over the routed SPI0 and the general
purpose I/O function if the routed CAN0 module is enabled. The routed SPI0 function takes precedence of the
general purpose I/O function if the routed SPI0 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
1-0
PTM
Port M general purpose input/output data—Data Register
Port M pins 1 and 0 are associated with TXCAN and RXCAN signals of CAN0, respectively.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.38
Port M Input Register (PTIM)
Access: User read1
Address 0x0251
R
7
6
5
4
3
2
1
0
PTIM7
PTIM6
PTIM5
PTIM4
PTIM3
PTIM2
PTIM1
PTIM0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-36. Port M Input Register (PTIM)
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1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-33. PTIM Register Field Descriptions
Field
Description
7-0
PTIM
Port M input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.39
Port M Data Direction Register (DDRM)
Access: User read/write1
Address 0x0252
7
6
5
4
3
2
1
0
DDRM7
DDRM6
DDRM5
DDRM4
DDRM3
DDRM2
DDRM1
DDRM0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-37. Port M Data Direction Register (DDRM)
1
Read: Anytime.
Write: Anytime.
Table 2-34. DDRM Register Field Descriptions
Field
Description
7
DDRM
Port M data direction—
This register controls the data direction of pin 7.
The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an output. In those cases the data
direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated
peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
6
DDRM
Port M data direction—
This register controls the data direction of pin 6.
The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an input. In those cases the data direction
bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
5
DDRM
Port M data direction—
This register controls the data direction of pin 5.
The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an output. Depending on the
configuration of the enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction
bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
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Chapter 2 Port Integration Module (S12XEPIMV1)
Table 2-34. DDRM Register Field Descriptions (continued)
Field
Description
4
DDRM
Port M data direction—
This register controls the data direction of pin 4.
The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an input. Depending on the configuration
of the enabled routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
3
DDRM
Port M data direction—
This register controls the data direction of pin 3.
The enabled CAN1 or routed CAN0 forces the I/O state to be an output. Depending on the configuration of the
enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
2
DDRM
Port M data direction—
This register controls the data direction of pin 2.
The enabled CAN1 or routed CAN0 forces the I/O state to be an input. Depending on the configuration of the enabled
routed SPI0 this pin will be forced to be input or output.In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
1
DDRM
Port M data direction—
This register controls the data direction of pin 1.
The enabled CAN0 forces the I/O state to be an output. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0
DDRM
Port M data direction—
This register controls the data direction of pin 0.
The enabled CAN0 forces the I/O state to be an input. In those cases the data direction bits will not change. The
DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTM or PTIM registers, when changing the
DDRM register.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.40
Port M Reduced Drive Register (RDRM)
Access: User read/write1
Address 0x0253
7
6
5
4
3
2
1
0
RDRM7
RDRM6
RDRM5
RDRM4
RDRM3
RDRM2
RDRM1
RDRM0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-38. Port M Reduced Drive Register (RDRM)
1
Read: Anytime.
Write: Anytime.
Table 2-35. RDRM Register Field Descriptions
Field
Description
7-0
RDRM
Port M reduced drive—Select reduced drive for outputs
This register configures the drive strength of Port M output pins 7 through 0 as either full or reduced. If a pin is used
as input this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.41
Port M Pull Device Enable Register (PERM)
Access: User read/write1
Address 0x0254
7
6
5
4
3
2
1
0
PERM7
PERM6
PERM5
PERM4
PERM3
PERM2
PERM1
PERM0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-39. Port M Pull Device Enable Register (PERM)
1
Read: Anytime.
Write: Anytime.
Table 2-36. PERM Register Field Descriptions
Field
Description
7-0
PERM
Port M pull device enable—Enable pull-up devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input or wired-or output.
This bit has no effect if the pin is used as push-pull output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
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2.3.42
Port M Polarity Select Register (PPSM)
Access: User read/write1
Address 0x0255
7
6
5
4
3
2
1
0
PPSM7
PPSM6
PPSM5
PPSM4
PPSM3
PPSM2
PPSM1
PPSM0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-40. Port M Polarity Select Register (PPSM)
1
Read: Anytime.
Write: Anytime.
Table 2-37. PPSM Register Field Descriptions
Field
Description
7-0
PPSM
Port M pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin. If CAN is active a pull-up device
can be activated on the RXCAN[3:0] inputs, but not a pull-down.
1 A pull-down device is connected to the associated Port M pin, if enabled by the associated bit in register PERM
and if the port is used as a general purpose but not as RXCAN.
0 A pull-up device is connected to the associated Port M pin, if enabled by the associated bit in register PERM and
if the port is used as general purpose or RXCAN input.
2.3.43
Port M Wired-Or Mode Register (WOMM)
Access: User read/write1
Address 0x0256
7
6
5
4
3
2
1
0
WOMM7
WOMM6
WOMM5
WOMM4
WOMM3
WOMM2
WOMM1
WOMM0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-41. Port M Wired-Or Mode Register (WOMM)
1
Read: Anytime.
Write: Anytime.
Table 2-38. WOMM Register Field Descriptions
Field
7-0
WOMM
Description
Port M wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.44
Module Routing Register (MODRR)
Access: User read/write1
Address 0x0257
7
R
6
5
4
3
2
1
0
MODRR6
MODRR5
MODRR4
MODRR3
MODRR2
MODRR1
MODRR0
0
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 2-42. Module Routing Register (MODRR)
1
Read: Anytime.
Write: Anytime.
This register configures the re-routing of CAN0, CAN4, SPI0, SPI1, and SPI2 on alternative ports.
Table 2-39. Module Routing Summary
Module
MODRR
6
CAN0
CAN4
SPI0
5
4
3
Related Pins
2
1
0
RXCAN
TXCAN
x
x
x
x
x
0
0
PM0
PM1
x
x
x
x
x
0
1
PM2
PM3
x
x
x
x
x
1
0
PM4
PM5
x
x
x
x
x
1
1
PJ6
PJ7
x
x
x
0
0
x
x
PJ6
PJ7
x
x
x
0
1
x
x
PM4
PM5
x
x
x
1
0
x
x
PM6
x
x
x
1
1
x
x
x
PM7
Reserved
MISO
MOSI
SCK
SS
x
0
x
x
x
x
PS4
PS5
PS6
PS7
x
x
1
x
x
x
x
PM2
PM4
PM5
PM3
SPI1
x
0
x
x
x
x
x
PP0
PP1
PP2
PP3
x
1
x
x
x
x
x
PH0
PH1
PH2
PH3
SPI2
0
x
x
x
x
x
x
PP4
PP5
PP7
PP6
1
x
x
x
x
x
x
PH4
PH5
PH6
PH7
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2.3.45
Port P Data Register (PTP)
Access: User read/write1
Address 0x0258
7
6
5
4
3
2
1
0
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
PWM7
PWM6
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
SCK2
SS2
MOSI2
MISO2
SS1
SCK1
MOSI1
MISO1
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-43. Port P Data Register (PTP)
1
Read: Anytime.
Write: Anytime.
Table 2-40. PTP Register Field Descriptions
Field
Description
7
PTP
Port P general purpose input/output data—Data Register
Port P pin 6 is associated with the PWM output channel 7 and the SCK signal of SPI2 .
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 7 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
6
PTP
Port P general purpose input/output data—Data Register
Port P pin 6 is associated with the PWM output channel 6 and the SS signal of SPI2 .
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 6 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
5
PTP
Port P general purpose input/output data—Data Register
Port P pin 5 is associated with the PWM output channel 5 and the MOSI signal of SPI2 .
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 5 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
4
PTP
Port P general purpose input/output data—Data Register
Port P pin 4 is associated with the PWM output channel 4 and the MISO signal of SPI2 .
The PWM function takes precedence over the SPI2 and the general purpose I/O function if the PWM channel 4 is
enabled. The SPI2 function takes precedence of the general purpose I/O function if the routed SPI2 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
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Table 2-40. PTP Register Field Descriptions (continued)
Field
Description
3
PTP
Port P general purpose input/output data—Data Register
Port P pin 3 is associated with the PWM output channel 3 and the SS signal of SPI1 .
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 3 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2
PTP
Port P general purpose input/output data—Data Register
Port P pin 2 is associated with the PWM output channel 2 and the SCK signal of SPI1 .
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 2 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
1
PTP
Port P general purpose input/output data—Data Register
Port P pin 1 is associated with the PWM output channel 1 and the MOSI signal of SPI1 .
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 1 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
0
PTP
Port P general purpose input/output data—Data Register
Port P pin 0 is associated with the PWM output channel 0 and the MISO signal of SPI1 .
The PWM function takes precedence over the SPI1 and the general purpose I/O function if the PWM channel 0 is
enabled. The SPI1 function takes precedence of the general purpose I/O function if the routed SPI1 is enabled.
When not used with the alternative functions, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.46
Port P Input Register (PTIP)
Access: User read1
Address 0x0259
R
7
6
5
4
3
2
1
0
PTIP7
PTIP6
PTIP5
PTIP4
PTIP3
PTIP2
PTIP1
PTIP0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-44. Port P Input Register (PTIP)
1
Read: Anytime.
Write:Never, writes to this register have no effect.
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Table 2-41. PTIP Register Field Descriptions
Field
Description
7-0
PTIP
Port P input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.47
Port P Data Direction Register (DDRP)
Access: User read/write1
Address 0x025A
7
6
5
4
3
2
1
0
DDRP7
DDRP6
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-45. Port P Data Direction Register (DDRP)
1
Read: Anytime.
Write: Anytime.
Table 2-42. DDRP Register Field Descriptions
Field
Description
7
DDRP
Port P data direction—
This register controls the data direction of pin 7.
The enabled PWM channel 7 forces the I/O state to be an output. If the PWM shutdown feature is enabled this pin
is forced to be an input. In these cases the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
6-0
DDRP
Port P data direction—
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM6-0 channel. In this
case the data direction bit will not change.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTP or PTIP registers, when changing the
DDRP register.
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2.3.48
Port P Reduced Drive Register (RDRP)
Access: User read/write1
Address 0x025B
7
6
5
4
3
2
1
0
RDRP7
RDRP6
RDRP5
RDRP4
RDRP3
RDRP2
RDRP1
RDRP0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-46. Port P Reduced Drive Register (RDRP)
1
Read: Anytime.
Write: Anytime.
Table 2-43. RDRP Register Field Descriptions
Field
Description
7-0
RDRP
Port P reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.49
Port P Pull Device Enable Register (PERP)
Access: User read/write1
Address 0x025C
7
6
5
4
3
2
1
0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSP0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-47. Port P Pull Device Enable Register (PERP)
1
Read: Anytime.
Write: Anytime.
Table 2-44. PERP Register Field Descriptions
Field
Description
7-0
PERP
Port P pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.50
Port P Polarity Select Register (PPSP)
Access: User read/write1
Address 0x025D
7
6
5
4
3
2
1
0
PPSP7
PPSP6
PPSP5
PPSP4
PPSP3
PPSP2
PPSP1
PPSP0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-48. Port P Polarity Select Register (PPSP)
1
Read: Anytime.
Write: Anytime.
Table 2-45. PPSP Register Field Descriptions
Field
Description
7-0
PPSP
Port P pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up
or pull-down device if enabled.
1 A rising edge on the associated Port P pin sets the associated flag bit in the PIFP register. A pull-down device is
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
0 A falling edge on the associated Port P pin sets the associated flag bit in the PIFP register.A pull-up device is
connected to the associated Port P pin, if enabled by the associated bit in register PERP and if the port is used
as input.
2.3.51
Port P Interrupt Enable Register (PIEP)
Read: Anytime.
Access: User read/write1
Address 0x025E
7
6
5
4
3
2
1
0
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-49. Port P Interrupt Enable Register (PIEP)
1
Read: Anytime.
Write: Anytime.
Table 2-46. PPSP Register Field Descriptions
Field
7-0
PIEP
Description
Port P interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port P.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
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Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.52
Port P Interrupt Flag Register (PIFP)
Access: User read/write1
Address 0x025F
7
6
5
4
3
2
1
0
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-50. Port P Interrupt Flag Register (PIFP)
1
Read: Anytime.
Write: Anytime.
Table 2-47. PPSP Register Field Descriptions
Field
Description
7-0
PIFP
Port P interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSP register. To clear this flag, write logic level 1 to the corresponding bit in the PIFP register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
2.3.53
Port H Data Register (PTH)
Access: User read/write1
Address 0x0260
7
6
5
4
3
2
1
0
PTH7
PTH6
PTH5
PTH4
PTH3
PTH2
PTH1
PTH0
SS2
SCK2
MOSI2
MISO2
SS1
SCK1
MOSI1
MISO1
TXD5
RXD5
TXD4
RXD4
TXD7
RXD7
TXD6
RXD6
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-51. Port H Data Register (PTH)
1
Read: Anytime.
Write: Anytime.
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Table 2-48. PTH Register Field Descriptions
Field
Description
7
PTH
Port H general purpose input/output data—Data Register
Port H pin 7 is associated with the TXD signal of the SCI5 module and the SS signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
6
PTH
Port H general purpose input/output data—Data Register
Port H pin 6 is associated with the RXD signal of the SCI5 module and the SCK signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI5 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI5 function takes precedence over the general purpose I/O function if the SCI5 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTH
Port H general purpose input/output data—Data Register
Port H pin 5 is associated with the TXD signal of the SCI4 module and the MOSI signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
4
PTH
Port H general purpose input/output data—Data Register
Port H pin 4 is associated with the RXD signal of the SCI4 module and the MISO signal of the routed SPI2.
The routed SPI2 function takes precedence over the SCI4 and the general purpose I/O function if the routed SPI2
module is enabled. The SCI4 function takes precedence over the general purpose I/O function if the SCI4 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
3
PTH
Port H general purpose input/output data—Data Register
Port H pin 3 is associated with the TXD signal of the SCI7 module and the SS signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2
PTH
Port H general purpose input/output data—Data Register
Port H pin 2 is associated with the RXD signal of the SCI7 module and the SCK signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI7 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI7 function takes precedence over the general purpose I/O function if the SCI7 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
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Table 2-48. PTH Register Field Descriptions (continued)
Field
Description
1
PTH
Port H general purpose input/output data—Data Register
Port H pin 1 is associated with the TXD signal of the SCI6 module and the MOSI signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTH
Port H general purpose input/output data—Data Register
Port H pin 0 is associated with the RXD signal of the SCI6 module and the MISO signal of the routed SPI1.
The routed SPI1 function takes precedence over the SCI6 and the general purpose I/O function if the routed SPI1
module is enabled. The SCI6 function takes precedence over the general purpose I/O function if the SCI6 is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.54
Port H Input Register (PTIH)
Access: User read1
Address 0x0261
R
7
6
5
4
3
2
1
0
PTIH7
PTIH6
PTIH5
PTIH4
PTIH3
PTIH2
PTIH1
PTIH0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-52. Port H Input Register (PTIH)
1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-49. PTIH Register Field Descriptions
Field
Description
7-0
PTIH
Port H input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
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2.3.55
Port H Data Direction Register (DDRH)
Access: User read/write1
Address 0x0262
7
6
5
4
3
2
1
0
DDRH7
DDRH6
DDRH5
DDRH4
DDRH3
DDRH2
DDRH1
DDRH0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-53. Port H Data Direction Register (DDRH)
1
Read: Anytime.
Write: Anytime.
Table 2-50. DDRH Register Field Descriptions
Field
Description
7
DDRH
Port H data direction—
This register controls the data direction of pin 7.
The enabled SCI5 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
6
DDRH
Port H data direction—
This register controls the data direction of pin 6.
The enabled SCI5 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
5
DDRH
Port H data direction—
This register controls the data direction of pin 5.
The enabled SCI4 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
4
DDRH
Port H data direction—
This register controls the data direction of pin 4.
The enabled SCI4 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI2
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
3
DDRH
Port H data direction—
This register controls the data direction of pin 3.
The enabled SCI7 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
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Table 2-50. DDRH Register Field Descriptions (continued)
Field
Description
2
DDRH
Port H data direction—
This register controls the data direction of pin 2.
The enabled SCI7 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
1
DDRH
Port H data direction—
This register controls the data direction of pin 1.
The enabled SCI6 forces the I/O state to be an output. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0
DDRH
Port H data direction—
This register controls the data direction of pin 0.
The enabled SCI6 forces the I/O state to be an input. Depending on the configuration of the enabled routed SPI1
this pin will be forced to be input or output. In those cases the data direction bits will not change. The DDRM bits
revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
2.3.56
Port H Reduced Drive Register (RDRH)
Access: User read/write1
Address 0x0263
7
6
5
4
3
2
1
0
RDRH7
RDRH6
RDRH5
RDRH4
RDRH3
RDRH2
RDRH1
RDRH0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-54. Port H Reduced Drive Register (RDRH)
1
Read: Anytime.
Write: Anytime.
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Table 2-51. RDRH Register Field Descriptions
Field
Description
7-0
RDRH
Port H reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.57
Port H Pull Device Enable Register (PERH)
Access: User read/write1
Address 0x0264
7
6
5
4
3
2
1
0
PERH7
PERH6
PERH5
PERH4
PERH3
PERH2
PERH1
PERH0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-55. Port H Pull Device Enable Register (PERH)
1
Read: Anytime.
Write: Anytime.
Table 2-52. PERH Register Field Descriptions
Field
Description
7-0
PERH
Port H pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.58
Port H Polarity Select Register (PPSH)
Access: User read/write1
Address 0x025D
7
6
5
4
3
2
1
0
PPSH7
PPSH6
PPSH5
PPSH4
PPSH3
PPSH2
PPSH1
PPSH0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-56. Port H Polarity Select Register (PPSH)
1
Read: Anytime.
Write: Anytime.
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Table 2-53. PPSH Register Field Descriptions
Field
Description
7-0
PPSH
Port H pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up
or pull-down device if enabled.
1 A rising edge on the associated Port H pin sets the associated flag bit in the PIFH register. A pull-down device is
connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used
as input.
0 A falling edge on the associated Port H pin sets the associated flag bit in the PIFH register.A pull-up device is
connected to the associated Port H pin, if enabled by the associated bit in register PERH and if the port is used
as input.
2.3.59
Port H Interrupt Enable Register (PIEH)
Read: Anytime.
Access: User read/write1
Address 0x025E
7
6
5
4
3
2
1
0
PIEH7
PIEH6
PIEH5
PIEH4
PIEH3
PIEH2
PIEH1
PIEH0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-57. Port H Interrupt Enable Register (PIEH)
1
Read: Anytime.
Write: Anytime.
Table 2-54. PPSP Register Field Descriptions
Field
7-0
PIEH
2.3.60
Description
Port H interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port H.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
Port H Interrupt Flag Register (PIFH)
Access: User read/write1
Address 0x025F
7
6
5
4
3
2
1
0
PIFH7
PIFH6
PIFH5
PIFH4
PIFH3
PIFH2
PIFH1
PIFH0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-58. Port H Interrupt Flag Register (PIFH)
1
Read: Anytime.
Write: Anytime.
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Table 2-55. PPSP Register Field Descriptions
Field
Description
7-0
PIFH
Port H interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSH register. To clear this flag, write logic level 1 to the corresponding bit in the PIFH register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
2.3.61
Port J Data Register (PTJ)
Access: User read/write1
Address 0x0268
7
6
5
4
3
2
1
0
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
TXCAN4
RXCAN4
—
—
—
—
TXD2
RXD2
SCL0
SDA0
SCL1
SDA1
—
—
—
—
(TXCAN0)
(RXCAN0)
CS2
CS0
—
CS1
—
CS3
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-59. Port J Data Register (PTJ)
1
Read: Anytime.
Write: Anytime.
Table 2-56. PTJ Register Field Descriptions
Field
Description
7-6
PTJ
Port J general purpose input/output data—Data Register
Port J pins 7 and 6 are associated with TXCAN and RXCAN signals of CAN4 and the routed CAN0, as well as with
SCL and SDA signals of IIC0, respectively.
The CAN4 function takes precedence over the IIC0, the routed CAN0 and the general purpose I/O function if the
CAN4 module is enabled. The IIC0 function takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured as
open drain outputs. The routed CAN0 function takes precedence over the general purpose I/O function if the routed
CAN0 module is enabled.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5-4
PTJ
Port J general purpose input/output data—Data Register
This pin is associated with the SCL and SDA signals of IIC1, and with chip select outputs CS2 and CS0, respectivley.
The IIC1 function takes precedence over the chip select and general purpose I/O function if the IIC1 is enabled. The
chip selects take precedence over the general purpose I/O. If the IIC1 module takes precedence the SDA1 and SCL1
outputs are configured as open drain outputs. Refer to IIC section for details.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
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Table 2-56. PTJ Register Field Descriptions (continued)
Field
Description
3
PTJ
Port J general purpose input/output data—Data Register
This pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2
PTJ
Port J general purpose input/output data—Data Register
This pin is associated with the chip select output signal CS2.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
1
PTJ
Port J general purpose input/output data—Data Register
This pin is associated with the TXD signal of SCI2.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTJ
Port J general purpose input/output data—Data Register
This pin is associated with the TXD signal of SCI2 and chip select output CS3. The SCI function takes precedence
over the chip select and general purpose I/O function if the SCI2 is enabled. The chip select takes precedence over
the general purpose I/O.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.62
Port J Input Register (PTIJ)
Access: User read1
Address 0x0269
R
7
6
5
4
3
2
1
0
PTIJ7
PTIJ6
PTIJ5
PTIJ4
PTIJ3
PTIJ2
PTIJ1
PTIJ0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-60. Port J Input Register (PTIJ)
1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-57. PTIJ Register Field Descriptions
Field
Description
7-0
PTIJ
Port J input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
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2.3.63
Port J Data Direction Register (DDRJ)
Access: User read/write1
Address 0x026A
7
6
5
4
3
2
1
0
DDRJ7
DDRJ6
DDRJ5
DDRJ4
DDRJ3
DDRJ2
DDRJ1
DDRJ0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-61. Port J Data Direction Register (DDRJ)
1
Read: Anytime.
Write: Anytime.
Table 2-58. DDRJ Register Field Descriptions
Field
Description
7
DDRJ
Port J data direction—
This register controls the data direction of pin 7.
The enabled CAN4 or routed CAN0 forces the I/O state to be an output. The enabled IIC0 module forces this pin to
be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling
the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
6
DDRJ
Port J data direction—
This register controls the data direction of pin 6.
The enabled CAN4 or routed CAN0 forces the I/O state to be an input. The enabled IIC0 module forces this pin to
be a open drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling
the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
5
DDRJ
Port J data direction—
This register controls the data direction of pin 5.
The enabled CS2 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open
drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O
direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
4
DDRJ
Port J data direction—
This register controls the data direction of pin 4.
The enabled CS0 signal forces the I/O state to be an output. The enabled IIC1 module forces this pin to be a open
drain output. In those cases the data direction bits will not change. The DDRM bits revert to controlling the I/O
direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
3
DDRJ
Port J data direction—
This register controls the data direction of pin 3.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
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Table 2-58. DDRJ Register Field Descriptions (continued)
Field
Description
2
DDRJ
Port J data direction—
This register controls the data direction of pin 2.
The enabled CS1 signal forces the I/O state to be an output. In those cases the data direction bits will not change.
The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
1
DDRJ
Port J data direction—
This register controls the data direction of pin 1.
The enabled SCI2 forces the I/O state to be an output. The DDRM bits revert to controlling the I/O direction of a pin
when the associated peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0
DDRJ
Port J data direction—
This register controls the data direction of pin 0.
The enabled SCI3 or CS3 signal forces the I/O state to be an output. In those cases the data direction bits will not
change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
2.3.64
Port J Reduced Drive Register (RDRJ)
Access: User read/write1
Address 0x026B
7
6
5
4
3
2
1
0
RDRJ7
RDRJ6
RDRJ5
RDRJ4
RDRJ3
RDRJ2
RDRJ1
RDRJ0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-62. Port J Reduced Drive Register (RDRJ)
1
Read: Anytime.
Write: Anytime.
Table 2-59. RDRJ Register Field Descriptions
Field
Description
7-0
RDRJ
Port J reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
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2.3.65
Port J Pull Device Enable Register (PERJ)
Access: User read/write1
Address 0x026C
7
6
5
4
3
2
1
0
PERJ7
PERJ6
PERJ5
PERJ4
PERJ3
PERJ2
PERJ1
PERJ0
1
1
1
1
1
1
1
1
R
W
Reset
Figure 2-63. Port J Pull Device Enable Register (PERJ)
1
Read: Anytime.
Write: Anytime.
Table 2-60. PERJ Register Field Descriptions
Field
Description
7-0
PERJ
Port J pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull device are enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.66
Port J Polarity Select Register (PPSJ)
Access: User read/write1
Address 0x026D
7
6
5
4
3
2
1
0
PPSJ7
PPSJ6
PPSJ5
PPSJ4
PPSJ3
PPSJ2
PPSJ1
PPSJ0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-64. Port J Polarity Select Register (PPSJ)
1
Read: Anytime.
Write: Anytime.
Table 2-61. PPSJ Register Field Descriptions
Field
Description
7-0
PPSJ
Port J pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up
or pull-down device if enabled.
1 A rising edge on the associated Port J pin sets the associated flag bit in the PIFJ register. A pull-down device is
connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as
input.
0 A falling edge on the associated Port J pin sets the associated flag bit in the PIFJ register.A pull-up device is
connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as
input.
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2.3.67
Port J Interrupt Enable Register (PIEJ)
Read: Anytime.
Access: User read/write1
Address 0x026E
7
6
5
4
3
2
1
0
PIEJ7
PIEJ6
PIEJ5
PIEJ4
PIEJ3
PIEJ2
PIEJ1
PIEJ0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-65. Port J Interrupt Enable Register (PIEJ)
1
Read: Anytime.
Write: Anytime.
Table 2-62. PPSP Register Field Descriptions
Field
7-0
PIEJ
2.3.68
Description
Port J interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port J.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
Port J Interrupt Flag Register (PIFJ)
Access: User read/write1
Address 0x026F
7
6
5
4
3
2
1
0
PIFJ7
PIFJ6
PIFJ5
PIFJ4
PIFJ3
PIFJ2
PIFJ1
PIFJ0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-66. Port J Interrupt Flag Register (PIFJ)
1
Read: Anytime.
Write: Anytime.
Table 2-63. PPSP Register Field Descriptions
Field
Description
7-0
PIFJ
Port J interrupt flag—
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the
state of the PPSJ register. To clear this flag, write logic level 1 to the corresponding bit in the PIFJ register. Writing
a 0 has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
0 No active edge pending.
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2.3.69
Port AD0 Data Register 0 (PT0AD0)
Access: User read/write1
Address 0x0270
7
6
5
4
3
2
1
0
PT0AD07
PT0AD06
PT0AD05
PT0AD04
PT0AD03
PT0AD02
PT0AD01
PT0AD00
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-67. Port AD0 Data Register 0 (PT0AD0)
1
Read: Anytime.
Write: Anytime.
Table 2-64. PT0AD0 Register Field Descriptions
Field
Description
7-0
PT0AD0
Port AD0 general purpose input/output data—Data Register
This register is associated with ATD0 analog inputs AN[15:8] on PAD[15:8], respectively.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.70
Port AD0 Data Register 1 (PT1AD0)
Access: User read/write1
Address 0x0271
7
6
5
4
3
2
1
0
PT1AD07
PT1AD06
PT1AD05
PT1AD04
PT1AD03
PT1AD02
PT1AD01
PT1AD00
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-68. Port AD0 Data Register 1 (PT1AD0)
1
Read: Anytime.
Write: Anytime.
Table 2-65. PT1AD0 Register Field Descriptions
Field
Description
7-0
PT1AD0
Port AD0 general purpose input/output data—Data Register
This register is associated with ATD0 analog inputs AN[7:0] on PAD[7:0], respectively.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
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2.3.71
Port AD0 Data Direction Register 0 (DDR0AD0)
Access: User read/write1
Address 0x0272
7
6
5
4
3
2
1
0
DDR0AD07
DDR0AD06
DDR0AD05
DDR0AD04
DDR0AD03
DDR0AD02
DDR0AD01
DDR0AD00
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-69. Port AD0 Data Direction Register 0 (DDR0AD0)
1
Read: Anytime.
Write: Anytime.
Table 2-66. DDR0AD0 Register Field Descriptions
Field
Description
7-0
Port AD0 data direction—
DDR0AD0 This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR0AD0 register.
NOTE
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.72
Port AD0 Data Direction Register 1 (DDR1AD0)
Access: User read/write1
Address 0x0273
7
6
5
4
3
2
1
0
DDR1AD07
DDR1AD06
DDR1AD05
DDR1AD04
DDR1AD03
DDR1AD02
DDR1AD01
DDR1AD00
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-70. Port AD0 Data Direction Register 1 (DDR1AD0)
1
Read: Anytime.
Write: Anytime.
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Table 2-67. DDR1AD0 Register Field Descriptions
Field
Description
7-0
Port AD0 data direction—
DDR1AD0 This register controls the data direction of pins 7 through 0.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD0 registers, when changing the
DDR1AD0 register.
NOTE
To use the digital input function on Port AD0 the ATD Digital Input Enable
Register (ATD0DIEN1) has to be set to logic level “1”.
2.3.73
Port AD0 Reduced Drive Register 0 (RDR0AD0)
Access: User read/write1
Address 0x0274
7
6
5
4
3
2
1
0
RDR0AD07
RDR0AD06
RDR0AD05
RDR0AD04
RDR0AD03
RDR0AD02
RDR0AD01
RDR0AD00
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-71. Port AD0 Reduced Drive Register 0 (RDR0AD0)
1
Read: Anytime.
Write: Anytime.
Table 2-68. RDR0AD0 Register Field Descriptions
Field
Description
7-0
Port AD0 reduced drive—Select reduced drive for Port AD0 outputs
RDR0AD0 This register configures the drive strength of Port AD0 output pins 15 through 8 as either full or reduce. If a pin is
used as input this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
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2.3.74
Port AD0 Reduced Drive Register 1 (RDR1AD0)
Access: User read/write1
Address 0x0275
7
6
5
4
3
2
1
0
RDR1AD07
RDR1AD06
RDR1AD05
RDR1AD04
RDR1AD03
RDR1AD02
RDR1AD01
RDR1AD00
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-72. Port AD0 Reduced Drive Register 1 (RDR1AD0)
1
Read: Anytime.
Write: Anytime.
Table 2-69. RDR1AD0 Register Field Descriptions
Field
Description
7-0
Port AD0 reduced drive—Select reduced drive for Port AD0 outputs
RDR1AD0 This register configures the drive strength of Port AD0 output pins 7 through 0 as either full or reduced. If a pin is
used as input this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.75
Port AD0 Pull Up Enable Register 0 (PER0AD0)
Access: User read/write1
Address 0x0276
7
6
5
4
3
2
1
0
PER0AD07
PER0AD06
PER0AD05
PER0AD04
PER0AD03
PER0AD02
PER0AD01
PER0AD00
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-73. Port AD0 Pull Device Up Register 0 (PER0AD0)
1
Read: Anytime.
Write: Anytime.
Table 2-70. PER0AD0 Register Field Descriptions
Field
Description
7-0
Port AD0 pull device enable—Enable pull devices on input pins
PER0AD0 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
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2.3.76
Port AD0 Pull Up Enable Register 1 (PER1AD0)
Access: User read/write1
Address 0x0277
7
6
5
4
3
2
1
0
PER1AD07
PER1AD06
PER1AD05
PER1AD04
PER1AD03
PER1AD02
PER1AD01
PER1AD00
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-74. Port AD0 Pull Up Enable Register 1 (PER1AD0)
1
Read: Anytime.
Write: Anytime.
Table 2-71. PER1AD0 Register Field Descriptions
Field
Description
7-0
Port AD0 pull device enable—Enable pull devices on input pins
PER1AD0 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.77
Port AD1 Data Register 0 (PT0AD1)
Access: User read/write1
Address 0x0278
7
6
5
4
3
2
1
0
PT0AD17
PT0AD16
PT0AD15
PT0AD14
PT0AD13
PT0AD12
PT0AD11
PT0AD10
AN15
AN14
AN13
AN12
AN11
AN10
AN9
AN8
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-75. Port AD1 Data Register 0 (PT0AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-72. PT0AD1 Register Field Descriptions
Field
Description
7-0
PT0AD1
Port AD1 general purpose input/output data—Data Register
This register is associated with ATD1 analog inputs AN[15:8] on PAD[31:24], respectively.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
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2.3.78
Port AD1 Data Register 1 (PT1AD1)
Access: User read/write1
Address 0x0279
7
6
5
4
3
2
1
0
PT1AD17
PT1AD16
PT1AD15
PT1AD14
PT1AD13
PT1AD12
PT1AD11
PT1AD10
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-76. Port AD1 Data Register 1 (PT1AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-73. PT1AD1 Register Field Descriptions
Field
Description
7-0
PT1AD1
Port AD1 general purpose input/output data—Data Register
This register is associated with ATD1 analog inputs AN[7:0] on PAD[23:16], respectively.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
2.3.79
Port AD1 Data Direction Register 0 (DDR0AD1)
Access: User read/write1
Address 0x027A
7
6
5
4
3
2
1
0
DDR0AD17
DDR0AD16
DDR0AD15
DDR0AD14
DDR0AD13
DDR0AD12
DDR0AD11
DDR0AD10
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-77. Port AD1 Data Direction Register 0 (DDR0AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-74. DDR0AD1 Register Field Descriptions
Field
Description
7-0
Port AD1 data direction—
DDR0AD1 This register controls the data direction of pins 15 through 8.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
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NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR0AD1 register.
NOTE
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
2.3.80
Port AD1 Data Direction Register 1 (DDR1AD1)
Access: User read/write1
Address 0x027B
7
6
5
4
3
2
1
0
DDR1AD17
DDR1AD16
DDR1AD15
DDR1AD14
DDR1AD13
DDR1AD12
DDR1AD11
DDR1AD10
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-78. Port AD1 Data Direction Register 1 (DDR1AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-75. DDR1AD1 Register Field Descriptions
Field
Description
7-0
Port AD1 data direction—
DDR1AD1 This register controls the data direction of pins 7 through 0.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PT0AD1 registers, when changing the
DDR1AD1 register.
NOTE
To use the digital input function on Port AD1 the ATD Digital Input Enable
Register (ATD1DIEN1) has to be set to logic level “1”.
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2.3.81
Port AD1 Reduced Drive Register 0 (RDR0AD1)
Access: User read/write1
Address 0x027C
7
6
5
4
3
2
1
0
RDR0AD17
RDR0AD16
RDR0AD15
RDR0AD14
RDR0AD13
RDR0AD12
RDR0AD11
RDR0AD10
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-79. Port AD1 Reduced Drive Register 0 (RDR0AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-76. RDR0AD1 Register Field Descriptions
Field
Description
7-0
Port AD1 reduced drive—Select reduced drive for Port AD1 outputs
RDR0AD1 This register configures the drive strength of Port AD1 output pins 15 through 8 as either full or reduce. If a pin is
used as input this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.82
Port AD1 Reduced Drive Register 1 (RDR1AD1)
Access: User read/write1
Address 0x027D
7
6
5
4
3
2
1
0
RDR1AD17
RDR1AD16
RDR1AD15
RDR1AD14
RDR1AD13
RDR1AD12
RDR1AD11
RDR1AD10
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-80. Port AD1 Reduced Drive Register 1 (RDR1AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-77. RDR1AD1 Register Field Descriptions
Field
Description
7-0
Port AD1 reduced drive—Select reduced drive for Port AD1 outputs
RDR1AD1 This register configures the drive strength of Port AD1 output pins 7 through 0 as either full or reduced. If a pin is
used as input this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
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2.3.83
Port AD1 Pull Up Enable Register 0 (PER0AD1)
Access: User read/write1
Address 0x027E
7
6
5
4
3
2
1
0
PER0AD17
PER0AD16
PER0AD15
PER0AD14
PER0AD13
PER0AD12
PER0AD11
PER0AD10
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-81. Port AD1 Pull Device Up Register 0 (PER0AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-78. PER0AD1 Register Field Descriptions
Field
Description
7-0
Port AD1 pull device enable—Enable pull devices on input pins
PER0AD1 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.84
Port AD1 Pull Up Enable Register 1 (PER1AD1)
Access: User read/write1
Address 0x027F
7
6
5
4
3
2
1
0
PER1AD17
PER1AD16
PER1AD15
PER1AD14
PER1AD13
PER1AD12
PER1AD11
PER1AD10
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-82. Port AD1 Pull Up Enable Register 1 (PER1AD1)
1
Read: Anytime.
Write: Anytime.
Table 2-79. PER1AD1 Register Field Descriptions
Field
Description
7-0
Port AD1 pull device enable—Enable pull devices on input pins
PER1AD1 These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
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2.3.85
Port R Data Register (PTR)
Access: User read/write1
Address 0x0368
7
6
5
4
3
2
1
0
PTR7
PTR6
PTR5
PTR4
PTR3
PTR2
PTR1
PTR0
TIMIOC7
TIMIOC6
TIMIOC5
TIMIOC4
TIMIOC3
TIMIOC2
TIMIOC1
TIMIOC0
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-83. Port R Data Register (PTR)
1
Read: Anytime.
Write: Anytime.
Table 2-80. PTR Register Field Descriptions
Field
Description
7-0
PTR
Port R general purpose input/output data—Data Register
Port R pins 7 through 0 are associated with TIM channels TIMIOC7 through TIMIOC0.
When not used with the alternative function, these pins can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.86
Port R Input Register (PTIR)
Access: User read1
Address 0x0369
R
7
6
5
4
3
2
1
0
PTIR7
PTIR6
PTIR5
PTIR4
PTIR3
PTIR2
PTIR1
PTIR0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-84. Port R Input Register (PTIR)
1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-81. PTIR Register Field Descriptions
Field
Description
7-0
PTIR
Port R input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
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2.3.87
Port R Data Direction Register (DDRR)
Access: User read/write1
Address 0x036A
7
6
5
4
3
2
1
0
DDRR7
DDRR6
DDRR5
DDRR4
DDRR3
DDRR2
DDRR1
DDRR0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-85. Port R Data Direction Register (DDRR)
1
Read: Anytime.
Write: Anytime.
Table 2-82. DDRR Register Field Descriptions
Field
Description
7-0
DDRR
Port R data direction—
This register controls the data direction of pins 7 through 0.
The TIM forces the I/O state to be an output for each timer port associated with an enabled output compare. In this
case the data direction bits will not change.
The data direction bits revert to controlling the I/O direction of a pin when the associated timer output compare is
disabled.
The timer Input Capture always monitors the state of the pin.
1 Associated pin is configured as output.
0 Associated pin is configured as high-impedance input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTR or PTIR registers, when changing the
DDRR register.
2.3.88
Port R Reduced Drive Register (RDRR)
Access: User read/write1
Address 0x036B
7
6
5
4
3
2
1
0
RDRR7
RDRR6
RDRR5
RDRR4
RDRR3
RDRR2
RDRR1
RDRR0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-86. Port R Reduced Drive Register (RDRR)
1
Read: Anytime.
Write: Anytime.
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Table 2-83. RDRR Register Field Descriptions
Field
Description
7-0
RDRR
Port R reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.89
Port R Pull Device Enable Register (PERR)
Access: User read/write1
Address 0x036C
7
6
5
4
3
2
1
0
PERR7
PERR6
PERR5
PERR4
PERR3
PERR2
PERR1
PERR0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-87. Port R Pull Device Enable Register (PERR)
1
Read: Anytime.
Write: Anytime.
Table 2-84. PERR Register Field Descriptions
Field
Description
7-0
PERR
Port R pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.90
Port R Polarity Select Register (PPSR)
Access: User read/write1
Address 0x036D
7
6
5
4
3
2
1
0
PPSR7
PPSR6
PPSR5
PPSR4
PPSR3
PPSR2
PPSR1
PPSR0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-88. Port R Polarity Select Register (PPSR)
1
Read: Anytime.
Write: Anytime.
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Table 2-85. PPSR Register Field Descriptions
Field
7-0
PPSR
2.3.91
Description
Port R pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
PIM Reserved Register
Access: User read1
Address 0x036E
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-89. PIM Reserved Register
1
Read: Always reads 0x00
Write: Unimplemented
2.3.92
Port R Routing Register (PTRRR)
Access: User read/write1
Address 0x036F
7
6
5
4
3
2
1
0
PTRRR7
PTRRR6
PTRRR5
PTRRR4
PTRRR3
PTRRR2
PTRRR1
PTRRR0
0
0
0
0
0
0
0
0
R
W
Reset
= Unimplemented or Reserved
Figure 2-90. Port R Routing Register (PTRRR)
1
Read: Anytime.
Write: Anytime.
Table 2-86. PTR Routing Register Field Descriptions
Field
Description
7
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC7 is available on PP7
0 TIMIOC7 is available on PR7
6
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC6 is available on PP6
0 TIMIOC6 is available on PR6
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Table 2-86. PTR Routing Register Field Descriptions (continued)
Field
Description
5
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC5 is available on PP5
0 TIMIOC5 is available on PR5
4
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC4 is available on PP4
0 TIMIOC4 is available on PR4
3
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC3 is available on PP3
0 TIMIOC3 is available on PR3
2
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC2 is available on PP2
0 TIMIOC2 is available on PR2
1
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC1 is available on PP1
0 TIMIOC1 is available on PR1
0
PTRRR
Port R routing—
This register configures the re-routing of the associated TIM channel.
1 TIMIOC0 is available on PP0
0 TIMIOC0 is available on PR0
2.3.93
Port L Data Register (PTL)
Access: User read/write1
Address 0x0370
7
6
5
4
3
2
1
0
PTL7
PTLT6
PTL5
PTL4
PTL3
PTL2
PTL1
PTL0
(TXD7)
(RXD7)
(TXD6)
(RXD6)
(TXD5)
(RXD5)
(TXD4)
(RXD4)
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-91. Port L Data Register (PTL)
1
Read: Anytime.
Write: Anytime.
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Table 2-87. PTL Register Field Descriptions
Field
Description
7
PTL
Port L general purpose input/output data—Data Register
Port L pin 7 is associated with the TXD signal of the SCI7 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
6
PTL
Port L general purpose input/output data—Data Register
Port L pin 6 is associated with the RXD signal of the SCI7 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTL
Port L general purpose input/output data—Data Register
Port L pin 5 is associated with the TXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
4
PTL
Port L general purpose input/output data—Data Register
Port L pin 4 is associated with the RXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
3
PTL
Port L general purpose input/output data—Data Register
Port L pin 3 is associated with the TXD signal of the SC5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2
PTL
Port L general purpose input/output data—Data Register
Port L pin 2 is associated with the RXD signal of the SCI5 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
1
PTL
Port L general purpose input/output data—Data Register
Port L pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTL
Port L general purpose input/output data—Data Register
Port L pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
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2.3.94
Port L Input Register (PTIL)
Access: User read1
Address 0x0371
R
7
6
5
4
3
2
1
0
PTIL7
PTIL6
PTIL5
PTIL4
PTIL3
PTIL2
PTIL1
PTIL0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-92. Port L Input Register (PTIL)
1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-88. PTIL Register Field Descriptions
Field
Description
7-0
PTIL
Port L input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.95
Port L Data Direction Register (DDRL)
Access: User read/write1
Address 0x0372
7
6
5
4
3
2
1
0
DDRL7
DDRL6
DDRL5
DDRL4
DDRL3
DDRL2
DDRL1
DDRL0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-93. Port L Data Direction Register (DDRL)
1
Read: Anytime.
Write: Anytime.
Table 2-89. DDRL Register Field Descriptions
Field
Description
7-0
DDRL
Port L data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port L pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
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NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTL or PTIL registers, when changing the
DDRL register.
2.3.96
Port L Reduced Drive Register (RDRL)
Access: User read/write1
Address 0x0373
7
6
5
4
3
2
1
0
RDRL7
RDRL6
RDRL5
RDRL4
RDRL3
RDRL2
RDRL1
RDRL0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-94. Port L Reduced Drive Register (RDRL)
1
Read: Anytime.
Write: Anytime.
Table 2-90. RDRL Register Field Descriptions
Field
Description
7-0
RDRL
Port L reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
2.3.97
Port L Pull Device Enable Register (PERL)
Access: User read/write1
Address 0x0374
7
6
5
4
3
2
1
0
PERL7
PERL6
PERL5
PERL4
PERL3
PERL2
PERL1
PERL0
1
1
1
1
1
1
1
1
R
W
Reset
Figure 2-95. Port L Pull Device Enable Register (PERL)
1
Read: Anytime.
Write: Anytime.
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Table 2-91. PERL Register Field Descriptions
Field
Description
7-0
PERL
Port L pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.98
Port L Polarity Select Register (PPSL)
Access: User read/write1
Address 0x0375
7
6
5
4
3
2
1
0
PPSL7
PPSL6
PPSL5
PPSL4
PPSL3
PPSL2
PPSL1
PPSL0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-96. Port L Polarity Select Register (PPSL)
1
Read: Anytime.
Write: Anytime.
Table 2-92. PPSL Register Field Descriptions
Field
7-0
PPSL
2.3.99
Description
Port L pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
Port L Wired-Or Mode Register (WOML)
Access: User read/write1
Address 0x0376
7
6
5
4
3
2
1
0
WOML7
WOML6
WOML5
WOML4
WOML3
WOML2
WOML1
WOML0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-97. Port L Wired-Or Mode Register (WOML)
1
Read: Anytime.
Write: Anytime.
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Table 2-93. WOML Register Field Descriptions
Field
7-0
WOML
Description
Port L wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or. If enabled the output is driven active low only (open-drain). A
logic level of “1” is not driven.This allows a multipoint connection of several serial modules. These bits have no
influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
2.3.100 Port L Routing Register (PTLRR)
Access: User read/write1
Address 0x0377
7
6
5
4
PTLRR7
PTLRR6
PTLRR5
PTLRR4
0
0
0
0
R
3
2
1
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-98. Port L Routing Register (PTLRR)
1
Read: Anytime.
Write: Anytime.
This register configures the re-routing of SCI7, SCI6, SCI5, and SCI4 on alternative ports.
Table 2-94. Port L Routing Summary
Module
PTLRR
7
SCI7
SCI6
SCI5
SCI4
0
6
5
Related Pins
4
TXD
RXD
PH3
PH2
x
x
x
1
x
x
x
PL7
PL6
x
0
x
x
PH1
PH0
x
1
x
x
PL5
PL4
x
x
0
x
PH7
PH6
x
x
1
x
PL3
PL2
x
x
x
0
PH5
PH4
x
x
x
1
PL1
PL0
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2.3.101 Port F Data Register (PTF)
Access: User read/write1
Address 0x0378
7
6
5
4
3
2
1
0
PTF7
PTFT6
PTF5
PTF4
PTF3
PTF2
PTF1
PTF0
(TXD3)
(RXD3)
(SCL0)
(SDA0)
(CS3)
(CS2)
(CS1)
(CS0)
0
0
0
0
0
0
0
0
R
W
Altern.
Function
Reset
Figure 2-99. Port F Data Register (PTF)
1
Read: Anytime.
Write: Anytime.
Table 2-95. PTF Register Field Descriptions
Field
Description
7
PTF
Port F general purpose input/output data—Data Register
Port F pin 7 is associated with the TXD signal of the SCI3 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
6
PTF
Port F general purpose input/output data—Data Register
Port F pin 6 is associated with the RXD signal of the SCI3 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
5
PTF
Port F general purpose input/output data—Data Register
Port F pin 5 is associated with the TXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
4
PTF
Port F general purpose input/output data—Data Register
Port F pin 4 is associated with the RXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
3
PTF
Port F general purpose input/output data—Data Register
Port F pin 3 is associated with the TXD signal of the SC5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2
PTF
Port F general purpose input/output data—Data Register
Port F pin 2 is associated with the RXD signal of the SCI5 module .
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
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Table 2-95. PTF Register Field Descriptions (continued)
Field
Description
1
PTF
Port F general purpose input/output data—Data Register
Port F pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
0
PTF
Port F general purpose input/output data—Data Register
Port F pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
2.3.102 Port F Input Register (PTIF)
Access: User read1
Address 0x0379
R
7
6
5
4
3
2
1
0
PTIF7
PTIF6
PTIF5
PTIF4
PTIF3
PTIF2
PTIF1
PTIF0
u
u
u
u
u
u
u
u
W
Reset
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-100. Port F Input Register (PTIF)
1
Read: Anytime.
Write:Never, writes to this register have no effect.
Table 2-96. PTIF Register Field Descriptions
Field
Description
7-0
PTIF
Port F input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
2.3.103 Port F Data Direction Register (DDRF)
Access: User read/write1
Address 0x037A
7
6
5
4
3
2
1
0
DDRF7
DDRF6
DDRF5
DDRF4
DDRF3
DDRF2
DDRF1
DDRF0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-101. Port F Data Direction Register (DDRF)
1
Read: Anytime.
Write: Anytime.
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Table 2-97. DDRF Register Field Descriptions
Field
Description
7-0
DDRF
Port F data direction—
This register controls the data direction of pins 7 through 0.This register configures each Port F pin as either input
or output.
If SPI0 is enabled, the SPI0 determines the pin direction. Refer to SPI section for details.
If the associated SCI transmit or receive channel is enabled this register has no effect on the pins. The pin is forced
to be an output if a SCI transmit channel is enabled, it is forced to be an input if the SCI receive channel is enabled.
The data direction bits revert to controlling the I/O direction of a pin when the associated channel is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTF or PTIF registers, when changing the
DDRF register.
2.3.104 Port F Reduced Drive Register (RDRF)
Access: User read/write1
Address 0x037B
7
6
5
4
3
2
1
0
RDRF7
RDRF6
RDRF5
RDRF4
RDRF3
RDRF2
RDRF1
RDRF0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-102. Port F Reduced Drive Register (RDRF)
1
Read: Anytime.
Write: Anytime.
Table 2-98. RDRF Register Field Descriptions
Field
Description
7-0
RDRF
Port F reduced drive—Select reduced drive for outputs
This register configures the drive strength of output pins 7 through 0 as either full or reduced. If a pin is used as input
this bit has no effect.
1 Reduced drive selected (1/6 of the full drive strength).
0 Full drive strength enabled.
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2.3.105 Port F Pull Device Enable Register (PERF)
Access: User read/write1
Address 0x037C
7
6
5
4
3
2
1
0
PERF7
PERF6
PERF5
PERF4
PERF3
PERF2
PERF1
PERF0
1
1
1
1
1
1
1
1
R
W
Reset
Figure 2-103. Port F Pull Device Enable Register (PERF)
1
Read: Anytime.
Write: Anytime.
Table 2-99. PERF Register Field Descriptions
Field
Description
7-0
PERF
Port F pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull devices are enabled.
1 Pull device enabled.
0 Pull device disabled.
2.3.106 Port F Polarity Select Register (PPSF)
Access: User read/write1
Address 0x037D
7
6
5
4
3
2
1
0
PPSF7
PPSF6
PPSF5
PPSF4
PPSF3
PPSF2
PPSF1
PPSF0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 2-104. Port F Polarity Select Register (PPSF)
1
Read: Anytime.
Write: Anytime.
Table 2-100. PPSF Register Field Descriptions
Field
7-0
PPSF
Description
Port F pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
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2.3.107 PIM Reserved Register
Access: User read1
Address 0x037E
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 2-105. PIM Reserved Register
1
Read: Always reads 0x00
Write: Unimplemented
2.3.108 Port F Routing Register (PTFRR)
Access: User read/write1
Address 0x037F
R
7
6
0
0
5
4
3
2
1
0
PTFRR5
PTFRR4
PTFRR3
PTFRR2
PTFRR1
PTFRR0
0
0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 2-106. Port F Routing Register (PTFRR)
1
Read: Anytime.
Write: Anytime.
This register configures the re-routing of SCI3, IIC0, CS[3:0] on alternative ports.
Table 2-101. Port F Routing Summary
Module
PTFRR
5
SCI3
IIC0
4
3
2
Related Pins
1
0
TXD
RXD
0
x
x
x
x
x
PM7
PM6
1
x
x
x
x
x
PF7
PF6
SCL
SDA
x
0
x
x
x
x
PJ7
PJ6
x
1
x
x
x
x
PF5
PF4
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Table 2-101. Port F Routing Summary
Module
PTFRR
Related Pins
CS
CS3
CS2
CS1
CS0
2.4
2.4.1
x
x
0
x
x
x
PJ0
x
x
1
x
x
x
PF3
x
x
x
0
x
x
PJ5
x
x
x
1
x
x
PF2
x
x
x
x
0
x
PJ2
x
x
x
x
1
x
PF1
x
x
x
x
x
0
PJ4
x
x
x
x
x
1
PF0
Functional Description
General
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output from the external bus interface module or a peripheral module or an input to the external bus
interface module or a peripheral module.
2.4.2
Registers
A set of configuration registers is common to all ports with exceptions in the expanded bus interface and
ATD ports (Table 2-102). All registers can be written at any time, however a specific configuration might
not become active.
Example 2-1. Selecting a pull-up device
This device does not become active while the port is used as a push-pull output.
Table 2-102. Register availability per port1
Data
Reduced
Direction
Drive
Pull
Enable
Polarity
Select
WiredOr Mode
Interrupt
Enable
Interrupt
Flag
Routing
yes
-
-
-
-
-
yes
-
-
-
-
-
yes
-
-
-
-
-
-
yes
-
-
-
-
-
-
yes
-
-
-
-
-
-
-
-
-
-
yes
-
-
-
-
yes
yes
-
-
yes
yes
yes
-
-
yes
Port
Data
Input
A
yes
-
yes
B
yes
-
C
yes
-
D
yes
E
yes
K
yes
-
yes
T
yes
yes
yes
yes
yes
S
yes
yes
yes
yes
yes
M
yes
yes
yes
yes
yes
yes
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Table 2-102. Register availability per port1
1
Data
Reduced
Direction
Drive
Port
Data
Input
P
yes
yes
yes
H
yes
yes
yes
Pull
Enable
Polarity
Select
WiredOr Mode
Interrupt
Enable
Interrupt
Flag
Routing
yes
yes
yes
-
yes
yes
-
yes
yes
yes
-
yes
yes
-
J
yes
yes
yes
yes
yes
yes
-
yes
yes
-
AD0
yes
-
yes
yes
yes
-
-
-
-
-
AD1
yes
-
yes
yes
yes
-
-
-
-
-
R
yes
yes
yes
yes
yes
yes
-
-
-
-
L
yes
yes
yes
yes
yes
yes
yes
-
-
yes
F
yes
yes
yes
yes
yes
yes
-
-
-
yes
Each cell represents one register with individual configuration bits
2.4.2.1
Data register (PORTx, PTx)
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration (Figure 2-107).
2.4.2.2
Input register (PTIx)
This is a read-only register and always returns the buffered state of the pin (Figure 2-107).
2.4.2.3
Data direction register (DDRx)
This register defines whether the pin is used as an input or an output.
If a peripheral module controls the pin the contents of the data direction register is ignored (Figure 2-107).
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PTI
0
1
PT
0
PIN
1
DDR
0
1
data out
Module
output enable
module enable
Figure 2-107. Illustration of I/O pin functionality
2.4.2.4
Reduced drive register (RDRx)
If the pin is used as an output this register allows the configuration of the drive strength.
2.4.2.5
Pull device enable register (PERx)
This register turns on a pull-up or pull-down device.
It becomes active only if the pin is used as an input or as a wired-or output.
2.4.2.6
Polarity select register (PPSx)
This register selects either a pull-up or pull-down device if enabled.
It becomes only active if the pin is used as an input. A pull-up device can be activated if the pin is used as
a wired-or output.
2.4.2.7
Wired-or mode register (WOMx)
If the pin is used as an output this register turns off the active high drive. This allows wired-or type
connections of outputs.
2.4.2.8
Interrupt enable register (PIEx)
If the pin is used as an interrupt input this register serves as a mask to the interrupt flag to enable/disable
the interrupt.
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2.4.2.9
Interrupt flag register (PIFx)
If the pin is used as an interrupt input this register holds the interrupt flag after a valid pin event.
2.4.2.10
Module routing register (MODRR, PTRRR, PTLRR, PTFRR)
This register supports the re-routing of the CAN0, CAN4, SPI2-0, SCI7-3, IIC0, TIM and CS[3:0] pins to
alternative ports. This allows a software re-configuration of the pinouts of the different package options
with respect to above peripherals.
2.4.3
Pins and Ports
NOTE
Please refer to the SOC Guide to determine the pin availability in the
different package options.
2.4.3.1
BKGD pin
The BKGD pin is associated with the S12X_BDM and S12X_EBI modules.
During reset, the BKGD pin is used as MODC input.
2.4.3.2
Port A, B
Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O with the external
bus interface. In this case Port A and Port B are associated with the external address bus outputs
ADDR15-ADDR8 and ADDR7-ADDR0, respectively. PB0 is the ADDR0 or UDS output.
2.4.3.3
Port C, D
Port C pins PC[7:0] and Port D pins PD[7:0] can be used for either general-purpose I/O with the external
bus interface. In this case Port C and Port D are associated with the external data bus inputs/outputs
DATA15-DATA8 and DATA7-DATA0, respectively.
These pins are configured for reduced input threshold in certain operating modes (refer to S12X_EBI
section).
2.4.3.4
Port E
Port E is associated with the external bus control outputs RW, LSTRB, LDS and RE, the free-running clock
outputs ECLK and ECLK2X, as well as with the TAGHI, TAGLO, MODA and MODB and interrupt inputs
IRQ and XIRQ.
Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.
Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output
running at the Core Clock rate. The clock output is always enabled in emulation modes.
Port E pin PE[6] an be used for either general-purpose I/O, as TAGHI input or as MODB input during reset.
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Port E pin PE[5] an be used for either general-purpose I/O, as TAGLO input, RE output or as MODB input
during reset.
Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output
running at the Bus Clock rate or at the programmed divided clock rate. The clock output is always enabled
in emulation modes.
Port E pin PE[3] an be used for either general-purpose I/O, as LSTRB or LDS output, or as EROMCTL
input during reset.
Port E pin PE[2] an be used for either general-purpose I/O, or as RW or RE output.
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ
interrupt input. IRQ will be enabled by setting the IRQEN configuration bit (2.3.17/2-112) and clearing
the I-bit in the CPU condition code register. It is inhibited at reset so this pin is initially configured as a
simple input with a pull-up.
Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt input.
XIRQ can be enabled by clearing the X-bit in the CPU condition code register. It is inhibited at reset so
this pin is initially configured as a high-impedance input with a pull-up.
Port E pins PE[5] and PE[6] are configured for reduced input threshold in certain modes (refer to
S12X_EBI section).
2.4.3.5
Port K
Port K pins PK[7:0] can be used for either general-purpose I/O, or with the external bus interface. In this
case Port K pins PK[6:0] are associated with the external address bus outputs ADDR22-ADDR16 and PK7
is associated to the EWAIT input.
Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).
2.4.3.6
Port T
This port is associated with the ECT module.
Port T pins PT[7:0] can be used for either general-purpose I/O, or with the channels of the Enhanced
Capture Timer.
2.4.3.7
Port S
This port is associated with SCI0, SCI1 and SPI0.
Port S pins PS[7:4] can be used either for general-purpose I/O, or with the SPI0 subsystem.
Port S pins PS[3:2] can be used either for general-purpose I/O, or with the SCI1 subsystem.
Port S pins PS[1:0] can be used either for general-purpose I/O, or with the SCI0 subsystem.
The SPI0 pins can be re-routed.
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2.4.3.8
Port M
This port is associated with the SCI3 CAN4-0 and SPI0.
Port M pins PM[7:6] can be used for either general purpose I/O, or with the CAN3 subsystem.
Port M pins PM[5:4] can be used for either general purpose I/O, or with the CAN2 subsystem.
Port M pins PM[3:2] can be used for either general purpose I/O, or with the CAN1 subsystem.
Port M pins PM[1:0] can be used for either general purpose I/O, or with the CAN0 subsystem.
Port M pins PM[5:2] can be used for either general purpose I/O, or with the SPI0 subsystem.
The CAN0, CAN4 and SPI0 pins can be re-routed.
2.4.3.9
Port P
This port is associated with the PWM, SPI1, SPI2 and TIM.
Port P pins PP[7:0] can be used for either general purpose I/O, or with the PWM or with the channels of
the standard Timer.subsystem.
Port P pins PP[7:4] can be used for either general purpose I/O, or with the SPI2 subsystem.
Port P pins PP[3:0] can be used for either general purpose I/O, or with the SPI1 subsystem.
2.4.3.10
Port H
This port is associated with the SPI1, SPI2, and SCI7-4.
Port H pins PH[7:4] can be used for either general purpose I/O, or with the SPI2 subsystem.
Port H pins PH[3:0] can be used for either general purpose I/O, or with the SPI1 subsystem.
Port H pins PH[7:6] can be used for either general purpose I/O, or with the SCI5 subsystem.
Port H pins PH[5:4] can be used for either general purpose I/O, or with the SCI4 subsystem.
Port H pins PH[3:2] can be used for either general purpose I/O, or with the SCI7 subsystem.
Port H pins PH[1:0] can be used for either general purpose I/O, or with the SCI6 subsystem.
2.4.3.11
Port J
This port is associated with the chip selects CS[3:0] as well as with CAN4, CAN0, IIC1, IIC0, and SCI2.
Port J pins PJ[7:6] can be used for either general purpose I/O, or with the CAN4, IIC0 or CAN0
subsystems.
Port J pins PJ[5:4] can be used for either general purpose I/O, or with the IIC1 subsystem or as chip select
outputs.
Port J pin PJ[3] can be used for general purpose I/O.
Port J pin PJ[2] can be used for either general purpose I/O or as chip select output.
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Port J pin PJ[1] can be used for either general purpose I/O, or with the SCI2 subsystem.
Port J pin PJ[0] can be used for either general purpose I/O, or with the SCI2 subsystem or as chip select
output.
2.4.3.12
Port AD0
This port is associated with the ATD0.
Port AD0 pins PAD[15:0] can be used for either general purpose I/O, or with the ATD0 subsystem.
2.4.3.13
Port AD1
This port is associated with the ATD1.
Port AD1 pins PAD[31:16] can be used for either general purpose I/O, or with the ATD1 subsystem.
2.4.3.14
Port R
This port is associated with the TIM module.
Port R pins PR[7:0] can be used for either general-purpose I/O, or with the channels of the standard Timer.
The TIM channels can be re-routed.
2.4.3.15
Port L
This port is associated with SCI7-4.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI7 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with SCI6 subsystem.
Port L pins PL[3:2] can be used for either general purpose I/O, or with SCI5 subsystem.
Port L pins PL[1:0] can be used for either general purpose I/O, or with SCI4 subsystem.
2.4.3.16
Port F
This port is associated with SCI3, IIC0 and chip selects.
Port L pins PL[7:6] can be used for either general purpose I/O, or with SCI3 subsystem.
Port L pins PL[5:4] can be used for either general purpose I/O, or with IIC0 subsystem.
Port L pins PL[3:0] can be used for either general purpose I/O, or with chip selects.
2.4.4
Pin interrupts
Ports P, H and J offer pin interrupt capability. The interrupt enable as well as the sensitivity to rising or
falling edges can be individually configured on per-pin basis. All bits/pins in a port share the same interrupt
vector. Interrupts can be used with the pins configured as inputs or outputs.
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An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. The pin interrupt feature is also capable to wake up the CPU when it is in STOP or
WAIT mode.
A digital filter on each pin prevents pulses (Figure 2-109) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 2-108 and
Table 2-103).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
uncertain
tpign
tpval
Figure 2-108. Interrupt Glitch Filter on Port P, H and J (PPS=0)
Table 2-103. Pulse Detection Criteria
Mode
Pulse
STOP1
STOP
Unit
Ignored
Uncertain
Valid
tpulse ≤ 3
bus clocks
tpulse ≤ tpign
3 < tpulse < 4
bus clocks
tpign < tpulse < tpval
tpulse ≥ 4
bus clocks
tpulse ≥ tpval
1These
values include the spread of the oscillator frequency over temperature, voltage and process.
tpulse
Figure 2-109. Pulse Illustration
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
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The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0).
2.5
2.5.1
Initialization Information
Port Data and Data Direction Register writes
It is not recommended to write PORTx/PTx and DDRx in a word access. When changing the register pins
from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data
register before enabling the outputs.
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Chapter 3
Memory Mapping Control (S12XMMCV4)
Revision History
Rev. No.
(Item No.)
Date (Submitted
By)
v04.04
26-Oct-05
- Reorganization of MEMCTL0 register bits.
v04.05
26-Jul-06
- Updated XGATE Memory Map
v04.06
15-Nov-06
- Adding AUTOSAR Compliance concerning illegal CPU accesses
3.1
Sections
Affected
Substantial Change(s)
Introduction
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X
platform. The block diagram of the MMC is shown in Figure 3-1.
The MMC module controls the multi-master priority accesses, the selection of internal resources and
external space. Internal buses, including internal memories and peripherals, are controlled in this module.
The local address space for each master is translated to a global memory space.
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3.1.1
Terminology
Table 3-1. Acronyms and Abbreviations
Logic level “1”
Voltage that corresponds to Boolean true state
Logic level “0”
Voltage that corresponds to Boolean false state
0x
Represents hexadecimal number
x
Represents logic level ’don’t care’
byte
8-bit data
word
16-bit data
local address
based on the 64 KBytes Memory Space (16-bit address)
global address
based on the 8 MBytes Memory Space (23-bit address)
Aligned address
Address on even boundary
Mis-aligned address
Address on odd boundary
Bus Clock
expanded modes
single-chip modes
Normal Single-Chip Mode
Special Single-Chip Mode
emulation modes
Emulation Single-Chip Mode
Emulation Expanded Mode
normal modes
Normal Single-Chip Mode
Normal Expanded Mode
special modes
Special Single-Chip Mode
Special Test Mode
NS
Normal Single-Chip Mode
SS
Special Single-Chip Mode
NX
Normal Expanded Mode
ES
Emulation Single-Chip Mode
EX
Emulation Expanded Mode
ST
Special Test Mode
Unimplemented areas
External Space
external resource
3.1.2
System Clock. Refer to CRG Block Guide.
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented
Area which is accessible in the global address range 14_0000 to 3F_FFFF
Resources (Emulator, Application) connected to the MCU via the external bus on
expanded modes (Unimplemented areas and External Space)
PRR
Port Replacement Registers
PRU
Port Replacement Unit located on the emulator side
MCU
MicroController Unit
NVM
Non-volatile Memory; Flash EEPROM or ROM
Features
The main features of this block are:
• Paging capability to support a global 8 Mbytes memory address space
• Bus arbitration between the masters CPU, BDM and XGATE
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•
•
•
•
•
•
•
•
Simultaneous accesses to different resources1 (internal, external, and peripherals) (see Figure 3-1 )
Resolution of target bus access collision
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
3.1.3
S12X Memory Mapping
The S12X architecture implements a number of memory mapping schemes including
• a CPU 8 MByte global map, defined using a global page (GPAGE) register and dedicated 23-bit
address load/store instructions.
• a BDM 8 MByte global map, defined using a global page (BDMGPR) register and dedicated 23-bit
address load/store instructions.
• a (CPU or BDM) 64 KByte local map, defined using specific resource page (RPAGE, EPAGE and
PPAGE) registers and the default instruction set. The 64 KBytes visible at any instant can be
considered as the local map accessed by the 16-bit (CPU or BDM) address.
• The XGATE 64 Kbyte local map.
The MMC module performs translation of the different memory mapping schemes to the specific global
(physical) memory implementation.
3.1.4
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the MMC.
3.1.4.1
•
•
•
Run mode
MMC is functional during normal run mode.
Wait mode
MMC is functional during wait mode.
Stop mode
MMC is inactive during stop mode.
3.1.4.2
•
Power Saving Modes
Functional Modes
Single chip modes
1. Resources are also called targets.
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In normal and special single chip mode the internal memory is used. External bus is not active.
Expanded modes
Address, data, and control signals are activated in normal expanded and special test modes when
accessing the external bus. Access to internal resources will not cause activity on the external bus.
Emulation modes
External bus is active to emulate, via an external tool, the normal expanded or the normal single
chip mode.}
•
•
3.1.5
Block Diagram
Figure 3-11 shows a block diagram of the MMC.
BDM
CPU
XGATE
FLEXRAY
EEEPROM
MMC
FLASH
Address Decoder & Priority
DBG
Target Bus Controller
EBI
RAM
Peripherals
Figure 3-1. MMC Block Diagram
3.2
External Signal Description
The user is advised to refer to the SoC Guide for port configuration and location of external bus signals.
Some pins may not be bonded out in all implementations.
Table 3-2 and Table 3-3 outline the pin names and functions. It also provides a brief description of their
operation.
Table 3-2. External Input Signals Associated with the MMC
Signal
I/O
Description
Availability
MODC
I
Mode input
Latched after
RESET (active low)
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
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Table 3-2. External Input Signals Associated with the MMC
Signal
I/O
Description
Availability
MODB
I
Mode input
Latched after
RESET (active low)
MODA
I
Mode input
Latched after
RESET (active low)
EROMCTL
I
EROM control input
Latched after
RESET (active low)
ROMCTL
I
ROM control input
Latched after
RESET (active low)
Table 3-3. External Output Signals Associated with the MMC
Available in Modes
Signal
I/O
Description
NS
CS0
O
Chip select line 0
CS1
O
Chip select line 1
CS2
O
Chip select line 2
CS3
O
Chip select line 3
SS
NX
ES
EX
ST
(see Table 3-4)
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3.3
3.3.1
Memory Map and Registers
Module Memory Map
A summary of the registers associated with the MMC block is shown in Figure 3-2. Detailed descriptions
of the registers and bits are given in the subsections that follow.
Address
Register
Name
0x000A
MMCCTL0
R
W
0x000B
MODE
R
W
0x0010
GPAGE
R
Bit 7
6
5
4
3
2
1
Bit 0
CS3E1
CS3E0
CS2E1
CS2E0
CS1E1
CS1E0
CS0E1
CS0E0
MODC
MODB
MODA
0
0
0
0
0
GP6
GP5
GP4
GP3
GP2
GP1
GP0
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
0
0
0
0
0
0
0
0
0
W
0x0011
DIRECT
R
W
0x0012
Reserved
R
W
0x0013
MMCCTL1
R
W
0x0014
Reserved
R
TGMRAMON
0
EEEIFRON PGMIFRON RAMHM
EROMON ROMHM
ROMON
0
0
0
0
0
0
0
0
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
W
0x0015
PPAGE
R
W
0x0016
RPAGE
R
W
0x0017
EPAGE
R
W
= Unimplemented or Reserved
Figure 3-2. MMC Register Summary
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3.3.2
Register Descriptions
3.3.2.1
MMC Control Register (MMCCTL0)
Address: 0x000A PRR
R
W
Reset
7
6
5
4
3
2
1
0
CS3E1
CS3E0
CS2E1
CS2E0
CS1E1
CS1E0
CS0E1
CS0E0
0
0
0
0
0
0
0
ROMON1
1. ROMON is bit[0] of the register MMCTL1 (see Figure 3-10)
= Unimplemented or Reserved
Figure 3-3. MMC Control Register (MMCCTL0)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data is read from this register.
Write: Anytime. In emulation modes write operations will also be directed to the external bus.
Table 3-4. Chip Selects Function Activity
Chip Modes
Register Bit
NS
CS0E[1:0], CS1E[1:0],
CS2E[1:0], CS3E[1:0]
1
2
Disabled1
SS
Disabled
NX
Enabled
2
ES
EX
ST
Disabled
Enabled
Disabled
Disabled: feature always inactive.
Enabled: activity is controlled by the appropriate register bit value.
The MMCCTL0 register is used to control external bus functions, like:
• Availability of chip selects. (See Table 3-4 and Table 3-5)
• Control of different external stretch mechanism. For more detail refer to the S12X_EBI
BlockGuide.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
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Table 3-5. MMCCTL0 Field Descriptions
Field
Description
7–6
CS3E[1:0]
Chip Select 3 Enables — These bits enable the external chip select CS3 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 3-6 and
Figure 3-17.
Chip select 3 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 3 is disabled
01,10,11 Chip select 3 is enabled
5–4
CS2E[1:0]
Chip Select 2 Enables — These bits enable the external chip select CS2 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 3-6 and
Figure 3-17.
Chip select 2 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 2 is disabled
01,10,11 Chip select 2 is enabled
3–2
CS1E[1:0]
Chip Select 1 Enables — These bits enable the external chip select CS1 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 3-6 and
Figure 3-17.
Chip select 1 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 1 is disabled
01,10,11 Chip select 1 is enabled
1–0
CS0E[1:0]
Chip Select 0 Enables — These bits enable the external chip select CS0 output which is asserted during
accesses to specific external addresses. The associated global address range is shown in Table 3-6 and
Figure 3-17.
Chip select 0 is only active if enabled in Normal Expanded mode, Emulation Expanded mode.
The function disabled in all other operating modes.
00
Chip select 0 is disabled
01,10,11 Chip select 0 is enabled
Table 3-6 shows the address boundaries of each chip select and the relationship with the implemented
resources (internal) parameters.
Table 3-6. Global Chip Selects Memory Space
Chip Selects
Bottom Address
Top Address
CS3
0x00_0800
0x0F_FFFF minus RAMSIZE1
CS22
0x14_0000
0x1F_FFFF
CS1
0x20_0000
0x3F_FFFF
CS03
0x40_0000
0x7F_FFFF minus FLASHSIZE4
1
External RPAGE accesses in (NX, EX)
When ROMHM is set (see ROMHM in Table 3-15) the CS2 is asserted in the space occupied by this on-chip
memory block.
3 When the internal NVM is enabled (see ROMON in Section 3.3.2.5, “MMC Control Register (MMCCTL1))
the CS0 is not asserted in the space occupied by this on-chip memory block.
4 External PPAGE accesses in (NX, EX)
2
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3.3.2.2
Mode Register (MODE)
Address: 0x000B PRR
7
R
W
Reset
6
5
MODC
MODB
MODA
MODC1
MODB1
MODA1
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
1. External signal (see Table 3-2).
= Unimplemented or Reserved
Figure 3-4. Mode Register (MODE)
Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all
other modes the data are read from this register.
Write: Only if a transition is allowed (see Figure 3-5). In emulation modes write operations will be also
directed to the external bus.
The MODE bits of the MODE register are used to establish the MCU operating mode.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Table 3-7. MODE Field Descriptions
Field
Description
7–5
MODC,
MODB,
MODA
Mode Select Bits — These bits control the current operating mode during RESET high (inactive). The external
mode pins MODC, MODB, and MODA determine the operating mode during RESET low (active). The state of
the pins is latched into the respective register bits after the RESET signal goes inactive (see Figure 3-4).
Write restrictions exist to disallow transitions between certain modes. Figure 3-5 illustrates all allowed mode
changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to
these register bits except in special modes.
Both transitions from normal single-chip mode to normal expanded mode and from emulation single-chip to
emulation expanded mode are only executed by writing a value of 3’b101 (write once). Writing any other value
will not change the MODE bits, but will block further writes to these register bits.
Changes of operating modes are not allowed when the device is secured, but it will block further writes to these
register bits except in special modes.
In emulation modes reading this address returns data from the external bus which has to be driven by the
emulator. It is therefore responsibility of the emulator hardware to provide the expected value (i.e. a value
corresponding to normal single chip mode while the device is in emulation single-chip mode or a value
corresponding to normal expanded mode while the device is in emulation expanded mode).
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RESET
010
Special
Test
(ST)
010
1
1
10
0
10
Normal
Expanded
(NX)
101
Emulation
Single-Chip
(ES)
001
Emulation
Expanded
(EX)
011
101
10
1
011
RESET
0
10
RESET
RESET
000
001
101
101
010
110
111
Normal
Single-Chip
(NS)
100
1
00
01
RESET
100
1
01
1
00
Special
Single-Chip
(SS)
000
000
RESET
Transition done by external pins (MODC, MODB, MODA)
RESET
Transition done by write access to the MODE register
110
111
Illegal (MODC, MODB, MODA) pin values.
Do not use. (Reserved for future use).
Figure 3-5. Mode Transition Diagram when MCU is Unsecured
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3.3.2.3
Global Page Index Register (GPAGE)
Address: 0x0010
7
R
0
W
Reset
0
6
5
4
3
2
1
0
GP6
GP5
GP4
GP3
GP2
GP1
GP0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 3-6. Global Page Index Register (GPAGE)
Read: Anytime
Write: Anytime
The global page index register is used to construct a 23 bit address in the global map format. It is only used
when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,
GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global
address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see
Figure 3-7).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
Bit22
Bit16 Bit15
GPAGE Register [6:0]
Bit 0
CPU Address [15:0]
Figure 3-7. GPAGE Address Mapping
Table 3-8. GPAGE Field Descriptions
Field
Description
6–0
GP[6:0]
Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is
to be accessed.
Example 3-1. This example demonstrates usage of the GPAGE register
LDX
MOVB
GLDAA
#0x5000
#0x14, GPAGE
X
;Set GPAGE offset to the value of 0x5000
;Initialize GPAGE register with the value of 0x14
;Load Accu A from the global address 0x14_5000
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3.3.2.4
Direct Page Register (DIRECT)
Address: 0x0011
R
W
7
6
5
4
3
2
1
0
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
0
0
0
0
0
0
0
0
Reset
Figure 3-8. Direct Register (DIRECT)
Read: Anytime
Write: anytime in special modes, one time only in other modes.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both
global and local mapping scheme.
Table 3-9. DIRECT Field Descriptions
Field
Description
7–0
DP[15:8]
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. The bits from this register form bits [15:8] of the address (see Figure 3-9).
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
Bit16 Bit15
Bit22
Bit8
Bit7
Bit0
DP [15:8]
CPU Address [15:0]
Figure 3-9. DIRECT Address Mapping
Bits [22:16] of the global address will be formed by the GPAGE[6:0] bits in case the CPU executes a global
instruction in direct addressing mode or by the appropriate local address to the global address expansion
(refer to Section 3.4.2.1.1, “Expansion of the Local Address Map).
Example 3-2. This example demonstrates usage of the Direct Addressing Mode
MOVB
#0x80,DIRECT
;Set DIRECT register to 0x80. Write once only.
;Global data accesses to the range 0xXX_80XX can be direct.
;Logical data accesses to the range 0x80XX are direct.
LDY
<00
;Load the Y index register from 0x8000 (direct access).
;< operator forces direct access on some assemblers but in
;many cases assemblers are “direct page aware” and can
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;automatically select direct mode.
3.3.2.5
MMC Control Register (MMCCTL1)
Address: 0x0013 PRR
7
R
W
6
0
TGMRAMON
Reset
0
0
5
4
3
2
1
0
EEEIFRON
PGMIFRON
RAMHM
EROMON
ROMHM
ROMON
0
0
0
EROMCTL
0
ROMCTL
= Unimplemented or Reserved
Figure 3-10. MMC Control Register (MMCCTL1)
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.
Write: Refer to each bit description. In emulation modes write operations will also be directed to the
external bus.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Table 3-10. MMCCTL1 Field Descriptions
Field
Description
7
EEE Tag RAM and FTM SCRATCH RAM visible in the memory map
TGMRAMON Write: Anytime
This bit is used to made the EEE Tag RAM nd FTM SCRATCH RAM visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
5
EEEIFRON
EEE IFR visible in the memory map
Write: Anytime
This bit is used to made the IFR sector of EEE DATA FLASH visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
4
Program IFR visible in the memory map
PGMIFRON Write: Anytime
This bit is used to made the IFR sector of the Program Flash visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
3
RAMHM
RAM only in higher Half of the memory map
Write: Once in normal and emulation modes and anytime in special modes
0 Accesses to $4000–$7FFF will be mapped to $14_4000-$14_7FFF in the global memory space (external
access).
1 Accesses to $4000–$7FFF will be mapped to $0F_C000-$0F_FFFF in the global memory space (RAM area).
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Table 3-10. MMCCTL1 Field Descriptions (continued)
Field
2
EROMON
Description
Enables emulated Flash or ROM memory in the memory map
Write: Never
This bit is used in some modes to define the placement of the Emulated Flash or ROM (Refer to Table 3-11)
0 Disables the emulated Flash or ROM in the memory map.
1 Enables the emulated Flash or ROM in the memory map.
1
ROMHM
FLASH or ROM only in higher Half of Memory Map
Write: Once in normal and emulation modes and anytime in special modes
0 The fixed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to
0x4000–0x7FFF will be mapped to 0x7F_4000-0x7F_7FFF in the global memory space.
1 Disables access to the Flash or ROM in the lower half of the memory map.These physical locations of the
Flash or ROM can still be accessed through the program page window. Accesses to 0x4000–0x7FFF will be
mapped to 0x14_4000-0x14_7FFF in the global memory space (external access).
0
ROMON
Enable FLASH or ROM in the memory map
Write: Once in normal and emulation modes and anytime in special modes.
This bit is used in some modes to define the placement of the ROM (Refer to Table 3-11)
0 Disables the Flash or ROM from the memory map.
1 Enables the Flash or ROM in the memory map.
EROMON and ROMON control the visibility of the Flash in the memory map for CPU or BDM (not for
XGATE). Both local and global memory maps are affected.
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Table 3-11. Data Sources when CPU or BDM is Accessing Flash Area
Chip Modes
ROMON
EROMON
DATA SOURCE1
Stretch2
Normal Single Chip
X
X
Internal Flash
N
X
0
Emulation Memory
N
X
1
Internal Flash
0
X
External Application
Y
1
X
Internal Flash
N
0
X
External Application
Y
1
0
Emulation Memory
N
1
1
Internal Flash
0
X
External Application
1
X
Internal Flash
Special Single Chip
Emulation Single Chip
Normal Expanded
Emulation Expanded
Special Test
N
1
Internal Flash means Flash resources inside the MCU are read/written.
Emulation memory means resources inside the emulator are read/written (PRU registers, flash
replacement, RAM, EEPROM and register space are always considered internal).
External application means resources residing outside the MCU are read/written.
2
The external access stretch mechanism is part of the EBI module (refer to EBI Block Guide for details).
3.3.2.6
Program Page Index Register (PPAGE)
Address: 0x0015
R
W
Reset
7
6
5
4
3
2
1
0
PIX7
PIX6
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
1
1
1
1
1
1
1
0
Figure 3-11. Program Page Index Register (PPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local
(CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see Figure 3-12). This supports
accessing up to 4 Mbytes of Flash (in the Global map) within the 64 KByte Local map. The PPAGE register
is effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions..
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
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Global Address [22:0]
1
Bit21
Bit0
Bit14 Bit13
PPAGE Register [7:0]
Address [13:0]
Address: CPU Local Address
or BDM Local Address
Figure 3-12. PPAGE Address Mapping
NOTE
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
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Table 3-12. PPAGE Field Descriptions
Field
7–0
PIX[7:0]
Description
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
The fixed 16K page from 0x4000–0x7FFF (when ROMHM = 0) is the page number 0xFD.
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and
0xFFFF out of reset.
The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF.
3.3.2.7
RAM Page Index Register (RPAGE)
Address: 0x0016
R
W
Reset
7
6
5
4
3
2
1
0
RP7
RP6
RP5
RP4
RP3
RP2
RP1
RP0
1
1
1
1
1
1
0
1
Figure 3-13. RAM Page Index Register (RPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 4 KByte blocks into the RAM page window located in the local
(CPU or BDM) memory map from address 0x1000 to address 0x1FFF (see Figure 3-14). This supports
accessing up to 1022 KByte of RAM (in the Global map) within the 64 KByte Local map. The RAM page
index register is effectively used to construct paged RAM addresses in the Local map format.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
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Global Address [22:0]
0
0
0
Bit19 Bit18
Bit12 Bit11
Bit0
Address [11:0]
RPAGE Register [7:0]
Address: CPU Local Address
or BDM Local Address
Figure 3-14. RPAGE Address Mapping
NOTE
Because RAM page 0 has the same global address as the register space, it is
possible to write to registers through the RAM space when RPAGE = 0x00.
Table 3-13. RPAGE Field Descriptions
Field
Description
7–0
RP[7:0]
RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
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3.3.2.8
EEPROM Page Index Register (EPAGE)
Address: 0x0017
R
W
7
6
5
4
3
2
1
0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
1
1
1
1
1
1
1
0
Reset
Figure 3-15. EEPROM Page Index Register (EPAGE)
Read: Anytime
Write: Anytime
These eight index bits are used to page 1 KByte blocks into the EEPROM page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see Figure 3-16). This supports
accessing up to 256 KByte of EEPROM (in the Global map) within the 64 KByte Local map. The
EEPROM page index register is effectively used to construct paged EEPROM addresses in the Local map
format.
CAUTION
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Global Address [22:0]
0
0
1
0
0
Bit17 Bit16
Bit10 Bit9
Bit0
Address [9:0]
EPAGE Register [7:0]
Address: CPU Local Address
or BDM Local Address
Figure 3-16. EPAGE Address Mapping
Table 3-14. EPAGE Field Descriptions
Field
7–0
EP[7:0]
Description
EEPROM Page Index Bits 7–0 — These page index bits are used to select which of the 256 EEPROM array
pages is to be accessed in the EEPROM Page Window.
The reset value of 0xFE ensures that there is a linear EEPROM space available between addresses 0x0800
and 0x0FFF out of reset.
The fixed 1K page 0x0C00–0x0FFF of EEPROM is equivalent to page 255 (page number 0xFF).
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3.4
Functional Description
The MMC block performs several basic functions of the S12X sub-system operation: MCU operation
modes, priority control, address mapping, select signal generation and access limitations for the system.
Each aspect is described in the following subsections.
3.4.1
•
•
•
MCU Operating Mode
Normal single-chip mode
There is no external bus in this mode. The MCU program is executed from the internal memory
and no external accesses are allowed.
Special single-chip mode
This mode is generally used for debugging single-chip operation, boot-strapping or security related
operations. The active background debug mode is in control of the CPU code execution and the
BDM firmware is waiting for serial commands sent through the BKGD pin. There is no external
bus in this mode.
Emulation single-chip mode
Tool vendors use this mode for emulation systems in which the user’s target application is normal
single-chip mode. Code is executed from external or internal memory depending on the set-up of
the EROMON bit (see Section 3.3.2.5, “MMC Control Register (MMCCTL1)). The external bus
is active in both cases to allow observation of internal operations (internal visibility).
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•
•
•
Normal expanded mode
The external bus interface is configured as an up to 23-bit address bus, 8 or 16-bit data bus with
dedicated bus control and status signals. This mode allows 8 or 16-bit external memory and
peripheral devices to be interfaced to the system. The fastest external bus rate is half of the internal
bus rate. An external signal can be used in this mode to cause the external bus to wait as desired by
the external logic.
Emulation expanded mode
Tool vendors use this mode for emulation systems in which the user’s target application is normal
expanded mode.
Special test mode
This mode is an expanded mode for factory test.
3.4.2
3.4.2.1
Memory Map Scheme
CPU and BDM Memory Map Scheme
The BDM firmware lookup tables and BDM register memory locations share addresses with other
modules; however they are not visible in the memory map during user’s code execution. The BDM
memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish
between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block
Guide for further details).
When the MCU enters active BDM mode, the BDM firmware lookup tables and the BDM registers
become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x7F_FF00 0x7F_FFFF) and the CPU begins execution of firmware commands or the BDM begins execution of
hardware commands. The resources which share memory space with the BDM module will not be visible
in the memory map during active BDM mode.
Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM
registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value
of 0xFF.
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CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
2K REGISTERS
0x00_0800
2K RAM
RAM
253*4K paged
0x0800
0x0C00
0x1000
0x0F_E000
2K REGISTERS
8K RAM
1K EEPROM window
EPAGE
0x10_0000
1K EEPROM
EEPROM
255*1K paged
RPAGE
4K RAM window
0x2000
8K RAM
0x4000
0x13_FC00
256 Kilobytes
0x0000
1M minus 2 Kilobytes
0x00_1000
1K EEPROM
0x14_0000
2.75 Mbytes
Unpaged
16K FLASH
External
Space
0x8000
16K FLASH window
PPAGE
0x40_0000
0xC000
0xFFFF
Reset Vectors
0x7F_4000
0x7F_8000
0x7F_C000
16K FLASH
(PPAGE 0xFD)
4 Mbytes
FLASH
253 *16K paged
Unpaged
16K FLASH
16K FLASH
(PPAGE 0xFE)
16K FLASH
(PPAGE 0xFF)
0x7F_FFFF
Figure 3-17. Expansion of the Local Address Map
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3.4.2.1.1
Expansion of the Local Address Map
Expansion of the CPU Local Address Map
The program page index register in MMC allows accessing up to 4 Mbyte of FLASH or ROM in the global
memory map by using the eight page index bits to page 256 16 Kbyte blocks into the program page
window located from address 0x8000 to address 0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions
(see Section 3.5.1, “CALL and RTC Instructions).
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64-kilobyte local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper
16-kilobyte block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that
all reset and interrupt vectors point to locations in this area or to the other unpaged sections of the local
CPU memory map.
Table 3-15 summarizes mapping of the address bus in Flash/External space based on the address, the
PPAGE register value and value of the ROMHM bit in the MMCCTL1 register.
Table 3-15. Global FLASH/ROM Allocated
Local
CPU Address
ROMHM
External
Access
Global Address
0x4000–0x7FFF
0
No
0x7F_4000 –0x7F_7FFF
1
Yes
0x14_4000–0x14_7FFF
N/A
No1
0x40_0000–0x7F_FFFF
N/A
Yes1
N/A
No
0x8000–0xBFFF
0xC000–0xFFFF
1
0x7F_C000–0x7F_FFFF
The internal or the external bus is accessed based on the size of the memory resources
implemented on-chip. Please refer to Figure 1-23 for further details.
The RAM page index register allows accessing up to 1 Mbyte –2 Kbytes of RAM in the global memory
map by using the eight RPAGE index bits to page 4 Kbyte blocks into the RAM page window located in
the local CPU memory space from address 0x1000 to address 0x1FFF. The EEPROM page index register
EPAGE allows accessing up to 256 Kbytes of EEPROM in the system by using the eight EPAGE index
bits to page 1 Kbyte blocks into the EEPROM page window located in the local CPU memory space from
address 0x0800 to address 0x0BFF.
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Expansion of the BDM Local Address Map
PPAGE, RPAGE, and EPAGE registers are also used for the expansion of the BDM local address to the
global address. These registers can be read and written by the BDM.
The BDM expansion scheme is the same as the CPU expansion scheme.
3.4.2.2
Global Addresses Based on the Global Page
CPU Global Addresses Based on the Global Page
The seven global page index bits allow access to the full 8 Mbyte address map that can be accessed with
23 address bits. This provides an alternative way to access all of the various pages of FLASH, RAM and
EEE as well as additional external memory.
The GPAGE Register is used only when the CPU is executing a global instruction (see Section 3.3.2.3,
“Global Page Index Register (GPAGE)). The generated global address is the result of concatenation of the
CPU local address [15:0] with the GPAGE register [22:16] (see Figure 3-7).
BDM Global Addresses Based on the Global Page
The seven BDMGPR Global Page index bits allow access to the full 8 Mbyte address map that can be
accessed with 23 address bits. This provides an alternative way to access all of the various pages of
FLASH, RAM and EEE as well as additional external memory.
The BDM global page index register (BDMGPR) is used only in the case the CPU is executing a firmware
command which uses a global instruction (like GLDD, GSTD) or by a BDM hardware command (like
WRITE_W, WRITE_BYTE, READ_W, READ_BYTE). See the BDM Block Guide for further details.
The generated global address is a result of concatenation of the BDM local address with the BDMGPR
register [22:16] in the case of a hardware command or concatenation of the CPU local address and the
BDMGPR register [22:16] in the case of a firmware command (see Figure 3-18).
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BDM HARDWARE COMMAND
Global Address [22:0]
Bit22
Bit16 Bit15
BDMGPR Register [6:0]
Bit0
BDM Local Address
BDM FIRMWARE COMMAND
Global Address [22:0]
Bit22
Bit16 Bit15
BDMGPR Register [6:0]
Bit0
CPU Local Address
Figure 3-18. BDMGPR Address Mapping
3.4.2.3
Implemented Memory Map
The global memory spaces reserved for the internal resources (RAM, EEE, and FLASH) are not
determined by the MMC module. Size of the individual internal resources are however fixed in the design
of the device cannot be changed by the user. Please refer to the Device User Guide for further details.
Figure 3-19 and Table 3-16 show the memory spaces occupied by the on-chip resources. Please note that
the memory spaces have fixed top addresses.
Table 3-16. Global Implemented Memory Space
1
2
Internal Resource
$Address
RAM
RAM_LOW = 0x10_0000 minus RAMSIZE1
FLASH
FLASH_LOW = 0x80_0000 minus FLASHSIZE2
RAMSIZE is the hexadecimal value of RAM SIZE in bytes
FLASHSIZE is the hexadecimal value of FLASH SIZE in bytes
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When the device is operating in expanded modes except emulation single-chip mode, accesses to global
addresses which are not occupied by the on-chip resources (unimplemented areas or external memory
space) result in accesses to the external bus (see Figure 3-19).
In emulation single-chip mode, accesses to global addresses which are not occupied by the on-chip
resources (unimplemented areas) result in accesses to the external bus. CPU accesses to global addresses
which are occupied by external memory space result in an illegal access reset (system reset) in case of no
MPU error. BDM accesses to the external space are performed but the data will be undefined.
In single-chip modes accesses by the CPU (except for firmware commands) to any of the unimplemented
areas (see Figure 3-19) will result in an illegal access reset (system reset) in case of no MPU error. BDM
accesses to the unimplemented areas are allowed but the data will be undefined.
No misaligned word access from the BDM module will occur; these accesses are blocked in the BDM
module (Refer to BDM Block Guide).
Misaligned word access to the last location of RAM is performed but the data will be undefined.
Misaligned word access to the last location of any global page (64 Kbyte) by any global instruction, is
performed by accessing the last byte of the page and the first byte of the same page, considering the above
mentioned misaligned access cases.
The non-internal resources (unimplemented areas or external space) are used to generate the chip selects
(CS0,CS1,CS2 and CS3) (see Figure 3-19), which are only active in normal expanded, emulation
expanded (see Section 3.3.2.1, “MMC Control Register (MMCCTL0)).
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CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_07FF
2K REGISTERS
CS3
Unimplemented
RAM
0x0000
0x0800
0x0C00
0x1000
RAM
2K REGISTERS
1K EEPROM window
EPAGE
RAMSIZE
RAM_LOW
0x0F_FFFF
1K EEPROM
4K RAM window
RPAGE
0x2000
256 K EEEPROM
8K RAM
0x4000
0x13_FFFF
CS2
Unpaged
16K FLASH
0x1F_FFFF
External
Space
CS1
0x8000
PPAGE
0x3F_FFFF
0xC000
CS0
16K FLASH window
Unimplemented
FLASH
Unpaged
16K FLASH
Reset Vectors
FLASH_LOW
FLASH
FLASHSIZE
0xFFFF
0x7F_FFFF
Figure 3-19. S12XE CPU & BDM Global Address Mapping
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3.4.2.4
XGATE Memory Map Scheme
3.4.2.4.1
Expansion of the XGATE Local Address Map
The XGATE 64 Kbyte memory space allows access to internal resources only (Registers, RAM, and
FLASH). The 2 Kilobyte register address range is the same register address range as for the CPU and the
BDM module (see Table 3-17).
XGATE can access the FLASH in single chip modes, even when the MCU is secured. In expanded modes,
XGATE can not access the FLASH when MCU is secured.
The local address of the XGATE RAM access is translated to the global RAM address range. The XGATE
shares the RAM resource with the CPU and the BDM module (see Table 3-17).
XGATE RAM size (XGRAMSIZE) may be lower or equal to the MCU RAM size (RAMSIZE).In case of
XGATE RAM size less than 32 Kbytes (see Figure 3-20), the gap in the xgate local memory map will
result in an illegal RAM access (see Section 3.4.3.1, “Illegal XGATE Accesses)
The local address of the XGATE FLASH access is always translated to the global address 0x78_0800 0x78_7FFF.
Example 3-3. is a general example of the XGATE memory map implementation.
Table 3-17. XGATE Implemented Memory Space
1
Internal Resource
$Address
XGATE RAM
XGRAM_LOW = 0x0F_0000 plus (0x1_0000 minus XGRAMSIZE)1
XGRAMSIZE is the hexadecimal value of XGATE RAM SIZE in bytes.
Example 3-3.
The MCU FLASHSIZE is 64 Kbytes (0x10000) and MCU RAMSIZE is 32 Kbytes (0x8000).
The XGATE RAMSIZE is 16 Kbytes (0x4000).
The space occupied by the XGATE RAM in the global address space will be:
Bottom address: (0x10_0000 minus 0x4000) = 0x0F_C000
Top address: 0x0F_FFFF
XGATE accesses to local address range 0x0800–0x7FFF will result always in accesses to the
following FLASH block in the global address space:
Bottom address: 0x78_0800
Top address: 0x78_7FFF
The gap range in the local memory map 0x8000–0xBFFF will be translated in the global address
space:
0x0F_8000 - 0x0F_BFFF (illegal xgate access to system RAM).
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XGATE
Local Memory Map
Global Memory Map
0x00_0000
Registers
0x00_07FF
XGRAM_LOW
0x0800
RAM
0x0F_FFFF
RAMSIZE
Registers
XGRAMSIZE
0x0000
FLASH
0x7FFF
XGRAMSIZE
Unimplemented
area
RAM
0x78_0800
0xFFFF
FLASHSIZE
FLASH
0x78_7FFF
0x7F_FFFF
Figure 3-20. XGATE Global Address Mapping
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3.4.2.5
Memory Configuration
Two bits in the MMCCTL1 register (ROMHM, RAMHM) configure the mapping of the local address
(0x4000-0x7FFF) in the global memory map.
ROMHM, RAMHM are write once in normal and emulation modes and anytime in special modes.
Three areas are identified (See Figure 3-21):
• Program FLASH (0x7F_4000-0x7F_7FFF) when ROMHM = 0.
• External Space (0x14_4000-0x14_7FFF) when ROMHM = 1 and RAMHM = 0.
• XSRAM Space (0x0F_C000-0x0F_FFFF) when ROMHM = 1 and RAMHM = 1.
Table 3-18 shows the translation from the local memory map to the global memory map taking in
consideration the different configurations of ROMHM and RAMHM.
Table 3-18. ROMHM and RAMHM Address Location
Local Address
0x4000 - 0x7FFF
0x2000 - 0x3FFF
0x2000 - 0x3FFF
ROMHM
RAMHM
Global Address
Location
0
X
0x7F_4000 - 0x7F_7FFF
Internal Flash
1
0
0x14_4000 - 0x14_7FFF
External Space
0x0F_C000 - 0x0F_FFFF
Bottom of the Implemented RAM
1
1
0x0F_A000 - 0x0F_BFFF
Fixed up to 8K RAM
1
0
0x0F_E000 - 0x0F_FFFF
Fixed up to 8K RAM
Table 3-19 describes the application note of the RAM configuration and its dedicated global address.
Table 3-19. RAM Configuration
phase
RPAGE
ROMHM
RAMHM
RAM AREA
Global Address
After reset
RPAGE = 0xFD
(Reset value)
0
0
12 Kilobytes
0x0F_D000 - 0x0F_FFFF
During setup
RPAGE = 0xFD
(Reset value)
1
1
24 Kilobytes
0x0F_A000 - 0x0F_FFFF
(0x00 <= RPAGE <= 0xF9)
1
1
28 Kilobytes
0x00_0000 - 0x0F_9FFF
(0xFA <= RPAGE <= 0xFF)
1
1
24 Kilobytes
0x0F_A000 - 0x0F_FFFF
Normal Operation
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CPU and BDM
Local Memory Map
Global Memory Map
0x00_0000
0x00_0800
2K REGISTERS
2K RAM
RAM
251*4K paged
0x0F_A000
8K RAM
0x0800
0x0C00
0x1000
2K REGISTERS
1K EEPROM window
16K RAM
0x10_0000
1K EEPROM
EEPROM
255*1K paged
4K RAM window
0x2000
8K RAM
0x4000
0x13_FC00
256 Kilobytes
0x0000
ROMHM RAMHM
0x0F_C000
1
1
1M minus 2 Kilobytes
0x00_1000
1K EEPROM
1
16K External
0
0x8000
External
Space
2.75 Mbytes
0x14_0000
ROMHM RAMHM 0x14_4000
16K FLASH window
0x40_0000
0xC000
0xFFFF
Reset Vectors
ROMHM RAMHM
0x7F_4000
0
16K FLASH
x
0x7F_8000
0x7F_C000
4 Mbytes
FLASH
253 *16K paged
Unpaged
16K FLASH
16K FLASH
(PPAGE 0xFE)
16K FLASH
(PPAGE 0xFF)
0x7F_FFFF
Figure 3-21. ROMHM, RAMHM Memory Configuration
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3.4.2.5.1
System XSRAM
System XSRAM has two ways to be accessed by the CPU. One is by the programming of RPAGE and the
fixed XSRAM areas configured by the values of ROMHM, RAMHM, or by the usage of the global
instruction and the usage of GPAGE.
Figure 3-22 shows the memory map for the implemented XSRAM. The size of the implemented XSRAM
is done by the device definition and denoted by RAMSIZE.
RAM Area in the Memory Map
ROMHM = 1 RAMHM = 0
0x00_0000
0x00_07FF
ROMHM = 0 RAMHM = X
ROMHM = 1 RAMHM = 1
REG. Area
0x00_0800
0x00_0800
Unimplemented
RAM
RAM Area
Unimplemented
RAM
0x0F_FFFF
0x0F_A000
EEPROM Area
RAMSIZE
8K RAM
0x13_FFFF
0x0F_C000
16K RAM
0x0F_E000
External
Space Area
8K RAM
0x0F_FFFF
0x0F_FFFF
0x3F_FFFF
FLASH Area
0x7F_FFFF
Figure 3-22. S12XE System RAM in the Memory Map
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3.4.3
Chip Access Restrictions
CPU and XGATE accesses are watched in the memory protection unit (See MPU Block Guide). In case of
access violation, the suspect master is acknowledged with an indication of an error; the victim target will
not be accessed.
Other violations MPU is not handling are listed below.
3.4.3.1
Illegal XGATE Accesses
A possible access error is flagged by the MMC and signalled to XGATE under the following conditions:
• XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).
• XGATE accesses the register space (in case of opcode or vector fetch).
• XGATE performs a write to Flash in any modes (in case of load-store access).
• XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode
or vector fetch accesses).
For further details refer to the XGATE Block Guide.
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3.4.4
Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 3-231).
DBG
XGATE
BDM
CPU
XGATE
FLEXRAY
S12X1
S12X0
S12X2
MMC “Crossbar Switch”
EBI
XBUS0
XBUS1
BLKX
XBUS3
FTM
FLASH
EEE
XRAM
BDM
resources
XSRAM
XBUS2
IPBI
Figure 3-23. MMC Block Diagram
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
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3.4.4.1
Master Bus Prioritization regarding access conflicts on Target Buses
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
• CPU always has priority over BDM and XGATE.
• XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
for its duration.
• XGATE has priority over BDM.
• BDM has priority over CPU and XGATE when its access is stalled for more than 128 cycles. In the
later case the suspect master will be stalled after finishing the current operation and the BDM will
gain access to the bus.
• In emulation modes all internal accesses are visible on the external bus as well and the external bus
is used during access to the PRU registers.
3.5
3.5.1
Initialization/Application Information
CALL and RTC Instructions
CALL and RTC instructions are uninterruptable CPU instructions that automate page switching in the
program page window. The CALL instruction is similar to the JSR instruction, but the subroutine that is
called can be located anywhere in the local address space or in any Flash or ROM page visible through the
program page window. The CALL instruction calculates and stacks a return address, stacks the current
PPAGE value and writes a new instruction-supplied value to the PPAGE register. The PPAGE value
controls which of the 256 possible pages is visible through the 16 Kbyte program page window in the
64 Kbyte local CPU memory map. Execution then begins at the address of the called subroutine.
During the execution of the CALL instruction, the CPU performs the following steps:
1. Writes the current PPAGE value into an internal temporary register and writes the new
instruction-supplied PPAGE value into the PPAGE register
2. Calculates the address of the next instruction after the CALL instruction (the return address) and
pushes this 16-bit value onto the stack
3. Pushes the temporarily stored PPAGE value onto the stack
4. Calculates the effective address of the subroutine, refills the queue and begins execution at the new
address
This sequence is uninterruptable. There is no need to inhibit interrupts during the CALL instruction
execution. A CALL instruction can be performed from any address to any other address in the local CPU
memory space.
The PPAGE value supplied by the instruction is part of the effective address of the CPU. For all addressing
mode variations (except indexed-indirect modes) the new page value is provided by an immediate operand
in the instruction. In indexed-indirect variations of the CALL instruction a pointer specifies memory
locations where the new page value and the address of the called subroutine are stored. Using indirect
addressing for both the new page value and the address within the page allows usage of values calculated
at run time rather than immediate values that must be known at the time of assembly.
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The RTC instruction terminates subroutines invoked by a CALL instruction. The RTC instruction unstacks
the PPAGE value and the return address and refills the queue. Execution resumes with the next instruction
after the CALL instruction.
During the execution of an RTC instruction the CPU performs the following steps:
1. Pulls the previously stored PPAGE value from the stack
2. Pulls the 16-bit return address from the stack and loads it into the PC
3. Writes the PPAGE value into the PPAGE register
4. Refills the queue and resumes execution at the return address
This sequence is uninterruptable. The RTC can be executed from anywhere in the local CPU memory
space.
The CALL and RTC instructions behave like JSR and RTS instruction, they however require more
execution cycles. Usage of JSR/RTS instructions is therefore recommended when possible and
CALL/RTC instructions should only be used when needed. The JSR and RTS instructions can be used to
access subroutines that are already present in the local CPU memory map (i.e. in the same page in the
program memory page window for example). However calling a function located in a different page
requires usage of the CALL instruction. The function must be terminated by the RTC instruction. Because
the RTC instruction restores contents of the PPAGE register from the stack, functions terminated with the
RTC instruction must be called using the CALL instruction even when the correct page is already present
in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time
of the RTC instruction execution.
3.5.2
Port Replacement Registers (PRRs)
Registers used for emulation purposes must be rebuilt by the in-circuit emulator hardware to achieve full
emulation of single chip mode operation. These registers are called port replacement registers (PRRs) (see
Table 1-25). PRRs are accessible from CPU, BDM and XGATE using different access types (word
aligned, word-misaligned and byte).
Each access to PRRs will be extended to 2 bus cycles for write or read accesses independent of the
operating mode. In emulation modes all write operations result in simultaneous writing to the internal
registers (peripheral access) and to the emulated registers (external access) located in the PRU in the
emulator. All read operations are performed from external registers (external access) in emulation modes.
In all other modes the read operations are performed from the internal registers (peripheral access).
Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses:
• An aligned word access to a PRR will take 2 bus cycles.
• A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
• A byte access to a PRR will take 2 cycles.
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Table 3-20. PRR Listing
PRR Name
PRR Local Address
PRR Location
PORTA
0x0000
PIM
PORTB
0x0001
PIM
DDRA
0x0002
PIM
DDRB
0x0003
PIM
PORTC
0x0004
PIM
PORTD
0x0005
PIM
DDRC
0x0006
PIM
DDRD
0x0007
PIM
PORTE
0x0008
PIM
DDRE
0x0009
PIM
MMCCTL0
0x000A
MMC
MODE
0x000B
MMC
PUCR
0x000C
PIM
RDRIV
0x000D
PIM
EBICTL0
0x000E
EBI
EBICTL1
0x000F
EBI
Reserved
0x0012
MMC
MMCCTL1
0x0013
MMC
ECLKCTL
0x001C
PIM
Reserved
0x001D
PIM
PORTK
0x0032
PIM
DDRK
0x0033
PIM
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3.5.3
On-Chip ROM Control
The MCU offers two modes to support emulation. In the first mode (called generator) the emulator
provides the data instead of the internal FLASH and traces the CPU actions. In the other mode (called
observer) the internal FLASH provides the data and all internal actions are made visible to the emulator.
3.5.3.1
ROM Control in Single-Chip Modes
In single-chip modes the MCU has no external bus. All memory accesses and program fetches are internal
(see Figure 3-24).
No External Bus
MCU
Flash
Figure 3-24. ROM in Single Chip Modes
3.5.3.2
ROM Control in Emulation Single-Chip Mode
In emulation single-chip mode the external bus is connected to the emulator. If the EROMON bit is set,
the internal FLASH provides the data and the emulator can observe all internal CPU actions on the external
bus. If the EROMON bit is cleared, the emulator provides the data (generator) and traces the all CPU
actions (see Figure 3-25).
Observer
Emulator
MCU
Flash
EROMON = 1
Generator
MCU
Emulator
Flash
EROMON = 0
Figure 3-25. ROM in Emulation Single-Chip Mode
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3.5.3.3
ROM Control in Normal Expanded Mode
In normal expanded mode the external bus will be connected to the application. If the ROMON bit is set,
the internal FLASH provides the data. If the ROMON bit is cleared, the application memory provides the
data (see Figure 3-26).
MCU
Application
Memory
Flash
ROMON = 1
MCU
Application
Memory
ROMON = 0
Figure 3-26. ROM in Normal Expanded Mode
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3.5.3.4
ROM Control in Emulation Expanded Mode
In emulation expanded mode the external bus will be connected to the emulator and to the application. If
the ROMON bit is set, the internal FLASH provides the data. If the EROMON bit is set as well the
emulator observes all CPU internal actions, otherwise the emulator provides the data and traces all CPU
actions (see Figure 3-27). When the ROMON bit is cleared, the application memory provides the data and
the emulator will observe the CPU internal actions (see Figure 3-28).
Observer
MCU
Emulator
Flash
Application
Memory
EROMON = 1
Generator
MCU
Emulator
Flash
Application
Memory
EROMON = 0
Figure 3-27. ROMON = 1 in Emulation Expanded Mode
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Observer
MCU
Emulator
Application
Memory
Figure 3-28. ROMON = 0 in Emulation Expanded Mode
3.5.3.5
ROM Control in Special Test Mode
In special test mode the external bus is connected to the application. If the ROMON bit is set, the internal
FLASH provides the data, otherwise the application memory provides the data (see Figure 3-29).
Application
MCU
Memory
ROMON = 0
Application
MCU
Flash
Memory
ROMON = 1
Figure 3-29. ROM in Special Test Mode
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Chapter 4
Memory Protection Unit (S12XMPUV1)
Table 4-1. Revision History
Version
Number
Revision
Date
Effective
Date
01.04
14 Sep
2005
14 Sep
2005
- added note to only use the CPU to clear the AE flag.
- added disclaimer to avoid changing descriptors while they are in
use because of other bus-masters doing accesses
01.05
14 Mar
2006
14 Mar
2006
- clarified that interrupt generation is independent of AEF bit state
- corrected preliminary statement about execution of violating
accesses
01.06
09 Oct
2006
09 Oct
2006
- made Revision History entries public
4.1
Author
Description of Changes
Introduction
The MPU module provides basic functionality required to protect memory mapped resources from
undesired accesses. Multiple address range comparators compare memory accesses against eight memory
protection descriptors located in the MPU module to determine if each access is valid or not. The
comparison is sensitive to which bus master generates the access and the type of the access.
The MPU module can be used to isolate memory ranges accessible by different bus masters. It can be also
be used by an operating system or software kernel to isolate the regions of memory “legally” available to
specific software tasks, with the kernel re-configuring the task specific memory protection descriptors in
supervisor state during task-switching.
4.1.1
Preface
The following terms and abbreviations are used in the document.
Table 4-2. Terminology
Term
MCU
MPU
CPU
XGATE
supervisor state
user state
Meaning
Micro-Controller Unit
Memory Protection Unit
S12X Central Processing Unit (see S12XCPU Reference Manual)
XGATE Co-processor (see XGATE chapter)
refers to the supervisor state of the S12XCPU (see S12XCPU Reference Manual)
refers to the user state of the S12XCPU (see S12XCPU Reference Manual)
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4.1.2
Overview
The MPU module monitors the bus activity of each bus master. The data describing each access is fed into
multiple address range comparators. The output of the comparators is used to determine if a particular
access is allowed or represents an access violation. If an access violation caused by the S12X CPU is
detected, the MPU module raises an access violation interrupt. If the MPU module detects an access
violation caused by a bus master other than the S12X CPU, it flags an access error condition to the
respective master. In addition to the restrictions defined for memory ranges in the MPU descriptors,
accesses to memory not covered by any MPU descriptor (even read accesses!) are considered access
violations.
Figure 4-1 shows a block diagram of the MPU module.
MPU
Bus Interface
Access Validation
Protection
Descriptors
Bus Interface
Bus Interface
Access Validation
Comparators
Bus Interface
Access Validation
Bus Interface
Op-code Fetch
MPU Monitoring
Bus Interface
Data Access
CPU
Protection
Descriptors
Op-code Fetch
MPU Monitoring
Comparators
Data Access
XGATE
Data Access
“Master3”
Comparators
MPU Monitoring
Status
Registers
MMC
Access Violation
Interrupt
Figure 4-1. Block Diagram
4.1.3
•
Features
Protects memory from undesired accesses coming from up to 3 bus masters1
1. Master 3 can be implemented or left out depending the chip configuration. Please refer to the Device Reference Manual for
information about the availability and function of Master 3.
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•
•
•
4.1.4
Eight memory protection descriptors
— each descriptor can cover the full global memory map (8 MBytes)
— each descriptor has a granularity of 8 Bytes
Each descriptor can be configured to allow one of four types of access privilege for the defined
memory region
— Bus master has full access (read, write and execute enabled)
— Bus master can read and execute (write illegal)
— Bus master can read and write (execution illegal)
— Bus master can only read (write and execution illegal)
Accesses to memory not covered by any protection descriptor will cause an access violation
Modes of Operation
The MPU module can be used in all MCU modes.
4.2
External Signal Description
The MPU module has no external signals.
4.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the MPU module.
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Chapter 4 Memory Protection Unit (S12XMPUV1)
4.3.1
Register Descriptions
This section describes in address order all the MPU module registers and their individual bits.
Register
Name
0x0000
MPUFLG
Bit 7
R
W
0x0001
MPUASTAT0
W
0x0002
MPUASTAT1
W
0x0003
MPUASTAT2
R
W
R
R
R
W
0x0007
MPUDESC11
W
0x0008
MPUDESC21
W
0x000B
MPUDESC51
3
2
1
Bit 0
WPF
NEXF
0
0
0
0
SVSF
0
0
0
0
ADDR[22:16]
ADDR[15:8]
ADDR[7:0]
W
0x0005
MPUSEL
0x000A
MPUDESC41
4
R
W
0x0009
MPUDESC31
5
R
0x0004
Reserved
0x0006
MPUDESC01
AEF
6
0
SVSEN
MSTR0
0
0
0
0
0
0
0
0
MSTR1
MSTR2
MSTR3
R
W
R
W
R
W
LOW_ADDR[22:19]
LOW_ADDR[18:11]
R
R
SEL[2:0]
LOW_ADDR[10:3]
WP
NEX
0
0
HIGH_ADDR[22:19]
HIGH_ADDR[18:11]
HIGH_ADDR[10:3]
= Unimplemented or Reserved
1
The module addresses 0x0006−0x000B represent a window in the register map through which different descriptor registers
are visible.
Figure 4-2. MPU Register Summary
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4.3.1.1
MPU Flag Register (MPUFLG)
Address: Module Base + 0x0000
7
R
W
Reset
AEF
0
6
5
4
3
2
1
0
WPF
NEXF
0
0
0
0
SVSF
0
0
0
0
0
0
0
Figure 4-3. MPU Flag Register (MPUFLG)
Read: Anytime
Write: Write of 1 clears flag, write of 0 ignored
Table 4-3. MPUFLG Field Descriptions
Field
Description
7
AEF
Access Error Flag — This bit is the CPU access error interrupt flag. It is set if a CPU access violation has
occurred. At the same time this bit is set, all the other status flags in this register and the access violation
address bits in the MPUASTATn registers are captured. Clear this flag by writing a one.
Note: If a CPU access error is flagged and both the WPF bit and the NEXF bit are zero, the access violation
was caused by an access to memory not covered by the MPU descriptors.
Note: While this bit is set, the CPU in supervisor state (“Master 0”) can read from and write to the peripheral
register space even if there is no memory protection descriptor explicitly allowing this. This is to prevent
the case that the CPU cannot clear the AEF bit if the registers are write protected for the CPU in
supervisor state.
Note: This bit should only be cleared by an access from the S12X CPU. Otherwise, when using one of the
other masters (such as the XGATE) to clear this bit, the status flags and the address status registers
may not get updated correctly if a CPU access causes a violation in the same bus cycle.
6
WPF
Write-Protect Violation Flag — This flag is set if the current CPU access violation has occurred because of
an attempt to write to memory configured as read-only. The WPF bit is read-only; it will be automatically
updated when the next access violation is flagged with the AEF bit.
5
NEXF
No-Execute Violation Flag — This bit is set if the current CPU access violation has occurred because of an
attempt to fetch code from memory configured as No-Execute. The NEXF bit is read-only; it will be
automatically updated when the next access violation is flagged with the AEF bit.
0
SVSF
Supervisor State Flag — This bit is set if the current CPU access violation occurred while the CPU was in
supervisor state. This bit is cleared if the current CPU access violation occurred while the CPU was in user
state. The supervisor state flag is read-only; it will be automatically updated when the next CPU access
violation is flagged with the AEF bit.
If the AEF bit is set further violations are not captured into the MPU status registers. The status of the AEF
bit has no effect on the access restrictions, i.e. access restrictions for all masters are still enforced if the
AEF bit is set. Also, the non-maskable hardware interrupt for violating accesses coming from the S12X
CPU is generated regardless of the state of the AEF bit.
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4.3.1.2
MPU Address Status Register 0 (MPUASTAT0)
Address: Module Base + 0x0001
7
R
6
5
4
0
3
2
1
0
0
0
0
ADDR[22:16]
W
Reset
0
0
0
0
0
Figure 4-4. MPU Address Status Register 0 (MPUASTAT0)
Read: Anytime
Write: Never
Table 4-4. MPUASTAT0 Field Descriptions
Field
Description
6–0
Access violation address bits — The ADDR[22:16] bits contain bits [22:16] of the global address which
ADDR[22:16] caused the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the
MPUFLG register is not set.
4.3.1.3
MPU Address Status Register 1 (MPUASTAT1)
Address: Module Base + 0x0002
7
6
5
4
R
3
2
1
0
0
0
0
0
ADDR[15:8]
W
Reset
0
0
0
0
Figure 4-5. MPU Address Status Register 1 (MPUASTAT1)
Read: Anytime
Write: Never
Table 4-5. MPUASTAT1 Field Descriptions
Field
Description
7–0
ADDR[15:8]
Access violation address bits — The ADDR[15:8] bits contain bits [15:8] of the global address which caused
the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the MPUFLG
register is not set.
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4.3.1.4
MPU Address Status Register 2 (MPUASTAT2)
Address: Module Base + 0x0003
7
6
5
4
R
3
2
1
0
0
0
0
0
ADDR[7:0]
W
Reset
0
0
0
0
Figure 4-6. MPU Address Status Register (MPUASTAT2)
Read: Anytime
Write: Never
Table 4-6. MPUASTAT2 Field Descriptions
Field
Description
7–0
ADDR[7:0]
Access violation address bits — The ADDR[7:0] bits contain bits [7:0] of the global address which caused
the current access violation interrupt. These bits are undefined if the access error flag bit (AEF) in the MPUFLG
register is not set.
4.3.1.5
MPU Descriptor Select Register (MPUSEL)
Address: Module Base + 0x0005
7
R
W
Reset
SVSEN
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
SEL[2:0]
0
0
0
Figure 4-7. MPU Descriptor Select Register (MPUSEL)
Read: Anytime
Write: Anytime
Table 4-7. MPUSEL Field Descriptions
Field
Description
7
SVSEN
MPU supervisor state enable bit — This bit enables the memory protection for the CPU in supervisor state.
If this bit is cleared, the MPU does not affect any accesses coming from the CPU in supervisor state. This is to
prevent the CPU from locking out itself while configuring the protection descriptors (during initialization after a
system reset and during the update of the protection descriptors for a task switch). The memory protection
functionality for the other bus-masters is unaffected by this bit.
0 MPU is disabled for the CPU in supervisor state
1 MPU is enabled for the CPU in supervisor state
2–0
SEL[2:0]
Descriptor select bits — The SEL[2:0] bits select which descriptor is visible in the MPU Descriptor Register
window (MPUDESC0—MPUDESC5).
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4.3.1.6
MPU Descriptor Register 0 (MPUDESC0)
Address: Module Base + 0x0006
R
W
Reset
1
2
7
6
5
4
3
MSTR0
MSTR1
MSTR2
MSTR3
11
11
11
12
2
1
0
LOW_ADDR[22:19]
0
0
0
0
initialized as set for descriptor 0 only, cleared for all others
initialized as set for descriptor 0 only, if MSTR3 is implemented on the device
Figure 4-8. MPU Descriptor Register 0 (MPUDESC0)
Read: Anytime
Write: Anytime
Table 4-8. MPUDESC0 Field Descriptions
Field
Description
7
MSTR0
Master 0 select bit — If this bit is set the descriptor is valid for bus master 0 (CPU in supervisor state).
6
MSTR1
Master 1 select bit — If this bit is set the descriptor is valid for bus master 1 (CPU in user state).
5
MSTR2
Master 2 select bit — If this bit is set the descriptor is valid for bus master 2 (XGATE).
4
MSTR3
Master 3 select bit — If this bit is set the descriptor is valid for bus master 3.
3–0
Memory range lower boundary address bits — The LOW_ADDR[22:19] bits represent bits [22:19] of the
LOW_ADDR[ global memory address that is used as the lower boundary for the described memory range.
22:19]
A descriptor can be configured as valid for more than one bus-master at the same time by setting multiple
Master select bits to one. Setting all Master select bits of a descriptor to zero disables the descriptor.
4.3.1.7
MPU Descriptor Register 1 (MPUDESC1)
Address: Module Base + 0x0007
7
6
5
R
3
2
1
0
0
0
0
LOW_ADDR[18:11]
W
Reset
4
0
0
0
0
0
Figure 4-9. MPU Descriptor Register 1 (MPUDESC1)
Read: Anytime
Write: Anytime
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Table 4-9. MPUDESC1 Field Descriptions
Field
Description
7–0
Memory range lower boundary address bits — The LOW_ADDR[18:11] bits represent bits [18:11] of the
LOW_ADDR[ global memory address that is used as the lower boundary for the described memory range.
18:11]
4.3.1.8
MPU Descriptor Register 2 (MPUDESC2)
Address: Module Base + 0x0008
7
6
5
R
3
2
1
0
0
0
0
LOW_ADDR[10:3]
W
Reset
4
0
0
0
0
0
Figure 4-10. MPU Descriptor Register 2 (MPUDESC2)
Read: Anytime
Write: Anytime
Table 4-10. MPUDESC2 Field Descriptions
Field
Description
7–0
Memory range lower boundary address bits — The LOW_ADDR[10:3] bits represent bits [10:3] of the global
LOW_ADDR[ memory address that is used as the lower boundary for the described memory range.
10:3]
4.3.1.9
MPU Descriptor Register 3 (MPUDESC3)
Address: Module Base + 0x0009
7
R
W
Reset
6
WP
NEX
0
0
5
4
0
0
0
0
3
2
1
0
HIGH_ADDR[22:19]
1
1
1
1
Figure 4-11. MPU Descriptor Register 3 (MPUDESC3)
Read: Anytime
Write: Anytime
Table 4-11. MPUDESC3 Field Descriptions
Field
Description
7
WP
Write-Protect bit — The WP bit causes the described memory range to be treated as write-protected. If this
bit is set every attempt to write in the described memory range causes an access violation.
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Field
Description
6
NEX
No-Execute bit — The NEX bit prevents the described memory range from being used as code memory. If this
bit is set every Op-code fetch in this memory range causes an access violation.
3–0
Memory range upper boundary address bits — The HIGH_ADDR[22:19] bits represent bits [22:19] of the
HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range.
22:19]
4.3.1.10
MPU Descriptor Register 4 (MPUDESC4)
Address: Module Base + 0x000A
7
6
5
R
3
2
1
0
1
1
1
HIGH_ADDR[18:11]
W
Reset
4
1
1
1
1
1
Figure 4-12. MPU Descriptor Register 4 (MPUDESC4)
Read: Anytime
Write: Anytime
Table 4-12. MPUDESC4 Field Descriptions
Field
Description
7–0
Memory range upper boundary address bits — The HIGH_ADDR[18:11] bits represent bits [18:11] of the
HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range.
18:11]
4.3.1.11
MPU Descriptor Register 5 (MPUDESC5)
Address: Module Base + 0x000B
7
6
5
R
3
2
1
0
1
1
1
HIGH_ADDR[10:3]
W
Reset
4
1
1
1
1
1
Figure 4-13. MPU Descriptor Register 5 (MPUDESC5)
Read: Anytime
Write: Anytime
Table 4-13. MPUDESC5 Field Descriptions
Field
Description
7–0
Memory range upper boundary address bits — The HIGH_ADDR[10:3] bits represent bits [10:3] of the
HIGH_ADDR[ global memory address that is used as the upper boundary for the described memory range.
10:3]
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4.4
Functional Description
The MPU module provides memory protection for accesses coming from multiple masters in the system.
This is done by monitoring bus traffic of each master and compare this with the configuration information
from a set of eight programmable descriptors located in the MPU module. If the MPU module detects an
access violation caused by the S12X CPU, it will assert the CPU access violation interrupt signal. If the
MPU module detects an access violation caused by a bus master other than the S12X CPU, it raises an
access error signal. Please refer to the documentation chapter of the individual master modules (i.e.
XGATE, etc.) for more information about the access error condition.
Violating accesses are not executed. The return value of a violating read access is undefined for both 8 bit
and 16 bit accesses.
NOTE
Accesses from BDM are not restricted. BDM hardware accesses always
bypass the MPU module. During execution of BDM firmware code S12X
CPU accesses are masked from the MPU module as well.
4.4.1
Protection Descriptors
Each of the eight protection descriptors can be used to restrict the allowed types of memory accesses for
a given memory range. Each of these memory ranges can cover up the entire 23 bits global memory range
(8 MBytes).
The descriptors are banked in the MPU module register map.
Each descriptor can be selected for modifying using the SEL bits in the MPU Descriptor Select (MPUSEL)
register.
Table 4-14 gives an overview of the types of accesses that can be configured using the protection
descriptors.
Table 4-14. Access Types
WP
NEX
Meaning
0
0
read, write and execute
0
1
read, write
1
0
read and execute
1
1
read only
The granularity of each descriptor is 8 bytes. This means the protection comparators in the MPU module
cover only address bits [22:3] of each access. The lower address bits [2:0] are ignored.
NOTE
A mis-aligned word access to the upper boundary address of a descriptor is
always flagged as an access violation.
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Chapter 4 Memory Protection Unit (S12XMPUV1)
NOTE
Configuring the lower boundary address of a descriptor to be higher than the
upper boundary address of a descriptor causes this descriptor to be ignored
by the comparator block. This effectively disables the descriptor.
NOTE
Avoid changing descriptors while they are in active use to validate accesses
from bus-masters. This can be done by temporarily disabling the affected
master during the update (XGATE, Master 3, switch S12X CPU states).
Otherwise accesses from bus-masters affected by a descriptor which is
updated concurrently could yield undefined results.
4.4.1.1
Overlapping Descriptors
If the memory ranges of two protection descriptors defined for the same bus-master overlap, the access
restrictions for the overlapped memory range are accumulated. For example:
• a memory protection descriptor defines memory range 0x40_0000−0x41_FFFF as WP=1, NEX=0
(read and execute)
• another descriptor defines memory range 0x41_0000−0x43_FFFF as WP=0, NEX=1 (read and
write)
• the resulting access rights for the overlapping range 0x41_0000−0x41_FFFF are WP=1, NEX=1
(read only)
4.4.1.2
Implicitly defined memory descriptors
As mentioned in the bit description of the Access Error Flag (AEF) in the MPUFLG register (Table 4-3),
there is an additional memory range implicitly defined only while the AEF bit is set: The CPU in
supervisor state can read from and write to the peripheral register space even if there is no memory
protection descriptor explicitly allowing this. This is to prevent the case that the CPU cannot clear the AEF
bit if the registers are write protected for the CPU in supervisor state.
The register address space containing the PAGE registers (EPAGE, RPAGE, GPAGE, PPAGE) at
0x0010−0x0017 gets special treatment. It is defined like this:
• The S12X CPU can always read and write these registers, regardless of the configuration in the
descriptors.
• XGATE or Master3 (if available) are never allowed to read or write these registers, even if the
descriptor configuration allows accesses for other masters than the S12X CPU.
4.4.1.3
Op-code pre-fetch cycles and the NEX bit
Some bus-masters (CPU, XGATE) do a pre-fetch of program-code past the current instruction. The
S12XCPU pre-fetches two words past the current instruction, the XGATE pre-fetches one word, even if
the pre-fetched code is not executed. The MPU module has no way of knowing this at the time when the
pre-fetch cycles occur. Therefore this will result in an access violation if the op-code pre-fetch accesses a
memory range marked as “No-Execute” (NEX=1). This must be taken into account when defining memory
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Chapter 4 Memory Protection Unit (S12XMPUV1)
ranges with the NEX bit set adjacent to memory used for program code. The best way to do this would be
to leave some fill-bytes between the memory ranges in this case, i.e. do not set the upper memory boundary
to the address of the last op-code but to a following address which is at least two words (four bytes) away.
4.4.2
Interrupts
This section describes all interrupts originated by the MPU module.
4.4.2.1
Description of Interrupt Operation
The MPU module generates one interrupt request. It cannot be masked locally in the MPU module and is
meant to be used as the source of a non-maskable hardware interrupt request for the S12X CPU.
Table 4-15. Interrupt vectors
Interrupt Source
S12X CPU access error interrupt (AEF)
4.4.2.2
CCR Mask Local Enable
−
−
CPU Access Error Interrupt
An S12X CPU access error interrupt request is generated if the MPU module has detected an illegal
memory access originating from the S12X CPU. This is a non-maskable hardware interrupt. Due to the
non-maskable nature of this interrupt, the de-assertion of this interrupt request is coupled to the S12X CPU
interrupt vector fetch instead of the local access error flag (AEF). This means leaving the access error flag
(AEF) in the MPUFLG register set will not cause the same interrupt to be serviced again after leaving the
interrupt service routine with “RTI”. Instead, the interrupt request will be asserted again only when the
next illegal S12X CPU access is detected.
4.5
4.5.1
Initialization/Application Information
Initialization
After reset the MPU module is in an unconfigured state, with all eight protection descriptors covering the
whole memory map. The master bits are all set for descriptor “0” and cleared for all other descriptors. The
S12XCPU in supervisor state can access everything because the SVSEN bit in the MPUSEL register is
cleared by a system reset. After system reset every master has full access to the memory map because of
descriptor “0”.
In order to use the MPU module to protect memory ranges from undesired accesses, software needs to:
• Initialize the protection descriptors.
• Make sure there are meaningful interrupt service routines defined for the Access Violation
interrupts because these are non-maskable (See S12XINT chapter for details).
• Initialize peripherals and other masters for use (i.e. set-up XGATE, Master3 if applicable).
• Enable the MPU protection for the S12X CPU in supervisor state, if desired.
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•
Switch the S12X CPU to user state, if desired.
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Chapter 5
External Bus Interface (S12XEBIV4)
Revision History
Rev. No.
Date
(Item No.) (Submitted By)
V04.01
V04.02
V04.03
5.1
Sections
Affected
Substantial Change(s)
12-Sep-05
- Added CSx stretch description.
23-May-06
- Internal updates
24-Jul-06
- Removed term IVIS
Introduction
This document describes the functionality of the XEBI block controlling the external bus interface.
The XEBI controls the functionality of a non-multiplexed external bus (a.k.a. ‘expansion bus’) in
relationship with the chip operation modes. Dependent on the mode, the external bus can be used for data
exchange with external memory, peripherals or PRU, and provide visibility to the internal bus externally
in combination with an emulator.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.1.1
Glossary or Terms
bus clock
expanded modes
Normal Expanded Mode
Emulation Single-Chip Mode
Emulation Expanded Mode
Special Test Mode
single-chip modes
Normal Single-Chip Mode
Special Single-Chip Mode
emulation modes
Emulation Single-Chip Mode
Emulation Expanded Mode
normal modes
Normal Single-Chip Mode
Normal Expanded Mode
special modes
Special Single-Chip Mode
Special Test Mode
NS
Normal Single-Chip Mode
SS
Special Single-Chip Mode
NX
Normal Expanded Mode
ES
Emulation Single-Chip Mode
EX
Emulation Expanded Mode
ST
Special Test Mode
external resource
Addresses outside MCU
PRR
Port Replacement Registers
PRU
Port Replacement Unit
EMULMEM
access source
5.1.2
System Clock. Refer to CRG Block Guide.
External emulation memory
CPU or BDM or XGATE
Features
The XEBI includes the following features:
• Output of up to 23-bit address bus and control signals to be used with a non-muxed external bus
• Bidirectional 16-bit external data bus with option to disable upper half
• Visibility of internal bus activity
5.1.3
•
•
•
Modes of Operation
Single-chip modes
The external bus interface is not available in these modes.
Expanded modes
Address, data, and control signals are activated on the external bus in normal expanded mode and
special test mode.
Emulation modes
The external bus is activated to interface to an external tool for emulation of normal expanded mode
or normal single-chip mode applications.
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Refer to the S12X_MMC section for a detailed description of the MCU operating modes.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.1.4
Block Diagram
Figure 5-1 is a block diagram of the XEBI with all related I/O signals.
ADDR[22:0]
DATA[15:0]
IVD[15:0]
LSTRB
RW
EWAIT
XEBI
UDS
LDS
RE
WE
ACC[2:0]
IQSTAT[3:0]
CS[3:0]
Figure 5-1. XEBI Block Diagram
5.2
External Signal Description
The user is advised to refer to the SoC section for port configuration and location of external bus signals.
NOTE
The following external bus related signals are described in other sections:
ECLK, ECLKX2 (free-running clocks) — PIM section
TAGHI, TAGLO (tag inputs) — PIM section, S12X_DBG section
Table 5-1 outlines the pin names and gives a brief description of their function. Refer to the SoC section
and PIM section for reset states of these pins and associated pull-ups or pull-downs.
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Table 5-1. External System Signals Associated with XEBI
Signal
1
I /O
EBI Signal
Multiplex
(T)ime2
(F)unction3
Available in Modes
Description
NS
SS
NX
ES
EX
ST
RE
O
—
—
Read Enable, indicates external read access
No
No
Yes
No
No
No
ADDR[22:20]
O
T
—
External address
No
No
Yes
Yes
Yes
Yes
ACC[2:0]
O
—
Access source
No
No
No
Yes
Yes
Yes
ADDR[19:16]
O
—
External address
No
No
Yes
Yes
Yes
Yes
IQSTAT[3:0]
O
—
Instruction Queue Status
No
No
No
Yes
Yes
Yes
ADDR[15:1]
O
—
External address
No
No
Yes
Yes
Yes
Yes
IVD[15:1]
O
—
Internal visibility read data
No
No
No
Yes
Yes
Yes
ADDR0
O
F
External address
No
No
No
Yes
Yes
Yes
IVD0
O
Internal visibility read data
No
No
No
Yes
Yes
Yes
UDS
O
—
Upper Data Select, indicates external access
to the high byte DATA[15:8]
No
No
Yes
No
No
No
LSTRB
O
—
Low Strobe, indicates valid data on DATA[7:0]
No
No
No
Yes
Yes
Yes
LDS
O
—
Lower Data Select, indicates external access
to the low byte DATA[7:0]
No
No
Yes
No
No
No
RW
O
—
Read/Write, indicates the direction of internal
data transfers
No
No
No
Yes
Yes
Yes
WE
O
—
Write Enable, indicates external write access
No
No
Yes
No
No
No
CS[3:0]
O
—
—
Chip select
No
No
Yes
No
Yes
No
DATA[15:8]
I/O
—
—
Bidirectional data (even address)
No
No
Yes
Yes
Yes
Yes
DATA[7:0]
I/O
—
—
Bidirectional data (odd address)
No
No
Yes
Yes
Yes
Yes
I
—
—
External control for external bus access
stretches (adding wait states)
No
No
Yes
No
Yes
No
EWAIT
T
T
T
F
F
1
All inputs are capable of reducing input threshold level
Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated
time slot (in modes where applicable).
3 Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin
depending on configuration and reset state.
2
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Chapter 5 External Bus Interface (S12XEBIV4)
5.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XEBI.
5.3.1
Module Memory Map
The registers associated with the XEBI block are shown in Figure 5-2.
Register
Name
0x0E
EBICTL0
0x0F
EBICTL1
Bit 7
R
W
R
W
ITHRS
0
6
0
EXSTR12
5
4
3
2
1
Bit 0
HDBE
ASIZ4
ASIZ3
ASIZ2
ASIZ1
ASIZ0
EXSTR11
EXSTR10
EXSTR02
EXSTR01
EXSTR00
0
= Unimplemented or Reserved
Figure 5-2. XEBI Register Summary
5.3.2
Register Descriptions
The following sub-sections provide a detailed description of each register and the individual register bits.
All control bits can be written anytime, but this may have no effect on the related function in certain
operating modes. This allows specific configurations to be set up before changing into the target operating
mode.
NOTE
Depending on the operating mode an available function may be enabled,
disabled or depend on the control register bit. Reading the register bits will
reflect the status of related function only if the current operating mode
allows user control. Please refer the individual bit descriptions.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.3.2.1
External Bus Interface Control Register 0 (EBICTL0)
Module Base +0x000E (PRR)
7
R
W
Reset
6
0
ITHRS
0
0
5
4
3
2
1
0
HDBE
ASIZ4
ASIZ3
ASIZ2
ASIZ1
ASIZ0
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 5-3. External Bus Interface Control Register 0 (EBICTL0)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes, the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register controls input pin threshold level and determines the external address and data bus sizes in
normal expanded mode. If not in use with the external bus interface, the related pins can be used for
alternative functions.
External bus is available as programmed in normal expanded mode and always full-sized in emulation
modes and special test mode; function not available in single-chip modes.
Table 5-2. EBICTL0 Field Descriptions
Field
Description
7
ITHRS
Reduced Input Threshold — This bit selects reduced input threshold on external data bus pins and specific
control input signals which are in use with the external bus interface in order to adapt to external devices with a
3.3 V, 5 V tolerant I/O.
The reduced input threshold level takes effect depending on ITHRS, the operating mode and the related enable
signals of the EBI pin function as summarized in Table 5-3.
0 Input threshold is at standard level on all pins
1 Reduced input threshold level enabled on pins in use with the external bus interface
5
HDBE
High Data Byte Enable — This bit enables the higher half of the 16-bit data bus. If disabled, only the lower 8-bit
data bus can be used with the external bus interface. In this case the unused data pins and the data select
signals (UDS and LDS) are free to be used for alternative functions.
0 DATA[15:8], UDS, and LDS disabled
1 DATA[15:8], UDS, and LDS enabled
4–0
ASIZ[4:0]
External Address Bus Size — These bits allow scalability of the external address bus. The programmed value
corresponds to the number of available low-aligned address lines (refer to Table 5-4). All address lines
ADDR[22:0] start up as outputs after reset in expanded modes. This needs to be taken into consideration when
using alternative functions on relevant pins in applications which utilize a reduced external address bus.
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Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-3. Input Threshold Levels on External Signals
ITHRS
External Signal
NS
SS
NX
Standard
Standard
Standard
DATA[15:8]
TAGHI, TAGLO
0
DATA[7:0]
EWAIT
Reduced
if HDBE = 1
DATA[15:8]
TAGHI, TAGLO
1
DATA[7:0]
Standard
EWAIT
1
Standard
ES
EX
ST
Reduced
Reduced
Standard
Standard
Reduced
Reduced
Reduced
Standard
Reduced
if EWAIT
enabled1
Standard
Standard
Reduced
Reduced
if EWAIT
enabled1
EWAIT function is enabled if at least one CSx line is configured respectively in MMCCTL0. Refer to S12X_MMC section and
Table 5-5.
Table 5-4. External Address Bus Size
ASIZ[4:0]
Available External Address Lines
00000
None
00001
UDS
00010
ADDR1, UDS
00011
ADDR[2:1], UDS
:
:
10110
ADDR[21:1], UDS
10111
:
11111
ADDR[22:1], UDS
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Chapter 5 External Bus Interface (S12XEBIV4)
5.3.2.2
External Bus Interface Control Register 1 (EBICTL1)
Module Base +0x000F (PRR)
7
R
6
0
W
Reset
5
4
3
EXSTR12
EXSTR11
EXSTR10
1
1
1
0
0
2
1
0
EXSTR02
EXSTR01
EXSTR00
1
1
1
0
= Unimplemented or Reserved
Figure 5-4. External Bus Interface Control Register 1 (EBICTL1)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data is read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register allows programming of two independent values determining the amount of additional stretch
cycles for external accesses (wait states).
With two bits in S12X_MMC register MMCCTL0 for every individual CSx line one of the two counter
options or the EWAIT input is selected as stretch source. The chip select outputs can also be disabled to
free up the pins for alternative functions (Table 5-5). Refer also to S12X_MMC section for register bit
descriptions.
Table 5-5. Chip select function
CSxE1
CSxE0
Function
0
0
CSx disabled
0
1
CSx stretched with EXSTR0
1
0
CSx stretched with EXSTR1
1
1
CSx stretched with EWAIT
If EWAIT input usage is selected in MMCCTL0 the minimum number of stretch cycles is 2 for accesses
to the related address range.
If configured respectively, stretch cycles are added as programmed or dependent on EWAIT in normal
expanded mode and emulation expanded mode; function not available in all other operating modes.
Table 5-6. EBICTL1 Field Descriptions
Field
Description
6–4
External Access Stretch Option 1 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
EXSTR1[2:0] stretch cycles on every access to the external address space as shown in Table 5-7.
2–0
External Access Stretch Option 0 Bits 2, 1, 0 — This three bit field determines the amount of additional clock
EXSTR0[2:0] stretch cycles on every access to the external address space as shown in Table 5-7.
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Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-7. External Access Stretch Bit Definition
5.4
EXSTRx[2:0]
Number of Stretch Cycles
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
Functional Description
This section describes the functions of the external bus interface. The availability of external signals and
functions in relation to the operating mode is initially summarized and described in more detail in separate
sub-sections.
5.4.1
Operating Modes and External Bus Properties
A summary of the external bus interface functions for each operating mode is shown in Table 5-8.
Table 5-8. Summary of Functions
Single-Chip Modes
Properties
(if Enabled)
Normal
Single-Chip
Expanded Modes
Special
Single-Chip
Normal
Expanded
Emulation
Single-Chip
Emulation
Expanded
Special
Test
2 cycles
read external
write int & ext
2 cycles
read external
write int & ext
2 cycles
read internal
write internal
1 cycle
1 cycle
1 cycle
Timing Properties
PRR
access1
2 cycles
read internal
write internal
2 cycles
read internal
write internal
2 cycles
read internal
write internal
Internal access
visible externally
—
—
External
address access
and
unimplemented area
access2
—
—
Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait3
1 cycle
Max. of 2 to 9
programmed
cycles
or n cycles of
ext. wait3
1 cycle
Flash area
address access4
—
—
—
1 cycle
1 cycle
1 cycle
ADDR[22:20]/
ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
ADDR[15:0]/
IVD[15:0]
DATA[15:0]
ADDR[22:20]/
ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
ADDR[15:0]/
IVD[15:0]
DATA[15:0]
ADDR[22:0]
DATA[15:0]
—
Signal Properties
Bus signals
—
—
ADDR[22:1]
DATA[15:0]
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Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-8. Summary of Functions
Single-Chip Modes
Properties
(if Enabled)
Expanded Modes
Normal
Single-Chip
Special
Single-Chip
Normal
Expanded
Emulation
Single-Chip
Emulation
Expanded
Special
Test
Data select signals
(if 16-bit data bus)
—
—
UDS
LDS
ADDR0
LSTRB
ADDR0
LSTRB
ADDR0
LSTRB
Data direction signals
—
—
RE
WE
RW
RW
RW
—
CS0
CS1
CS2
CS3
—
Chip Selects
—
—
CS0
CS1
CS2
CS3
External wait
feature
—
—
EWAIT
—
EWAIT
—
Reduced input
threshold enabled on
—
—
Refer to
Table 5-3
DATA[15:0]
EWAIT
DATA[15:0]
EWAIT
Refer to
Table 5-3
1
Incl. S12X_EBI registers
Refer to S12X_MMC section.
3 If EWAIT enabled for at least one CSx line (refer to S12X_MMC section), the minimum number of external bus cycles is 3.
4 Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
2
5.4.2
Internal Visibility
Internal visibility allows the observation of the internal CPU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware
instructions.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see Table 5-11 to
Table 5-13), internal writes on ADDRx and DATAx (see Table 5-14 to Table 5-16). RW and LSTRB
show the type of access. External read data are also visible on IVDx.
During ‘no access’ cycles RW is held in read position while LSTRB is undetermined.
All accesses which make use of the external bus interface are considered external accesses.
5.4.2.1
Access Source Signals (ACC)
The access source can be determined from the external bus control signals ACC[2:0] as shown in
Table 5-9.
Table 5-9. Determining Access Source from Control Signals
ACC[2:0]
Access Description
000
Repetition of previous access cycle
001
CPU access
010
BDM external access
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Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-9. Determining Access Source from Control Signals
ACC[2:0]
Access Description
011
XGATE PRR access
100
No access1
101
CPU access error
110, 111
1
5.4.2.2
Reserved
Denotes also CPU accesses to BDM firmware and BDM registers (IQSTATx
are ‘XXXX’ and RW = 1 in these cases)
Instruction Queue Status Signals (IQSTAT)
The CPU instruction queue status (execution-start and data-movement information) is brought out as
IQSTAT[3:0] signals. For decoding of the IQSTAT values, refer to the S12X_CPU section.
5.4.2.3
Internal Visibility Data (IVD)
Depending on the access size and alignment, either a word of read data is made visible on the address lines
or only the related data byte will be presented in the ECLK low phase. For details refer to Table 5-10.
Invalid IVD are brought out in case of non-CPU read accesses.
Table 5-10. IVD Read Data Output
Access
IVD[15:8]
IVD[7:0]
ivd(even)
ivd(even+1)
ivd(odd+1)
ivd(odd)
Byte read of data at an even address
ivd(even)
addr[7:0] (rep.)
Byte read of data at an odd address
addr[15:8] (rep.)
ivd(odd)
Word read of data at an even and even+1 address
Word read of data at an odd and odd+1 internal RAM address (misaligned)
5.4.2.4
Emulation Modes Timing
A bus access lasts 1 ECLK cycle. In case of a stretched external access (emulation expanded mode), up to
an infinite amount of ECLK cycles may be added. ADDRx values will only be shown in ECLK high
phases, while ACCx, IQSTATx, and IVDx values will only be presented in ECLK low phases.
Based on this multiplex timing, ACCx are only shown in the current (first) access cycle. IQSTATx and
(for read accesses) IVDx follow in the next cycle. If the access takes more than one bus cycle, ACCx
display NULL (0x000) in the second and all following cycles of the access. IQSTATx display NULL
(0x0000) from the third until one cycle after the access to indicate continuation.
The resulting timing pattern of the external bus signals is outlined in the following tables for read, write
and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus
cycles. Non-shaded bold entries denote all values related to Access #0.
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The following terminology is used:
‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins
‘x’ — Undefined output pin values
‘z’ — Tristate pins
‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’
5.4.2.4.1
Read Access Timing
Table 5-11. Read Access (1 Cycle)
Access #0
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0]
...
ADDR[19:16] / IQSTAT[3:0] ...
1
Access #1
2
high
low
addr 0
iqstat -1
high
low
addr 1
iqstat 0
acc 0
...
DATA[15:0] (internal read)
...
?
DATA[15:0] (external read)
...
RW
...
low
...
acc 2
...
addr 2
iqstat 1
...
ivd 1
...
z
...
ivd 0
z
z
?
z
1
1
...
high
acc 1
?
ADDR[15:0] / IVD[15:0]
3
z
z
data 0
z
data 1
z
...
1
1
1
1
...
Table 5-12. Read Access (2 Cycles)
Access #0
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0]
...
ADDR[19:16] / IQSTAT[3:0] ...
1
high
2
low
high
acc 0
addr 0
Access #1
3
low
high
000
iqstat-1
addr 0
iqstat 0
?
addr 1
x
...
low
...
acc 1
...
0000
...
ADDR[15:0] / IVD[15:0]
...
ivd 0
...
DATA[15:0] (internal read)
...
?
z
z
z
z
z
...
DATA[15:0] (external read)
...
?
z
z
z
data 0
z
...
RW
...
1
1
1
1
1
1
...
Table 5-13. Read Access (n–1 Cycles)
Access #0
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0]
...
ADDR[19:16] / IQSTAT[3:0] ...
1
Access #1
2
high
low
addr 0
iqstat-1
3
high
low
addr 0
iqstat 0
acc 0
high
low
...
000
...
addr 0
0000
...
x
...
z
...
z
000
?
n
...
x
high
addr 1
...
low
...
acc 1
...
0000
...
ivd 0
...
z
...
ADDR[15:0] / IVD[15:0]
...
DATA[15:0] (internal read)
...
?
DATA[15:0] (external read)
...
?
z
z
z
z
z
...
data 0
z
...
RW
...
1
1
1
1
1
1
...
1
1
...
z
z
z
z
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Chapter 5 External Bus Interface (S12XEBIV4)
5.4.2.4.2
Write Access Timing
Table 5-14. Write Access (1 Cycle)
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0]
...
ADDR[19:16] / IQSTAT[3:0] ...
Access #0
Access #1
Access #2
1
2
3
high
low
addr 0
iqstat -1
high
low
addr 1
iqstat 0
?
ADDR[15:0] / IVD[15:0]
...
DATA[15:0] (write)
...
?
RW
...
0
high
low
...
acc 2
...
addr 2
iqstat 1
...
x
...
data 2
...
1
...
acc 1
acc 0
...
x
data 0
data 1
0
1
1
1
Table 5-15. Write Access (2 Cycles)
Access #0
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0]
...
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
Access #1
1
2
high
low
3
high
low
acc 0
addr 0
iqstat-1
iqstat 0
addr 0
?
...
DATA[15:0] (write)
...
?
RW
...
0
high
000
addr 1
...
low
...
acc 1
...
0000
...
x
...
x
...
1
...
x
data 0
0
0
0
1
Table 5-16. Write Access (n–1 Cycles)
Access #0
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0]
...
ADDR[19:16] / IQSTAT[3:0] ...
1
high
high
iqstat-1
...
DATA[15:0] (write)
...
?
RW
...
0
3
low
high
000
addr 0
?
ADDR[15:0] / IVD[15:0]
5.4.2.4.3
2
low
acc 0
addr 0
Access #1
iqstat 0
addr 0
x
n
...
low
...
000
...
0000
...
x
...
high
addr 1
data 0
0
0
0
0
0
...
1
...
low
...
acc 1
...
0000
...
x
...
x
...
1
...
Read-Write-Read Access Timing
Table 5-17. Interleaved Read-Write-Read Accesses (1 Cycle)
Bus cycle ->
...
ECLK phase
...
ADDR[22:20] / ACC[2:0]
...
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
...
Access #0
Access #1
Access #2
1
2
3
high
low
high
acc 0
addr 0
iqstat -1
?
low
high
acc 1
addr 1
iqstat 0
ivd 0
addr 2
...
low
...
acc 2
...
iqstat 1
...
x
...
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Table 5-17. Interleaved Read-Write-Read Accesses (1 Cycle)
DATA[15:0] (internal read)
...
?
z
z
DATA[15:0] (external read)
...
?
z
data 0
RW
...
1
1
0
5.4.3
(write) data 1
z
...
(write) data 1
z
...
0
1
...
1
Accesses to Port Replacement Registers
All read and write accesses to PRR addresses take two bus clock cycles independent of the operating mode.
If writing to these addresses in emulation modes, the access is directed to both, the internal register and
the external resource while reads will be treated external.
The XEBI control registers also belong to this category.
5.4.4
Stretched External Bus Accesses
In order to allow fast internal bus cycles to coexist in a system with slower external resources, the XEBI
supports stretched external bus accesses (wait states) for each external address range related to one of the
4 chip select lines individually.
This feature is available in normal expanded mode and emulation expanded mode for accesses to all
external addresses except emulation memory and PRR. In these cases the fixed access times are 1 or 2
cycles, respectively.
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Chapter 5 External Bus Interface (S12XEBIV4)
Stretched accesses are controlled by:
1. EXSTR1[2:0] and EXSTR0[2:0] bits in the EBICTL1 register configuring a fixed amount of
stretch cycles individually for each CSx line in MMCCTL0
2. Activation of the external wait feature for each CSx line MMCCTL0 register
3. Assertion of the external EWAIT signal when at least one CSx line is configured for EWAIT
The EXSTRx[2:0] control bits can be programmed for generation of a fixed number of 1 to 8 stretch
cycles. If the external wait feature is enabled, the minimum number of additional stretch cycles is 2. An
arbitrary amount of stretch cycles can be added using the EWAIT input.
EWAIT needs to be asserted at least for a minimal specified time window within an external access cycle
for the internal logic to detect it and add a cycle (refer to electrical characteristics). Holding it for additional
cycles will cause the external bus access to be stretched accordingly.
Write accesses are stretched by holding the initiator in its current state for additional cycles as programmed
and controlled by external wait after the data have been driven out on the external bus. This results in an
extension of time the bus signals and the related control signals are valid externally.
Read data are not captured by the system in normal expanded mode until the specified setup time before
the RE rising edge.
Read data are not captured in emulation expanded mode until the specified setup time before the falling
edge of ECLK.
In emulation expanded mode, accesses to the internal flash or the emulation memory (determined by
EROMON and ROMON bits; see S12X_MMC section for details) always take 1 cycle and stretching is
not supported. In case the internal flash is taken out of the map in user applications, accesses are stretched
as programmed and controlled by external wait.
5.4.5
Data Select and Data Direction Signals
The S12X_EBI supports byte and word accesses at any valid external address. The big endian system of
the MCU is extended to the external bus; however, word accesses are restricted to even aligned addresses.
The only exception is the visibility of misaligned word accesses to addresses in the internal RAM as this
module exclusively supports these kind of accesses in a single cycle.
With the above restriction, a fixed relationship is implied between the address parity and the dedicated bus
halves where the data are accessed: DATA[15:8] is related to even addresses and DATA[7:0] is related to
odd addresses.
In expanded modes the data access type is externally determined by a set of control signals, i.e., data select
and data direction signals, as described below. The data select signals are not available if using the external
bus interface with an 8-bit data bus.
5.4.5.1
Normal Expanded Mode
In normal expanded mode, the external signals RE, WE, UDS, LDS indicate the access type (read/write),
data size and alignment of an external bus access (Table 5-18).
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Chapter 5 External Bus Interface (S12XEBIV4)
Table 5-18. Access in Normal Expanded Mode
DATA[15:8]
Access
DATA[7:0]
RE WE UDS LDS
I/O data(addr) I/O data(addr)
Word write of data on DATA[15:0] at an even and even+1 address
1
0
0
0
Out data(even) Out
Byte write of data on DATA[7:0] at an odd address
1
0
1
0
Byte write of data on DATA[15:8] at an even address
1
0
0
1
In
Word read of data on DATA[15:0] at an even and even+1 address
0
1
0
0
In
Byte read of data on DATA[7:0] at an odd address
0
1
1
0
x
data(odd)
Out
data(odd)
In
x
data(even)
In
data(odd)
In
x
In
data(odd)
Out data(even)
Byte read of data on DATA[15:8] at an even address
0
1
0
1
In
data(even)
In
x
Indicates No Access
1
1
1
1
In
x
In
x
Unimplemented
1
1
1
0
In
x
In
x
1
1
0
1
In
x
In
x
5.4.5.2
Emulation Modes and Special Test Mode
In emulation modes and special test mode, the external signals LSTRB, RW, and ADDR0 indicate the
access type (read/write), data size and alignment of an external bus access. Misaligned accesses to the
internal RAM and misaligned XGATE PRR accesses in emulation modes are the only type of access that
are able to produce LSTRB = ADDR0 = 1. This is summarized in Table 5-19.
Table 5-19. Access in Emulation Modes and Special Test Mode
DATA[15:8]
Access
DATA[7:0]
RW LSTRB ADDR0
I/O
data(addr)
I/O
data(addr)
Word write of data on DATA[15:0] at an even and even+1
address
0
0
0
Out
data(even)
Out
data(odd)
Byte write of data on DATA[7:0] at an odd address
0
0
1
In
x
Out
data(odd)
data(odd)
In
Byte write of data on DATA[15:8] at an even address
0
1
0
Out
Word write at an odd and odd+1 internal RAM address
(misaligned — only in emulation modes)
0
1
1
Out data(odd+1) Out
x
Word read of data on DATA[15:0] at an even and even+1
address
1
0
0
In
data(even)
In
data(even+1)
Byte read of data on DATA[7:0] at an odd address
1
0
1
In
x
In
data(odd)
Byte read of data on DATA[15:8] at an even address
1
1
0
In
data(even)
In
x
Word read at an odd and odd+1 internal RAM address
(misaligned - only in emulation modes)
1
1
1
In
data(odd+1)
In
data(odd)
data(odd)
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Chapter 5 External Bus Interface (S12XEBIV4)
5.4.6
Low-Power Options
The XEBI does not support any user-controlled options for reducing power consumption.
5.4.6.1
Run Mode
The XEBI does not support any options for reducing power in run mode.
Power consumption is reduced in single-chip modes due to the absence of the external bus interface.
Operation in expanded modes results in a higher power consumption, however any unnecessary toggling
of external bus signals is reduced to the lowest indispensable activity by holding the previous states
between external accesses.
5.4.6.2
Wait Mode
The XEBI does not support any options for reducing power in wait mode.
5.4.6.3
Stop Mode
The XEBI will cease to function in stop mode.
5.5
Initialization/Application Information
This section describes the external bus interface usage and timing. Typical customer operating modes are
normal expanded mode and emulation modes, specifically to be used in emulator applications. Taking the
availability of the external wait feature into account the use cases are divided into four scenarios:
• Normal expanded mode
— External wait feature disabled
– External wait feature enabled
• Emulation modes
– Emulation single-chip mode (without wait states)
– Emulation expanded mode (with optional access stretching)
Normal single-chip mode and special single-chip mode do not have an external bus. Special test mode is
used for factory test only. Therefore, these modes are omitted here.
All timing diagrams referred to throughout this section are available in the Electrical Characteristics
appendix of the SoC section.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.5.1
Normal Expanded Mode
This mode allows interfacing to external memories or peripherals which are available in the commercial
market. In these applications the normal bus operation requires a minimum of 1 cycle stretch for each
external access.
5.5.1.1
Example 1a: External Wait Feature Disabled
The first example of bus timing of an external read and write access with the external wait feature disabled
is shown in
• Figure ‘Example 1a: Normal Expanded Mode — Read Followed by Write’
The associated supply voltage dependent timing are numbers given in
•
•
Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAIT disabled)’
Table ‘Example 1a: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAIT disabled)’
Systems designed this way rely on the internal programmable access stretching. These systems have
predictable external memory access times. The additional stretch time can be programmed up to 8 cycles
to provide longer access times.
5.5.1.2
Example 1b: External Wait Feature Enabled
The external wait operation is shown in this example. It can be used to exceed the amount of stretch cycles
over the programmed number in EXSTR[2:0]. The feature must be enabled by configuring at least one
CSx line for EWAIT.
If the EWAIT signal is not asserted, the number of stretch cycles is forced to a minimum of 2 cycles. If
EWAIT is asserted within the predefined time window during the access it will be strobed active and
another stretch cycle is added. If strobed inactive, the next cycle will be the last cycle before the access is
finished. EWAIT can be held asserted as long as desired to stretch the access.
An access with 1 cycle stretch by EWAIT assertion is shown in
• Figure ‘Example 1b: Normal Expanded Mode — Stretched Read Access’
• Figure ‘Example 1b: Normal Expanded Mode — Stretched Write Access’
The associated timing numbers for both operations are given in
• Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 5.0 V (EWAIT enabled)’
• Table ‘Example 1b: Normal Expanded Mode Timing VDD5 = 3.0 V (EWAIT enabled)’
It is recommended to use the free-running clock (ECLK) at the fastest rate (bus clock rate) to synchronize
the EWAIT input signal.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.5.2
Emulation Modes
In emulation mode applications, the development systems use a custom PRU device to rebuild the
single-chip or expanded bus functions which are lost due to the use of the external bus with an emulator.
Accesses to a set of registers controlling the related ports in normal modes (refer to SoC section) are
directed to the external bus in emulation modes which are substituted by PRR as part of the PRU. Accesses
to these registers take a constant time of 2 cycles.
Depending on the setting of ROMON and EROMON (refer to S12X_MMC section), the program code
can be executed from internal memory or an optional external emulation memory (EMULMEM). No wait
state operation (stretching) of the external bus access is done in emulation modes when accessing internal
memory or emulation memory addresses.
In both modes observation of the internal operation is supported through the external bus (internal
visibility).
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Chapter 5 External Bus Interface (S12XEBIV4)
5.5.2.1
Example 2a: Emulation Single-Chip Mode
This mode is used for emulation systems in which the target application is operating in normal single-chip
mode.
Figure 5-5 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI
Emulator
ADDR[22:0]/IVD[15:0]
DATA[15:0]
EMULMEM
PRU
PRR
Ports
LSTRB
RW
ADDR[22:20]/ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
ECLK
ECLKX2
Figure 5-5. Application in Emulation Single-Chip Mode
The timing diagram for this operation is shown in:
• Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’
The associated timing numbers are given in:
• Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAIT disabled)’
Timing considerations:
• Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing.
• LSTRB has the same timing as RW.
• ECLKX2 rising edges have the same timing as ECLK edges.
• The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing
for an external non-PRR access with 1 cycle of stretch as shown in example 2b.
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Chapter 5 External Bus Interface (S12XEBIV4)
5.5.2.2
Example 2b: Emulation Expanded Mode
This mode is used for emulation systems in which the target application is operating in normal expanded
mode.
If the external bus is used with a PRU, the external device rebuilds the data select and data direction signals
UDS, LDS, RE, and WE from the ADDR0, LSTRB, and RW signals.
Figure 5-6 shows the PRU connection with the available external bus signals in an emulator application.
S12X_EBI
Emulator
ADDR[22:0]/IVD[15:0]
DATA[15:0]
EMULMEM
PRU
PRR
LSTRB
RW
Ports
UDS
LDS
RE
WE
ADDR[22:20]/ACC[2:0]
ADDR[19:16]/
IQSTAT[3:0]
CS[3:0]
EWAIT
ECLK
ECLKX2
Figure 5-6. Application in Emulation Expanded Mode
The timings of accesses with 1 stretch cycle are shown in
• Figure ‘Example 2b: Emulation Expanded Mode — Read with 1 Stretch Cycle’
• Figure ‘Example 2b: Emulation Expanded Mode — Write with 1 Stretch Cycle’
The associated timing numbers are given in
• Table ‘Example 2b: Emulation Expanded Mode Timing VDD5 = 5.0 V (EWAIT disabled)’ (this
also includes examples for alternative settings of 2 and 3 additional stretch cycles)
Timing considerations:
• If no stretch cycle is added, the timing is the same as in Emulation Single-Chip Mode.
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Chapter 6
Interrupt (S12XINTV2)
Table 6-1. Revision History
Version
Number
Revision
Date
Effective
Date
02.00
01 JUL
2005
01 JUL
2005
initial V2 release, added new features:
- XGATE threads can be interrupted
- SYS instruction vector
- access violation interrupt vectors
02.04
11 JAN
2007
11 JAN
2007
- added Notes for devices without XGATE module
02.05
20 MAR
2007
23 MAR
2007
- fixed priority definition for software exceptions in “1.4.6 Exception
Priority”
6.1
Author
Description of Changes
Introduction
The XINT module decodes the priority of all system exception requests and provides the applicable vector
for processing the exception to either the CPU or the XGATE module. The XINT module supports:
• I bit and X bit maskable interrupt requests
• One non-maskable unimplemented op-code trap
• One non-maskable software interrupt (SWI) or background debug mode request
• One non-maskable system call interrupt (SYS)
• Three non-maskable access violation interrupt
• One spurious interrupt vector request
• Three system reset vector requests
Each of the I bit maskable interrupt requests can be assigned to one of seven priority levels supporting a
flexible priority scheme. For interrupt requests that are configured to be handled by the CPU, the priority
scheme can be used to implement nested interrupt capability where interrupts from a lower level are
automatically blocked if a higher level interrupt is being processed. Interrupt requests configured to be
handled by the XGATE module can be nested one level deep.
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Chapter 6 Interrupt (S12XINTV2)
NOTE
The HPRIO register and functionality of the original S12 interrupt module
is no longer supported, since it is superseded by the 7-level interrupt request
priority scheme.
6.1.1
Glossary
The following terms and abbreviations are used in the document.
Table 6-2. Terminology
Term
CCR
DMA
INT
IPL
ISR
MCU
XGATE
IRQ
XIRQ
6.1.2
•
•
•
•
•
•
•
•
•
•
•
Meaning
Condition Code Register (in the S12X CPU)
Direct Memory Access
Interrupt
Interrupt Processing Level
Interrupt Service Routine
Micro-Controller Unit
please refer to the "XGATE Block Guide"
refers to the interrupt request associated with the IRQ pin
refers to the interrupt request associated with the XIRQ pin
Features
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base1 + 0x0010).
One non-maskable system call interrupt vector request (at address vector base + 0x0012).
Three non-maskable access violation interrupt vector requests (at address vector base +
0x0014−0x0018).
2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2).
Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module2.
I bit maskable interrupts can be nested, depending on their priority levels.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used
as upper byte) and 0x00 (used as lower byte).
2. The IRQ interrupt can only be handled by the CPU
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Chapter 6 Interrupt (S12XINTV2)
•
•
•
6.1.3
•
•
•
•
Determines the highest priority XGATE and interrupt vector requests, drives the vector to the
XGATE module or to the bus on CPU request, respectively.
Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.
XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.
Modes of Operation
Run mode
This is the basic mode of operation.
Wait mode
In wait mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 6.5.3, “Wake Up from Stop or Wait Mode” for details.
Stop Mode
In stop mode, the XINT module is frozen. It is however capable of either waking up the CPU if an
interrupt occurs or waking up the XGATE if an XGATE request occurs. Please refer to
Section 6.5.3, “Wake Up from Stop or Wait Mode” for details.
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please
refer to Section 6.3.2.1, “Interrupt Vector Base Register (IVBR)” for details.
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Chapter 6 Interrupt (S12XINTV2)
6.1.4
Block Diagram
Figure 6-1 shows a block diagram of the XINT module.
Peripheral
Interrupt Requests
Wake Up
CPU
Non I Bit Maskable
Channels
Priority
Decoder
Interrupt
Requests
PRIOLVL2
PRIOLVL1
PRIOLVL0
RQST
IVBR
New
IPL
To CPU
Vector
Address
IRQ Channel
Current
IPL
One Set Per Channel
(Up to 108 Channels)
INT_XGPRIO
XGATE
Requests
Priority
Decoder
Wake up
XGATE
Vector
ID
XGATE
Interrupts
To XGATE Module
RQST
XGATE Request Route,
PRIOLVLn
Priority Level
= bits from the channel configuration
in the associated configuration register
INT_XGPRIO = XGATE Interrupt Priority
IVBR
= Interrupt Vector Base
IPL
= Interrupt Processing Level
Figure 6-1. XINT Block Diagram
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Chapter 6 Interrupt (S12XINTV2)
6.2
External Signal Description
The XINT module has no external signals.
6.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the XINT module.
6.3.1
Module Memory Map
Table 6-3 gives an overview over all XINT module registers.
Table 6-3. XINT Memory Map
Address
Use
Access
0x0120
RESERVED
—
0x0121
Interrupt Vector Base Register (IVBR)
R/W
0x0122–0x0125
RESERVED
—
0x0126
XGATE Interrupt Priority Configuration Register
(INT_XGPRIO)
R/W
0x0127
Interrupt Request Configuration Address Register
(INT_CFADDR)
R/W
0x0128
Interrupt Request Configuration Data Register 0
(INT_CFDATA0)
R/W
0x0129
Interrupt Request Configuration Data Register 1
(INT_CFDATA1)
R/W
0x012A
Interrupt Request Configuration Data Register 2
(INT_CFDATA2
R/W
0x012B
Interrupt Request Configuration Data Register 3
(INT_CFDATA3)
R/W
0x012C
Interrupt Request Configuration Data Register 4
(INT_CFDATA4)
R/W
0x012D
Interrupt Request Configuration Data Register 5
(INT_CFDATA5)
R/W
0x012E
Interrupt Request Configuration Data Register 6
(INT_CFDATA6)
R/W
0x012F
Interrupt Request Configuration Data Register 7
(INT_CFDATA7)
R/W
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Chapter 6 Interrupt (S12XINTV2)
6.3.2
Register Descriptions
This section describes in address order all the XINT module registers and their individual bits.
Address
Register
Name
0x0121
IVBR
Bit 7
6
5
R
INT_XGPRIO
R
3
2
0
0
0
0
0
INT_CFADDR
R
R
W
0x0129 INT_CFDATA1
R
W
0x012A INT_CFDATA2
R
W
0x012B INT_CFDATA3
R
W
0x012C INT_CFDATA4
R
W
0x012D INT_CFDATA5
R
W
0x012E INT_CFDATA6
R
W
0x012F INT_CFDATA7
R
W
0
INT_CFADDR[7:4]
W
0x0128 INT_CFDATA0
Bit 0
XILVL[2:0]
W
0x0127
1
IVB_ADDR[7:0]7
W
0x0126
4
RQST
RQST
RQST
RQST
RQST
RQST
RQST
RQST
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
PRIOLVL[2:0]
= Unimplemented or Reserved
Figure 6-2. XINT Register Summary
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6.3.2.1
Interrupt Vector Base Register (IVBR)
Address: 0x0121
7
6
5
R
3
2
1
0
1
1
1
IVB_ADDR[7:0]
W
Reset
4
1
1
1
1
1
Figure 6-3. Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
Table 6-4. IVBR Field Descriptions
Field
Description
7–0
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
IVB_ADDR[7:0] reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
HCS12.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
6.3.2.2
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Address: 0x0126
R
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
2
0
XILVL[2:0]
W
Reset
1
0
0
1
= Unimplemented or Reserved
Figure 6-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime
Write: Anytime
Table 6-5. INT_XGPRIO Field Descriptions
Field
Description
2–0
XILVL[2:0]
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
accesses to this register will return all 0.
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Table 6-6. XGATE Interrupt Priority Levels
Priority
low
high
6.3.2.3
XILVL2
XILVL1
XILVL0
Meaning
0
0
0
Interrupt request is disabled
0
0
1
Priority level 1
0
1
0
Priority level 2
0
1
1
Priority level 3
1
0
0
Priority level 4
1
0
1
Priority level 5
1
1
0
Priority level 6
1
1
1
Priority level 7
Interrupt Request Configuration Address Register (INT_CFADDR)
Address: 0x0127
7
R
5
4
INT_CFADDR[7:4]
W
Reset
6
0
0
0
1
3
2
1
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-5. Interrupt Configuration Address Register (INT_CFADDR)
Read: Anytime
Write: Anytime
Table 6-7. INT_CFADDR Field Descriptions
Field
Description
7–4
Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128
INT_CFADDR[7:4] configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal
value written to this register corresponds to the upper nibble of the lower byte of the address of the interrupt
vector, i.e., writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector
requests starting with vector at address (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.
Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to
INT_CFDATA0–7 will be ignored and read accesses will return all 0.
6.3.2.4
Interrupt Request Configuration Data Registers (INT_CFDATA0–7)
The eight register window visible at addresses INT_CFDATA0–7 contains the configuration data for the
block of eight interrupt requests (out of 128) selected by the interrupt configuration address register
(INT_CFADDR) in ascending order. INT_CFDATA0 represents the interrupt configuration data register
of the vector with the lowest address in this block, while INT_CFDATA7 represents the interrupt
configuration data register of the vector with the highest address, respectively.
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Chapter 6 Interrupt (S12XINTV2)
Address: 0x0128
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-6. Interrupt Request Configuration Data Register 0 (INT_CFDATA0)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x0129
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-7. Interrupt Request Configuration Data Register 1 (INT_CFDATA1)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012A
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-8. Interrupt Request Configuration Data Register 2 (INT_CFDATA2)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012B
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-9. Interrupt Request Configuration Data Register 3 (INT_CFDATA3)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
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Address: 0x012C
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-10. Interrupt Request Configuration Data Register 4 (INT_CFDATA4)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012D
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-11. Interrupt Request Configuration Data Register 5 (INT_CFDATA5)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012E
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-12. Interrupt Request Configuration Data Register 6 (INT_CFDATA6)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Address: 0x012F
7
R
W
Reset
RQST
0
6
5
4
3
0
0
0
0
0
0
0
0
2
1
0
PRIOLVL[2:0]
0
0
11
= Unimplemented or Reserved
Figure 6-13. Interrupt Request Configuration Data Register 7 (INT_CFDATA7)
1
Please refer to the notes following the PRIOLVL[2:0] description below.
Read: Anytime
Write: Anytime
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Table 6-8. INT_CFDATA0–7 Field Descriptions
Field
Description
7
RQST
XGATE Request Enable — This bit determines if the associated interrupt request is handled by the CPU or by
the XGATE module.
0 Interrupt request is handled by the CPU
1 Interrupt request is handled by the XGATE module
Note: The IRQ interrupt cannot be handled by the XGATE module. For this reason, the configuration register
for vector (vector base + 0x00F2) = IRQ vector address) does not contain a RQST bit. Writing a 1 to the
location of the RQST bit in this register will be ignored and a read access will return 0.
Note: If the XGATE module is not available on the device, writing a 1 to the location of the RQST bit in this
register will be ignored and a read access will return 0.
2–0
Interrupt Request Priority Level Bits — The PRIOLVL[2:0] bits configure the interrupt request priority level of
PRIOLVL[2:0] the associated interrupt request. Out of reset all interrupt requests are enabled at the lowest active level (“1”)
to provide backwards compatibility with previous HCS12 interrupt controllers. Please also refer to Table 6-9 for
available interrupt request priority levels.
Note: Write accesses to configuration data registers of unused interrupt channels will be ignored and read
accesses will return all 0. For information about what interrupt channels are used in a specific MCU,
please refer to the Device Reference Manual of that MCU.
Note: When vectors (vector base + 0x00F0–0x00FE) are selected by writing 0xF0 to INT_CFADDR, writes to
INT_CFDATA2–7 (0x00F4–0x00FE) will be ignored and read accesses will return all 0s. The
corresponding vectors do not have configuration data registers associated with them.
Note: When vectors (vector base + 0x0010–0x001E) are selected by writing 0x10 to INT_CFADDR, writes to
INT_CFDATA1–INT_CFDATA4 (0x0012–0x0018) will be ignored and read accesses will return all 0s. The
corresponding vectors do not have configuration data registers associated with them.
Note: Write accesses to the configuration register for the spurious interrupt vector request
(vector base + 0x0010) will be ignored and read accesses will return 0x07 (request is handled by the
CPU, PRIOLVL = 7).
Table 6-9. Interrupt Priority Levels
Priority
low
high
6.4
PRIOLVL2
PRIOLVL1
PRIOLVL0
Meaning
0
0
0
Interrupt request is disabled
0
0
1
Priority level 1
0
1
0
Priority level 2
0
1
1
Priority level 3
1
0
0
Priority level 4
1
0
1
Priority level 5
1
1
0
Priority level 6
1
1
1
Priority level 7
Functional Description
The XINT module processes all exception requests to be serviced by the CPU module. These exceptions
include interrupt vector requests and reset vector requests. Each of these exception types and their overall
priority level is discussed in the subsections below.
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6.4.1
S12X Exception Requests
The CPU handles both reset requests and interrupt requests. The XINT module contains registers to
configure the priority level of each I bit maskable interrupt request which can be used to implement an
interrupt priority scheme. This also includes the possibility to nest interrupt requests. A priority decoder
is used to evaluate the priority of a pending interrupt request.
6.4.2
Interrupt Prioritization
After system reset all interrupt requests with a vector address lower than or equal to (vector base + 0x00F2)
are enabled, are set up to be handled by the CPU and have a pre-configured priority level of 1. Exceptions
to this rule are the non-maskable interrupt requests and the spurious interrupt vector request at (vector base
+ 0x0010) which cannot be disabled, are always handled by the CPU and have a fixed priority levels. A
priority level of 0 effectively disables the associated I bit maskable interrupt request.
If more than one interrupt request is configured to the same interrupt priority level the interrupt request
with the higher vector address wins the prioritization.
The following conditions must be met for an I bit maskable interrupt request to be processed.
1. The local interrupt enabled bit in the peripheral module must be set.
2. The setup in the configuration register associated with the interrupt request channel must meet the
following conditions:
a) The XGATE request enable bit must be 0 to have the CPU handle the interrupt request.
b) The priority level must be set to non zero.
c) The priority level must be greater than the current interrupt processing level in the condition
code register (CCR) of the CPU (PRIOLVL[2:0] > IPL[2:0]).
3. The I bit in the condition code register (CCR) of the CPU must be cleared.
4. There is no access violation interrupt request pending.
5. There is no SYS, SWI, BDM, TRAP, or XIRQ request pending.
NOTE
All non I bit maskable interrupt requests always have higher priority than
I bit maskable interrupt requests. If an I bit maskable interrupt request is
interrupted by a non I bit maskable interrupt request, the currently active
interrupt processing level (IPL) remains unaffected. It is possible to nest
non I bit maskable interrupt requests, e.g., by nesting SWI or TRAP calls.
6.4.2.1
Interrupt Priority Stack
The current interrupt processing level (IPL) is stored in the condition code register (CCR) of the CPU. This
way the current IPL is automatically pushed to the stack by the standard interrupt stacking procedure. The
new IPL is copied to the CCR from the priority level of the highest priority active interrupt request channel
which is configured to be handled by the CPU. The copying takes place when the interrupt vector is
fetched. The previous IPL is automatically restored by executing the RTI instruction.
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Chapter 6 Interrupt (S12XINTV2)
6.4.3
XGATE Requests
If the XGATE module is implemented on the device, the XINT module is also used to process all exception
requests to be serviced by the XGATE module. The overall priority level of those exceptions is discussed
in the subsections below.
6.4.3.1
XGATE Request Prioritization
An interrupt request channel is configured to be handled by the XGATE module, if the RQST bit of the
associated configuration register is set to 1 (please refer to Section 6.3.2.4, “Interrupt Request
Configuration Data Registers (INT_CFDATA0–7)”). The priority level configuration (PRIOLVL) for this
channel becomes the XGATE priority which will be used to determine the highest priority XGATE request
to be serviced next by the XGATE module. Additionally, XGATE interrupts may be raised by the XGATE
module by setting one or more of the XGATE channel interrupt flags (by using the SIF instruction). This
will result in an CPU interrupt with vector address vector base + (2 * channel ID number), where the
channel ID number corresponds to the highest set channel interrupt flag, if the XGIE and channel RQST
bits are set.
The shared interrupt priority for the XGATE interrupt requests is taken from the XGATE interrupt priority
configuration register (please refer to Section 6.3.2.2, “XGATE Interrupt Priority Configuration Register
(INT_XGPRIO)”). If more than one XGATE interrupt request channel becomes active at the same time,
the channel with the highest vector address wins the prioritization.
6.4.4
Priority Decoders
The XINT module contains priority decoders to determine the priority for all interrupt requests pending
for the respective target.
There are two priority decoders, one for each interrupt request target, CPU or XGATE. The function of
both priority decoders is basically the same with one exception: the priority decoder for the XGATE
module does not take the current XGATE thread processing level into account. Instead, XGATE requests
are handed to the XGATE module including a 1-bit priority identifier. The XGATE module uses this
additional information to decide if the new request can interrupt a currently running thread. The 1-bit
priority identifier corresponds to the most significant bit of the priority level configuration of the requesting
channel. This means that XGATE requests with priority levels 4, 5, 6 or 7 can interrupt running XGATE
threads with priority levels 1, 2 and 3.
A CPU interrupt vector is not supplied until the CPU requests it. Therefore, it is possible that a higher
priority interrupt request could override the original exception which caused the CPU to request the vector.
In this case, the CPU will receive the highest priority vector and the system will process this exception
instead of the original request.
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive
after the interrupt has been recognized, but prior to the vector request), the vector address supplied to the
CPU will default to that of the spurious interrupt vector.
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NOTE
Care must be taken to ensure that all exception requests remain active until
the system begins execution of the applicable service routine; otherwise, the
exception request may not get processed at all or the result may be a
spurious interrupt request (vector at address (vector base + 0x0010)).
6.4.5
Reset Exception Requests
The XINT module supports three system reset exception request types (for details please refer to the Clock
and Reset Generator module (CRG)):
1. Pin reset, power-on reset, low-voltage reset, or illegal address reset
2. Clock monitor reset request
3. COP watchdog reset request
6.4.6
Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the XINT module upon
request by the CPU is shown in Table 6-10. Generally, all non-maskable interrupts have higher priorities
than maskable interrupts. Please note that between the three software interrupts (Unimplemented op-code
trap request, SWI/BGND request, SYS request) there is no real priority defined because they cannot occur
simultaneously (the S12XCPU executes one instruction at a time).
Table 6-10. Exception Vector Map and Priority
Vector Address1
0xFFFE
Source
Pin reset, power-on reset, low-voltage reset, illegal address reset
0xFFFC
Clock monitor reset
0xFFFA
COP watchdog reset
(Vector base + 0x00F8)
Unimplemented op-code trap
(Vector base + 0x00F6)
Software interrupt instruction (SWI) or BDM vector request
(Vector base + 0x0012)
System call interrupt instruction (SYS)
(Vector base + 0x0018)
(reserved for future use)
(Vector base + 0x0016)
XGATE Access violation interrupt request2
(Vector base + 0x0014)
CPU Access violation interrupt request3
(Vector base + 0x00F4)
XIRQ interrupt request
(Vector base + 0x00F2)
IRQ interrupt request
(Vector base +
0x00F0–0x001A)
(Vector base + 0x0010)
Device specific I bit maskable interrupt sources (priority determined by the associated
configuration registers, in descending order)
Spurious interrupt
1
16 bits vector address based
only implemented if device features both a Memory Protection Unit (MPU) and an XGATE co-processor
3 only implemented if device features a Memory Protection Unit (MPU)
2
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Chapter 6 Interrupt (S12XINTV2)
6.5
6.5.1
Initialization/Application Information
Initialization
After system reset, software should:
• Initialize the interrupt vector base register if the interrupt vector table is not located at the default
location (0xFF10–0xFFF9).
• Initialize the interrupt processing level configuration data registers (INT_CFADDR,
INT_CFDATA0–7) for all interrupt vector requests with the desired priority levels and the request
target (CPU or XGATE module). It might be a good idea to disable unused interrupt requests.
• If the XGATE module is used, setup the XGATE interrupt priority register (INT_XGPRIO) and
configure the XGATE module (please refer the XGATE Block Guide for details).
• Enable I maskable interrupts by clearing the I bit in the CCR.
• Enable the X maskable interrupt by clearing the X bit in the CCR (if required).
6.5.2
Interrupt Nesting
The interrupt request priority level scheme makes it possible to implement priority based interrupt request
nesting for the I bit maskable interrupt requests handled by the CPU.
• I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority,
so that there can be up to seven nested I bit maskable interrupt requests at a time (refer to
Figure 6-14 for an example using up to three nested interrupt requests).
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, I bit maskable interrupt requests with higher priority can
interrupt the current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
• Service interrupt, e.g., clear interrupt flags, copy data, etc.
• Clear I bit in the CCR by executing the instruction CLI (thus allowing interrupt requests with
higher priority)
• Process data
• Return from interrupt by executing the instruction RTI
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0
Stacked IPL
IPL in CCR
0
0
4
0
0
0
4
7
4
3
1
0
7
6
RTI
L7
5
4
RTI
Processing Levels
3
L3 (Pending)
2
L4
RTI
1
L1 (Pending)
0
RTI
Reset
Figure 6-14. Interrupt Processing Example
6.5.3
6.5.3.1
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
Every I bit maskable interrupt request which is configured to be handled by the CPU is capable of waking
the MCU from stop or wait mode. To determine whether an I bit maskable interrupts is qualified to wake
up the CPU or not, the same settings as in normal run mode are applied during stop or wait mode:
• If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking up the MCU.
• An I bit maskable interrupt is ignored if it is configured to a priority level below or equal to the
current IPL in CCR.
• I bit maskable interrupt requests which are configured to be handled by the XGATE module are not
capable of waking up the CPU.
An XIRQ request can wake up the MCU from stop or wait mode at anytime, even if the X bit in CCR is set.
6.5.3.2
XGATE Wake Up from Stop or Wait Mode
Interrupt request channels which are configured to be handled by the XGATE module are capable of
waking up the XGATE module. Interrupt request channels handled by the XGATE module do not affect
the state of the CPU.
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Chapter 7
Background Debug Module (S12XBDMV2)
Revision History
Revision Number
Date
s12x_bdm.01.00.00
Bluefin1
First version of S12XBDMV1
s12x_bdm.02.00.02
Bluefin2
First version of S12XBDMV2
7.1
Author
Summary of Changes
Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the
HCS12X core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
• TAGGO command no longer supported by BDM
• External instruction tagging feature now part of DBG module
• BDM register map and register content extended/modified
• Global page access functionality
• Enabled but not active out of reset in emulation modes (if modes available)
• CLKSW bit set out of reset in emulation modes (if modes available).
• Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices
is 0xC1)
7.1.1
Features
The BDM includes these distinctive features:
• Single-wire communication with host development system
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•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
Software control of BDM operation during wait mode
Software selectable clocks
Global page access functionality
Enabled but not active out of reset in emulation modes (if modes available)
CLKSW bit set out of reset in emulation modes (if modes available).
When secured, hardware commands are allowed to access the register space in special single chip
mode, if the non-volatile memory erase test fail.
Family ID readable from firmware ROM at global address 0x7FFF0F (value for HCS12X devices
is 0xC1)
BDM hardware commands are operational until system stop mode is entered (all bus masters are
in stop mode)
7.1.2
Modes of Operation
BDM is available in all operating modes but must be enabled before firmware commands are executed.
Some systems may have a control bit that allows suspending thefunction during background debug mode.
7.1.2.1
Regular Run Modes
All of these operations refer to the part in run mode and not being secured. The BDM does not provide
controls to conserve power during run mode.
• Normal modes
General operation of the BDM is available and operates the same in all normal modes.
• Special single chip mode
In special single chip mode, background operation is enabled and active out of reset. This allows
programming a system with blank memory.
• Emulation modes (if modes available)
In emulation mode, background operation is enabled but not active out of reset. This allows
debugging and programming a system in this mode more easily.
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Chapter 7 Background Debug Module (S12XBDMV2)
7.1.2.2
Secure Mode Operation
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run
mode operation. Secure operation prevents BDM and CPU accesses to non-volatile memory (Flash and/or
EEPROM) other than allowing erasure. For more information please see Section 7.4.1, “Security”.
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Chapter 7 Background Debug Module (S12XBDMV2)
7.1.2.3
Low-Power Modes
The BDM can be used until all bus masters (e.g., CPU or XGATE or others depending on which masters
are available on the SOC) are in stop mode. When CPU is in a low power mode (wait or stop mode) all
BDM firmware commands as well as the hardware BACKGROUND command can not be used
respectively are ignored. In this case the CPU can not enter BDM active mode, and only hardware read and
write commands are available. Also the CPU can not enter a low power mode during BDM active mode.
If all bus masters are in stop mode, the BDM clocks are stopped as well. When BDM clocks are disabled
and one of the bus masters exits from stop mode the BDM clocks will restart and BDM will have a soft
reset (clearing the instruction register, any command in progress and disable the ACK function). The BDM
is now ready to receive a new command.
7.1.3
Block Diagram
A block diagram of the BDM is shown in Figure 7-1.
Host
System
BKGD
Serial
Interface
Data
16-Bit Shift Register
Control
Register Block
Address
TRACE
BDMACT
Instruction Code
and
Execution
Bus Interface
and
Control Logic
Data
Control
Clocks
ENBDM
SDV
UNSEC
CLKSW
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
BDMSTS
Register
Figure 7-1. BDM Block Diagram
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Chapter 7 Background Debug Module (S12XBDMV2)
7.2
External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode.
7.3
7.3.1
Memory Map and Register Definition
Module Memory Map
Table 7-1 shows the BDM memory map when BDM is active.
Table 7-1. BDM Memory Map
Global Address
Module
Size
(Bytes)
0x7FFF00–0x7FFF0B
BDM registers
12
0x7FFF0C–0x7FFF0E
BDM firmware ROM
3
0x7FFF0F
Family ID (part of BDM firmware ROM)
1
0x7FFF10–0x7FFFFF
BDM firmware ROM
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Chapter 7 Background Debug Module (S12XBDMV2)
7.3.2
Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 7-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global
Address
Register
Name
0x7FFF00
Reserved
R
Bit 7
6
5
4
3
2
1
Bit 0
X
X
X
X
X
X
0
0
BDMACT
0
SDV
TRACE
UNSEC
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
0
0
0
0
0
CCR10
CCR9
CCR8
BGAE
BGP6
BGP5
BGP4
BGP3
BGP2
BGP1
BGP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
0x7FFF01
BDMSTS
R
W
0x7FFF02
Reserved
R
ENBDM
CLKSW
W
0x7FFF03
Reserved
R
W
0x7FFF04
Reserved
R
W
0x7FFF05
Reserved
R
W
0x7FFF06
BDMCCRL R
W
0x7FFF07
BDMCCRH R
W
0x7FFF08
BDMGPR
R
W
0x7FFF09
Reserved
R
W
0x7FFF0A
Reserved
R
W
0x7FFF0B
Reserved
R
W
= Unimplemented, Reserved
X
= Indeterminate
= Implemented (do not alter)
0
= Always read zero
Figure 7-2. BDM Register Summary
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Chapter 7 Background Debug Module (S12XBDMV2)
7.3.2.1
BDM Status Register (BDMSTS)
Register Global Address 0x7FFF01
7
R
W
ENBDM
6
5
4
3
BDMACT
0
SDV
TRACE
1
0
0
0
2
1
0
UNSEC
0
0
03
0
2
1
0
0
0
0
0
CLKSW
Reset
Special Single-Chip Mode
Emulation Modes
01
1
0
0
0
0
0
0
0
0
(if modes available)
All Other Modes
0
= Unimplemented, Reserved
0
= Implemented (do not alter)
= Always read zero
1
ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (non-volatile memory). This is because the ENBDM bit is set by the standard firmware before a BDM command
can be fully transmitted and executed.
2 CLKSW is read as 1 by a debugging environment in emulation modes when the device is not secured and read as 0 when
secured if emulation modes available.
3 UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
Figure 7-3. BDM Status Register (BDMSTS)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured, but subject to the following:
— ENBDM should only be set via a BDM hardware command if the BDM firmware commands
are needed. (This does not apply in special single chip and emulation modes).
— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by
the standard BDM firmware lookup table upon exit from BDM active mode.
— CLKSW can only be written via BDM hardware WRITE_BD commands.
— All other bits, while writable via BDM hardware or standard BDM firmware write commands,
should only be altered by the BDM hardware or standard firmware lookup table as part of BDM
command execution.
Table 7-2. BDMSTS Field Descriptions
Field
Description
7
ENBDM
Enable BDM — This bit controls whether the BDM is enabled or disabled. When enabled, BDM can be made
active to allow firmware commands to be executed. When disabled, BDM cannot be made active but BDM
hardware commands are still allowed.
0 BDM disabled
1 BDM enabled
Note: ENBDM is set by the firmware out of reset in special single chip mode. In emulation modes (if modes
available) the ENBDM bit is set by BDM hardware out of reset. In special single chip mode with the device
secured, this bit will not be set by the firmware until after the non-volatile memory erase verify tests are
complete. In emulation modes (if modes available) with the device secured, the BDM operations are
blocked.
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Table 7-2. BDMSTS Field Descriptions (continued)
Field
Description
6
BDMACT
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM firmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM firmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
0 BDM not active
1 BDM active
4
SDV
Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as
part of a firmware or hardware read command or after data has been received as part of a firmware or hardware
write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used
by the standard BDM firmware to control program flow execution.
0 Data phase of command not complete
1 Data phase of command is complete
3
TRACE
TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 firmware
command is first recognized. It will stay set until BDM firmware is exited by one of the following BDM commands:
GO or GO_UNTIL.
0 TRACE1 command is not being executed
1 TRACE1 command is being executed
2
CLKSW
Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware
BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the
command send to change the clock source should occur before the next command can be send. The delay
should be obtained no matter which bit is modified to effectively change the clock source (either PLLSEL bit or
CLKSW bit). This guarantees that the start of the next BDM command uses the new clock for timing subsequent
BDM communications.
Table 7-3 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (PLL select in the CRG
module, the bit is part of the CLKSEL register) bits.
Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial
interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency
restriction on the alternate clock which was required on previous versions. Refer to the device
specification to determine which clock connects to the alternate clock source input.
Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new
rate for the write command which changes it.
Note: In emulation modes (if modes available), the CLKSW bit will be set out of RESET.
1
UNSEC
Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure
firmware. It is in a zero state as secure mode is entered so that the secure BDM firmware lookup table is enabled
and put into the memory map overlapping the standard BDM firmware lookup table.
The secure BDM firmware lookup table verifies that the non-volatile memories (e.g. on-chip EEPROM and/or
Flash EEPROM) are erased. This being the case, the UNSEC bit is set and the BDM program jumps to the start
of the standard BDM firmware lookup table and the secure BDM firmware lookup table is turned off. If the erase
test fails, the UNSEC bit will not be asserted.
0 System is in a secured mode.
1 System is in a unsecured mode.
Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip
Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the
system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect
when the security byte in the Flash EEPROM is configured for unsecure mode.
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Table 7-3. BDM Clock Sources
PLLSEL
CLKSW
0
0
Bus clock dependent on oscillator
0
1
Bus clock dependent on oscillator
1
0
Alternate clock (refer to the device specification to determine the alternate clock source)
1
1
Bus clock dependent on the PLL
7.3.2.2
BDMCLK
BDM CCR LOW Holding Register (BDMCCRL)
Register Global Address 0x7FFF06
7
6
5
4
3
2
1
0
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
Special Single-Chip Mode
1
1
0
0
1
0
0
0
All Other Modes
0
0
0
0
0
0
0
0
R
W
Reset
Figure 7-4. BDM CCR LOW Holding Register (BDMCCRL)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCRL register
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCRL register in this CPU mode. Out of reset in all other modes the
BDMCCRL register is read zero.
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
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7.3.2.3
BDM CCR HIGH Holding Register (BDMCCRH)
Register Global Address 0x7FFF07
R
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
W
Reset
2
1
0
CCR10
CCR9
CCR8
0
0
0
= Unimplemented or Reserved
Figure 7-5. BDM CCR HIGH Holding Register (BDMCCRH)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
When entering background debug mode, the BDM CCR HIGH holding register is used to save the high
byte of the condition code register of the user’s program. The BDM CCR HIGH holding register can be
written to modify the CCR value.
7.3.2.4
BDM Global Page Index Register (BDMGPR)
Register Global Address 0x7FFF08
R
W
Reset
7
6
5
4
3
2
1
0
BGAE
BGP6
BGP5
BGP4
BGP3
BGP2
BGP1
BGP0
0
0
0
0
0
0
0
0
Figure 7-6. BDM Global Page Register (BDMGPR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
Table 7-4. BDMGPR Field Descriptions
Field
Description
7
BGAE
BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and firmware
read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and
WRITE_BD_) can not be used for global accesses even if the BGAE bit is set.
0 BDM Global Access disabled
1 BDM Global Access enabled
6–0
BGP[6:0]
BDM Global Page Index Bits 6–0 — These bits define the extended address bits from 22 to 16. For more
detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.
7.3.3
Family ID Assignment
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x7FFF0F). The read-only
value is a unique family ID which is 0xC1 for S12X devices.
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7.4
Functional Description
The BDM receives and executes commands from a host via a single wire serial interface. There are two
types of BDM commands: hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode, see Section 7.4.3, “BDM Hardware Commands”. Target system memory
includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug
mode, see Section 7.4.4, “Standard BDM Firmware Commands”. The CPU resources referred to are the
accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as
highlighted (see Section 7.4.3, “BDM Hardware Commands”) and in secure mode (see Section 7.4.1,
“Security”). Firmware commands can only be executed when the system is not secure and is in active
background debug mode (BDM).
7.4.1
Security
If the user resets into special single chip mode with the system secured, a secured mode BDM firmware
lookup table is brought into the map overlapping a portion of the standard BDM firmware lookup table.
The secure BDM firmware verifies that the on-chip non-volatile memory (e.g. EEPROM and Flash
EEPROM) is erased. This being the case, the UNSEC and ENBDM bit will get set. The BDM program
jumps to the start of the standard BDM firmware and the secured mode BDM firmware is turned off and
all BDM commands are allowed. If the non-volatile memory does not verify as erased, the BDM firmware
sets the ENBDM bit, without asserting UNSEC, and the firmware enters a loop. This causes the BDM
hardware commands to become enabled, but does not enable the firmware commands. This allows the
BDM hardware to be used to erase the non-volatile memory.
BDM operation is not possible in any other mode than special single chip mode when the device is secured.
The device can be unsecured via BDM serial interface in special single chip mode only. For more
information regarding security, please see the S12X_9SEC Block Guide.
7.4.2
Enabling and Activating BDM
The system must be in active BDM to execute standard BDM firmware commands. BDM can be activated
only after being enabled. BDM is enabled by setting the ENBDM bit in the BDM status (BDMSTS)
register. The ENBDM bit is set by writing to the BDM status (BDMSTS) register, via the single-wire
interface, using a hardware command such as WRITE_BD_BYTE.
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After being enabled, BDM is activated by one of the following1:
• Hardware BACKGROUND command
• CPU BGND instruction
• External instruction tagging mechanism2
• Breakpoint force or tag mechanism2
When BDM is activated, the CPU finishes executing the current instruction and then begins executing the
firmware in the standard BDM firmware lookup table. When BDM is activated by a breakpoint, the type
of breakpoint used determines if BDM becomes active before or after execution of the next instruction.
NOTE
If an attempt is made to activate BDM before being enabled, the CPU
resumes normal instruction execution after a brief delay. If BDM is not
enabled, any hardware BACKGROUND commands issued are ignored by
the BDM and the CPU is not delayed.
In active BDM, the BDM registers and standard BDM firmware lookup table are mapped to addresses
0x7FFF00 to 0x7FFFFF. BDM registers are mapped to addresses 0x7FFF00 to 0x7FFF0B. The BDM uses
these registers which are readable anytime by the BDM. However, these registers are not readable by user
programs.
7.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode. Target system memory includes all memory that is accessible by the CPU on the
SOC which can be on-chip RAM, non-volatile memory (e.g. EEPROM, Flash EEPROM), I/O and control
registers, and all external memory.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to
be in active BDM for execution, although, they can still be executed in this mode. When executing a
hardware command, the BDM sub-block waits for a free bus cycle so that the background access does not
disturb the running application program. If a free cycle is not found within 128 clock cycles, the CPU is
momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the operation
does not intrude on normal CPU operation provided that it can be completed in a single cycle. However,
if an operation requires multiple cycles the CPU is frozen until the operation is complete, even though the
BDM found a free cycle.
The BDM hardware commands are listed in Table 7-5.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations
are not normally in the system memory map but share addresses with the application in memory. To
distinguish between physical memory locations that share the same address, BDM memory resources are
enabled just for the READ_BD and WRITE_BD access cycle. This allows the BDM to access BDM
locations unobtrusively, even if the addresses conflict with the application memory map.
1. BDM is enabled and active immediately out of special single-chip reset.
2. This method is provided by the S12X_DBG module.
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Chapter 7 Background Debug Module (S12XBDMV2)
Table 7-5. Hardware Commands
Opcode
(hex)
Data
BACKGROUND
90
None
Enter background mode if firmware is enabled. If enabled, an ACK will be
issued when the part enters active background mode.
ACK_ENABLE
D5
None
Enable Handshake. Issues an ACK pulse after the command is executed.
ACK_DISABLE
D6
None
Disable Handshake. This command does not issue an ACK pulse.
READ_BD_BYTE
E4
16-bit address Read from memory with standard BDM firmware lookup table in map.
16-bit data out Odd address data on low byte; even address data on high byte.
READ_BD_WORD
EC
16-bit address Read from memory with standard BDM firmware lookup table in map.
16-bit data out Must be aligned access.
READ_BYTE
E0
16-bit address Read from memory with standard BDM firmware lookup table out of map.
16-bit data out Odd address data on low byte; even address data on high byte.
READ_WORD
E8
16-bit address Read from memory with standard BDM firmware lookup table out of map.
16-bit data out Must be aligned access.
WRITE_BD_BYTE
C4
16-bit address Write to memory with standard BDM firmware lookup table in map.
16-bit data in Odd address data on low byte; even address data on high byte.
WRITE_BD_WORD
CC
16-bit address Write to memory with standard BDM firmware lookup table in map.
16-bit data in Must be aligned access.
WRITE_BYTE
C0
16-bit address Write to memory with standard BDM firmware lookup table out of map.
16-bit data in Odd address data on low byte; even address data on high byte.
WRITE_WORD
C8
16-bit address Write to memory with standard BDM firmware lookup table out of map.
16-bit data in Must be aligned access.
Command
Description
NOTE:
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
7.4.4
Standard BDM Firmware Commands
Firmware commands are used to access and manipulate CPU resources. The system must be in active
BDM to execute standard BDM firmware commands, see Section 7.4.2, “Enabling and Activating BDM”.
Normal instruction execution is suspended while the CPU executes the firmware located in the standard
BDM firmware lookup table. The hardware command BACKGROUND is the usual way to activate BDM.
As the system enters active BDM, the standard BDM firmware lookup table and BDM registers become
visible in the on-chip memory map at 0x7FFF00–0x7FFFFF, and the CPU begins executing the standard
BDM firmware. The standard BDM firmware watches for serial commands and executes them as they are
received.
The firmware commands are shown in Table 7-6.
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Table 7-6. Firmware Commands
Command1
Opcode
(hex)
Data
Description
READ_NEXT2
62
16-bit data out Increment X index register by 2 (X = X + 2), then read word X points to.
READ_PC
63
16-bit data out Read program counter.
READ_D
64
16-bit data out Read D accumulator.
READ_X
65
16-bit data out Read X index register.
READ_Y
66
16-bit data out Read Y index register.
READ_SP
67
16-bit data out Read stack pointer.
WRITE_NEXT
42
16-bit data in
Increment X index register by 2 (X = X + 2), then write word to location
pointed to by X.
WRITE_PC
43
16-bit data in
Write program counter.
WRITE_D
44
16-bit data in
Write D accumulator.
WRITE_X
45
16-bit data in
Write X index register.
WRITE_Y
46
16-bit data in
Write Y index register.
WRITE_SP
47
16-bit data in
Write stack pointer.
GO
08
none
Go to user program. If enabled, ACK will occur when leaving active
background mode.
GO_UNTIL3
0C
none
Go to user program. If enabled, ACK will occur upon returning to active
background mode.
TRACE1
10
none
Execute one user instruction then return to active BDM. If enabled,
ACK will occur upon returning to active background mode.
TAGGO -> GO
18
none
(Previous enable tagging and go to user program.)
This command will be deprecated and should not be used anymore.
Opcode will be executed as a GO command.
1
If enabled, ACK will occur when data is ready for transmission for all BDM READ commands and will occur after the write is
complete for all BDM WRITE commands.
2 When the firmware command READ_NEXT or WRITE_NEXT is used to access the BDM address space the BDM resources
are accessed rather than user code. Writing BDM firmware is not possible.
3 System stop disables the ACK function and ignored commands will not have an ACK-pulse (e.g., CPU in stop or wait mode).
The GO_UNTIL command will not get an Acknowledge if CPU executes the wait or stop instruction before the “UNTIL”
condition (BDM active again) is reached (see Section 7.4.7, “Serial Interface Hardware Handshake Protocol” last Note).
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7.4.5
BDM Command Structure
Hardware and firmware BDM commands start with an 8-bit opcode followed by a 16-bit address and/or a
16-bit data word depending on the command. All the read commands return 16 bits of data despite the byte
or word implication in the command name.
8-bit reads return 16-bits of data, of which, only one byte will contain valid
data. If reading an even address, the valid data will appear in the MSB. If
reading an odd address, the valid data will appear in the LSB.
16-bit misaligned reads and writes are generally not allowed. If attempted
by BDM hardware command, the BDM will ignore the least significant bit
of the address and will assume an even address from the remaining bits.
For devices with external bus:
The following cycle count information is only valid when the external wait
function is not used (see wait bit of EBI sub-block). During an external wait
the BDM can not steal a cycle. Hence be careful with the external wait
function if the BDM serial interface is much faster than the bus, because of
the BDM soft-reset after time-out (see Section 7.4.11, “Serial
Communication Time Out”).
For hardware data read commands, the external host must wait at least 150 bus clock cycles after sending
the address before attempting to obtain the read data. This is to be certain that valid data is available in the
BDM shift register, ready to be shifted out. For hardware write commands, the external host must wait
150 bus clock cycles after sending the data to be written before attempting to send a new command. This
is to avoid disturbing the BDM shift register before the write has been completed. The 150 bus clock cycle
delay in both cases includes the maximum 128 cycle delay that can be incurred as the BDM waits for a
free cycle before stealing a cycle.
For firmware read commands, the external host should wait at least 48 bus clock cycles after sending the
command opcode and before attempting to obtain the read data. This includes the potential of extra cycles
when the access is external and stretched (+1 to maximum +7 cycles) or to registers of the PRU (port
replacement unit) in emulation modes (if modes available). The 48 cycle wait allows enough time for the
requested data to be made available in the BDM shift register, ready to be shifted out.
NOTE
This timing has increased from previous BDM modules due to the new
capability in which the BDM serial interface can potentially run faster than
the bus. On previous BDM modules this extra time could be hidden within
the serial time.
For firmware write commands, the external host must wait 36 bus clock cycles after sending the data to be
written before attempting to send a new command. This is to avoid disturbing the BDM shift register
before the write has been completed.
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The external host should wait at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
NOTE
If the bus rate of the target processor is unknown or could be changing or the
external wait function is used, it is recommended that the ACK
(acknowledge function) is used to indicate when an operation is complete.
When using ACK, the delay times are automated.
Figure 7-7 represents the BDM command structure. The command blocks illustrate a series of eight bit
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 × 16 target clock cycles.1
Hardware
Read
8 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
Command
Address
150-BC
Delay
16 Bits
AT ~16 TC/Bit
Data
Next
Command
150-BC
Delay
Hardware
Write
Command
Address
Next
Command
Data
48-BC
DELAY
Firmware
Read
Command
Next
Command
Data
36-BC
DELAY
Firmware
Write
Command
Data
Next
Command
76-BC
Delay
GO,
TRACE
Command
Next
Command
BC = Bus Clock Cycles
TC = Target Clock Cycles
Figure 7-7. BDM Command Structure
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See Section 7.4.6, “BDM Serial Interface”
and Section 7.3.2.1, “BDM Status Register (BDMSTS)” for information on how serial clock rate is selected.
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7.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed using the clock selected by the CLKSW bit in the status register see
Section 7.3.2.1, “BDM Status Register (BDMSTS)”. This clock will be referred to as the target clock in
the following explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 7-8 and that of target-to-host in Figure 7-9 and
Figure 7-10. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since
the host and target are operating from separate clocks, it can take the target system up to one full clock
cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the
host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
earlier. Synchronization between the host and target is established in this manner at the start of every bit
time.
Figure 7-8 shows an external host transmitting a logic 1 and transmitting a logic 0 to the BKGD pin of a
target system. The host is asynchronous to the target, so there is up to a one clock-cycle delay from the
host-generated falling edge to where the target recognizes this edge as the beginning of the bit time. Ten
target clock cycles later, the target senses the bit level on the BKGD pin. Internal glitch detect logic
requires the pin be driven high no later that eight target clock cycles after the falling edge for a logic 1
transmission.
Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven
signals.
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BDM Clock
(Target MCU)
Host
Transmit 1
Host
Transmit 0
Perceived
Start of Bit Time
Target Senses Bit
Earliest
Start of
Next Bit
10 Cycles
Synchronization
Uncertainty
Figure 7-8. BDM Host-to-Target Serial Bit Timing
The receive cases are more complicated. Figure 7-9 shows the host receiving a logic 1 from the target
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
Target System
Speedup
Pulse
High-Impedance
High-Impedance
High-Impedance
Perceived
Start of Bit Time
R-C Rise
BKGD Pin
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Earliest
Start of
Next Bit
Figure 7-9. BDM Target-to-Host Serial Bit Timing (Logic 1)
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Figure 7-10 shows the host receiving a logic 0 from the target. Since the host is asynchronous to the target,
there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of the bit
time as perceived by the target. The host initiates the bit time but the target finishes it. Since the target
wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly drives
it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after starting
the bit time.
BDM Clock
(Target MCU)
Host
Drive to
BKGD Pin
High-Impedance
Speedup Pulse
Target System
Drive and
Speedup Pulse
Perceived
Start of Bit Time
BKGD Pin
10 Cycles
10 Cycles
Host Samples
BKGD Pin
Earliest
Start of
Next Bit
Figure 7-10. BDM Target-to-Host Serial Bit Timing (Logic 0)
7.4.7
Serial Interface Hardware Handshake Protocol
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Since the BDM
clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to
provide a handshake protocol in which the host could determine when an issued command is executed by
the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles at
the slowest possible rate the clock could be running. This sub-section will describe the hardware
handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a
brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued
by the host, has been successfully executed (see Figure 7-11). This pulse is referred to as the ACK pulse.
After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read
command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL or TRACE1). The ACK pulse is not issued earlier than 32 serial clock
cycles after the BDM command was issued. The end of the BDM command is assumed to be the 16th tick
of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse. Note also
that, there is no upper limit for the delay between the command and the related ACK pulse, since the
command execution depends upon the CPU bus frequency, which in some cases could be very slow
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compared to the serial communication rate. This protocol allows a great flexibility for the POD designers,
since it does not rely on any accurate time measurement or short response time to any event in the serial
communication.
BDM Clock
(Target MCU)
16 Cycles
Target
Transmits
ACK Pulse
High-Impedance
High-Impedance
32 Cycles
Speedup Pulse
Minimum Delay
From the BDM Command
BKGD Pin
Earliest
Start of
Next Bit
16th Tick of the
Last Command Bit
Figure 7-11. Target Acknowledge Pulse (ACK)
NOTE
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters wait or stop prior to executing a
hardware command, the ACK pulse will not be issued meaning that the
BDM command was not executed. After entering wait or stop mode, the
BDM command is no longer pending.
Figure 7-12 shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE
instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the
address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed
(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the
BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.
After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form
of a word and the host needs to determine which is the appropriate byte based on whether the address was
odd or even.
Target
BKGD Pin READ_BYTE
Host
Byte Address
Host
(2) Bytes are
Retrieved
New BDM
Command
Host
Target
Target
BDM Issues the
ACK Pulse (out of scale)
BDM Decodes
the Command
BDM Executes the
READ_BYTE Command
Figure 7-12. Handshake Protocol at Command Level
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Differently from the normal bit transfer (where the host initiates the transmission), the serial interface ACK
handshake pulse is initiated by the target MCU by issuing a negative edge in the BKGD pin. The hardware
handshake protocol in Figure 7-11 specifies the timing when the BKGD pin is being driven, so the host
should follow this timing constraint in order to avoid the risk of an electrical conflict in the BKGD pin.
NOTE
The only place the BKGD pin can have an electrical conflict is when one
side is driving low and the other side is issuing a speedup pulse (high). Other
“highs” are pulled rather than driven. However, at low rates the time of the
speedup pulse can become lengthy and so the potential conflict time
becomes longer as well.
The ACK handshake protocol does not support nested ACK pulses. If a BDM command is not
acknowledge by an ACK pulse, the host needs to abort the pending command first in order to be able to
issue a new BDM command. When the CPU enters wait or stop while the host issues a hardware command
(e.g., WRITE_BYTE), the target discards the incoming command due to the wait or stop being detected.
Therefore, the command is not acknowledged by the target, which means that the ACK pulse will not be
issued in this case. After a certain time the host (not aware of stop or wait) should decide to abort any
possible pending ACK pulse in order to be sure a new command can be issued. Therefore, the protocol
provides a mechanism in which a command, and its corresponding ACK, can be aborted.
NOTE
The ACK pulse does not provide a time out. This means for the GO_UNTIL
command that it can not be distinguished if a stop or wait has been executed
(command discarded and ACK not issued) or if the “UNTIL” condition
(BDM active) is just not reached yet. Hence in any case where the ACK
pulse of a command is not issued the possible pending command should be
aborted before issuing a new command. See the handshake abort procedure
described in Section 7.4.8, “Hardware Handshake Abort Procedure”.
7.4.8
Hardware Handshake Abort Procedure
The abort procedure is based on the SYNC command. In order to abort a command, which had not issued
the corresponding ACK pulse, the host controller should generate a low pulse in the BKGD pin by driving
it low for at least 128 serial clock cycles and then driving it high for one serial clock cycle, providing a
speedup pulse. By detecting this long low pulse in the BKGD pin, the target executes the SYNC protocol,
see Section 7.4.9, “SYNC — Request Timed Reference Pulse”, and assumes that the pending command
and therefore the related ACK pulse, are being aborted. Therefore, after the SYNC protocol has been
completed the host is free to issue new BDM commands. For Firmware READ or WRITE commands it
can not be guaranteed that the pending command is aborted when issuing a SYNC before the
corresponding ACK pulse. There is a short latency time from the time the READ or WRITE access begins
until it is finished and the corresponding ACK pulse is issued. The latency time depends on the firmware
READ or WRITE command that is issued and if the serial interface is running on a different clock rate
than the bus. When the SYNC command starts during this latency time the READ or WRITE command
will not be aborted, but the corresponding ACK pulse will be aborted. A pending GO, TRACE1 or
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GO_UNTIL command can not be aborted. Only the corresponding ACK pulse can be aborted by the
SYNC command.
Although it is not recommended, the host could abort a pending BDM command by issuing a low pulse in
the BKGD pin shorter than 128 serial clock cycles, which will not be interpreted as the SYNC command.
The ACK is actually aborted when a negative edge is perceived by the target in the BKGD pin. The short
abort pulse should have at least 4 clock cycles keeping the BKGD pin low, in order to allow the negative
edge to be detected by the target. In this case, the target will not execute the SYNC protocol but the pending
command will be aborted along with the ACK pulse. The potential problem with this abort procedure is
when there is a conflict between the ACK pulse and the short abort pulse. In this case, the target may not
perceive the abort pulse. The worst case is when the pending command is a read command (i.e.,
READ_BYTE). If the abort pulse is not perceived by the target the host will attempt to send a new
command after the abort pulse was issued, while the target expects the host to retrieve the accessed
memory byte. In this case, host and target will run out of synchronism. However, if the command to be
aborted is not a read command the short abort pulse could be used. After a command is aborted the target
assumes the next negative edge, after the abort pulse, is the first bit of a new BDM command.
NOTE
The details about the short abort pulse are being provided only as a reference
for the reader to better understand the BDM internal behavior. It is not
recommended that this procedure be used in a real application.
Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)
does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC
very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to
assure the SYNC pulse will not be misinterpreted by the target. See Section 7.4.9, “SYNC — Request
Timed Reference Pulse”.
Figure 7-13 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE
command. Note that, after the command is aborted a new command could be issued by the host computer.
READ_BYTE CMD is Aborted
by the SYNC Request
(Out of Scale)
BKGD Pin READ_BYTE
Host
Memory Address
Target
BDM Decode
and Starts to Execute
the READ_BYTE Command
SYNC Response
From the Target
(Out of Scale)
READ_STATUS
Host
Target
New BDM Command
Host
Target
New BDM Command
Figure 7-13. ACK Abort Procedure at the Command Level
NOTE
Figure 7-13 does not represent the signals in a true timing scale
Figure 7-14 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
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Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
At Least 128 Cycles
BDM Clock
(Target MCU)
ACK Pulse
Target MCU
Drives to
BKGD Pin
High-Impedance
Host and
Target Drive
to BKGD Pin
Host
Drives SYNC
To BKGD Pin
Electrical Conflict
Speedup Pulse
Host SYNC Request Pulse
BKGD Pin
16 Cycles
Figure 7-14. ACK Pulse and SYNC Request Conflict
NOTE
This information is being provided so that the MCU integrator will be aware
that such a conflict could eventually occur.
The hardware handshake protocol is enabled by the ACK_ENABLE and disabled by the ACK_DISABLE
BDM commands. This provides backwards compatibility with the existing POD devices which are not
able to execute the hardware handshake protocol. It also allows for new POD devices, that support the
hardware handshake protocol, to freely communicate with the target device. If desired, without the need
for waiting for the ACK pulse.
The commands are described as follows:
• ACK_ENABLE — enables the hardware handshake protocol. The target will issue the ACK pulse
when a CPU command is executed by the CPU. The ACK_ENABLE command itself also has the
ACK pulse as a response.
• ACK_DISABLE — disables the ACK pulse protocol. In this case, the host needs to use the worst
case delay time at the appropriate places in the protocol.
The default state of the BDM after reset is hardware handshake protocol disabled.
All the read commands will ACK (if enabled) when the data bus cycle has completed and the data is then
ready for reading out by the BKGD serial pin. All the write commands will ACK (if enabled) after the data
has been received by the BDM through the BKGD serial pin and when the data bus cycle is complete. See
Section 7.4.3, “BDM Hardware Commands” and Section 7.4.4, “Standard BDM Firmware Commands”
for more information on the BDM commands.
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The ACK_ENABLE sends an ACK pulse when the command has been completed. This feature could be
used by the host to evaluate if the target supports the hardware handshake protocol. If an ACK pulse is
issued in response to this command, the host knows that the target supports the hardware handshake
protocol. If the target does not support the hardware handshake protocol the ACK pulse is not issued. In
this case, the ACK_ENABLE command is ignored by the target since it is not recognized as a valid
command.
The BACKGROUND command will issue an ACK pulse when the CPU changes from normal to
background mode. The ACK pulse related to this command could be aborted using the SYNC command.
The GO command will issue an ACK pulse when the CPU exits from background mode. The ACK pulse
related to this command could be aborted using the SYNC command.
The GO_UNTIL command is equivalent to a GO command with exception that the ACK pulse, in this
case, is issued when the CPU enters into background mode. This command is an alternative to the GO
command and should be used when the host wants to trace if a breakpoint match occurs and causes the
CPU to enter active background mode. Note that the ACK is issued whenever the CPU enters BDM, which
could be caused by a breakpoint match or by a BGND instruction being executed. The ACK pulse related
to this command could be aborted using the SYNC command.
The TRACE1 command has the related ACK pulse issued when the CPU enters background active mode
after one instruction of the application program is executed. The ACK pulse related to this command could
be aborted using the SYNC command.
7.4.9
SYNC — Request Timed Reference Pulse
The SYNC command is unlike other BDM commands because the host does not necessarily know the
correct communication speed to use for BDM communications until after it has analyzed the response to
the SYNC command. To issue a SYNC command, the host should perform the following steps:
1. Drive the BKGD pin low for at least 128 cycles at the lowest possible BDM serial communication
frequency (the lowest serial communication frequency is determined by the crystal oscillator or the
clock chosen by CLKSW.)
2. Drive BKGD high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically
one cycle of the host clock.)
3. Remove all drive to the BKGD pin so it reverts to high impedance.
4. Listen to the BKGD pin for the sync response pulse.
Upon detecting the SYNC request from the host, the target performs the following steps:
1. Discards any incomplete command received or bit retrieved.
2. Waits for BKGD to return to a logic one.
3. Delays 16 cycles to allow the host to stop driving the high speedup pulse.
4. Drives BKGD low for 128 cycles at the current BDM serial communication frequency.
5. Drives a one-cycle high speedup pulse to force a fast rise time on BKGD.
6. Removes all drive to the BKGD pin so it reverts to high impedance.
The host measures the low time of this 128 cycle SYNC response pulse and determines the correct speed
for subsequent BDM communications. Typically, the host can determine the correct communication speed
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within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
As soon as the SYNC request is detected by the target, any partially received command or bit retrieved is
discarded. This is referred to as a soft-reset, equivalent to a time-out in the serial communication. After the
SYNC response, the target will consider the next negative edge (issued by the host) as the start of a new
BDM command or the start of new SYNC request.
Another use of the SYNC command pulse is to abort a pending ACK pulse. The behavior is exactly the
same as in a regular SYNC command. Note that one of the possible causes for a command to not be
acknowledged by the target is a host-target synchronization problem. In this case, the command may not
have been understood by the target and so an ACK response pulse will not be issued.
7.4.10
Instruction Tracing
When a TRACE1 command is issued to the BDM in active BDM, the CPU exits the standard BDM
firmware and executes a single instruction in the user code. Once this has occurred, the CPU is forced to
return to the standard BDM firmware and the BDM is active and ready to receive a new command. If the
TRACE1 command is issued again, the next user instruction will be executed. This facilitates stepping or
tracing through the user code one instruction at a time.
If an interrupt is pending when a TRACE1 command is issued, the interrupt stacking operation occurs but
no user instruction is executed. Once back in standard BDM firmware execution, the program counter
points to the first instruction in the interrupt service routine.
Be aware when tracing through the user code that the execution of the user code is done step by step but
all peripherals are free running. Hence possible timing relations between CPU code execution and
occurrence of events of other peripherals no longer exist.
Do not trace the CPU instruction BGND used for soft breakpoints. Tracing the BGND instruction will
result in a return address pointing to BDM firmware address space.
When tracing through user code which contains stop or wait instructions the following will happen when
the stop or wait instruction is traced:
The CPU enters stop or wait mode and the TRACE1 command can not be finished before leaving
the low power mode. This is the case because BDM active mode can not be entered after CPU
executed the stop instruction. However all BDM hardware commands except the BACKGROUND
command are operational after tracing a stop or wait instruction and still being in stop or wait
mode. If system stop mode is entered (all bus masters are in stop mode) no BDM command is
operational.
As soon as stop or wait mode is exited the CPU enters BDM active mode and the saved PC value
points to the entry of the corresponding interrupt service routine.
In case the handshake feature is enabled the corresponding ACK pulse of the TRACE1 command
will be discarded when tracing a stop or wait instruction. Hence there is no ACK pulse when BDM
active mode is entered as part of the TRACE1 command after CPU exited from stop or wait mode.
All valid commands sent during CPU being in stop or wait mode or after CPU exited from stop or
wait mode will have an ACK pulse. The handshake feature becomes disabled only when system
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stop mode has been reached. Hence after a system stop mode the handshake feature must be
enabled again by sending the ACK_ENABLE command.
7.4.11
Serial Communication Time Out
The host initiates a host-to-target serial transmission by generating a falling edge on the BKGD pin. If
BKGD is kept low for more than 128 target clock cycles, the target understands that a SYNC command
was issued. In this case, the target will keep waiting for a rising edge on BKGD in order to answer the
SYNC request pulse. If the rising edge is not detected, the target will keep waiting forever without any
time-out limit.
Consider now the case where the host returns BKGD to logic one before 128 cycles. This is interpreted as
a valid bit transmission, and not as a SYNC request. The target will keep waiting for another falling edge
marking the start of a new bit. If, however, a new falling edge is not detected by the target within 512 clock
cycles since the last falling edge, a time-out occurs and the current command is discarded without affecting
memory or the operating mode of the MCU. This is referred to as a soft-reset.
If a read command is issued but the data is not retrieved within 512 serial clock cycles, a soft-reset will
occur causing the command to be disregarded. The data is not available for retrieval after the time-out has
occurred. This is the expected behavior if the handshake protocol is not enabled. However, consider the
behavior where the BDM is running in a frequency much greater than the CPU frequency. In this case, the
command could time out before the data is ready to be retrieved. In order to allow the data to be retrieved
even with a large clock frequency mismatch (between BDM and CPU) when the hardware handshake
protocol is enabled, the time out between a read command and the data retrieval is disabled. Therefore, the
host could wait for more then 512 serial clock cycles and still be able to retrieve the data from an issued
read command. However, once the handshake pulse (ACK pulse) is issued, the time-out feature is
re-activated, meaning that the target will time out after 512 clock cycles. Therefore, the host needs to
retrieve the data within a 512 serial clock cycles time frame after the ACK pulse had been issued. After
that period, the read command is discarded and the data is no longer available for retrieval. Any negative
edge in the BKGD pin after the time-out period is considered to be a new command or a SYNC request.
Note that whenever a partially issued command, or partially retrieved data, has occurred the time out in the
serial communication is active. This means that if a time frame higher than 512 serial clock cycles is
observed between two consecutive negative edges and the command being issued or data being retrieved
is not complete, a soft-reset will occur causing the partially received command or data retrieved to be
disregarded. The next negative edge in the BKGD pin, after a soft-reset has occurred, is considered by the
target as the start of a new BDM command, or the start of a SYNC request pulse.
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S12X Debug (S12XDBGV3) Module
Revision History
Revision Number
8.1
Date
Author
Summary of Changes
03.17
20.MAR.2007
Tabulated glossary
Renamed S12XCPU to CPU12X
03.18
20.APR.2007
Added “Data Bus Comparison NDB Dependency” section
Clarified effect TRIG has on state sequencer
03.19
24.APR.2007
Clarified simultaneous arm and disarm effect
Introduction
The S12XDBG module provides an on-chip trace buffer with flexible triggering capability to allow
non-intrusive debug of application software. The S12XDBG module is optimized for the S12X 16-bit
architecture and allows debugging of CPU12Xand XGATE module operations.
Typically the S12XDBG module is used in conjunction with the S12XBDM module, whereby the user
configures the S12XDBG module for a debugging session over the BDM interface. Once configured the
S12XDBG module is armed and the device leaves BDM Mode returning control to the user program,
which is then monitored by the S12XDBG module. Alternatively the S12XDBG module can be configured
over a serial interface using SWI routines.
8.1.1
Glossary
Table 8-1. Glossary Of Terms
Term
COF
BDM
DUG
WORD
Definition
Change Of Flow.
Change in the program flow due to a conditional branch, indexed jump or interrupt
Background Debug Mode
Device User Guide, describing the features of the device into which the DBG is integrated
16 bit data entity
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Table 8-1. Glossary Of Terms
Term
Definition
Data Line
64 bit data entity
CPU
CPU12X module
Tag
Tags can be attached to XGATE or CPU opcodes as they enter the instruction pipe. If the
tagged opcode reaches the execution stage a tag hit occurs.
8.1.2
Overview
The comparators monitor the bus activity of the CPU12X and XGATE. When a match occurs the control
logic can trigger the state sequencer to a new state. On a transition to the Final State, bus tracing is triggered
and/or a breakpoint can be generated.
Independent of comparator matches a transition to Final State with associated tracing and breakpoint can
be triggered by the external TAGHI and TAGLO signals, or by an XGATE module S/W breakpoint request
or by writing to the TRIG control bit.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads. Tracing is disabled when the MCU system is secured.
8.1.3
•
•
•
•
Features
Four comparators (A, B, C, and D)
— Comparators A and C compare the full address bus and full 16-bit data bus
— Comparators A and C feature a data bus mask register
— Comparators B and D compare the full address bus only
— Each comparator can be configured to monitor CPU12X or XGATE buses
— Each comparator features selection of read or write access cycles
— Comparators B and D allow selection of byte or word access cycles
— Comparisons can be used as triggers for the state sequencer
Three comparator modes
— Simple address/data comparator match mode
— Inside address range mode, Addmin ≤ Address ≤ Addmax
— Outside address range match mode, Address < Addmin or Address > Addmax
Two types of triggers
— Tagged — This triggers just before a specific instruction begins execution
— Force — This triggers on the first instruction boundary after a match occurs.
The following types of breakpoints
— CPU12X breakpoint entering BDM on breakpoint (BDM)
— CPU12X breakpoint executing SWI on breakpoint (SWI)
— XGATE breakpoint
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•
•
•
•
External CPU12X instruction tagging trigger independent of comparators
XGATE S/W breakpoint request trigger independent of comparators
TRIG Immediate software trigger independent of comparators
Four trace modes
— Normal: change of flow (COF) PC information is stored (see Section 8.4.5.2.1) for change of
flow definition.
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
•
8.1.4
Modes of Operation
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled but XGATE bus monitoring
accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM
or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to
generate a breakpoint to the XGATE module. When the CPU12X enters active BDM Mode through a
BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
Table 8-2. Mode Dependent Restriction Summary
BDM
Enable
BDM
Active
MCU
Secure
Comparator
Matches Enabled
Breakpoints
Possible
Tagging
Possible
Tracing
Possible
x
x
1
Yes
Yes
Yes
No
0
0
0
Yes
Only SWI
Yes
Yes
0
1
0
1
0
0
Yes
Yes
Yes
Yes
1
1
0
XGATE only
XGATE only
XGATE only
XGATE only
Active BDM not possible when not enabled
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8.1.5
Block Diagram
TAGS
TAGHITS
EXTERNAL TAGHI / TAGLO
BREAKPOINT REQUESTS
XGATE S/W BREAKPOINT REQUEST
CPU12X & XGATE
XGATE BUS
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MATCH0
COMPARATOR
MATCH CONTROL
CPU12X BUS
BUS INTERFACE
SECURE
MATCH1
TAG &
TRIGGER
CONTROL
LOGIC
TRIGGER
STATE
STATE SEQUENCER
STATE
MATCH2
MATCH3
TRACE
CONTROL
TRIGGER
TRACE BUFFER
READ TRACE DATA (DBG READ DATA BUS)
Figure 8-1. Debug Module Block Diagram
8.2
External Signal Description
The S12XDBG sub-module features two external tag input signals. See Device User Guide (DUG) for the
mapping of these signals to device pins. These tag pins may be used for the external tagging in emulation
modes only.
Table 8-3. External System Pins Associated With S12XDBG
Pin Name
Pin Functions
TAGHI
(See DUG)
TAGHI
When instruction tagging is on, tags the high half of the instruction word being
read into the instruction queue.
TAGLO
(See DUG)
TAGLO
When instruction tagging is on, tags the low half of the instruction word being
read into the instruction queue.
TAGLO
(See DUG)
Unconditional
Tagging Enable
In emulation modes, a low assertion on this pin in the 7th or 8th cycle after the
end of reset enables the Unconditional Tagging function.
8.3
8.3.1
Description
Memory Map and Registers
Module Memory Map
A summary of the registers associated with the S12XDBG sub-block is shown in Table 8-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
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Address
Name
0x0020
DBGC1
R
W
0x0021
DBGSR
R
W
0x0022
DBGTCR
R
W
0x0023
DBGC2
R
W
0
0
0
0
0x0024
DBGTBH
R
W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x0025
DBGTBL
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0026
DBGCNT
R
W
0
0x0027
DBGSCRX
0
0
0
0
SC3
SC2
SC1
SC0
0x0027
DBGMFR
R
W
R
W
0
0
0
0
MC3
MC2
MC1
MC0
DBGXCTL R
(COMPA/C) W
DBGXCTL R
(COMPB/D) W
0
NDB
TAG
BRK
RW
RWE
SRC
COMPE
SZ
TAG
BRK
RW
RWE
SRC
COMPE
Bit 22
21
20
19
18
17
Bit 16
0x00281
0x00282
Bit 7
ARM
TBF
6
0
TRIG
EXTF
5
4
XGSBPE
BDM
0
0
TSOURCE
SZE
0
3
2
1
DBGBRK
0
TRANGE
Bit 0
COMRV
SSF2
SSF1
SSF0
TRCMOD
TALIGN
CDCM
ABCM
CNT
0x0029
DBGXAH
R
W
0x002A
DBGXAM
R
W
Bit 15
14
13
12
11
10
9
Bit 8
0x002B
DBGXAL
R
W
Bit 7
6
5
4
3
2
1
Bit 0
0x002C
DBGXDH
R
W
Bit 15
14
13
12
11
10
9
Bit 8
0x002D
DBGXDL
R
W
Bit 7
6
5
4
3
2
1
Bit 0
0x002E
DBGXDHM
R
W
Bit 15
14
13
12
11
10
9
Bit 8
1
Bit 0
R
Bit 7
6
5
4
3
2
W
1 This represents the contents if the Comparator A or C control register is blended into this address.
2 This represents the contents if the Comparator B or D control register is blended into this address
0x002F
DBGXDLM
Figure 8-2. Quick Reference to S12XDBG Registers
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Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2
Register Descriptions
This section consists of the S12XDBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the S12XDBG module register address map. When ARM is set in DBGC1, the only bits in the
S12XDBG module registers that can be written are ARM, TRIG, and COMRV[1:0]
8.3.2.1
Debug Control Register 1 (DBGC1)
Address: 0x0020
7
R
W
Reset
6
ARM
0
0
TRIG
0
5
4
XGSBPE
BDM
0
0
3
2
1
DBGBRK
0
0
COMRV
0
0
0
Figure 8-3. Debug Control Register (DBGC1)
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 5:2 anytime S12XDBG is not armed.
NOTE
If a write access to DBGC1 with the ARM bit position set occurs
simultaneously to a hardware disarm from an internal trigger event, then the
ARM bit is cleared due to the hardware disarm.
NOTE
When disarming the S12XDBG by clearing ARM with software, the
contents of bits[5:2] are not affected by the write, since up until the write
operation, ARM = 1 preventing these bits from being written. These bits
must be cleared using a second write if required.
Table 8-4. DBGC1 Field Descriptions
Field
Description
7
ARM
Arm Bit — The ARM bit controls whether the S12XDBG module is armed. This bit can be set and cleared by
user software and is automatically cleared on completion of a tracing session, or if a breakpoint is generated with
tracing not enabled. On setting this bit the state sequencer enters State1.
0 Debugger disarmed
1 Debugger armed
6
TRIG
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of
comparator or external tag signal status. When tracing is complete a forced breakpoint may be generated
depending upon DBGBRK and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no
effect. If TSOURCE are clear no tracing is carried out. If tracing has already commenced using BEGIN- or MID
trigger alignment, it continues until the end of the tracing session as defined by the TALIGN bit settings, thus
TRIG has no affect. In secure mode tracing is disabled and writing to this bit has no effect.
0 Do not trigger until the state sequencer enters the Final State.
1 Trigger immediately .
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Table 8-4. DBGC1 Field Descriptions (continued)
Field
5
XGSBPE
Description
XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is
passed to the CPU12X. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can
request an CPU12X breakpoint depending on the state of this bit.
0 XGATE S/W breakpoint request is disabled
1 XGATE S/W breakpoint request is enabled
4
BDM
Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter
Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled
by the ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
3–2
DBGBRK
S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint
to either CPU12X or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the
breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is
generated immediately. Please refer to Section 8.4.7 for further details. XGATE software breakpoints are
independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the CPU12X independent
of the DBGBRK bit field configuration. See Table 8-5.
1–0
COMRV
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See Table 8-6.
Table 8-5. DBGBRK Encoding
DBGBRK
Resource Halted by Breakpoint
00
No breakpoint generated
01
XGATE breakpoint generated
10
CPU12X breakpoint generated
11
Breakpoints generated for CPU12X and XGATE
Table 8-6. COMRV Encoding
8.3.2.2
COMRV
Visible Comparator
Visible Register at 0x0027
00
Comparator A
DBGSCR1
01
Comparator B
DBGSCR2
10
Comparator C
DBGSCR3
11
Comparator D
DBGMFR
Debug Status Register (DBGSR)
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Address: 0x0021
R
7
6
5
4
3
2
1
0
TBF
EXTF
0
0
0
SSF2
SSF1
SSF0
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
POR
= Unimplemented or Reserved
Figure 8-4. Debug Status Register (DBGSR)
Read: Anytime
Write: Never
Table 8-7. DBGSR Field Descriptions
Field
Description
7
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
6
EXTF
External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was
met since arming. This bit is cleared when ARM in DBGC1 is written to a one.
0 External tag hit has not occurred
1 External tag hit has occurred
2–0
SSF[2:0]
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See Table 8-8.
Table 8-8. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0]
Current State
000
State0 (disarmed)
001
State1
010
State2
011
State3
100
Final State
101,110,111
Reserved
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Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.3
Debug Trace Control Register (DBGTCR)
Address: 0x0022
7
6
R
TSOURCE
W
Reset
5
0
4
3
TRANGE
0
0
2
1
TRCMOD
0
0
0
TALIGN
0
0
0
Figure 8-5. Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bits 7:6 only when S12XDBG is neither secure nor armed.
Bits 5:0 anytime the module is disarmed.
Table 8-9. DBGTCR Field Descriptions
Field
7–6
TSOURCE
Description
Trace Source Control Bits — The TSOURCE bits select the data source for the tracing session. If the MCU
system is secured, these bits cannot be set and tracing is inhibited. See Table 8-10.
5–4
TRANGE
Trace Range Bits — The TRANGE bits allow filtering of trace information from a selected address range when
tracing from the CPU12X in Detail Mode. The XGATE tracing range cannot be narrowed using these bits. To use
a comparator for range filtering, the corresponding COMPE and SRC bits must remain cleared. If the COMPE
bit is not clear then the comparator will also be used to generate state sequence triggers. If the corresponding
SRC bit is set the comparator is mapped to the XGATE buses, the TRANGE bits have no effect on the valid
address range, memory accesses within the whole memory map are traced. See Table 8-11.
3–2
TRCMOD
Trace Mode Bits — See Section 8.4.5.2 for detailed Trace Mode descriptions. In Normal Mode, change of flow
information is stored. In Loop1 Mode, change of flow information is stored but redundant entries into trace
memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored. See
Table 8-12.
1–0
TALIGN
Trigger Align Bits — These bits control whether the trigger is aligned to the beginning, end or the middle of a
tracing session. See Table 8-13.
Table 8-10. TSOURCE — Trace Source Bit Encoding
TSOURCE
Tracing Source
00
No tracing requested
01
CPU12X
10
1
111,2
1
2
XGATE
Both CPU12X and XGATE
No range limitations are allowed. Thus tracing operates as if TRANGE = 00.
No Detail Mode tracing supported. If TRCMOD = 10, no information is stored.
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Table 8-11. TRANGE Trace Range Encoding
TRANGE
Tracing Range
00
Trace from all addresses (No filter)
01
Trace only in address range from $00000 to Comparator D
10
Trace only in address range from Comparator C to $7FFFFF
11
Trace only in range from Comparator C to Comparator D
Table 8-12. TRCMOD Trace Mode Bit Encoding
TRCMOD
Description
00
Normal
01
Loop1
10
Detail
11
Pure PC
Table 8-13. TALIGN Trace Alignment Encoding
TALIGN
Description
00
Trigger at end of stored data
01
Trigger before storing data
10
Trace buffer entries before and after trigger
11
Reserved
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8.3.2.4
Debug Control Register2 (DBGC2)
Address: 0x0023
R
7
6
5
4
0
0
0
0
0
0
0
0
3
1
CDCM
W
Reset
2
0
0
ABCM
0
0
0
= Unimplemented or Reserved
Figure 8-6. Debug Control Register2 (DBGC2)
Read: Anytime
Write: Anytime the module is disarmed.
This register configures the comparators for range matching.
Table 8-14. DBGC2 Field Descriptions
Field
Description
3–2
CDCM[1:0]
C and D Comparator Match Control — These bits determine the C and D comparator match mapping as
described in Table 8-15.
1–0
ABCM[1:0]
A and B Comparator Match Control — These bits determine the A and B comparator match mapping as
described in Table 8-16.
Table 8-15. CDCM Encoding
1
CDCM
Description
00
Match2 mapped to comparator C match....... Match3 mapped to comparator D match.
01
Match2 mapped to comparator C/D inside range....... Match3 disabled.
10
Match2 mapped to comparator C/D outside range....... Match3 disabled.
11
Reserved1
Currently defaults to Match2 mapped to comparator C : Match3 mapped to comparator D
Table 8-16. ABCM Encoding
1
ABCM
Description
00
Match0 mapped to comparator A match....... Match1 mapped to comparator B match.
01
Match 0 mapped to comparator A/B inside range....... Match1 disabled.
10
Match 0 mapped to comparator A/B outside range....... Match1 disabled.
11
Reserved1
Currently defaults to Match0 mapped to comparator A : Match1 mapped to comparator B
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8.3.2.5
Debug Trace Buffer Register (DBGTBH:DBGTBL)
Address: 0x0024, 0x0025
15
R
W
14
13
12
11
10
9
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
8
7
6
5
4
3
2
1
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Other
Resets
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Figure 8-7. Debug Trace Buffer Register (DBGTB)
Read: Only when unlocked AND not secured AND not armed AND with a TSOURCE bit set.
Write: Aligned word writes when disarmed unlock the trace buffer for reading but do not affect trace buffer
contents.
Table 8-17. DBGTB Field Descriptions
Field
Description
15–0
Bit[15:0]
Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 64-bit wide data lines of the
Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer
which points to the next address to be read. When the ARM bit is written to 1 the trace buffer is locked to prevent
reading. The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when
the module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned
access of these registers will return 0 and will not cause the trace buffer pointer to increment to the next trace
buffer address. The same is true for word reads while the debugger is armed. The POR state is undefined Other
resets do not affect the trace buffer contents. .
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8.3.2.6
Debug Count Register (DBGCNT)
Address: 0x0026
7
R
6
5
4
0
3
2
1
0
—
0
—
0
—
0
CNT
W
Reset
POR
0
0
—
0
—
0
—
0
—
0
= Unimplemented or Reserved
Figure 8-8. Debug Count Register (DBGCNT)
Read: Anytime
Write: Never
Table 8-18. DBGCNT Field Descriptions
Field
Description
6–0
CNT[6:0]
Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
Table 8-19 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in
end-trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The
DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus
should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of
valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when
reading from the trace buffer.
Table 8-19. CNT Decoding Table
1
TBF (DBGSR)
CNT[6:0]
Description
0
0000000
No data valid
0
0000001
32 bits of one line valid1
0
0000010
0000100
0000110
..
1111100
1 line valid
2 lines valid
3 lines valid
..
62 lines valid
0
1111110
63 lines valid
1
0000000
64 lines valid; if using Begin trigger alignment,
ARM bit will be cleared and the tracing session ends.
1
0000010
..
..
1111110
64 lines valid,
oldest data has been overwritten by most recent data
This applies to Normal/Loop1/PurePC Modes when tracing from either CPU12X or XGATE only.
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Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.7
Debug State Control Registers
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
Table 8-20. State Control Register Access Encoding
COMRV
Visible State Control Register
00
DBGSCR1
01
DBGSCR2
10
DBGSCR3
11
DBGMFR
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8.3.2.7.1
Debug State Control Register 1 (DBGSCR1)
Address: 0x0027
R
7
6
5
4
0
0
0
0
0
0
0
W
Reset
0
3
2
1
0
SC3
SC2
SC1
SC0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1”. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-21. DBGSCR1 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State1, based upon the match event.
Table 8-22. State1 Sequencer Next State Selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Any match triggers to state2
Any match triggers to state3
Any match triggers to Final State
Match2 triggers to State2....... Other matches have no effect
Match2 triggers to State3....... Other matches have no effect
Match2 triggers to Final State....... Other matches have no effect
Match0 triggers to State2....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State2....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match1 triggers to State2....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers to Final State....... Other matches have no effect
Match3 has no effect....... All other matches (M0,M1,M2) trigger to State2
Reserved
Reserved
Reserved
The trigger priorities described in Table 8-41 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
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8.3.2.7.2
Debug State Control Register 2 (DBGSCR2)
Address: 0x0027
R
7
6
5
4
0
0
0
0
0
0
0
W
Reset
0
3
2
1
0
SC3
SC2
SC1
SC0
0
0
0
0
= Unimplemented or Reserved
Figure 8-10. Debug State Control Register 2 (DBGSCR2)
Read: If COMRV[1:0] = 01
Write: If COMRV[1:0] = 01 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 01. The state control register 2 selects the
targeted next state whilst in State2. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1”. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-23. DBGSCR2 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State2, based upon the match event.
Table 8-24. State2 —Sequencer Next State Selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Any match triggers to state1
Any match triggers to state3
Any match triggers to Final State
Match3 triggers to State1....... Other matches have no effect
Match3 triggers to State3....... Other matches have no effect
Match3 triggers to Final State....... Other matches have no effect
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect
Match2 triggers to State1..... Match3 trigger to Final State
Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State
Reserved
Reserved
The trigger priorities described in Table 8-41 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
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8.3.2.7.3
Debug State Control Register 3 (DBGSCR3)
Address: 0x0027
R
7
6
5
4
0
0
0
0
0
0
0
W
Reset
0
3
2
1
0
SC3
SC2
SC1
SC0
0
0
0
0
= Unimplemented or Reserved
Figure 8-11. Debug State Control Register 3 (DBGSCR3)
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 8-1 and described in Section 8.3.2.8.1”. Comparators must be enabled
by setting the comparator enable bit in the associated DBGXCTL control register.
Table 8-25. DBGSCR3 Field Descriptions
Field
3–0
SC[3:0]
Description
These bits select the targeted next state whilst in State3, based upon the match event.
Table 8-26. State3 — Sequencer Next State Selection
SC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Any match triggers to state1
Any match triggers to state2
Any match triggers to Final State
Match0 triggers to State1....... Other matches have no effect
Match0 triggers to State2....... Other matches have no effect
Match0 triggers to Final State.......Match1 triggers to State1
Match1 triggers to State1....... Other matches have no effect
Match1 triggers to State2....... Other matches have no effect
Match1 triggers to Final State....... Other matches have no effect
Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect
Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect
Match2 triggers to Final State....... Other matches have no effect
Match3 triggers to Final State....... Other matches have no effect
Reserved
Reserved
The trigger priorities described in Table 8-41 dictate that in the case of simultaneous matches, the match
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
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8.3.2.7.4
Debug Match Flag Register (DBGMFR)
Address: 0x0027
R
7
6
5
4
3
2
1
0
0
0
0
0
MC3
MC2
MC1
MC0
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 8-12. Debug Match Flag Register (DBGMFR)
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further triggers on the same channel have no affect.
8.3.2.8
Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
Comparators B and D consist of four register bytes (three address bus compare registers and a control
register).
Each set of comparator registers is accessible in the same 8-byte window of the register address map and
can be accessed using the COMRV bits in the DBGC1 register. If the Comparators B or D are accessed
through the 8-byte window, then only the address and control bytes are visible, the 4 bytes associated with
data bus and data bus masking read as zero and cannot be written. Furthermore the control registers for
comparators B and D differ from those of comparators A and C.
Table 8-27. Comparator Register Layout
0x0028
CONTROL
Read/Write
Comparators A,B,C,D
0x0029
ADDRESS HIGH
Read/Write
Comparators A,B,C,D
0x002A
ADDRESS MEDIUM
Read/Write
Comparators A,B,C,D
0x002B
ADDRESS LOW
Read/Write
Comparators A,B,C,D
0x002C
DATA HIGH COMPARATOR
Read/Write
Comparator A and C only
0x002D
DATA LOW COMPARATOR
Read/Write
Comparator A and C only
0x002E
DATA HIGH MASK
Read/Write
Comparator A and C only
0x002F
DATA LOW MASK
Read/Write
Comparator A and C only
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8.3.2.8.1
Debug Comparator Control Register (DBGXCTL)
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Address: 0x0028
7
R
0
W
Reset
0
6
5
4
3
2
1
0
NDB
TAG
BRK
RW
RWE
SRC
COMPE
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-13. Debug Comparator Control Register (Comparators A and C)
Address: 0x0028
R
W
7
6
5
4
3
2
1
0
SZE
SZ
TAG
BRK
RW
RWE
SRC
COMPE
0
0
0
0
0
0
0
0
Reset
Figure 8-14. Debug Comparator Control Register (Comparators B and D)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
The DBGC1_COMRV bits determine which comparator control, address, data and datamask registers are
visible in the 8-byte window from 0x0028 to 0x002F as shown in Section Table 8-28.
Table 8-28. Comparator Address Register Visibility
COMRV
Visible Comparator
00
DBGACTL, DBGAAH ,DBGAAM, DBGAAL, DBGADH, DBGADL, DBGADHM, DBGADLM
01
DBGBCTL, DBGBAH, DBGBAM, DBGBAL
10
DBGCCTL, DBGCAH, DBGCAM, DBGCAL, DBGCDH, DBGCDL, DBGCDHM, DBGCDLM
11
DBGDCTL, DBGDAH, DBGDAM, DBGDAL
Table 8-29. DBGXCTL Field Descriptions
Field
Description
7
SZE
(Comparators
B and D)
Size Comparator Enable Bit — The SZE bit controls whether access size comparison is enabled for the
associated comparator. This bit is ignored if the TAG bit in the same register is set.
0 Word/Byte access size is not used in comparison
1 Word/Byte access size is used in comparison
6
NDB
(Comparators
A and C
Not Data Bus — The NDB bit controls whether the match occurs when the data bus matches the comparator
register value or when the data bus differs from the register value. Furthermore data bus bits can be
individually masked using the comparator data mask registers. This bit is only available for comparators A
and C. This bit is ignored if the TAG bit in the same register is set. This bit position has an SZ functionality for
comparators B and D.
0 Match on data bus equivalence to comparator register contents
1 Match on data bus difference to comparator register contents
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Table 8-29. DBGXCTL Field Descriptions (continued)
Field
Description
6
SZ
(Comparators
B and D)
Size Comparator Value Bit — The SZ bit selects either word or byte access size in comparison for the
associated comparator. This bit is ignored if the SZE bit is cleared or if the TAG bit in the same register is set.
This bit position has NDB functionality for comparators A and C
0 Word access size will be compared
1 Byte access size will be compared
5
TAG
Tag Select — This bit controls whether the comparator match will cause a trigger or tag the opcode at the
matched address. Tagged opcodes trigger only if they reach the execution stage of the instruction queue.
0 Trigger immediately on match
1 On match, tag the opcode. If the opcode is about to be executed a trigger is generated
4
BRK
Break — This bit controls whether a channel match terminates a debug session immediately, independent
of state sequencer state. To generate an immediate breakpoint the module breakpoints must be enabled
using DBGBRK.
0 The debug session termination is dependent upon the state sequencer and trigger conditions.
1 A match on this channel terminates the debug session immediately; breakpoints if active are generated,
tracing, if active, is terminated and the module disarmed.
3
RW
Read/Write Comparator Value Bit — The RW bit controls whether read or write is used in compare for the
associated comparator . The RW bit is not used if RWE = 0.
0 Write cycle will be matched
1 Read cycle will be matched
2
RWE
Read/Write Enable Bit — The RWE bit controls whether read or write comparison is enabled for the
associated comparator. This bit is not used for tagged operations.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
1
SRC
Determines mapping of comparator to CPU12X or XGATE
0 The comparator is mapped to CPU12X buses
1 The comparator is mapped to XGATE address and data buses
0
COMPE
Determines if comparator is enabled
0 The comparator is not enabled
1 The comparator is enabled for state sequence triggers or tag generation
Table 8-30 shows the effect for RWE and RW on the comparison conditions. These bits are not useful for
tagged operations since the trigger occurs based on the tagged opcode reaching the execution stage of the
instruction queue. Thus these bits are ignored if tagged triggering is selected.
Table 8-30. Read or Write Comparison Logic Table
RWE Bit
RW Bit
RW Signal
Comment
0
x
0
RW not used in comparison
0
x
1
RW not used in comparison
1
0
0
Write
1
0
1
No match
1
1
0
No match
1
1
1
Read
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8.3.2.8.2
Debug Comparator Address High Register (DBGXAH)
Address: 0x0029
7
R
0
W
Reset
0
6
5
4
3
2
1
0
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-15. Debug Comparator Address High Register (DBGXAH)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-31. DBGXAH Field Descriptions
Field
Description
6–0
Bit[22:16]
Comparator Address High Compare Bits — The Comparator address high compare bits control whether the
selected comparator will compare the address bus bits [22:16] to a logic one or logic zero. This register byte is
ignored for XGATE compares.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
8.3.2.8.3
Debug Comparator Address Mid Register (DBGXAM)
Address: 0x002A
R
W
Reset
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 8-16. Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-32. DBGXAM Field Descriptions
Field
7–0
Bit[15:8]
Description
Comparator Address Mid Compare Bits— The Comparator address mid compare bits control whether the
selected comparator will compare the address bus bits [15:8] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
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8.3.2.8.4
Debug Comparator Address Low Register (DBGXAL)
Address: 0x002B
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 8-17. Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-33. DBGXAL Field Descriptions
Field
7–0
Bits[7:0]
Description
Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the
selected comparator will compare the address bus bits [7:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
8.3.2.8.5
Debug Comparator Data High Register (DBGXDH)
Address: 0x002C
R
W
Reset
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 8-18. Debug Comparator Data High Register (DBGXDH)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-34. DBGXAH Field Descriptions
Field
Description
7–0
Bits[15:8]
Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
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8.3.2.8.6
Debug Comparator Data Low Register (DBGXDL)
Address: 0x002D
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 8-19. Debug Comparator Data Low Register (DBGXDL)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-35. DBGXDL Field Descriptions
Field
Description
7–0
Bits[7:0]
Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected
comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
8.3.2.8.7
Debug Comparator Data High Mask Register (DBGXDHM)
Address: 0x002E
R
W
Reset
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 8-20. Debug Comparator Data High Mask Register (DBGXDHM)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-36. DBGXDHM Field Descriptions
Field
Description
7–0
Bits[15:8]
Comparator Data High Mask Bits — The Comparator data high mask bits control whether the selected
comparator compares the data bus bits [15:8] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
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Debug Comparator Data Low Mask Register (DBGXDLM)
Address: 0x002F
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 8-21. Debug Comparator Data Low Mask Register (DBGXDLM)
Read: Anytime. See Table 8-28 for visible register encoding.
Write: If DBG not armed. See Table 8-28 for visible register encoding.
Table 8-37. DBGXDLM Field Descriptions
Field
Description
7–0
Bits[7:0]
Comparator Data Low Mask Bits — The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit
8.4
Functional Description
This section provides a complete functional description of the S12XDBG module. If the part is in secure
mode, the S12XDBG module can generate breakpoints but tracing is not possible.
8.4.1
S12XDBG Operation
Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the
trace buffer and can be used to cause breakpoints to the CPU12X or the XGATE module. The DBG module
is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU12X and XGATE. Comparators can be configured to
monitor address and databus. Comparators can also be configured to mask out individual data bus bits
during a compare and to use R/W and word/byte access qualification in the comparison. When a match
with a comparator register value occurs the associated control logic can trigger the state sequencer to
another state (see Figure 8-22). Either forced or tagged triggers are possible. Using a forced trigger, the
trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match,
the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction
queue is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a
breakpoint can be generated. Tracing of both CPU12X and/or XGATE bus activity is possible.
Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals
or by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
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8.4.2
Comparator Modes
The S12XDBG contains four comparators, A, B, C, and D. Each comparator can be configured to monitor
CPU12X or XGATE buses. Each comparator compares the selected address bus with the address stored in
DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparators A and C also compare the data buses
to the data stored in DBGXDH, DBGXDL and allow masking of individual data bus bits.
S12X comparator matches are disabled in BDM and during BDM accesses.
The comparator match control logic configures comparators to monitor the buses for an exact address or
an address range, whereby either an access inside or outside the specified range generates a match
condition. The comparator configuration is controlled by the control register contents and the range control
by the DBGC2 contents.
On a match a trigger can initiate a transition to another state sequencer state (see Section 8.4.3”). The
comparator control register also allows the type of access to be included in the comparison through the use
of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled
for the associated comparator and the RW bit selects either a read or write access for a valid match.
Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare.
Only comparators B and D feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the triggering condition. By setting
TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs
before the tagged instruction executes (tagged-type trigger). Whilst tagging, the RW, RWE, SZE, and SZ
bits are ignored and the comparator register must be loaded with the exact opcode address.
If the TAG bit is clear (forced type trigger) a comparator match is generated when the selected address
appears on the system address bus. If the selected address is an opcode address, the match is generated
when the opcode is fetched from the memory. This precedes the instruction execution by an indefinite
number of cycles due to instruction pipe lining. For a comparator match of an opcode at an odd address
when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an
opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is verified at a given address, this
address may not still contain that data value when a subsequent match occurs.
Comparators C and D can also be used to select an address range to trace from. This is determined by the
TRANGE bits in the DBGTCR register. The TRANGE encoding is shown in Table 8-11. If the TRANGE
bits select a range definition using comparator D, then comparator D is configured for trace range
definition and cannot be used for address bus comparisons. Similarly if the TRANGE bits select a range
definition using comparator C, then comparator C is configured for trace range definition and cannot be
used for address bus comparisons.
Match[0, 1, 2, 3] map directly to Comparators[A, B, C, D] respectively, except in range modes (see
Section 8.3.2.4”). Comparator priority rules are described in the trigger priority section (Section 8.4.3.6”).
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8.4.2.1
Exact Address Comparator Match (Comparators A and C)
With range comparisons disabled, the match condition is an exact equivalence of address/data bus with the
value stored in the comparator address/data registers. Further qualification of the type of access (R/W,
word/byte) is possible.
Comparators A and C do not feature SZE or SZ control bits, thus the access size is not compared. The exact
address is compared, thus with the comparator address register loaded with address (n) a word access of
address (n–1) also accesses (n) but does not cause a match. Table 8-39 lists access considerations without
data bus compare. Table 8-38 lists access considerations with data bus comparison. To compare byte
accesses DBGXDH must be loaded with the data byte, the low byte must be masked out using the
DBGXDLM mask register. On word accesses the data byte of the lower address is mapped to DBGXDH.
Table 8-38. Comparator A and C Data Bus Considerations
Access
Address
DBGxDH
DBGxDL
DBGxDHM
DBGxDLM
Example Valid Match
Word
ADDR[n]
Data[n]
Data[n+1]
$FF
$FF
MOVW #$WORD ADDR[n]
Byte
ADDR[n]
Data[n]
x
$FF
$00
MOVB #$BYTE ADDR[n]
Word
ADDR[n]
Data[n]
x
$FF
$00
MOVW #$WORD ADDR[n]
Word
ADDR[n]
x
Data[n+1]
$00
$FF
MOVW #$WORD ADDR[n]
Comparators A and C feature an NDB control bit to determine if a match occurs when the data bus differs
to comparator register contents or when the data bus is equivalent to the comparator register contents.
8.4.2.2
Exact Address Comparator Match (Comparators B and D)
Comparators B and D feature SZ and SZE control bits. If SZE is clear, then the comparator address match
qualification functions the same as for comparators A and C.
If the SZE bit is set the access size (word or byte) is compared with the SZ bit value such that only the
specified type of access causes a match. Thus if configured for a byte access of a particular address, a word
access covering the same address does not lead to match.
Table 8-39. Comparator Access Size Considerations
1
Comparator
Address
SZE
SZ8
Condition For Valid Match
Comparators
A and C
ADDR[n]
—
—
Word and byte accesses of ADDR[n]1
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Comparators
B and D
ADDR[n]
0
X
Word and byte accesses of ADDR[n]1
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Comparators
B and D
ADDR[n]
1
0
Word accesses of ADDR[n]1
MOVW #$WORD ADDR[n]
Comparators
B and D
ADDR[n]
1
1
Byte accesses of ADDR[n]
MOVB #$BYTE ADDR[n]
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address used in the code.
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8.4.2.3
Data Bus Comparison NDB Dependency
Comparators A and C each feature an NDB control bit, which allows data bus comparators to be configured
to either trigger on equivalence or trigger on difference. This allows monitoring of a difference in the
contents of an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGxDHM/DBGxDLM), so that it is ignored in the comparison. A
match occurs when all data bus bits with corresponding mask bits set are equivalent. If all mask register
bits are clear, then a match is based on the address bus only, the data bus is ignored.
When matching on a difference, mask bits can be cleared to ignore bit positions. A match occurs when any
data bus bit with corresponding mask bit set is different. Clearing all mask bits, causes all bits to be ignored
and prevents a match because no difference can be detected. In this case address bus equivalence does not
cause a match.
Table 8-40. NDB and MASK bit dependency
8.4.2.4
NDB
DBGxDHM[n] /
DBGxDLM[n]
Comment
0
0
Do not compare data bus bit.
0
1
Compare data bus bit. Match on equivalence.
1
0
Do not compare data bus bit.
1
1
Compare data bus bit. Match on difference.
Range Comparisons
When using the AB comparator pair for a range comparison, the data bus can also be used for qualification
by using the comparator A data and data mask registers. Furthermore the DBGACTL RW and RWE bits
can be used to qualify the range comparison on either a read or a write access. The corresponding
DBGBCTL bits are ignored. Similarly when using the CD comparator pair for a range comparison, the
data bus can also be used for qualification by using the comparator C data and data mask registers.
Furthermore the DBGCCTL RW and RWE bits can be used to qualify the range comparison on either a
read or a write access if tagging is not selected. The corresponding DBGDCTL bits are ignored. The SZE
and SZ control bits are ignored in range mode. The comparator A and C TAG bits are used to tag range
comparisons for the AB and CD ranges respectively. The comparator B and D TAG bits are ignored in
range modes. In order for a range comparison using comparators A and B, both COMPEA and COMPEB
must be set; to disable range comparisons both must be cleared. Similarly for a range CD comparison, both
COMPEC and COMPED must be set. If a range mode is selected SRCA and SRCC select the source
(S12X or XGATE), SRCB and SRCD are ignored. The comparator A and C BRK bits are used for the AB
and CD ranges respectively, the comparator B and D BRK bits are ignored in range mode. When
configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
8.4.2.4.1
Inside Range (CompAC_Addr ≤ address ≤ CompBD_Addr)
In the Inside Range comparator mode, either comparator pair A and B or comparator pair C and D can be
configured for range comparisons by the control register (DBGC2). The match condition requires that a
valid match for both comparators happens on the same bus cycle. A match condition on only one
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comparator is not valid. An aligned word access which straddles the range boundary will cause a trigger
only if the aligned address is inside the range.
8.4.2.4.2
Outside Range (address < CompAC_Addr or address > CompBD_Addr)
In the Outside Range comparator mode, either comparator pair A and B or comparator pair C and D can
be configured for range comparisons. A single match condition on either of the comparators is recognized
as valid. An aligned word access which straddles the range boundary will cause a trigger only if the aligned
address is outside the range.
Outside range mode in combination with tagged triggers can be used to detect if the opcode fetches are
from an unexpected range. In forced trigger modes the outside range trigger would typically be activated
at any interrupt vector fetch or register access. This can be avoided by setting the upper range limit to
$7FFFFF or lower range limit to $000000 respectively.
When comparing the XGATE address bus in outside range mode, the initial vector fetch as determined by
the vector contained in the XGATE XGVBR register should be taken into consideration. The XGVBR
register and hence vector address can be modified.
8.4.3
Trigger Modes
Trigger modes are used as qualifiers for a state sequencer change of state. The control logic determines the
trigger mode and provides a trigger to the state sequencer. The individual trigger modes are described in
the following sections.
8.4.3.1
Forced Trigger On Comparator Match
If a forced trigger comparator match occurs, the trigger immediately initiates a transition to the next state
sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the
current state determines the next state for each trigger. Forced triggers are generated as soon as the
matching address appears on the address bus, which in the case of opcode fetches occurs several cycles
before the opcode execution. For this reason a forced trigger of an opcode address precedes a tagged trigger
at the same address by several cycles.
8.4.3.2
Trigger On Comparator Related Taghit
If a CPU12X or XGATE taghit occurs, a transition to another state sequencer state is initiated and the
corresponding DBGSR flags are set. For a comparator related taghit to occur, the S12XDBG must first
generate tags based on comparator matches. When the tagged instruction reaches the execution stage of
the instruction queue a taghit is generated by the CPU12X/XGATE. The state control register for the
current state determines the next state for each trigger.
8.4.3.3
External Tagging Trigger
In external tagging trigger mode, the TAGLO and TAGHI pins (mapped to device pins) are used to tag an
instruction. This function can be used as another breakpoint source. When the tagged opcode reaches the
execution stage of the instruction queue a transition to the disarmed state0 occurs, ending the debug session
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and generating a breakpoint, if breakpoints are enabled. External tagging is only possible in device
emulation modes.
8.4.3.4
Trigger On XGATE S/W Breakpoint Request
The XGATE S/W breakpoint request issues a forced breakpoint request to the CPU12X immediately
independent of S12XDBG settings and triggers the state sequencer into the disarmed state. Active tracing
sessions are terminated immediately, thus if tracing has not yet begun, no trace information is stored.
XGATE generated breakpoints are independent of the DBGBRK bits. The XGSBPE bit in DBGC1
determines if the XGATE S/W breakpoint function is enabled. The BDM bit in DBGC1 determines if the
XGATE requested breakpoint causes the system to enter BDM Mode or initiate a software interrupt (SWI).
8.4.3.5
TRIG Immediate Trigger
Independent of comparator matches or external tag signals it is possible to initiate a tracing session and/or
breakpoint by writing the TRIG bit in DBGC1 to a logic “1”. If configured for begin or mid aligned tracing,
this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit
disarms the module, ending the session. If breakpoints are enabled, a forced breakpoint request is issued
immediately (end alignment) or when tracing has completed (begin or mid alignment).
8.4.3.6
Trigger Priorities
In case of simultaneous triggers, the priority is resolved according to Table 8-41. The lower priority trigger
is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger
of a higher priority. The trigger priorities described in Table 8-41 dictate that in the case of simultaneous
matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that
a match leading to final state has priority over all other matches independent of current state sequencer
state. When configured for range modes a simultaneous match of comparators A and C generates an active
match0 whilst match2 is suppressed.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm
from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.
Table 8-41. Trigger Priorities
Priority
Source
Action
Highest
XGATE
Immediate forced breakpoint......(Tracing terminated immediately).
TRIG
Trigger immediately to final state (begin or mid aligned tracing enabled)
Trigger immediately to state 0 (end aligned or no tracing enabled)
External TAGHI/TAGLO
Enter State0
Match0 (force or tag hit)
Trigger to next state as defined by state control registers
Match1 (force or tag hit)
Trigger to next state as defined by state control registers
Match2 (force or tag hit)
Trigger to next state as defined by state control registers
Match3 (force or tag hit)
Trigger to next state as defined by state control registers
Lowest
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8.4.4
State Sequence Control
ARM = 0
State 0
(Disarmed)
ARM = 1
State1
State2
ARM = 0
Session Complete
(Disarm)
Final State
State3
ARM = 0
Figure 8-22. State Sequencer Diagram
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register,
then state1 of the state sequencer is entered. Further transitions between the states are then controlled by
the state control registers and depend upon a selected trigger mode condition being met. From Final State
the only permitted transition is back to the disarmed state0. Transition between any of the states 1 to 3 is
not restricted. Each transition updates the SSF[2:0] flags in DBGSR accordingly to indicate the current
state.
Alternatively by setting the TRIG bit in DBGSC1, the state machine can be triggered to state0 or Final
State depending on tracing alignment.
A tag hit through TAGHI/TAGLO brings the state sequencer immediately into state0, causes a breakpoint,
if breakpoints are enabled, and ends tracing immediately independent of the trigger alignment bits
TALIGN[1:0].
Independent of the state sequencer, each comparator channel can be individually configured to generate an
immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.
Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer
transition can be initiated by a match on other channels. If a debug session is ended by a trigger on a
channel with BRK = 1, the state sequencer transitions through Final State for a clock cycle to state0. This
is independent of tracing and breakpoint activity, thus with tracing and breakpoints disabled, the state
sequencer enters state0 and the debug module is disarmed.
An XGATE S/W breakpoint request, if enabled causes a transition to the State0 and generates a breakpoint
request to the CPU12X immediately.
8.4.4.1
Final State
On entering Final State a trigger may be issued to the trace buffer according to the trace position control
as defined by the TALIGN field (see Section 8.3.2.3”). If TSOURCE in the trace control register DBGTCR
are cleared then the trace buffer is disabled and the transition to Final State can only generate a breakpoint
request. In this case or upon completion of a tracing session when tracing is enabled, the ARM bit in the
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DBGC1 register is cleared, returning the module to the disarmed state0. If tracing is enabled a breakpoint
request can occur at the end of the tracing session. If neither tracing nor breakpoints are enabled then when
the final state is reached it returns automatically to state0 and the debug module is disarmed.
8.4.5
Trace Buffer Operation
The trace buffer is a 64 lines deep by 64-bits wide RAM array. The S12XDBG module stores trace
information in the RAM array in a circular buffer format. The RAM array can be accessed through a
register window (DBGTBH:DBGTBL) using 16-bit wide word accesses. After each complete 64-bit trace
buffer line is read, an internal pointer into the RAM is incremented so that the next read will receive fresh
information. Data is stored in the format shown in Table 8-42. After each store the counter register bits
DBGCNT[6:0] are incremented. Tracing of CPU12X activity is disabled when the BDM is active but
tracing of XGATE activity is still possible. Reading the trace buffer whilst the DBG is armed returns
invalid data and the trace buffer pointer is not incremented.
8.4.5.1
Trace Trigger Alignment
Using the TALIGN bits (see Section 8.3.2.3”) it is possible to align the trigger with the end, the middle, or
the beginning of a tracing session.
If End or Mid tracing is selected, tracing begins when the ARM bit in DBGC1 is set and State1 is entered.
The transition to Final State if End is selected signals the end of the tracing session. The transition to Final
State if Mid is selected signals that another 32 lines will be traced before ending the tracing session.
Tracing with Begin-Trigger starts at the opcode of the trigger.
8.4.5.1.1
Storing with Begin-Trigger
Storing with Begin-Trigger, data is not stored in the Trace Buffer until the Final State is entered. Once the
trigger condition is met the S12XDBG module will remain armed until 64 lines are stored in the Trace
Buffer. If the trigger is at the address of the change-of-flow instruction the change of flow associated with
the trigger will be stored in the Trace Buffer. Using Begin-trigger together with tagging, if the tagged
instruction is about to be executed then the trace is started. Upon completion of the tracing session the
breakpoint is generated, thus the breakpoint does not occur at the tagged instruction boundary.
8.4.5.1.2
Storing with Mid-Trigger
Storing with Mid-Trigger, data is stored in the Trace Buffer as soon as the S12XDBG module is armed.
When the trigger condition is met, another 32 lines will be traced before ending the tracing session,
irrespective of the number of lines stored before the trigger occurred, then the S12XDBG module is
disarmed and no more data is stored. Using Mid-trigger with tagging, if the tagged instruction is about to
be executed then the trace is continued for another 32 lines. Upon tracing completion the breakpoint is
generated, thus the breakpoint does not occur at the tagged instruction boundary.
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8.4.5.1.3
Storing with End-Trigger
Storing with End-Trigger, data is stored in the Trace Buffer until the Final State is entered, at which point
the S12XDBG module will become disarmed and no more data will be stored. If the trigger is at the
address of a change of flow instruction the trigger event will not be stored in the Trace Buffer.
8.4.5.2
Trace Modes
The S12XDBG module can operate in four trace modes. The mode is selected using the TRCMOD bits in
the DBGTCR register. In each mode tracing of XGATE or CPU12X information is possible. The source
for the trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the
following subsections. The trace buffer organization is shown in Table 8-42.
8.4.5.2.1
Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses will be stored.
COF addresses are defined as follows for the CPU12X:
• Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
• Destination address of indexed JMP, JSR, and CALL instruction.
• Destination address of RTI, RTS, and RTC instructions
• Vector address of interrupts, except for SWI and BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
COF addresses are defined as follows for the XGATE:
• Source address of taken conditional branches
• Destination address of indexed JAL instructions.
• First XGATE code address in a thread
Change-of-flow addresses stored include the full 23-bit address bus of CPU12X, the 16-bit address bus for
the XGATE module and an information byte, which contains a source/destination bit to indicate whether
the stored address was a source address or destination address.
NOTE
When an CPU12X COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets exectuted after the interrupt service routine.
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In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
MARK1
MARK2
LDX
JMP
NOP
#SUB_1
0,X
SUB_1
BRN
*
ADDR1
NOP
DBNE
A,PART5
IRQ_ISR
LDAB
STAB
RTI
#$F0
VAR_C1
; IRQ interrupt occurs during execution of this
;
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
The execution flow taking into account the IRQ is as follows
MARK1
IRQ_ISR
SUB_1
ADDR1
8.4.5.2.2
LDX
JMP
LDAB
STAB
RTI
BRN
NOP
DBNE
#SUB_1
0,X
#$F0
VAR_C1
;
;
;
*
A,PART5
;
;
Loop1 Mode
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
S12XDBG module writes this value into a background register. This prevents consecutive duplicate
address entries in the Trace Buffer resulting from repeated branches.
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Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the
S12XDBG module is designed to help find.
NOTE
In certain very tight loops, the source address will have already been fetched
again before the background comparator is updated. This results in the
source address being stored twice before further duplicate entries are
suppressed. This condition occurs with branch-on-bit instructions when the
branch is fetched by the first P-cycle of the branch or with loop-construct
instructions in which the branch is fetched with the first or second P cycle.
See examples below:
LOOP
LOOP2
8.4.5.2.3
INX
BRCLR
BRN
NOP
DBNE
CMPTMP,#$0c, LOOP
*
; 1-byte instruction fetched by 1st P-cycle of BRCLR
; the BRCLR instruction also will be fetched by 1st
; P-cycle of BRCLR
; 2-byte instruction fetched by 1st P-cycle of DBNE
; 1-byte instruction fetched by 2nd P-cycle of DBNE
; this instruction also fetched by 2nd P-cycle of DBNE
A,LOOP2
Detail Mode
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. In the
case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced.
This mode is intended to supply additional information on indexed, indirect addressing modes where
storing only the destination address would not provide all information required for a user to determine
where the code is in error. This mode also features information byte entries to the trace buffer, for each
address byte entry. The information byte indicates the size of access (word or byte) and the type of access
(read or write).
When tracing CPU12X activity in Detail Mode, all cycles are traced except those when the CPU12X is
either in a free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide
a snapshot of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity
occurring at the time of the trace buffer entry. When tracing CPU12X activity alone in Detail Mode, the
address range can be limited to a range specified by the TRANGE bits in DBGTCR. This function uses
comparators C and D to define an address range inside which CPU12X activity should be traced (see
Table 8-42). Thus the traced CPU12X activity can be restricted to particular register range accesses.
When tracing XGATE activity in Detail Mode, all load and store cycles are traced. Additionally the
CPU12X program counter is stored at the time of the XGATE trace buffer entry to provide a snapshot of
CPU12X activity.
8.4.5.2.4
Pure PC Mode
In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal
opcodes, are stored. In Pure PC Mode, tracing from the XGATE the PC addresses of all executed opcodes
are stored.
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8.4.5.3
Trace Buffer Organization
Referring to Table 8-42. An X prefix denotes information from the XGATE module, a C prefix denotes
information from the CPU12X. ADRH, ADRM, ADRL denote address high, middle and low byte
respectively. INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which
tracing step. The information format for Loop1 Mode and PurePC Mode is the same as that of Normal
Mode. Whilst tracing from XGATE or CPU12X only, in Normal or Loop1 modes each array line contains
2 data entries, thus in this case the DBGCNT[0] is incremented after each separate entry. In Detail mode
DBGCNT[0] remains cleared whilst the other DBGCNT bits are incremented on each trace buffer entry.
XGATE and CPU12X COFs occur independently of each other and the profile of COFs for the two sources
is totally different. When both sources are being traced in Normal or Loop1 mode, for each COF from one
source, there may be many COFs from the other source, depending on user code. COF events could occur
far from each other in the time domain, on consecutive cycles or simultaneously. When a COF occurs in
either source (S12X or XGATE) a trace buffer entry is made and the corresponding CDV or XDV bit is
set. The current PC of the other source is simultaneously stored to the trace buffer even if no COF has
occurred, in which case CDV/XDV remains cleared indicating the address is not associated with a COF,
but is simply a snapshot of the PC contents at the time of the COF from the other source.
Single byte data accesses in Detail Mode are always stored to the low byte of the trace buffer (CDATAL
or XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is
always stored to trace buffer byte3 and the byte at the higher address is stored to byte2
Table 8-42. Trace Buffer Organization
Mode
8-Byte Wide Word Buffer
7
6
5
4
3
2
1
0
XGATE
Detail
CXINF1
CADRH1
CADRM1
CADRL1
XDATAH1
XDATAL1
XADRM1
XADRL1
CXINF2
CADRH2
CADRM2
CADRL2
XDATAH2
XDATAL2
XADRM2
XADRL2
CPU12X
Detail
CXINF1
CADRH1
CADRM1
CADRL1
CDATAH1
CDATAL1
XADRM1
XADRL1
CXINF2
CADRH2
CADRM2
CADRL2
CDATAH2
CDATAL2
XADRM2
XADRL2
Both
Other Modes
XINF0
XPCM0
XPCL0
CINF0
CPCH0
CPCM0
CPCL0
XINF1
XPCM1
XPCL1
CINF1
CPCH1
CPCM1
CPCL1
XGATE
Other Modes
XINF1
XPCM1
XPCL1
XINF0
XPCM0
XPCL0
XINF3
XPCM3
XPCL3
XINF2
XPCM2
XPCL2
CPU12X
Other Modes
CINF1
CPCH1
CPCM1
CPCL1
CINF0
CPCH0
CPCM0
CPCL0
CINF3
CPCH3
CPCM3
CPCL3
CINF2
CPCH2
CPCM2
CPCL2
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8.4.5.3.1
Information Byte Organization
The format of the control information byte is dependent upon the active trace mode as described below. In
Normal, Loop1, or Pure PC modes tracing of XGATE activity, XINF is used to store control information.
In Normal, Loop1, or Pure PC modes tracing of CPU12X activity, CINF is used to store control
information. In Detail Mode, CXINF contains the control information
XGATE Information Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XSD
XSOT
XCOT
XDV
0
0
0
0
Figure 8-23. XGATE Information Byte XINF
Table 8-43. XINF Field Descriptions
Field
Description
7
XSD
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source address
1 Destination address or Start of Thread or Continuation of Thread
6
XSOT
Source Of Thread Indicator — This bit indicates that the corresponding stored address is a start of thread
address. This is only used in Normal and Loop1 mode tracing.
NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels.
0 Stored address not from a start of thread
1 Stored address from a start of thread
5
XCOT
Continuation Of Thread Indicator — This bit indicates that the corresponding stored address is the first
address following a return from a higher priority thread. This is only used in Normal and Loop1 mode tracing.
NOTE. This bit only has effect on devices where the XGATE module supports multiple interrupt levels.
0 Stored address not from a continuation of thread
1 Stored address from a continuation of thread
4
XDV
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the XGATE trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
XGATE info bit setting
XGATE FLOW
SOT1
SOT2
JAL
RTS
COT1
RTS
XSD
XSOT
XCOT
Figure 8-24. XGATE info bit setting
Figure 8-24 indicates the XGATE information bit setting when switching between threads, the initial
thread starting at SOT1 and continuing at COT1 after the higher priority thread2 has ended.
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CPU12X Information Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CSD
CVA
0
CDV
0
0
0
0
Figure 8-25. CPU12X Information Byte CINF
Table 8-44. CINF Field Descriptions
Field
Description
7
CSD
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or destination
address. This is only used in Normal and Loop1 mode tracing.
0 Source address
1 Destination address
6
CVA
Vector Indicator — This bit indicates if the corresponding stored address is a vector address.. Vector addresses
are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This is only used in Normal
and Loop1 mode tracing. This bit has no meaning in Pure PC mode.
0 Indexed jump destination address
1 Vector destination address
4
CDV
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in Normal, Loop1 and Pure PC modes, to indicate that the CPU12X trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
CXINF Information Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CFREE
CSZ
CRW
COCF
XACK
XSZ
XRW
XOCF
Figure 8-26. Information Byte CXINF
This describes the format of the information byte used only when tracing from CPU12X or XGATE in
Detail Mode. When tracing from the CPU12X in Detail Mode, information is stored to the trace buffer on
all cycles except opcode fetch and free cycles. The XGATE entry stored on the same line is a snapshot of
the XGATE program counter. In this case the CSZ and CRW bits indicate the type of access being made
by the CPU12X, whilst the XACK and XOCF bits indicate if the simultaneous XGATE cycle is a free cycle
(no bus acknowledge) or opcode fetch cycle. Similarly when tracing from the XGATE in Detail Mode,
information is stored to the trace buffer on all cycles except opcode fetch and free cycles. The CPU12X
entry stored on the same line is a snapshot of the CPU12X program counter. In this case the XSZ and XRW
bits indicate the type of access being made by the XGATE, whilst the CFREE and COCF bits indicate if
the simultaneous CPU12X cycle is a free cycle or opcode fetch cycle.
Table 8-45. CXINF Field Descriptions
Field
Description
7
CFREE
CPU12X Free Cycle Indicator — This bit indicates if the stored CPU12X address corresponds to a free cycle.
This bit only contains valid information when tracing the XGATE accesses in Detail Mode.
0 Stored information corresponds to free cycle
1 Stored information does not correspond to free cycle
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Table 8-45. CXINF Field Descriptions (continued)
Field
Description
6
CSZ
Access Type Indicator — This bit indicates if the access was a byte or word size access.This bit only contains
valid information when tracing CPU12X activity in Detail Mode.
0 Word Access
1 Byte Access
5
CRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing CPU12X activity in Detail Mode.
0 Write Access
1 Read Access
4
COCF
CPU12X Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch
cycle. This bit only contains valid information when tracing the XGATE accesses in Detail Mode.
0 Stored information does not correspond to opcode fetch cycle
1 Stored information corresponds to opcode fetch cycle
3
XACK
XGATE Access Indicator — This bit indicates if the stored XGATE address corresponds to a free cycle. This bit
only contains valid information when tracing the CPU12X accesses in Detail Mode.
0 Stored information corresponds to free cycle
1 Stored information does not correspond to free cycle
2
XSZ
Access Type Indicator — This bit indicates if the access was a byte or word size access. This bit only contains
valid information when tracing XGATE activity in Detail Mode.
0 Word Access
1 Byte Access
1
XRW
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access. This bit only contains valid information when tracing XGATE activity in Detail Mode.
0 Write Access
1 Read Access
0
XOCF
XGATE Opcode Fetch Indicator — This bit indicates if the stored address corresponds to an opcode fetch
cycle.This bit only contains valid information when tracing the CPU12X accesses in Detail Mode.
0 Stored information does not correspond to opcode fetch cycle
1 Stored information corresponds to opcode fetch cycle
8.4.5.4
Reading Data from Trace Buffer
The data stored in the Trace Buffer can be read using either the background debug module (BDM) module,
the XGATE or the CPU12X provided the S12XDBG module is not armed, is configured for tracing and
the system not secured. When the ARM bit is written to 1 the trace buffer is locked to prevent reading. The
trace buffer can only be unlocked for reading by an aligned word write to DBGTB when the module is
disarmed.
The Trace Buffer can only be read through the DBGTB register using aligned word reads, any byte or
misaligned reads return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. The Trace Buffer data is read out first-in first-out. By reading CNT in DBGCNT the number of
valid 64-bit lines can be determined. DBGCNT will not decrement as data is read.
Whilst reading an internal pointer is used to determine the next line to be read. After a tracing session, the
pointer points to the oldest data entry, thus if no overflow has occurred, the pointer points to line0,
otherwise it points to the line with the oldest entry. The pointer is initialized by each aligned write to
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DBGTBH to point to the oldest data again. This enables an interrupted trace buffer read sequence to be
easily restarted from the oldest data entry.
The least significant word of each 64-bit wide array line is read out first. This corresponds to the bytes 1
and 0 of Table 8-42. The bytes containing invalid information (shaded in Table 8-42) are also read out.
Reading the Trace Buffer while the S12XDBG module is armed will return invalid data and no shifting of
the RAM pointer will occur.
8.4.5.5
Trace Buffer Reset State
The Trace Buffer contents are not initialized by a system reset. Thus should a system reset occur, the trace
session information from immediately before the reset occurred can be read out. The DBGCNT bits are
not cleared by a system reset. Thus should a reset occur, the number of valid lines in the trace buffer is
indicated by DBGCNT. The internal pointer to the current trace buffer address is initialized by unlocking
the trace buffer thus points to the oldest valid data even if a reset occurred during the tracing session.
Generally debugging occurrences of system resets is best handled using mid or end trigger alignment since
the reset may occur before the trace trigger, which in the begin trigger alignment case means no
information would be stored in the trace buffer.
8.4.6
Tagging
A tag follows program information as it advances through the instruction queue. When a tagged instruction
reaches the head of the queue a tag hit occurs and triggers the state sequencer.
Each comparator control register features a TAG bit, which controls whether the comparator match will
cause a trigger immediately or tag the opcode at the matched address. If a comparator is enabled for tagged
comparisons, the address stored in the comparator match address registers must be an opcode address for
the trigger to occur.
Both CPU12X and XGATE opcodes can be tagged with the comparator register TAG bits.
Using Begin trigger together with tagging, if the tagged instruction is about to be executed then the
transition to the next state sequencer state occurs. If the transition is to the Final State, tracing is started.
Only upon completion of the tracing session can a breakpoint be generated. Similarly using Mid trigger
with tagging, if the tagged instruction is about to be executed then the trace is continued for another 32
lines. Upon tracing completion the breakpoint is generated. Using End trigger, when the tagged instruction
is about to be executed and the next transition is to Final State then a breakpoint is generated immediately,
before the tagged instruction is carried out.
R/W monitoring is not useful for tagged operations since the trigger occurs based on the tagged opcode
reaching the execution stage of the instruction queue. Similarly access size (SZ) monitoring and data bus
monitoring is not useful if tagged triggering is selected, since the tag is attached to the opcode at the
matched address and is not dependent on the data bus nor on the size of access. Thus these bits are ignored
if tagged triggering is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
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S12X tagging is disabled when the BDM becomes active. XGATE tagging is possible when the BDM is
active.
8.4.6.1
External Tagging using TAGHI and TAGLO
External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU12X opcodes;
tagging of XGATE code using these pins is not possible. An external tag triggers the state sequencer into
state0 when the tagged opcode reaches the execution stage of the instruction queue.
The pins operate independently, thus the state of one pin does not affect the function of the other. External
tagging is possible in emulation modes only. The presence of logic level 0 on either pin at the rising edge
of the external clock (ECLK) performs the function indicated in the Table 8-46. It is possible to tag both
bytes of an instruction word. If a taghit occurs, a breakpoint can be generated as defined by the DBGBRK
and BDM bits in DBGC1. Each time TAGHI or TAGLO are low on the rising edge of ECLK, the old tag
is replaced by a new one.
Table 8-46. Tag Pin Function
TAGHI
1
1
0
0
8.4.6.2
TAGLO
1
0
1
0
Tag
No tag
Low byte
High byte
Both bytes
Unconditional Tagging Function
In emulation modes a low assertion of PE5/TAGLO/MODA in the 7th or 8th bus cycle after reset enables
the unconditional tagging function, allowing immediate tagging via TAGHI/TAGLO with breakpoint to
BDM independent of the ARM, BDM and DBGBRK bits. Conversely these bits are not affected by
unconditional tagging. The unconditional tagging function remains enabled until the next reset. This
function allows an immediate entry to BDM in emulation modes before user code execution. The TAGLO
assertion must be in the 7th or 8th bus cycle following the end of reset, whereby the prior RESET pin
assertion lasts the full 192 bus cycles.
8.4.7
Breakpoints
Breakpoints can be generated as follows.
• Through XGATE software breakpoint requests.
• From comparator channel triggers to final state.
• Using software to write to the TRIG bit in the DBGC1 register.
• From taghits generated using the external TAGHI and TAGLO pins.
Breakpoints generated by the XGATE module or via the BDM BACKGROUND command have no affect
on the CPU12X in STOP or WAIT mode.
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8.4.7.1
XGATE Software Breakpoints
The XGATE software breakpoint instruction BRK can request an CPU12X breakpoint, via the S12XDBG
module. In this case, if the XGSBPE bit is set, the S12XDBG module immediately generates a forced
breakpoint request to the CPU12X, the state sequencer is returned to state0 and tracing, if active, is
terminated. If configured for BEGIN trigger and tracing has not yet been triggered from another source,
the trace buffer contains no information. Breakpoint requests from the XGATE module do not depend
upon the state of the DBGBRK or ARM bits in DBGC1. They depend solely on the state of the XGSBPE
and BDM bits. Thus it is not necessary to ARM the DBG module to use XGATE software breakpoints to
generate breakpoints in the CPU12X program flow, but it is necessary to set XGSBPE. Furthermore, if a
breakpoint to BDM is required, the BDM bit must also be set. When the XGATE requests an CPU12X
breakpoint, the XGATE program flow stops by default, independent of the S12XDBG module.
8.4.7.2
Breakpoints From Internal Comparator Channel Final State Triggers
Breakpoints can be generated when internal comparator channels trigger the state sequencer to the Final
State. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the
execution stage of the instruction queue.
If a tracing session is selected by TSOURCE, breakpoints are requested when the tracing session has
completed, thus if Begin or Mid aligned triggering is selected, the breakpoint is requested only on
completion of the subsequent trace (see Table 8-47). If no tracing session is selected, breakpoints are
requested immediately.
If the BRK bit is set on the triggering channel, then the breakpoint is generated immediately independent
of tracing trigger alignment.
Table 8-47. Breakpoint Setup For Both XGATE and CPU12X Breakpoints
BRK
TALIGN
DBGBRK[n]
Breakpoint Alignment
0
00
0
Fill Trace Buffer until trigger
(no breakpoints — keep running)
0
00
1
Fill Trace Buffer until trigger, then breakpoint request occurs
0
01
0
Start Trace Buffer at trigger
(no breakpoints — keep running)
0
01
1
Start Trace Buffer at trigger
A breakpoint request occurs when Trace Buffer is full
0
10
0
Store a further 32 Trace Buffer line entries after trigger
(no breakpoints — keep running)
0
10
1
Store a further 32 Trace Buffer line entries after trigger
Request breakpoint after the 32 further Trace Buffer entries
1
00,01,10
1
Terminate tracing and generate breakpoint immediately on trigger
1
00,01,10
0
Terminate tracing immediately on trigger
x
11
x
Reserved
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8.4.7.3
Breakpoints Generated Via The TRIG Bit
If a TRIG triggers occur, the Final State is entered. If a tracing session is selected by TSOURCE,
breakpoints are requested when the tracing session has completed, thus if Begin or Mid aligned triggering
is selected, the breakpoint is requested only on completion of the subsequent trace (see Table 8-47). If no
tracing session is selected, breakpoints are requested immediately. TRIG breakpoints are possible even if
the S12XDBG module is disarmed.
8.4.7.4
Breakpoints Via TAGHI Or TAGLO Pin Taghits
Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is
always end aligned, independent of internal channel trigger alignment configuration.
8.4.7.5
S12XDBG Breakpoint Priorities
XGATE software breakpoints have the highest priority. Active tracing sessions are terminated
immediately.
If a TRIG trigger occurs after Begin or Mid aligned tracing has already been triggered by a comparator
instigated transition to Final State, then TRIG no longer has an effect. When the associated tracing session
is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a
comparator channel, it has no effect, since tracing has already started.
If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer
enters state0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of
the tracing trigger alignment bits TALIGN[1:0].
8.4.7.5.1
S12XDBG Breakpoint Priorities And BDM Interfacing
Breakpoint operation is dependent on the state of the S12XBDM module. If the S12XBDM module is
active, the CPU12X is executing out of BDM firmware and S12X breakpoints are disabled. In addition,
while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active, the
breakpoint will give priority to BDM requests over SWI requests if the breakpoint coincides with a SWI
instruction in the user’s code. On returning from BDM, the SWI from user code gets executed.
Table 8-48. Breakpoint Mapping Summary
DBGBRK[1]
(DBGC1[3])
BDM Bit
(DBGC1[4])
BDM
Enabled
BDM
Active
S12X Breakpoint
Mapping
0
X
X
X
No Breakpoint
1
0
X
0
Breakpoint to SWI
1
0
X
1
No Breakpoint
1
1
0
X
Breakpoint to SWI
1
1
1
0
Breakpoint to BDM
1
1
1
1
No Breakpoint
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU12X actually
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executes the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced
by the monitor then the breakpoint is re-asserted when the BDM returns to normal CPU12X flow.
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code
and DBG breakpoint could occur simultaneously. The CPU12X ensures that BDM requests have a higher
priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid re
triggering a breakpoint.
NOTE
When program control returns from a tagged breakpoint using an RTI or
BDM GO command without program counter modification it will return to
the instruction whose tag generated the breakpoint. To avoid re triggering a
breakpoint at the same location reconfigure the S12XDBG module in the
SWI routine, if configured for an SWI breakpoint, or over the BDM
interface by executing a TRACE command before the GO to increment the
program flow past the tagged instruction.
An XGATE software breakpoint is forced immediately, the tracing session
terminated and the XGATE module execution stops. The user can thus
determine if an XGATE breakpoint has occurred by reading out the XGATE
program counter over the BDM interface.
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Chapter 9
Security (S12XE9SECV2)
Table 9-1. Revision History
Version
Number
Revision
Date
Effective
Date
02.00
27 Aug
2004
08 Sep
2004
reviewed and updated for S12XD architecture
02.01
21 Feb
2007
21 Feb
2007
added S12XE, S12XF and S12XS architectures
02.02
19 Apr
2007
19 Apr
2007
corrected statement about Backdoor key access via BDM on XE, XF,
XS
9.1
Author
Description of Changes
Introduction
This specification describes the function of the security mechanism in the S12XE chip family (9SEC).
NOTE
No security feature is absolutely secure. However, Freescale’s strategy is to
make reading or copying the FLASH and/or EEPROM difficult for
unauthorized users.
9.1.1
Features
The user must be reminded that part of the security must lie with the application code. An extreme example
would be application code that dumps the contents of the internal memory. This would defeat the purpose
of security. At the same time, the user may also wish to put a backdoor in the application program. An
example of this is the user downloads a security key through the SCI, which allows access to a
programming routine that updates parameters stored in another section of the Flash memory.
The security features of the S12XE chip family (in secure mode) are:
• Protect the content of non-volatile memories (Flash, EEPROM)
• Execution of NVM commands is restricted
• Disable access to internal memory via background debug module (BDM)
• Disable access to internal Flash/EEPROM in expanded modes
• Disable debugging features for the CPU and XGATE
9.1.2
Modes of Operation
Table 9-2 gives an overview over availability of security relevant features in unsecure and secure modes.
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Table 9-2. Feature Availability in Unsecure and Secure Modes on S12XE
Unsecure Mode
Secure Mode
NS
SS
NX
ES
EX
ST
NS
SS
NX
ES
EX
ST
Flash Array Access
✔
✔
✔(1)
✔1
✔1
✔1
✔
✔
—
—
—
—
EEPROM Array Access
✔
✔
✔
✔
✔
✔
✔
✔
—
—
—
—
✔
2
✔
✔
2
2
✔
✔
2
✔
2
✔
✔
2
2
✔
✔
2
✔2
NVM Commands
✔
(2)
BDM
✔
✔
✔
✔
✔
✔
—
✔(3)
—
—
—
—
DBG Module Trace
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
XGATE Debugging
✔
✔
✔
✔
✔
✔
—
—
—
—
—
—
External Bus Interface
—
—
✔
✔
✔
✔
—
—
✔
✔
✔
✔
Internal status visible
multiplexed on
external bus
—
—
—
✔
✔
—
—
—
—
✔
✔
—
Internal accesses visible
—
—
—
—
—
✔
—
—
—
—
—
✔
on external bus
1. Availability of Flash arrays in the memory map depends on ROMCTL/EROMCTL pins and/or the state of the
ROMON/EROMON bits in the MMCCTL1 register. Please refer to the S12X_MMC block guide for detailed
information.
2. Restricted NVM command set only. Please refer to the NVM wrapper block guides for detailed information.
3. BDM hardware commands restricted to peripheral registers only.
9.1.3
Securing the Microcontroller
Once the user has programmed the Flash and EEPROM, the chip can be secured by programming the
security bits located in the options/security byte in the Flash memory array. These non-volatile bits will
keep the device secured through reset and power-down.
The options/security byte is located at address 0xFF0F (= global address 0x7F_FF0F) in the Flash memory
array. This byte can be erased and programmed like any other Flash location. Two bits of this byte are used
for security (SEC[1:0]). On devices which have a memory page window, the Flash options/security byte
is also available at address 0xBF0F by selecting page 0x3F with the PPAGE register. The contents of this
byte are copied into the Flash security register (FSEC) during a reset sequence.
0xFF0F
7
6
5
4
3
2
1
0
KEYEN1
KEYEN0
NV5
NV4
NV3
NV2
SEC1
SEC0
Figure 9-1. Flash Options/Security Byte
The meaning of the bits KEYEN[1:0] is shown in Table 9-3. Please refer to Section 9.1.5.1, “Unsecuring
the MCU Using the Backdoor Key Access” for more information.
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Table 9-3. Backdoor Key Access Enable Bits
KEYEN[1:0]
Backdoor Key
Access Enabled
00
0 (disabled)
01
0 (disabled)
10
1 (enabled)
11
0 (disabled)
The meaning of the security bits SEC[1:0] is shown in Table 9-4. For security reasons, the state of device
security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to
SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put
the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.
Table 9-4. Security Bits
SEC[1:0]
Security State
00
1 (secured)
01
1 (secured)
10
0 (unsecured)
11
1 (secured)
NOTE
Please refer to the Flash block guide for actual security configuration (in
section “Flash Module Security”).
9.1.4
Operation of the Secured Microcontroller
By securing the device, unauthorized access to the EEPROM and Flash memory contents can be prevented.
However, it must be understood that the security of the EEPROM and Flash memory contents also depends
on the design of the application program. For example, if the application has the capability of downloading
code through a serial port and then executing that code (e.g. an application containing bootloader code),
then this capability could potentially be used to read the EEPROM and Flash memory contents even when
the microcontroller is in the secure state. In this example, the security of the application could be enhanced
by requiring a challenge/response authentication before any code can be downloaded.
Secured operation has the following effects on the microcontroller:
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9.1.4.1
•
•
•
•
Background debug module (BDM) operation is completely disabled.
Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
Tracing code execution using the DBG module is disabled.
Debugging XGATE code (breakpoints, single-stepping) is disabled.
9.1.4.2
•
•
•
•
•
Normal Single Chip Mode (NS)
Special Single Chip Mode (SS)
BDM firmware commands are disabled.
BDM hardware commands are restricted to the register space.
Execution of Flash and EEPROM commands is restricted. Please refer to the NVM block guide for
details.
Tracing code execution using the DBG module is disabled.
Debugging XGATE code (breakpoints, single-stepping) is disabled.
Special single chip mode means BDM is active after reset. The availability of BDM firmware commands
depends on the security state of the device. The BDM secure firmware first performs a blank check of both
the Flash memory and the EEPROM. If the blank check succeeds, security will be temporarily turned off
and the state of the security bits in the appropriate Flash memory location can be changed If the blank
check fails, security will remain active, only the BDM hardware commands will be enabled, and the
accessible memory space is restricted to the peripheral register area. This will allow the BDM to be used
to erase the EEPROM and Flash memory without giving access to their contents. After erasing both Flash
memory and EEPROM, another reset into special single chip mode will cause the blank check to succeed
and the options/security byte can be programmed to “unsecured” state via BDM.
While the BDM is executing the blank check, the BDM interface is completely blocked, which means that
all BDM commands are temporarily blocked.
9.1.4.3
•
•
•
•
•
Expanded Modes (NX, ES, EX, and ST)
BDM operation is completely disabled.
Internal Flash memory and EEPROM are disabled.
Execution of Flash and EEPROM commands is restricted. Please refer to the FTM block guide for
details.
Tracing code execution using the DBG module is disabled.
Debugging XGATE code (breakpoints, single-stepping) is disabled
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Chapter 9 Security (S12XE9SECV2)
9.1.5
Unsecuring the Microcontroller
Unsecuring the microcontroller can be done by three different methods:
1. Backdoor key access
2. Reprogramming the security bits
3. Complete memory erase (special modes)
9.1.5.1
Unsecuring the MCU Using the Backdoor Key Access
In normal modes (single chip and expanded), security can be temporarily disabled using the backdoor key
access method. This method requires that:
•
•
•
The backdoor key at 0xFF00–0xFF07 (= global addresses 0x7F_FF00–0x7F_FF07) has been
programmed to a valid value.
The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.
In single chip mode, the application program programmed into the microcontroller must be
designed to have the capability to write to the backdoor key locations.
The backdoor key values themselves would not normally be stored within the application data, which
means the application program would have to be designed to receive the backdoor key values from an
external source (e.g. through a serial port).
The backdoor key access method allows debugging of a secured microcontroller without having to erase
the Flash. This is particularly useful for failure analysis.
NOTE
No word of the backdoor key is allowed to have the value 0x0000 or
0xFFFF.
9.1.6
Reprogramming the Security Bits
In normal single chip mode (NS), security can also be disabled by erasing and reprogramming the security
bits within Flash options/security byte to the unsecured value. Because the erase operation will erase the
entire sector from 0xFE00–0xFFFF (0x7F_FE00–0x7F_FFFF), the backdoor key and the interrupt vectors
will also be erased; this method is not recommended for normal single chip mode. The application
software can only erase and program the Flash options/security byte if the Flash sector containing the Flash
options/security byte is not protected (see Flash protection). Thus Flash protection is a useful means of
preventing this method. The microcontroller will enter the unsecured state after the next reset following
the programming of the security bits to the unsecured value.
This method requires that:
• The application software previously programmed into the microcontroller has been designed to
have the capability to erase and program the Flash options/security byte, or security is first disabled
using the backdoor key method, allowing BDM to be used to issue commands to erase and program
the Flash options/security byte.
• The Flash sector containing the Flash options/security byte is not protected.
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9.1.7
Complete Memory Erase (Special Modes)
The microcontroller can be unsecured in special modes by erasing the entire EEPROM and Flash memory
contents.
When a secure microcontroller is reset into special single chip mode (SS), the BDM firmware verifies
whether the EEPROM and Flash memory are erased. If any EEPROM or Flash memory address is not
erased, only BDM hardware commands are enabled. BDM hardware commands can then be used to write
to the EEPROM and Flash registers to mass erase the EEPROM and all Flash memory blocks.
When next reset into special single chip mode, the BDM firmware will again verify whether all EEPROM
and Flash memory are erased, and this being the case, will enable all BDM commands, allowing the Flash
options/security byte to be programmed to the unsecured value. The security bits SEC[1:0] in the Flash
security register will indicate the unsecure state following the next reset.
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Chapter 10
XGATE (S12XGATEV3)
Revision History
Version
Number
03.22
03.23
03.24
10.1
Date
6 Oct
2005
14 Dec
2005
17 Jan
2006
Author
Description of Changes
Dirk Heisswolf
Internal updates
Dirk Heisswolf
Updated code example
Dirk Heisswolf
Internal updates
Introduction
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the
MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the
transferred data and perform complex communication protocols.
The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s
interrupt load.
Figure 10-1 gives an overview on the XGATE architecture.
This document describes the functionality of the XGATE module, including:
• XGATE registers (Section 10.3, “Memory Map and Register Definition”)
• XGATE RISC core (Section 10.4.1, “XGATE RISC Core”)
• Hardware semaphores (Section 10.4.4, “Semaphores”)
• Interrupt handling (Section 10.5, “Interrupts”)
• Debug features (Section 10.6, “Debug Mode”)
• Security (Section 10.7, “Security”)
• Instruction set (Section 10.8, “Instruction Set”)
10.1.1
Glossary of Terms
XGATE Request
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A service request from a peripheral module which is directed to the XGATE by the S12X_INT
module (see Figure 10-1). Each XGATE request attempts to activate a XGATE channel at a certain
priority level.
XGATE Channel
The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request
Vector, Interrupt Flag) which are associated with a particular XGATE Request.
XGATE Channel ID
A 7-bit identifier associated with an XGATE channel. In S12XE designs valid Channel IDs range
from $0D to $78.
XGATE Priority Level
A priority ranging from 1 to 7 which is associated with an XGATE channel. The priority level of
an XGATE channel is selected in the S12X_INT module.
XGATE Register Bank
A register bank consists of registers R1-R7, CCR and the PC. Each interrupt level is associated with
one register bank.
XGATE Channel Interrupt
An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module.
XGATE Software Channel
Special XGATE channel that is not associated with any peripheral service request. A Software
Channel is triggered by its Software Trigger Bit which is implemented in the XGATE module.
XGATE Semaphore
A set of hardware flip-flops that can be exclusively set by either the S12X_CPU or the XGATE.
(see Section 10.4.4, “Semaphores”)
XGATE Thread
A code sequence which is executed by the XGATE’s RISC core after receiving an XGATE request.
XGATE Debug Mode
A special mode in which the XGATE’s RISC core is halted for debug purposes. This mode enables
the XGATE’s debug features (see Section 10.6, “Debug Mode”).
XGATE Software Error
The XGATE is able to detect a number of error conditions caused by erratic software (see
Section 10.4.5, “Software Error Detection”). These error conditions will cause the XGATE to seize
program execution and flag an Interrupt to the S12X_CPU.
Word
A 16 bit entity.
Byte
An 8 bit entity.
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Chapter 10 XGATE (S12XGATEV3)
10.1.2
Features
The XGATE module includes these features:
• Data movement between various targets (i.e. Flash, RAM, and peripheral modules)
• Data manipulation through built in RISC core
• Provides up to 108 XGATE channels, including 8 software triggered channels
• Interruptible thread execution
• Two register banks to support fast context switching between threads
• Hardware semaphores which are shared between the S12X_CPU and the XGATE module
• Able to trigger S12X_CPU interrupts upon completion of an XGATE transfer
• Software error detection to catch erratic application code
10.1.3
Modes of Operation
There are four run modes on S12XE devices.
• Run mode, wait mode, stop mode
The XGATE is able to operate in all of these three system modes. Clock activity will be
automatically stopped when the XGATE module is idle.
• Freeze mode (BDM active)
In freeze mode all clocks of the XGATE module may be stopped, depending on the module
configuration (see Section 10.3.1.1, “XGATE Control Register (XGMCTL)”).
10.1.4
Block Diagram
Figure 10-1 shows a block diagram of the XGATE.
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Chapter 10 XGATE (S12XGATEV3)
Peripheral Interrupts
XGATE
Requests
XGATE
XGATE
Interrupts
(XGIF)
S12X_INT
Interrupt Flags
Semaphores
RISC Core
Software
Triggers
Software Triggers
SWE
Interrupt
Data/Code
Software Error Logic
S12X_DBG
Peripherals
S12X_MMC
Figure 10-1. XGATE Block Diagram
10.2
External Signal Description
The XGATE module has no external pins.
10.3
Memory Map and Register Definition
This section provides a detailed description of address space and registers used by the XGATE module.
The memory map for the XGATE module is given below in Figure 10-2.The address listed for each register
is the sum of a base address and an address offset. The base address is defined at the SoC level and the
address offset is defined at the module level. Reserved registers read zero. Write accesses to the reserved
registers have no effect.
10.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bits and field functions follow the register
diagrams, in bit order.
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Chapter 10 XGATE (S12XGATEV3)
Register
Name
0x0000 R
XGMCTL
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
XG
XG
XG
XGEM
XGSSM
W
FRZM DBGM
FACTM
XG
SWEFM
7
6
5
4
3
XG
XGE XGFRZ XGDBG XGSS
FACT
XGIEM
0x0002 R
XGCHID W
0
0x0003 R
XGCHPL W
0
0
0
0
0
0
0
0
0
0
2
0
1
0
XG
XGIE
SWEF
XGCHID[6:0]
XGCHPL[2:0]
0x0004 R
Reserved W
0x0005 R
XGISPSEL W
0x0006 R
XGISP74 W
XGISP74[15:1]
0x0006 R
XGISP31 W
XGISP31[15:1]
0x0006
XGVBR
R
XGVBR[15:1]
W
0
XGISPSEL[1:0]
0
0
0
= Unimplemented or Reserved
Figure 10-2. XGATE Register Summary (Sheet 1 of 3)
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Chapter 10 XGATE (S12XGATEV3)
0x0008
XGIF
R
127
126
125
124
123
122
121
0
0
0
0
0
0
0
W
113
112
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
R
W
XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
R
W
XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10
15
0x0016
XGIF
114
R
31
0x0014
XGIF
115
XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58 XGF_57 XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50
47
0x0012
XGIF
116
R
W
63
0x0010
XGIF
117
XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68 XGF_67 XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60
79
0x000E
XGIF
118
R
W
95
0x000C
XGIF
119
XGIF_78 XGF_77 XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70
W
111
0x000A
XGIF
120
14
13
R
W
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XGIF_0F XGIF_0E XGIF_0D
= Unimplemented or Reserved
Figure 10-2. XGATE Register Summary (Sheet 2 of 3)
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15
14
13
0x0018
R
XGSWTM W
0
0
0
0x001A
R
XGSEMM W
0
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
0
0
0
3
2
1
0
XGSWT[7:0]
XGSWTM[7:0]
0
4
XGSEM[7:0]
XGSEMM[7:0]
0x001C
R
Reserved W
0x001D
XGCCR
0x001E
XGPC
R
0
0
0
0
W
R
XGN XGZ
XGV XGC
XGPC
W
0x0020
R
Reserved W
0x0021
R
Reserved W
0x0022
XGR1
0x0024
XGR2
R
R
XGR2
W
0x0026
XGR3
W
0x0028
XGR4
W
0x002A
XGR5
XGR1
W
R
XGR3
R
XGR4
R
XGR5
W
0x002C
XGR6
R
W
0x002E
XGR7
W
XGR6
R
XGR7
= Unimplemented or Reserved
Figure 10-2. XGATE Register Summary (Sheet 3 of 3)
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.1
XGATE Control Register (XGMCTL)
All module level switches and flags are located in the XGATE Module Control Register Figure 10-3.
Module Base +0x00000
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
XG
SSM
XG
FACTM
0
0
R
W
XGEM
Reset
0
XG
XG
FRZM DBGM
0
0
7
0
0
5
4
3
2
0
XG
XGIEM
SWEFM
0
6
XGE
XGFRZ XGDBG XGSS XGFACT
0
0
0
0
0
0
1
0
XG
SWEF
XGIE
0
0
= Unimplemented or Reserved
Figure 10-3. XGATE Control Register (XGMCTL)
Read: Anytime
Write: Anytime
Table 10-1. XGMCTL Field Descriptions (Sheet 1 of 3)
Field
Description
15
XGEM
XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is
written to the XGEM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGE in the same bus cycle
1 Enable write access to the XGE in the same bus cycle
14
XGFRZM
XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared
if a "1" is written to the XGFRZM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGFRZ in the same bus cycle
1 Enable write access to the XGFRZ in the same bus cycle
13
XGDBGM
XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared
if a "1" is written to the XGDBGM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGDBG in the same bus cycle
1 Enable write access to the XGDBG in the same bus cycle
12
XGSSM
XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a
"1" is written to the XGSSM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGSS in the same bus cycle
1 Enable write access to the XGSS in the same bus cycle
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Chapter 10 XGATE (S12XGATEV3)
Table 10-1. XGMCTL Field Descriptions (Sheet 2 of 3)
Field
11
XGFACTM
Description
XGFACT Mask — This bit controls the write access to the XGFACT bit. The XGFACT bit can only be set or
cleared if a "1" is written to the XGFACTM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGFACT in the same bus cycle
1 Enable write access to the XGFACT in the same bus cycle
9
XGSWEF Mask — This bit controls the write access to the XGSWEF bit. The XGSWEF bit can only be cleared
XGSWEFM if a "1" is written to the XGSWEFM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGSWEF in the same bus cycle
1 Enable write access to the XGSWEF in the same bus cycle
8
XGIEM
XGIE Mask — This bit controls the write access to the XGIE bit. The XGIE bit can only be set or cleared if a "1"
is written to the XGIEM bit in the same register access.
Read:
This bit will always read "0".
Write:
0 Disable write access to the XGIE in the same bus cycle
1 Enable write access to the XGIE in the same bus cycle
7
XGE
XGATE Module Enable (Request Enable)— This bit enables incoming XGATE requests from the S12X_INT
module. If the XGE bit is cleared, pending XGATE requests will be ignored. The thread that is executed by the
RISC core while the XGE bit is cleared will continue to run.
Read:
0 Incoming requests are disabled
1 Incoming requests are enabled
Write:
0 Disable incoming requests
1 Enable incoming requests
6
XGFRZ
Halt XGATE in Freeze Mode — The XGFRZ bit controls the XGATE operation in Freeze Mode (BDM active).
Read:
0 RISC core operates normally in Freeze (BDM active)
1 RISC core stops in Freeze Mode (BDM active)
Write:
0 Don’t stop RISC core in Freeze Mode (BDM active)
1 Stop RISC core in Freeze Mode (BDM active)
5
XGDBG
XGATE Debug Mode — This bit indicates that the XGATE is in Debug Mode (see Section 10.6, “Debug Mode”).
Debug Mode can be entered by Software Breakpoints (BRK instruction), Tagged or Forced Breakpoints (see
S12X_DBG Section), or by writing a "1" to this bit.
Read:
0 RISC core is not in Debug Mode
1 RISC core is in Debug Mode
Write:
0 Leave Debug Mode
1 Enter Debug Mode
Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit.
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Chapter 10 XGATE (S12XGATEV3)
Table 10-1. XGMCTL Field Descriptions (Sheet 3 of 3)
Field
4
XGSS
2
XGATE Single Step — This bit forces the execution of a single instruction.1
Read:
0 No single step in progress
1 Single step in progress
Write
0 No effect
1 Execute a single RISC instruction
Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has
been executed.
3
XGFACT
Fake XGATE Activity — This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set
the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE
idle periods
Read:
0 XGATE will only flag activity if it is not idle or in debug mode.
1 XGATE will always signal activity to the MCU.
Write:
0 Only flag activity if not idle or in debug mode.
1 Always signal XGATE activity.
1
XGSWEF
XGATE Software Error Flag — This bit signals a software error. It is set whenever the RISC core detects an
error condition2. The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread
and cause the XGATE to become idle.
Read:
0 No software error detected
1 Software error detected
Write:
0 No effect
1 Clears the XGSWEF bit
0
XGIE
1
Description
XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module
Read:
0 All outgoing XGATE interrupts disabled (except software error interrupts)
1 All outgoing XGATE interrupts enabled
Write:
0 Disable all outgoing XGATE interrupts (except software error interrupts)
1 Enable all outgoing XGATE interrupts
Refer to Section 10.6.1, “Debug Features”
Refer to Section 10.4.5, “Software Error Detection”
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.2
XGATE Channel ID Register (XGCHID)
The XGATE Channel ID Register (Figure 10-4) shows the identifier of the XGATE channel that is
currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register
can be used to start and terminate threads. Refer to Section 10.6.1, “Debug Features” for further
information.
Module Base +0x0002
7
R
6
5
4
0
3
2
1
0
0
0
0
XGCHID[6:0]
W
Reset
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-4. XGATE Channel ID Register (XGCHID)
Read: Anytime
Write: In Debug Mode1
Table 10-2. XGCHID Field Descriptions
Field
Description
6–0
Request Identifier — ID of the currently active channel
XGCHID[6:0]
10.3.1.3
XGATE Channel Priority Level (XGCHPL)
The XGATE Channel Priority Level Register (Figure 10-5) shows the priority level of the current thread.
In debug mode this register can be used to select a priority level when launching a thread (see
Section 10.6.1, “Debug Features”).
Module Base +0x0003
R
7
6
5
4
3
0
0
0
0
0
0
0
0
0
2
1
0
XGCHPL[2:0]
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 10-5. XGATE Channel Priority Level Register (XGCHPL)
Read: Anytime
Write: In Debug Mode1
1. Refer to Section 10.6.1, “Debug Features”
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Chapter 10 XGATE (S12XGATEV3)
Table 10-3. XGCHPL Field Descriptions
Field
2-0
XGCHPL[2:0]
10.3.1.4
Description
Priority Level— Priority level of the currently active channel
XGATE Initial Stack Pointer Select Register (XGISPSEL)
The XGATE Initial Stack Pointer Select Register (Figure 10-6) determines the register which is mapped
to address “Module Base +0x0006”. A value of zero selects the Vector Base Register (XGVBR). Setting
this register to a channel priority level (non-zero value) selects the corresponding Initial Stack Pointer
Registers XGISP74 or XGISP31 (see Table 10-5).
Module Base +0x0005
R
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
1
XGISPSEL[1:0]
W
Reset
0
0
0
= Unimplemented or Reserved
Figure 10-6. XGATE Initial Stack Pointer Select Register (XGISPSEL)
Read: Anytime
Write: Anytime
Table 10-4. XGISPSEL Field Descriptions
Field
Description
1-0
Register select— Determines whether XGISP74, XGISP31, or XGVBR is mapped to “Module Base +0x0006”.
XGISPSEL[1:0] See Table 10-5.
Table 10-5. XGISP74, XGISP31, XGVBR Mapping
XGISPSEL[1:0]
Register Mapped to “Module Base +0x0006“
3
Reserved
2
XGISP74
1
XGISP31
0
XGVBR
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.5
XGATE Initial Stack Pointer for Interrupt Priorities 7 to 4 (XGISP74)
The XGISP74 register is intended to point to the stack region that is used by XGATE channels of priority
7 to 4. Every time a thread of such priority is started, RISC core register R7 will be initialized with the
content of XGISP74.
Module Base +0x0006
15
14
13
12
11
10
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
XGISP74[15:1]
W
Reset
9
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-7. XGATE Initial Stack Pointer for Interrupt Priorities 7 to 4 (XGISP74)
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Table 10-6. XGISP74 Field Descriptions
Field
15–1
XBISP74[15:1]
10.3.1.6
Description
Initial Stack Pointer— The XGISP74 register holds the initial value of RISC core register R7, for threads of
priority 7 to 4.
XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
The XGISP31 register is intended to point to the stack region that is used by XGATE channels of priority
3 to 1. Every time a thread of such priority is started, RISC core register R7 will be initialized with the
content of XGISP31.
Module Base +0x0006
15
14
13
12
11
10
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
XGISP31[15:1]
W
Reset
9
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Table 10-7. XGISP31 Field Descriptions
Field
15–1
XBISP31[15:1]
Description
Initial Stack Pointer— The XGISP31 register holds the initial value of RISC core register R7, for threads of
priority 3 to 1.
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.7
XGATE Vector Base Address Register (XGVBR)
The Vector Base Address Register (Figure 10-9) determines the location of the XGATE vector block (see
Section Figure 10-23., “XGATE Vector Block).
Module Base +0x0006
15
14
13
12
11
10
9
R
7
6
5
4
3
2
1
1
1
1
1
1
1
1
0
0
0
XGVBR[15:1]
W
Reset
8
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-9. XGATE Vector Base Address Register (XGVBR)
Read: Anytime
Write: Only if XGATE requests are disabled (XGE = 0) and idle (XGCHID = $00))
Table 10-8. XGVBR Field Descriptions
Field
Description
15–1
Vector Base Address — The XGVBR register holds the start address of the vector block in the XGATE
XBVBR[15:1] memory map.
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.8
XGATE Channel Interrupt Flag Vector (XGIF)
The XGATE Channel Interrupt Flag Vector (Figure 10-10) provides access to the interrupt flags of all
channels. Each flag may be cleared by writing a "1" to its bit location. Refer to Section 10.5.2, “Outgoing
Interrupt Requests” for further information.
Module Base +0x0008
R
127
126
125
124
123
122
121
0
0
0
0
0
0
0
120
119
XGIF_78
XGF_77
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
R
W
Reset
XGIF_6F XGIF_6E XGIF_6D XGIF_6C XGIF_6B XGIF_6A XGIF_69 XGIF_68
XGF_67
118
117
116
115
114
113
112
XGIF_76 XGIF_75 XGIF_74 XGIF_73 XGIF_72 XGIF_71 XGIF_70
XGIF_66 XGIF_65 XGIF_64 XGIF_63 XGIF_62 XGIF_61 XGIF_60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
XGIF_5F XGIF_5E XGIF_5D XGIF_5C XGIF_5B XGIF_5A XGIF_59 XGIF_58
XGF_57
XGIF_56 XGIF_55 XGIF_54 XGIF_53 XGIF_52 XGIF_51 XGIF_50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
XGIF_4F XGIF_4E XGIF_4D XGIF_4C XGIF_4B XGIF_4A XGIF_49 XGIF_48 XGF _47 XGIF_46 XGIF_45 XGIF_44 XGIF_43 XGIF_42 XGIF_41 XGIF_40
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
XGIF_3F XGIF_3E XGIF_3D XGIF_3C XGIF_3B XGIF_3A XGIF_39 XGIF_38 XGF _37 XGIF_36 XGIF_35 XGIF_34 XGIF_33 XGIF_32 XGIF_31 XGIF_30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
XGIF_2F XGIF_2E XGIF_2D XGIF_2C XGIF_2B XGIF_2A XGIF_29 XGIF_28 XGF _27 XGIF_26 XGIF_25 XGIF_24 XGIF_23 XGIF_22 XGIF_21 XGIF_20
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
XGIF_0F XGIF_0E XGIF_0D
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-10. XGATE Channel Interrupt Flag Vector (XGIF)
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Chapter 10 XGATE (S12XGATEV3)
Read: Anytime
Write: Anytime
Table 10-9. XGIV Field Descriptions
Field
Description
127–9
XGIF[78:9]
Channel Interrupt Flags — These bits signal pending channel interrupts. They can only be set by the RISC
core (see SIF instruction on page 10-455). Each flag can be cleared by writing a "1" to its bit location.
Unimplemented interrupt flags will always read "0". Section “Interrupts” of the SoC Guide for a list of
implemented Interrupts.
Read:
0 Channel interrupt is not pending
1 Channel interrupt is pending if XGIE is set
Write:
0 No effect
1 Clears the interrupt flag
NOTE
Suggested Mnemonics for accessing the interrupt flag vector on a word
basis are:
XGIF_7F_70 (XGIF[127:112]),
XGIF_6F_60 (XGIF[111:96]),
XGIF_5F_50 (XGIF[95:80]),
XGIF_4F_40 (XGIF[79:64]),
XGIF_3F_30 (XGIF[63:48]),
XGIF_2F_20 (XGIF[47:32]),
XGIF_1F_10 (XGIF[31:16]),
XGIF_0F_00 (XGIF[15:0])
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.9
XGATE Software Trigger Register (XGSWT)
The eight software triggers of the XGATE module can be set and cleared through the XGATE Software
Trigger Register (Figure 10-11). The upper byte of this register, the software trigger mask, controls the
write access to the lower byte, the software trigger bits. These bits can be set or cleared if a "1" is written
to the associated mask in the same bus cycle. Refer to Section 10.5.2, “Outgoing Interrupt Requests” for
further information.
Module Base +0x00018
R
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
6
5
0
0
0
0
0
4
3
2
1
0
0
0
0
XGSWT[7:0]
XGSWTM[7:0]
W
Reset
7
0
0
0
0
0
Figure 10-11. XGATE Software Trigger Register (XGSWT)
Read: Anytime
Write: Anytime
Table 10-10. XGSWT Field Descriptions
Field
Description
15–8
Software Trigger Mask — These bits control the write access to the XGSWT bits. Each XGSWT bit can only
XGSWTM[7:0] be written if a "1" is written to the corresponding XGSWTM bit in the same access.
Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSWT in the same bus cycle
1 Enable write access to the corresponding XGSWT bit in the same bus cycle
7–0
XGSWT[7:0]
Software Trigger Bits — These bits act as interrupt flags that are able to trigger XGATE software channels.
They can only be set and cleared by software.
Read:
0 No software trigger pending
1 Software trigger pending if the XGIE bit is set
Write:
0 Clear Software Trigger
1 Set Software Trigger
NOTE
The XGATE channel IDs that are associated with the eight software triggers
are determined on chip integration level. (see Section “Interrupts“ of the Soc
Guide)
XGATE software triggers work like any peripheral interrupt. They can be
used as XGATE requests as well as S12X_CPU interrupts. The target of the
software trigger must be selected in the S12X_INT module.
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.10 XGATE Semaphore Register (XGSEM)
The XGATE provides a set of eight hardware semaphores that can be shared between the S12X_CPU and
the XGATE RISC core. Each semaphore can either be unlocked, locked by the S12X_CPU or locked by
the RISC core. The RISC core is able to lock and unlock a semaphore through its SSEM and CSEM
instructions. The S12X_CPU has access to the semaphores through the XGATE Semaphore Register
(Figure 10-12). Refer to section Section 10.4.4, “Semaphores” for details.
Module Base +0x0001A
R
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
W
Reset
7
6
5
0
0
0
0
3
2
1
0
0
0
0
XGSEM[7:0]
XGSEMM[7:0]
0
4
0
0
0
0
0
Figure 10-12. XGATE Semaphore Register (XGSEM)
Read: Anytime
Write: Anytime (see Section 10.4.4, “Semaphores”)
Table 10-11. XGSEM Field Descriptions
Field
Description
15–8
Semaphore Mask — These bits control the write access to the XGSEM bits.
XGSEMM[7:0] Read:
These bits will always read "0".
Write:
0 Disable write access to the XGSEM in the same bus cycle
1 Enable write access to the XGSEM in the same bus cycle
7–0
XGSEM[7:0]
Semaphore Bits — These bits indicate whether a semaphore is locked by the S12X_CPU. A semaphore can
be attempted to be set by writing a "1" to the XGSEM bit and to the corresponding XGSEMM bit in the same
write access. Only unlocked semaphores can be set. A semaphore can be cleared by writing a "0" to the
XGSEM bit and a "1" to the corresponding XGSEMM bit in the same write access.
Read:
0 Semaphore is unlocked or locked by the RISC core
1 Semaphore is locked by the S12X_CPU
Write:
0 Clear semaphore if it was locked by the S12X_CPU
1 Attempt to lock semaphore by the S12X_CPU
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.11 XGATE Condition Code Register (XGCCR)
The XGCCR register (Figure 10-13) provides access to the RISC core’s condition code register.
Module Base +0x001D
R
7
6
5
4
0
0
0
0
0
0
0
W
Reset
0
3
2
1
0
XGN
XGZ
XGV
XGC
0
0
0
0
= Unimplemented or Reserved
Figure 10-13. XGATE Condition Code Register (XGCCR)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-12. XGCCR Field Descriptions
Field
Description
3
XGN
Sign Flag — The RISC core’s Sign flag
2
XGZ
Zero Flag — The RISC core’s Zero flag
1
XGV
Overflow Flag — The RISC core’s Overflow flag
0
XGC
Carry Flag — The RISC core’s Carry flag
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10.3.1.12 XGATE Program Counter Register (XGPC)
The XGPC register (Figure 10-14) provides access to the RISC core’s program counter.
Module Base +0x0001E
15
14
13
12
11
10
9
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGPC
W
Reset
8
0
0
0
0
0
0
0
0
Figure 10-14. XGATE Program Counter Register (XGPC)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-13. XGPC Field Descriptions
Field
15–0
XGPC[15:0]
Description
Program Counter — The RISC core’s program counter
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.13 XGATE Register 1 (XGR1)
The XGR1 register (Figure 10-15) provides access to the RISC core’s register 1.
Module Base +0x00022
15
14
13
12
11
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGR1
W
Reset
7
0
0
0
0
0
0
0
0
Figure 10-15. XGATE Register 1 (XGR1)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-14. XGR1 Field Descriptions
Field
15–0
XGR1[15:0]
Description
XGATE Register 1 — The RISC core’s register 1
10.3.1.14 XGATE Register 2 (XGR2)
The XGR2 register (Figure 10-16) provides access to the RISC core’s register 2.
Module Base +0x00024
15
14
13
12
11
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGR2
W
Reset
7
0
0
0
0
0
0
0
0
Figure 10-16. XGATE Register 2 (XGR2)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-15. XGR2 Field Descriptions
Field
15–0
XGR2[15:0]
Description
XGATE Register 2 — The RISC core’s register 2
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.15 XGATE Register 3 (XGR3)
The XGR3 register (Figure 10-17) provides access to the RISC core’s register 3.
Module Base +0x00026
15
14
13
12
11
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGR3
W
Reset
7
0
0
0
0
0
0
0
0
Figure 10-17. XGATE Register 3 (XGR3)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-16. XGR3 Field Descriptions
Field
15–0
XGR3[15:0]
Description
XGATE Register 3 — The RISC core’s register 3
10.3.1.16 XGATE Register 4 (XGR4)
The XGR4 register (Figure 10-18) provides access to the RISC core’s register 4.
Module Base +0x00028
15
14
13
12
11
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGR4
W
Reset
7
0
0
0
0
0
0
0
0
Figure 10-18. XGATE Register 4 (XGR4)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-17. XGR4 Field Descriptions
Field
15–0
XGR4[15:0]
Description
XGATE Register 4 — The RISC core’s register 4
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.17 XGATE Register 5 (XGR5)
The XGR5 register (Figure 10-19) provides access to the RISC core’s register 5.
Module Base +0x0002A
15
14
13
12
11
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGR5
W
Reset
7
0
0
0
0
0
0
0
0
Figure 10-19. XGATE Register 5 (XGR5)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-18. XGR5 Field Descriptions
Field
15–0
XGR5[15:0]
Description
XGATE Register 5 — The RISC core’s register 5
10.3.1.18 XGATE Register 6 (XGR6)
The XGR6 register (Figure 10-20) provides access to the RISC core’s register 6.
Module Base +0x0002C
15
14
13
12
11
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGR6
W
Reset
7
0
0
0
0
0
0
0
0
Figure 10-20. XGATE Register 6 (XGR6)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-19. XGR6 Field Descriptions
Field
15–0
XGR6[15:0]
Description
XGATE Register 6 — The RISC core’s register 6
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Chapter 10 XGATE (S12XGATEV3)
10.3.1.19 XGATE Register 7 (XGR7)
The XGR7 register (Figure 10-21) provides access to the RISC core’s register 7.
Module Base +0x0002E
15
14
13
12
11
10
9
8
R
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
XGR7
W
Reset
7
0
0
0
0
0
0
0
0
Figure 10-21. XGATE Register 7 (XGR7)
Read: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Write: In debug mode if unsecured and not idle (XGCHID ≠ 0x00)
Table 10-20. XGR7 Field Descriptions
Field
15–0
XGR7[15:0]
Description
XGATE Register 7 — The RISC core’s register 7
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Chapter 10 XGATE (S12XGATEV3)
10.4
Functional Description
The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories
and peripherals (see Figure 10-1). The RISC processor always remains in an idle state until it is triggered
by an XGATE request. Then it executes a code sequence (thread) that is associated with the requested
XGATE channel. Each thread can run on a priority level ranging from 1 to 7. Refer to the S12X_INT
Section for information on how to select priority levels for XGATE threads. Low priority threads (interrupt
levels 1 to 3) can be interrupted by high priority threads (interrupt levels 4 to 7). High priority threads are
not interruptible. The register content of an interrupted thread is maintained and restored by the XGATE
hardware.
To signal the completion of a task the XGATE is able to send interrupts to the S12X_CPU. Each XGATE
channel has its own interrupt vector. Refer to the S12X_INT Section for detailed information.
The XGATE module also provides a set of hardware semaphores which are necessary to ensure data
consistency whenever RAM locations or peripherals are shared with the S12X_CPU.
The following sections describe the components of the XGATE module in further detail.
10.4.1
XGATE RISC Core
The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit
manipulations, and simple arithmetic operations (see Section 10.8, “Instruction Set”).
It is able to access the MCU’s internal memories and peripherals without blocking these resources from
the S12X_CPU1. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core
will be stalled until the resource becomes available again.1
The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC
core can perform up to two RAM accesses per S12X_CPU bus cycle.
Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU
cycle can not be exceeded.
The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral
modules or by software.
1. With the exception of PRR registers (see Section “S12X_MMC”).
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Chapter 10 XGATE (S12XGATEV3)
10.4.2
Programmer’s Model
Register Block
15
15
R7 (Stack Pointer)
R6
15
R5
15
R4
15
R3
15
R2
15
R1(Data Pointer)
15
R0 = 0
Program Counter
0
15
0
PC
0
0
0
0
Condition
Code
Register
NZVC
3 2 1 0
0
0
0
Figure 10-22. Programmer’s Model
The programmer’s model of the XGATE RISC core is shown in Figure 10-22. The processor offers a set
of seven general purpose registers (R1 - R7), which serve as accumulators and index registers. An
additional eighth register (R0) is tied to the value “$0000”. Registers R1 and R7 have additional
functionality. R1 is preloaded with the initial data pointer of the channel’s service request vector (see
Figure 10-23). R7 is either preloaded with the content of XGISP74 if the interrupt priority of the current
channel is in the range 7 to 4, or it is with preloaded the content of XGISP31 if the interrupt priority of the
current channel is in the range 3 to 1. The remaining general purpose registers will be reset to an
unspecified value at the beginning of each thread.
The 16 bit program counter allows the addressing of a 64 kbyte address space.
The condition code register contains four bits: the sign bit (S), the zero flag (Z), the overflow flag (V), and
the carry bit (C). The initial content of the condition code register is undefined.
10.4.3
Memory Map
The XGATE’s RISC core is able to access an address space of 64K bytes. The allocation of memory blocks
within this address space is determined on chip level. Refer to the S12X_MMC Section for a detailed
information.
The XGATE vector block assigns a start address and a data pointer to each XGATE channel. Its position
in the XGATE memory map can be adjusted through the XGVBR register (see Section 10.3.1.7, “XGATE
Vector Base Address Register (XGVBR)”). Figure 10-23 shows the layout of the vector block. Each vector
consists of two 16 bit words. The first contains the start address of the service routine. This value will be
loaded into the program counter before a service routine is executed. The second word is a pointer to the
service routine’s data space. This value will be loaded into register R1 before a service routine is executed.
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Chapter 10 XGATE (S12XGATEV3)
XGVBR
+$0000
unused
Code
+$0024
Channel $09 Initial Program Counter
Channel $09 Initial Data Pointer
+$0028
Channel $0A Initial Program Counter
Data
Channel $0A Initial Data Pointer
+$002C
Channel $0B Initial Program Counter
Channel $0B Initial Data Pointer
+$0030
Channel $0C Initial Program Counter
Code
Channel $0C Initial Data Pointer
+$01E0
Channel $78 Initial Program Counter
Data
Channel $78 Initial Data Pointer
Figure 10-23. XGATE Vector Block
10.4.4
Semaphores
The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism
to protect system resources that are shared between two concurrent threads of program execution; one
thread running on the S12X_CPU and one running on the XGATE RISC core.
Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked
by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore
register (XGSEM, see Section 10.3.1.10, “XGATE Semaphore Register (XGSEM)”). The RISC core does
this through its SSEM and CSEM instructions.
IFigure 10-24 illustrates the valid state transitions.
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Chapter 10 XGATE (S12XGATEV3)
set_xgsem:
clr_xgsem:
ssem:
csem:
1 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
0 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
Executing SSEM instruction (on semaphore n)
Executing CSEM instruction (on semaphore n)
clr_xgsem
csem
LOCKED BY
S12X_CPU
LOCKED BY
XGATE
clr_xgsem
csem
ssem &
set_xgsem
ssem
UNLOCKED
ssem & set_xgsem
Figure 10-24. Semaphore State Transitions
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Chapter 10 XGATE (S12XGATEV3)
Figure 10-25 gives an example of the typical usage of the XGATE hardware semaphores.
Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is
running on the RISC core. They both have a critical section of code that accesses the same system resource.
To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence
must be embedded in a semaphore lock/release sequence as shown.
S12X_CPU
XGATE
.........
.........
1 ⇒ XGSEM[n]
SSEM
XGSEM[n] 1?
BCC?
critical
code
sequence
0 ⇒ XGSEM[n]
.........
critical
code
sequence
CSEM
.........
Figure 10-25. Algorithm for Locking and Releasing Semaphores
10.4.5
Software Error Detection
Upon detecting an error condition caused by erratic application code, the XGATE module will
immediately terminate program execution and trigger a non-maskable interrupt to the S12X_CPU. There
are three error conditions:
• Execution of an illegal opcode
• Illegal opcode fetches
• Illegal load or store accesses
All opcodes which are not listed in section Section 10.8, “Instruction Set” are illegal opcodes. Illegal
opcode fetches as well as illegal load and store accesses are defined on chip level. Refer to the
S12X_MMC Section for a detailed information.
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NOTE
When executing a branch (BCC, BCS,...), a jump (JAL) or an RTS
instruction, the XGATE prefetches and discards the opcode of the following
instruction. The XGATE will perform its software error handling actions
(see above) if this opcode fetch is illegal.
10.5
10.5.1
Interrupts
Incoming Interrupt Requests
XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see
S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which
specific interrupt requests these are and which channel ID they are assigned to is documented in Section
“Interrupts” of the SoC Guide.
10.5.2
Outgoing Interrupt Requests
There are three types of interrupt requests which can be triggered by the XGATE module:
4. Channel interrupts
For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector
(XGIF, see Section 10.3.1.8, “XGATE Channel Interrupt Flag Vector (XGIF)”). These flags can be
set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to
the S12X_CPU when the XGATE has completed one of its task.
5. Software triggers
Software triggers are interrupt flags, which can be set and cleared by software (see
Section 10.3.1.9, “XGATE Software Trigger Register (XGSWT)”). They are typically used to
trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to
the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software.
6. Software error interrupt
The software error interrupt signals to the S12X_CPU the detection of an error condition in the
XGATE application code (see Section 10.4.5, “Software Error Detection”). This is a non-maskable
interrupt. Executing the interrupt service routine will automatically reset the interrupt line.
All outgoing XGATE interrupts, except software error interrupts, can be disabled by the XGIE bit in the
XGATE module control register (XGMCTL, see Section 10.3.1.1, “XGATE Control Register
(XGMCTL)”).
10.6
Debug Mode
The XGATE debug mode is a feature to allow debugging of application code.
10.6.1
Debug Features
In debug mode the RISC core will be halted and the following debug features will be enabled:
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Chapter 10 XGATE (S12XGATEV3)
•
Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)1
All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue
program execution with the modified register values.
1. Only possible if MCU is unsecured
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•
•
Single Stepping
Writing a "1" to the XGSS bit will call the RISC core to execute a single instruction. All RISC core
registers will be updated accordingly.
Write accesses to the XGCHID register and the XGCHPL register
XGATE threads can be initiated and terminated through a 16 write access to the XGCHID and the
XGCHPL register or through a 8 bit write access to the XGCHID register. Detailed operation is
shown in Table 10-21. Once a thread has been initiated it’s code can be either single stepped or it
can be executed by leaving debug mode.
Table 10-21. Initiating and Terminating Threads in Debug Mode
Single Cycle Write
Access to...
Register Content
XGCHPL
XGCHID
XGCHPL
0
0
1..127
-1
Set new XGCHID
Set XGCHPL to 0x01
Initiate new thread
0
0
1..127
0..7
Set new XGCHID
Set new XGCHPL
Initiate new thread
4..7
Interrupt current thread
Set new XGCHID
Set new XGCHPL
Initiate new thread
1..127
0..3
1..127
1..127
0..7
0
0..7
All other combinations
1
Action
XGCHID
-1
Terminate current thread.
Resume interrupted thread or become idle if
no interrupted thread is pending
No action
8 bit write access to XGCHID
NOTE
Even though zero is not a valid interrupt priority level of the S12X_INT
module, a thread of priority level 0 can be initiated in debug mode. The
XGATE handles requests of priority level 0 in the same way as it handles
requests of priority levels 1 to 3.
NOTE
All channels 1 to 127 can be initiated by writing to the XGCHID register,
even if they are not assigned to any peripheral module.
NOTE
In Debug Mode the XGATE will ignore all requests from peripheral
modules.
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Chapter 10 XGATE (S12XGATEV3)
10.6.1.0.1
Entering Debug Mode
Debug mode can be entered in four ways:
1. Setting XGDBG to "1"
Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter
debug mode upon completion of the current instruction.
NOTE
After writing to the XGDBG bit the XGATE will not immediately enter
debug mode. Depending on the instruction that is executed at this time there
may be a delay of several clock cycles. The XGDBG will read "0" until
debug mode is entered.
2. Software breakpoints
XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A
software breakpoint is set by replacing an instruction of the program code with the "BRK"
instruction.
As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode.
Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of
the S12X_DBG Section).
Upon entering debug mode, the program counter will point to the "BRK" instruction. The other
RISC core registers will hold the result of the previous instruction.
To resume program execution, the "BRK" instruction must be replaced by the original instruction
before leaving debug mode.
3. Tagged Breakpoints
The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter
debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section).
Upon entering debug mode, the program counter will point to the tagged instruction. The other
RISC core registers will hold the result of the previous instruction.
4. Forced Breakpoints
Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG
Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion
of the current instruction.
10.6.2
Leaving Debug Mode
Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been
cleared in debug mode), program execution will resume at the value of XGPC.
10.7
Security
In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug
features have been made. These are:
• Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device
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•
•
Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device
Single stepping is not possible on a secured device
10.8
10.8.1
Instruction Set
Addressing Modes
For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all
operations must have one of the eight general purpose registers R0 … R7 as their source as well their
destination.
All word accesses must work with a word aligned address, that is A[0] = 0!
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10.8.1.1
Naming Conventions
RD
RD.L
RD.H
RS, RS1, RS2
RS.L, RS1.L, RS2.L
RS.H, RS1.H, RS2.H
RB
RI
RI+
–RI
Destination register, allowed range is R0–R7
Low byte of the destination register, bits [7:0]
High byte of the destination register, bits [15:8]
Source register, allowed range is R0–R7
Low byte of the source register, bits [7:0]
High byte of the source register, bits[15:8]
Base register for indexed addressing modes, allowed
range is R0–R7
Offset register for indexed addressing modes with
register offset, allowed range is R0–R7
Offset register for indexed addressing modes with
register offset and post-increment,
Allowed range is R0–R7 (R0+ is equivalent to R0)
Offset register for indexed addressing modes with
register offset and pre-decrement,
Allowed range is R0–R7 (–R0 is equivalent to R0)
NOTE
Even though register R1 is intended to be used as a pointer to the data
segment, it may be used as a general purpose data register as well.
Selecting R0 as destination register will discard the result of the instruction.
Only the condition code register will be updated
10.8.1.2
Inherent Addressing Mode (INH)
Instructions that use this addressing mode either have no operands or all operands are in internal XGATE
registers.
Examples:
BRK
RTS
10.8.1.3
Immediate 3-Bit Wide (IMM3)
Operands for immediate mode instructions are included in the instruction stream and are fetched into the
instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an
immediate addressing mode operand. This address mode is used for semaphore instructions.
Examples:
CSEM
SSEM
#1
#3
; Unlock semaphore 1
; Lock Semaphore 3
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10.8.1.4
Immediate 4 Bit Wide (IMM4)
The 4 bit wide immediate addressing mode is supported by all shift instructions.
RD = RD ∗ IMM4
Examples:
LSL
LSR
10.8.1.5
R4,#1
R4,#3
; R4 = R4 << 1; shift register R4 by 1 bit to the left
; R4 = R4 >> 3; shift register R4 by 3 bits to the right
Immediate 8 Bit Wide (IMM8)
The 8 bit wide immediate addressing mode is supported by four major commands (ADD, SUB, LD, CMP).
RD = RD ∗ imm8
Examples:
ADDL
SUBL
LDH
CMPL
10.8.1.6
R1,#1
R2,#2
R3,#3
R4,#4
;
;
;
;
adds an 8 bit value to register R1
subtracts an 8 bit value from register R2
loads an 8 bit immediate into the high byte of Register R3
compares the low byte of register R4 with an immediate value
Immediate 16 Bit Wide (IMM16)
The 16 bit wide immediate addressing mode is a construct to simplify assembler code. Instructions which
offer this mode are translated into two opcodes using the eight bit wide immediate addressing mode.
RD = RD ∗ IMM16
Examples:
LDW
ADD
10.8.1.7
R4,#$1234
R4,#$5678
; translated to LDL R4,#$34; LDH R4,#$12
; translated to ADDL R4,#$78; ADDH R4,#$56
Monadic Addressing (MON)
In this addressing mode only one operand is explicitly given. This operand can either be the source (f(RD)),
the target (RD = f()), or both source and target of the operation (RD = f(RD)).
Examples:
JAL
SIF
R1
R2
; PC = R1, R1 = PC+2
; Trigger IRQ associated with the channel number in R2.L
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10.8.1.8
Dyadic Addressing (DYA)
In this mode the result of an operation between two registers is stored in one of the registers used as
operands.
RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS
the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the
destination register, only the condition code flags are updated. This addressing mode is used only for shift
operations with a variable shift value
Examples:
LSL
LSR
10.8.1.9
R4,R5
R4,R5
; R4 = R4 << R5
; R4 = R4 >> R5
Triadic Addressing (TRI)
In this mode the result of an operation between two or three registers is stored into a third one.
RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the
8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code
flags are updated. This addressing mode is used for all arithmetic and logical operations.
Examples:
ADC
SUB
R5,R6,R7
R5,R6,R7
; R5 = R6 + R7 + Carry
; R5 = R6 - R7
10.8.1.10 Relative Addressing 9-Bit Wide (REL9)
A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for
conditional branch instructions.
Examples:
BCC
BEQ
REL9
REL9
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL9 << 1)
10.8.1.11 Relative Addressing 10-Bit Wide (REL10)
An 10-bit signed word address offset is included in the instruction word. This addressing mode is used for
the unconditional branch instruction.
Examples:
BRA
REL10
; PC = PC + 2 + (REL10 << 1)
10.8.1.12 Index Register plus Immediate Offset (IDO5)
(RS, #OFFS5) provides an unsigned offset from the base register.
Examples:
LDB
STW
R4,(R1,#OFFS5)
R4,(R1,#OFFS5)
; loads a byte from (R1+OFFS5) into R4
; stores R4 as a word to (R1+OFFS5)
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10.8.1.13 Index Register plus Register Offset (IDR)
For load and store instructions (RS, RI) provides a variable offset in a register.
Examples:
LDB
STW
R4,(R1,R2)
R4,(R1,R2)
; loads a byte from (R1+R2) into R4
; stores R4 as a word to (R1+R2)
10.8.1.14 Index Register plus Register Offset with Post-increment (IDR+)
[RS, RI+] provides a variable offset in a register, which is incremented after accessing the memory. In case
of a byte access the index register will be incremented by one. In case of a word access it will be
incremented by two.
Examples:
LDB
STW
R4,(R1,R2+)
R4,(R1,R2+)
; loads a byte from (R1+R2) into R4, R2+=1
; stores R4 as a word to (R1+R2), R2+=2
10.8.1.15 Index Register plus Register Offset with Pre-decrement (–IDR)
[RS, -RI] provides a variable offset in a register, which is decremented before accessing the memory. In
case of a byte access the index register will be decremented by one. In case of a word access it will be
decremented by two.
Examples:
LDB
STW
10.8.2
R4,(R1,-R2)
R4,(R1,-R2)
; R2 -=1, loads a byte from (R1+R2) into R4
; R2 -=2, stores R4 as a word to (R1+R2)
Instruction Summary and Usage
10.8.2.1
Load & Store Instructions
Any register can be loaded either with an immediate or from the address space using indexed addressing
modes.
LDL
LDW
RD,#IMM8
RD,(RB,RI)
; loads an immediate 8 bit value to the lower byte of RD
; loads data using RB+RI as effective address
LDB
RD,(RB, RI+)
; loads data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation
The same set of modes is available for the store instructions
STB
RS,(RB, RI)
; stores data using RB+RI as effective address
STW
RS,(RB, RI+)
; stores data using RB+RI as effective address
; followed by an increment of RI depending on
; the size of the operation.
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10.8.2.2
Logic and Arithmetic Instructions
All logic and arithmetic instructions support the 8 bit immediate addressing mode (IMM8: RD = RD ∗
#IMM8) and the triadic addressing mode (TRI: RD = RS1 ∗ RS2).
All arithmetic is considered as signed, sign, overflow, zero and carry flag will be updated. The carry will
not be affected for logical operations.
ADDL
ANDH
R2,#1
R4,#$FE
; increment R2
; R4.H = R4.H & $FE, clear lower bit of higher byte
ADD
SUB
R3,R4,R5
R3,R4,R5
; R3 = R4 + R5
; R3 = R4 - R5
AND
OR
R3,R4,R5
R3,R4,R5
; R3 = R4 & R5 logical AND on the whole word
; R3 = R4 | R5
10.8.2.3
Register – Register Transfers
This group comprises transfers from and to some special registers
TFR
R3,CCR
; transfers the condition code register to the low byte of
; register R3
Branch Instructions
The branch offset is +255 words or -256 words counted from the beginning of the next instruction. Since
instructions have a fixed 16 bit width, the branch offsets are word aligned by shifting the offset value by 2.
BEQ
label
; if Z flag = 1 branch to label
An unconditional branch allows a +511 words or -512 words branch distance.
BRA
10.8.2.4
label
Shift Instructions
Shift operations allow the use of a 4 bit wide immediate value to identify a shift width within a 16 bit word.
For shift operations a value of 0 does not shift at all, while a value of 15 shifts the register RD by 15 bits.
In a second form the shift value is contained in the bits 3:0 of the register RS.
Examples:
LSL
LSR
ASR
R4,#1
R4,#3
R4,R2
; R4 = R4 << 1; shift register R4 by 1 bit to the left
; R4 = R4 >> 3; shift register R4 by 3 bits to the right
; R4 = R4 >> R2;arithmetic shift register R4 right by the amount
;
of bits contained in R2[3:0].
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10.8.2.5
Bit Field Operations
This addressing mode is used to identify the position and size of a bit field for insertion or extraction. The
width and offset are coded in the lower byte of the source register 2, RS2. The content of the upper byte is
ignored. An offset of 0 denotes the right most position and a width of 0 denotes 1 bit. These instructions
are very useful to extract, insert, clear, set or toggle portions of a 16 bit word
7
4 3
W4
O4
5
2
W4=3, O4=2
15
0
RS2
0
RS1
Bit Field Extract
Bit Field Insert
15
3
0
RD
Figure 10-26. Bit Field Addressing
BFEXT
10.8.2.6
R3,R4,R5 ; R5: W4+1 bits with offset O4, will be extracted from R4 into R3
Special Instructions for DMA Usage
The XGATE offers a number of additional instructions for flag manipulation, program flow control and
debugging:
1. SIF: Set a channel interrupt flag
2. SSEM: Test and set a hardware semaphore
3. CSEM: Clear a hardware semaphore
4. BRK: Software breakpoint
5. NOP: No Operation
6. RTS: Terminate the current thread
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10.8.3
Cycle Notation
Table 10-22 show the XGATE access detail notation. Each code letter equals one XGATE cycle. Each
letter implies additional wait cycles if memories or peripherals are not accessible. Memories or peripherals
are not accessible if they are blocked by the S12X_CPU. In addition to this Peripherals are only accessible
every other XGATE cycle. Uppercase letters denote 16 bit operations. Lowercase letters denote 8 bit
operations. The XGATE is able to perform two bus or wait cycles per S12X_CPU cycle.
Table 10-22. Access Detail Notation
V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
r — 8 bit data read: lasts for at least one RISC core cycle
R — 16 bit data read: lasts for at least one RISC core cycle
w — 8 bit data write: lasts for at least one RISC core cycle
W — 16 bit data write: lasts for at least one RISC core cycle
A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
f — Free cycle: no read or write, lasts for one RISC core cycles
Special Cases
PP/P — Branch: PP if branch taken, P if not
10.8.4
Thread Execution
When the RISC core is triggered by an interrupt request (see Figure 10-1) it first executes a vector fetch
sequence which performs three bus accesses:
1. A V-cycle to fetch the initial content of the program counter.
2. A V-cycle to fetch the initial content of the data segment pointer (R1).
3. A P-cycle to load the initial opcode.
Afterwards a sequence of instructions (thread) is executed which is terminated by an "RTS" instruction. If
further interrupt requests are pending after a thread has been terminated, a new vector fetch will be
performed. Otherwise the RISC core will either resume a previous thread (beginning with a P-cycle to
refetch the interrupted opcode) or it will become idle until a new interrupt request is received. A thread can
only be interrupted by an interrupt request of higher priority.
10.8.5
Instruction Glossary
This section describes the XGATE instruction set in alphabetical order.
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ADC
ADC
Add with Carry
Operation
RS1 + RS2 + C ⇒ RD
Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary
addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the
previous operation allowing 32 and more bit additions.
Example:
ADD
ADC
BCC
R6,R2,R2
R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2
; conditional branch on 32 bit addition
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Set if bit 15 of the result is set; cleared otherwise.
Z:
Set if the result is $0000 and Z was set before this operation; cleared otherwise.
V:
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new
C:
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new
Code and CPU Cycles
Source Form
ADC RD, RS1, RS2
Address
Mode
TRI
Machine Code
0
0
0
1
1
RD
RS1
Cycles
RS2
1
1
P
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ADD
ADD
Add without Carry
Operation
RS1 + RS2 ⇒ RD
RD + IMM16 ⇒ RD (translates to ADDL RD, #IMM16[7:0]; ADDH RD, #IMM16[15:8])
Performs a 16 bit addition and stores the result in the destination register RD.
NOTE
When using immediate addressing mode (ADD RD, #IMM16), the V-flag
and the C-Flag of the first instruction (ADDL RD, #IMM16[7:0]) are not
considered by the second instruction (ADDH RD, #IMM16[15:8]).
⇒ Don’t rely on the V-Flag if RD + IMM16[7:0] ≥ 215.
⇒ Don’t rely on the C-Flag if RD + IMM16[7:0] ≥ 216.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new
Refer to ADDH instruction for #IMM16 operations.
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new
Refer to ADDH instruction for #IMM16 operations.
Code and CPU Cycles
Source Form
Address
Mode
Machine Code
RS1
Cycles
ADD RD, RS1, RS2
TRI
0
0
0
1
1
RD
RS2
1
0
P
ADD RD, #IMM16
IMM8
1
1
1
0
0
RD
IMM16[7:0]
P
IMM8
1
1
1
0
1
RD
IMM16[15:8]
P
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ADDH
ADDH
Add Immediate 8 bit Constant
(High Byte)
Operation
RD + IMM8:$00 ⇒ RD
Adds the content of high byte of register RD and a signed immediate 8 bit constant using binary addition
and stores the result in the high byte of the destination register RD. This instruction can be used after an
ADDL for a 16 bit immediate addition.
Example:
ADDL
ADDH
R2,#LOWBYTE
R2,#HIGHBYTE
; R2 = R2 + 16 bit immediate
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old & IMM8[7] & RD[15]new | RD[15]old & IMM8[7] & RD[15]new
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]old & IMM8[7] | RD[15]old & RD[15]new | IMM8[7] & RD[15]new
Code and CPU Cycles
Source Form
ADDH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
1
1
0
1
RD
Cycles
IMM8
P
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ADDL
Add Immediate 8 bit Constant
(Low Byte)
ADDL
Operation
RD + $00:IMM8 ⇒ RD
Adds the content of register RD and an unsigned immediate 8 bit constant using binary addition and stores
the result in the destination register RD. This instruction must be used first for a 16 bit immediate addition
in conjunction with the ADDH instruction.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
RD[15]old & RD[15]new
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]old & RD[15]new
Code and CPU Cycles
Source Form
ADDL RD, #IMM8
Address
Mode
IMM8
Machine Code
1
1
1
0
0
RD
Cycles
IMM8
P
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AND
AND
Logical AND
Operation
RS1 & RS2 ⇒ RD
RD & IMM16 ⇒ RD (translates to ANDL RD, #IMM16[7:0]; ANDH RD, #IMM16[15:8])
Performs a bit wise logical AND of two 16 bit values and stores the result in the destination register RD.
NOTE
When using immediate addressing mode (AND RD, #IMM16), the Z-flag
of the first instruction (ANDL RD, #IMM16[7:0]) is not considered by the
second instruction (ANDH RD, #IMM16[15:8]).
⇒ Don’t rely on the Z-Flag.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to ANDH instruction for #IMM16 operations.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
AND RD, RS1, RS2
AND RD, #IMM16
Address
Mode
Machine Code
RS1
Cycles
TRI
0
0
0
1
0
RD
RS2
0
0
P
IMM8
1
0
0
0
0
RD
IMM16[7:0]
P
IMM8
1
0
0
0
1
RD
IMM16[15:8]
P
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ANDH
Logical AND Immediate 8 bit Constant
(High Byte)
ANDH
Operation
RD.H & IMM8 ⇒ RD.H
Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant and
stores the result in the destination register RD.H. The low byte of RD is not affected.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
ANDH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
0
0
1
RD
Cycles
IMM8
P
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ANDL
Logical AND Immediate 8 bit Constant
(Low Byte)
ANDL
Operation
RD.L & IMM8 ⇒ RD.L
Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant and
stores the result in the destination register RD.L. The high byte of RD is not affected.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 7 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
ANDL RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
0
0
0
RD
Cycles
IMM8
P
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ASR
ASR
Arithmetic Shift Right
Operation
n
b15
RD
C
n = RS or IMM4
Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled
with the sign bit (RD[15]). The carry flag will be updated to the bit contained in RD[n-1] before the shift
for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old ^ RD[15]new
Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
ASR RD, #IMM4
ASR RD, RS
Address
Mode
Machine Code
IMM4
0
0
0
0
1
RD
IMM4
DYA
0
0
0
0
1
RD
RS
Cycles
1
1
0
0
1
P
0
0
0
1
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BCC
BCC
Branch if Carry Cleared
(Same as BHS)
Operation
If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the Carry flag and branches if C = 0.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BCC REL9
Address
Mode
REL9
Machine Code
0
0
1
0
0
0
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BCS
BCS
Branch if Carry Set
(Same as BLO)
Operation
If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the Carry flag and branches if C = 1.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BCS REL9
Address
Mode
REL9
Machine Code
0
0
1
0
0
0
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BEQ
BEQ
Branch if Equal
Operation
If Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the Zero flag and branches if Z = 1.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BEQ REL9
Address
Mode
REL9
Machine Code
0
0
1
0
0
1
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BFEXT
BFEXT
Bit Field Extract
Operation
RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)]
w = (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD.
The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
15
7
4
3
0
W4
15
O4
5
RS2
2
0
W4=3, O4=2
RS1
Bit Field Extract
15
3
0
0
RD
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
BFEXT RD, RS1, RS2
Address
Mode
TRI
Machine Code
0
1
1
0
0
RD
RS1
Cycles
RS2
1
1
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Chapter 10 XGATE (S12XGATEV3)
BFFO
BFFO
Bit Field Find First One
Operation
FirstOne(RS) ⇒ RD;
Searches the first “1” in register RS (from MSB to LSB) and writes the bit position into the destination
register RD. The upper bits of RD are cleared. In case the content of RS is equal to $0000, RD will be
cleared and the carry flag will be set. This is used to distinguish a “1” in position 0 versus no “1” in the
whole RS register at all.
CCR Effects
N
Z
V
C
0
∆
0
∆
N:
Z:
V:
C:
1
0; cleared.
Set if the result is $0000; cleared otherwise.
0; cleared.
Set if RS = $00001; cleared otherwise.
Before executing the instruction
Code and CPU Cycles
Source Form
BFFO RD, RS
Address
Mode
DYA
Machine Code
0
0
0
0
1
RD
RS
Cycles
1
0
0
0
0
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Chapter 10 XGATE (S12XGATEV3)
BFINS
BFINS
Bit Field Insert
Operation
RS1[w:0] ⇒ RD[(w+o):o];
w = (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position 0 and writes them into register RD starting at
position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using R0
as a RS1, this command can be used to clear bits.
15
7
4
3
0
W4
O4
15
RS2
3
0
RS1
Bit Field Insert
15
5
2
0
W4=3, O4=2
RD
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
BFINS RD, RS1, RS2
Address
Mode
TRI
Machine Code
0
1
1
0
1
RD
RS1
Cycles
RS2
1
1
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Chapter 10 XGATE (S12XGATEV3)
BFINSI
BFINSI
Bit Field Insert and Invert
Operation
!RS1[w:0] ⇒ RD[w+o:o];
w = (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD starting
at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using
R0 as a RS1, this command can be used to set bits.
15
7
4
3
0
W4
O4
15
3
RS2
0
RS1
Inverted Bit Field Insert
15
5
2
0
W4=3, O4=2
RD
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
BFINSI RD, RS1, RS2
Address
Mode
TRI
Machine Code
0
1
1
1
0
RD
RS1
Cycles
RS2
1
1
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Chapter 10 XGATE (S12XGATEV3)
BFINSX
BFINSX
Bit Field Insert and XNOR
Operation
!(RS1[w:0] ^ RD[w+o:o]) ⇒ RD[w+o:o];
w = (RS2[7:4])
o = (RS2[3:0])
Extracts w+1 bits from register RS1 starting at position 0, performs an XNOR with RD[w+o:o] and writes
the bits back to RD. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored.
Using R0 as a RS1, this command can be used to toggle bits.
15
7
4
3
0
W4
O4
15
3
RS2
0
RS1
Bit Field Insert XNOR
15
5
2
0
W4=3, O4=2
RD
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
BFINSX RD, RS1, RS2
Address
Mode
TRI
Machine Code
0
1
1
1
1
RD
RS1
Cycles
RS2
1
1
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Chapter 10 XGATE (S12XGATEV3)
BGE
BGE
Branch if Greater than or Equal to Zero
Operation
If N ^ V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare signed numbers.
Branch if RS1 ≥ RS2:
SUB
BGE
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BGE REL9
Address
Mode
REL9
Machine Code
0
0
1
1
0
1
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BGT
BGT
Branch if Greater than Zero
Operation
If Z | (N ^ V) = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare signed numbers.
Branch if RS1 > RS2:
SUB
BGT
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BGT REL9
Address
Mode
REL9
Machine Code
0
0
1
1
1
0
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BHI
BHI
Branch if Higher
Operation
If C | Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare unsigned numbers.
Branch if RS1 > RS2:
SUB
BHI
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BHI REL9
Address
Mode
REL9
Machine Code
0
0
1
1
0
0
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BHS
BHS
Branch if Higher or Same
(Same as BCC)
Operation
If C = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare unsigned numbers.
Branch if RS1 ≥ RS2:
SUB
BHS
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BHS REL9
Address
Mode
REL9
Machine Code
0
0
1
0
0
0
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BITH
BITH
Bit Test Immediate 8 bit Constant
(High Byte)
Operation
RD.H & IMM8 ⇒ NONE
Performs a bit wise logical AND between the high byte of register RD and an immediate 8 bit constant.
Only the condition code flags get updated, but no result is written back.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
BITH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
0
1
1
RD
Cycles
IMM8
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Chapter 10 XGATE (S12XGATEV3)
BITL
BITL
Bit Test Immediate 8 bit Constant
(Low Byte)
Operation
RD.L & IMM8 ⇒ NONE
Performs a bit wise logical AND between the low byte of register RD and an immediate 8 bit constant.
Only the condition code flags get updated, but no result is written back.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 7 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
BITL RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
0
1
0
RD
Cycles
IMM8
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Chapter 10 XGATE (S12XGATEV3)
BLE
BLE
Branch if Less or Equal to Zero
Operation
If Z | (N ^ V) = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare signed numbers.
Branch if RS1 ≤ RS2:
SUB
BLE
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BLE REL9
Address
Mode
REL9
Machine Code
0
0
1
1
1
0
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BLO
BLO
Branch if Carry Set
(Same as BCS)
Operation
If C = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare unsigned numbers.
Branch if RS1 < RS2:
SUB
BLO
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BLO REL9
Address
Mode
REL9
Machine Code
0
0
1
0
0
0
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BLS
BLS
Branch if Lower or Same
Operation
If C | Z = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare unsigned numbers.
Branch if RS1 ≤ RS2:
SUB
BLS
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BLS REL9
Address
Mode
REL9
Machine Code
0
0
1
1
0
0
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BLT
BLT
Branch if Lower than Zero
Operation
If N ^ V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Branch instruction to compare signed numbers.
Branch if RS1 < RS2:
SUB
BLT
R0,RS1,RS2
REL9
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BLT REL9
Address
Mode
REL9
Machine Code
0
0
1
1
0
1
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BMI
BMI
Branch if Minus
Operation
If N = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the sign flag and branches if N = 1.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BMI REL9
Address
Mode
REL9
Machine Code
0
0
1
0
1
0
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BNE
BNE
Branch if Not Equal
Operation
If Z = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the Zero flag and branches if Z = 0.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BNE REL9
Address
Mode
REL9
Machine Code
0
0
1
0
0
1
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BPL
BPL
Branch if Plus
Operation
If N = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the Sign flag and branches if N = 0.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BPL REL9
Address
Mode
REL9
Machine Code
0
0
1
0
1
0
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BRA
BRA
Branch Always
Operation
PC + $0002 + (REL10 << 1) ⇒ PC
Branches always.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BRA REL10
Address
Mode
REL10
Machine Code
0
0
1
1
1
1
Cycles
REL10
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Chapter 10 XGATE (S12XGATEV3)
BRK
BRK
Break
Operation
Put XGATE into Debug Mode (see Section 10.6.1.0.1, “Entering Debug Mode”) and signals a software
breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section).
NOTE
It is not possible to single step over a BRK instruction. This instruction does
not advance the program counter.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BRK
Address
Mode
INH
Machine Code
0
0
0
0
0
0
0
0
0
0
Cycles
0
0
0
0
0
0
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Chapter 10 XGATE (S12XGATEV3)
BVC
BVC
Branch if Overflow Cleared
Operation
If V = 0, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the Overflow flag and branches if V = 0.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BVC REL9
Address
Mode
REL9
Machine Code
0
0
1
0
1
1
0
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
BVS
BVS
Branch if Overflow Set
Operation
If V = 1, then PC + $0002 + (REL9 << 1) ⇒ PC
Tests the Overflow flag and branches if V = 1.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
BVS REL9
Address
Mode
REL9
Machine Code
0
0
1
0
1
1
1
Cycles
REL9
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Chapter 10 XGATE (S12XGATEV3)
CMP
CMP
Compare
Operation
RS1 – RS2
⇒ NONE (translates to SUB R0, RS1, RS2)
RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8])
Subtracts two 16 bit values and discards the result.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]
RD[15] & IMM16[15] & result[15] | RD[15] & IMM16[15] & result[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]
RD[15] & IMM16[15] | RD[15] & result[15] | IMM16[15] & result[15]
Code and CPU Cycles
Source Form
CMP RS1, RS2
CMP RS, #IMM16
Address
Mode
Machine Code
0
0
0
RS1
Cycles
TRI
0
0
0
1
1
RS2
0
0
P
IMM8
1
1
0
1
0
RS
IMM16[7:0]
P
IMM8
1
1
0
1
1
RS
IMM16[15:8]
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Chapter 10 XGATE (S12XGATEV3)
CMPL
Compare Immediate 8 bit Constant
(Low Byte)
CMPL
Operation
RS.L – IMM8 ⇒ NONE, only condition code flags get updated
Subtracts the 8 bit constant IMM8 contained in the instruction code from the low byte of the source register
RS.L using binary subtraction and updates the condition code register accordingly.
Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers
can be performed by using the subtract instruction with R0 as destination register.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 7 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
RS[7] & IMM8[7] & result[7] | RS[7] & IMM8[7] & result[7]
Set if there is a carry from the Bit 7 to Bit 8 of the result; cleared otherwise.
RS[7] & IMM8[7] | RS[7] & result[7] | IMM8[7] & result[7]
Code and CPU Cycles
Source Form
CMPL RS, #IMM8
Address
Mode
IMM8
Machine Code
1
1
0
1
0
RS
Cycles
IMM8
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Chapter 10 XGATE (S12XGATEV3)
COM
COM
One’s Complement
Operation
~RS ⇒ RD (translates to XNOR RD, R0, RS)
~RD ⇒ RD (translates to XNOR RD, R0, RD)
Performs a one’s complement on a general purpose register.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
Address
Mode
Machine Code
Cycles
COM RD, RS
TRI
0
0
0
1
0
RD
0
0
0
RS
1
1
P
COM RD
TRI
0
0
0
1
0
RD
0
0
0
RD
1
1
P
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CPC
CPC
Compare with Carry
Operation
RS1 – RS2 - C ⇒ NONE (translates to SBC R0, RS1, RS2)
Subtracts the carry bit and the content of register RS2 from the content of register RS1 using binary
subtraction and discards the result.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]
Code and CPU Cycles
Source Form
CPC RS1, RS2
Address
Mode
TRI
Machine Code
0
0
0
1
1
0
0
0
RS1
Cycles
RS2
0
1
P
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Chapter 10 XGATE (S12XGATEV3)
CPCH
CPCH
Compare Immediate 8 bit Constant with
Carry (High Byte)
Operation
RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated
Subtracts the carry bit and the 8 bit constant IMM8 contained in the instruction code from the high byte of
the source register RD using binary subtraction and updates the condition code register accordingly. The
carry bit and Zero bits are taken into account to allow a 16 bit compare in the form of
CMPL
CPCH
BCC
R2,#LOWBYTE
R2,#HIGHBYTE
; branch condition
Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers
can be performed by using the subtract instruction with R0 as destination register.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $00 and Z was set before this operation; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & IMM8[7] & result[15] | RS[15] & IMM8[7] & result[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS[15] & IMM8[7] | RS[15] & result[15] | IMM8[7] & result[15]
Code and CPU Cycles
Source Form
CPCH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
1
0
1
1
RS
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
CSEM
CSEM
Clear Semaphore
Operation
Unlocks a semaphore that was locked by the RISC core.
In monadic address mode, bits RS[2:0] select the semaphore to be cleared.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
Address
Mode
Machine Code
Cycles
CSEM #IMM3
IMM3
0
0
0
0
0
IMM3
1
1
1
1
0
0
0
0
PA
CSEM RS
MON
0
0
0
0
0
RS
1
1
1
1
0
0
0
1
PA
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CSL
CSL
Logical Shift Left with Carry
Operation
n
C
RD
C
C
C
C
n bits
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old ^ RD[15]new
Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
CSL RD, #IMM4
CSL RD, RS
Address
Mode
Machine Code
IMM4
0
0
0
0
1
RD
IMM4
DYA
0
0
0
0
1
RD
RS
Cycles
1
1
0
1
0
P
0
0
1
0
P
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CSR
CSR
Logical Shift Right with Carry
Operation
n
C
C
C
C
RD
C
n bits
n = RS or IMM4
Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled
with the carry flag. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 if IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old ^ RD[15]new
Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
CSR RD, #IMM4
CSR RD, RS
Address
Mode
Machine Code
IMM4
0
0
0
0
1
RD
IMM4
DYA
0
0
0
0
1
RD
RS
Cycles
1
1
0
1
1
P
0
0
1
1
P
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JAL
JAL
Jump and Link
Operation
PC + $0002 ⇒ RD; RD ⇒ PC
Jumps to the address stored in RD and saves the return address in RD.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
JAL RD
Address
Mode
MON
Machine Code
0
0
0
0
0
RD
1
1
Cycles
1
1
0
1
1
0
PP
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Chapter 10 XGATE (S12XGATEV3)
LDB
LDB
Load Byte from Memory
(Low Byte)
Operation
M[RB, #OFFS5]
M[RB, RI]
M[RB, RI]
RI-1
⇒ RD.L;
⇒ RD.L;
⇒ RD.L;
⇒ RI;
$00
⇒ RD.H
$00
⇒ RD.H
$00
⇒ RD.H;
M[RS, RI] ⇒ RD.L;
RI+1 ⇒ RI;1
$00 ⇒ RD.H
Loads a byte from memory into the low byte of register RD. The high byte is cleared.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
LDB RD, (RB, #OFFS5)
Address
Mode
Machine Code
Cycles
IDO5
0
1
0
0
0
RD
RB
OFFS5
Pr
LDB RD, (RS, RI)
IDR
0
1
1
0
0
RD
RB
RI
0
0
Pr
LDB RD, (RS, RI+)
IDR+
0
1
1
0
0
RD
RB
RI
0
1
Pr
LDB RD, (RS, -RI)
-IDR
0
1
1
0
0
RD
RB
RI
1
0
Pr
1.If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not
be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H
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Chapter 10 XGATE (S12XGATEV3)
LDH
LDH
Load Immediate 8 bit Constant
(High Byte)
Operation
IMM8 ⇒ RD.H;
Loads an 8 bit immediate constant into the high byte of register RD. The low byte is not affected.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
LDH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
1
1
1
1
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
LDL
LDL
Load Immediate 8 bit Constant
(Low Byte)
Operation
IMM8 ⇒ RD.L; $00 ⇒ RD.H
Loads an 8 bit immediate constant into the low byte of register RD. The high byte is cleared.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
LDL RD, #IMM8
Address
Mode
IMM8
Machine Code
1
1
1
1
0
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
LDW
LDW
Load Word from Memory
Operation
M[RB, #OFFS5]
M[RB, RI]
M[RB, RI]
RI-2
IMM16
⇒ RD
⇒ RD
⇒ RD;
RI+2
⇒ RI1
⇒ RI;
M[RS, RI] ⇒ RD
⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8])
Loads a 16 bit value into the register RD.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
LDW RD, (RB, #OFFS5)
Address
Mode
Machine Code
Cycles
IDO5
0
1
0
0
1
RD
RB
OFFS5
PR
LDW RD, (RB, RI)
IDR
0
1
1
0
1
RD
RB
RI
0
0
PR
LDW RD, (RB, RI+)
IDR+
0
1
1
0
1
RD
RB
RI
0
1
PR
LDW RD, (RB, -RI)
-IDR
0
1
1
0
1
RD
RB
RI
1
0
PR
LDW RD, #IMM16
IMM8
1
1
1
1
0
RD
IMM16[7:0]
P
IMM8
1
1
1
1
1
RD
IMM16[15:8]
P
1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be
incremented after the data move: M[RB, RI] ⇒ RD
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Chapter 10 XGATE (S12XGATEV3)
LSL
LSL
Logical Shift Left
Operation
n
C
RD
0
0
0
0
n bits
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old ^ RD[15]new
Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
LSL RD, #IMM4
LSL RD, RS
Address
Mode
Machine Code
IMM4
0
0
0
0
1
RD
IMM4
DYA
0
0
0
0
1
RD
RS
Cycles
1
1
1
0
0
P
0
1
0
0
P
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Chapter 10 XGATE (S12XGATEV3)
LSR
LSR
Logical Shift Right
Operation
n
0
0
0
0
RD
C
n bits
n = RS or IMM4
Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled
with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old ^ RD[15]new
Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Code and CPU Cycles
Source Form
LSR RD, #IMM4
LSR RD, RS
Address
Mode
Machine Code
IMM4
0
0
0
0
1
RD
IMM4
DYA
0
0
0
0
1
RD
RS
Cycles
1
1
1
0
1
P
0
1
0
1
P
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MOV
MOV
Move Register Content
Operation
RS ⇒ RD (translates to OR RD, R0, RS)
Copies the content of RS to RD.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
MOV RD, RS
Address
Mode
TRI
Machine Code
0
0
0
1
0
RD
0
0
Cycles
0
RS
1
0
P
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Chapter 10 XGATE (S12XGATEV3)
NEG
NEG
Two’s Complement
Operation
–RS ⇒ RD (translates to SUB RD, R0, RS)
–RD ⇒ RD (translates to SUB RD, R0, RD)
Performs a two’s complement on a general purpose register.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & RD[15]new
Set if there is a carry from the bit 15 of the result; cleared otherwise
RS[15] | RD[15]new
Code and CPU Cycles
Source Form
Address
Mode
Machine Code
Cycles
NEG RD, RS
TRI
0 0 0 1 1
RD
0 0 0
RS
0 0
P
NEG RD
TRI
0 0 0 1 1
RD
0 0 0
RD
0 0
P
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Chapter 10 XGATE (S12XGATEV3)
NOP
NOP
No Operation
Operation
No Operation for one cycle.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
NOP
Address
Mode
INH
Machine Code
0
0
0
0
0
0
0
1
0
0
Cycles
0
0
0
0
0
0
P
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Chapter 10 XGATE (S12XGATEV3)
OR
OR
Logical OR
Operation
RS1 | RS2 ⇒ RD
RD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8]
Performs a bit wise logical OR between two 16 bit values and stores the result in the destination
register RD.
NOTE
When using immediate addressing mode (OR RD, #IMM16), the Z-flag of
the first instruction (ORL RD, #IMM16[7:0]) is not considered by the
second instruction (ORH RD, #IMM16[15:8]).
⇒ Don’t rely on the Z-Flag.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to ORH instruction for #IMM16 operations.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
OR RD, RS1, RS2
OR RD, #IMM16
Address
Mode
Machine Code
RS1
Cycles
TRI
0
0
0
1
0
RD
RS2
1
0
P
IMM8
1
0
1
0
0
RD
IMM16[7:0]
P
IMM8
1
0
1
0
1
RD
IMM16[15:8]
P
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Chapter 10 XGATE (S12XGATEV3)
ORH
ORH
Logical OR Immediate 8 bit Constant
(High Byte)
Operation
RD.H | IMM8 ⇒ RD.H
Performs a bit wise logical OR between the high byte of register RD and an immediate 8 bit constant and
stores the result in the destination register RD.H. The low byte of RD is not affected.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
ORH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
1
0
1
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
ORL
ORL
Logical OR Immediate 8 bit Constant
(Low Byte)
Operation
RD.L | IMM8 ⇒ RD.L
Performs a bit wise logical OR between the low byte of register RD and an immediate 8 bit constant and
stores the result in the destination register RD.L. The high byte of RD is not affected.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 7 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
ORL RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
1
0
0
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
PAR
PAR
Calculate Parity
Operation
Calculates the number of ones in the register RD. The Carry flag will be set if the number is odd, otherwise
it will be cleared.
CCR Effects
N
Z
V
C
0
∆
0
∆
N:
Z:
V:
C:
0; cleared.
Set if RD is $0000; cleared otherwise.
0; cleared.
Set if the number of ones in the register RD is odd; cleared otherwise.
Code and CPU Cycles
Source Form
PAR, RD
Address
Mode
MON
Machine Code
0
0
0
0
0
RD
1
1
Cycles
1
1
0
1
0
1
P
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Chapter 10 XGATE (S12XGATEV3)
ROL
ROL
Rotate Left
Operation
RD
n bits
n = RS or IMM4
Rotates the bits in register RD n positions to the left. The lower n bits of the register RD are filled with the
upper n bits. Two source forms are available. In the first form, the parameter n is contained in the
instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits
of the source register RS[3:0]. All other bits in RS are ignored. If n is zero, no shift will take place and the
register RD will be unaffected; however, the condition code flags will be updated.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
ROL RD, #IMM4
ROL RD, RS
Address
Mode
Machine Code
IMM4
0
0
0
0
1
RD
IMM4
DYA
0
0
0
0
1
RD
RS
Cycles
1
1
1
1
0
P
0
1
1
0
P
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Chapter 10 XGATE (S12XGATEV3)
ROR
ROR
Rotate Right
Operation
RD
n bits
n = RS or IMM4
Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with
the lower n bits. Two source forms are available. In the first form, the parameter n is contained in the
instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits
of the source register RS[3:0]. All other bits in RS are ignored. If n is zero no shift will take place and the
register RD will be unaffected; however, the condition code flags will be updated.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
ROR RD, #IMM4
ROR RD, RS
Address
Mode
Machine Code
IMM4
0
0
0
0
1
RD
IMM4
DYA
0
0
0
0
1
RD
RS
Cycles
1
1
1
1
1
P
0
1
1
1
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RTS
RTS
Return to Scheduler
Operation
Terminates the current thread of program execution.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
RTS
Address
Mode
INH
Machine Code
0
0
0
0
0
0
1
0
0
0
Cycles
0
0
0
0
0
0
PA
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Chapter 10 XGATE (S12XGATEV3)
SBC
SBC
Subtract with Carry
Operation
RS1 - RS2 - C ⇒ RD
Subtracts the content of register RS2 and the value of the Carry bit from the content of register RS1 using
binary subtraction and stores the result in the destination register RD. Also the zero flag is carried forward
from the previous operation allowing 32 and more bit subtractions.
Example:
SUB
SBC
BCC
R6,R4,R2
R7,R5,R3
; R7:R6 = R5:R4 - R3:R2
; conditional branch on 32 bit subtraction
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000 and Z was set before this operation; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new
Code and CPU Cycles
Source Form
SBC RD, RS1, RS2
Address
Mode
TRI
Machine Code
0
0
0
1
1
RD
RS1
Cycles
RS2
0
1
P
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Chapter 10 XGATE (S12XGATEV3)
SEX
SEX
Sign Extend Byte to Word
Operation
The result in RD is the 16 bit sign extended representation of the original two’s complement number in the
low byte of RD.L.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
SEX RD
Address
Mode
MON
Machine Code
0
0
0
0
0
RD
1
1
Cycles
1
1
0
1
0
0
P
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Chapter 10 XGATE (S12XGATEV3)
SIF
SIF
Set Interrupt Flag
Operation
Sets the interrupt flag of an XGATE channel (XGIF). This instruction supports two source forms. If
inherent address mode is used, then the interrupt flag of the current channel (XGCHID) will be set. If the
monadic address form is used, the interrupt flag associated with the channel id number contained in
RS[6:0] is set. The content of RS[15:7] is ignored.
NOTE
Interrupt flags of reserved channels (see Device User Guide) can’t be set.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
SIF
SIF RS
Address
Mode
Machine Code
INH
0
0
0
0
0
MON
0
0
0
0
0
0
1
RS
1
Cycles
0
0
0
0
0
0
0
0
PA
1
1
1
1
0
1
1
1
PA
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Chapter 10 XGATE (S12XGATEV3)
SSEM
SSEM
Set Semaphore
Operation
Attempts to set a semaphore. The state of the semaphore will be stored in the Carry-Flag:
1 = Semaphore is locked by the RISC core
0 = Semaphore is locked by the S12X_CPU
In monadic address mode, bits RS[2:0] select the semaphore to be set.
CCR Effects
N
Z
V
C
—
—
—
∆
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Set if semaphore is locked by the RISC core; cleared otherwise.
Code and CPU Cycles
Source Form
Address
Mode
Machine Code
Cycles
SSEM #IMM3
IMM3
0
0
0
0
0
IMM3
1
1
1
1
0
0
1
0
PA
SSEM RS
MON
0
0
0
0
0
RS
1
1
1
1
0
0
1
1
PA
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Chapter 10 XGATE (S12XGATEV3)
STB
STB
Store Byte to Memory
(Low Byte)
Operation
RS.L ⇒ M[RB, #OFFS5]
RS.L ⇒ M[RB, RI]
RS.L ⇒ M[RB, RI];
RI+1 ⇒ RI;
RI–1 ⇒ RI;
RS.L ⇒ M[RB, RI]1
Stores the low byte of register RS to memory.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
STB RS, (RB, #OFFS5),
Address
Mode
Machine Code
Cycles
IDO5
0
1
0
1
0
RS
RB
OFFS5
Pw
STB RS, (RB, RI)
IDR
0
1
1
1
0
RS
RB
RI
0
0
Pw
STB RS, (RB, RI+)
IDR+
0
1
1
1
0
RS
RB
RI
0
1
Pw
STB RS, (RB, -RI)
-IDR
0
1
1
1
0
RS
RB
RI
1
0
Pw
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
register is written to the memory: RS.L ⇒ M[RB, RS-1]; RS-1 ⇒ RS
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Chapter 10 XGATE (S12XGATEV3)
STW
STW
Store Word to Memory
Operation
RS ⇒ M[RB, #OFFS5]
RS ⇒ M[RB, RI]
RS ⇒ M[RB, RI];
RI+2 ⇒ RI;
RI–2 ⇒ RI;
RS ⇒ M[RB, RI]1
Stores the content of register RS to memory.
CCR Effects
N
Z
V
C
—
—
—
—
N:
Z:
V:
C:
Not affected.
Not affected.
Not affected.
Not affected.
Code and CPU Cycles
Source Form
STW RS, (RB, #OFFS5)
Address
Mode
Machine Code
Cycles
IDO5
0
1
0
1
1
RS
RB
OFFS5
PW
STW RS, (RB, RI)
IDR
0
1
1
1
1
RS
RB
RI
0
0
PW
STW RS, (RB, RI+)
IDR+
0
1
1
1
1
RS
RB
RI
0
1
PW
STW RS, (RB, -RI)
-IDR
0
1
1
1
1
RS
RB
RI
1
0
PW
1. If the same general purpose register is used as index (RI) and source register (RS), the unmodified content of the source
register is written to the memory: RS ⇒ M[RB, RS–2]; RS–2 ⇒ RS
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Chapter 10 XGATE (S12XGATEV3)
SUB
SUB
Subtract without Carry
Operation
RS1 – RS2
⇒ RD
RD − IMM16 ⇒ RD (translates to SUBL RD, #IMM16[7:0]; SUBH RD, #IMM16{15:8])
Subtracts two 16 bit values and stores the result in the destination register RD.
NOTE
When using immediate addressing mode (SUB RD, #IMM16), the V-flag
and the C-Flag of the first instruction (SUBL RD, #IMM16[7:0]) are not
considered by the second instruction (SUBH RD, #IMM16[15:8]).
⇒ Don’t rely on the V-Flag if RD - IMM16[7:0] < −215.
⇒ Don’t rely on the C-Flag if RD < IMM16[7:0].
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new
Refer to SUBH instruction for #IMM16 operations.
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new
Refer to SUBH instruction for #IMM16 operations.
Code and CPU Cycles
Source Form
SUB RD, RS1, RS2
SUB RD, #IMM16
Address
Mode
Machine Code
RS1
Cycles
TRI
0
0
0
1
1
RD
RS2
0
0
P
IMM8
1
1
0
0
0
RD
IMM16[7:0]
P
IMM8
1
1
0
0
1
RD
IMM16[15:8]
P
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Chapter 10 XGATE (S12XGATEV3)
SUBH
SUBH
Subtract Immediate 8 bit Constant
(High Byte)
Operation
RD – IMM8:$00 ⇒ RD
Subtracts a signed immediate 8 bit constant from the content of high byte of register RD and using binary
subtraction and stores the result in the high byte of destination register RD. This instruction can be used
after an SUBL for a 16 bit immediate subtraction.
Example:
SUBL
SUBH
R2,#LOWBYTE
R2,#HIGHBYTE
; R2 = R2 - 16 bit immediate
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old & IMM8[7] & RD[15]new | RD[15]old & IMM8[7] & RD[15]new
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]old & IMM8[7] | RD[15]old & RD[15]new | IMM8[7] & RD[15]new
Code and CPU Cycles
Source Form
SUBH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
1
0
0
1
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
SUBL
Subtract Immediate 8 bit Constant
(Low Byte)
SUBL
Operation
RD – $00:IMM8 ⇒ RD
Subtracts an immediate 8 bit constant from the content of register RD using binary subtraction and stores
the result in the destination register RD.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the 8 bit operation; cleared otherwise.
RD[15]old & RD[15]new
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RD[15]old & RD[15]new
Code and CPU Cycles
Source Form
SUBL RD, #IMM8
Address
Mode
IMM8
Machine Code
1
1
0
0
0
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
TFR
TFR
Transfer from and to Special Registers
Operation
TFR RD,CCR: CCR ⇒ RD[3:0]; 0 ⇒ RD[15:4]
TFR CCR,RD: RD[3:0] ⇒ CCR
TFR RD,PC:
PC+4 ⇒ RD
Transfers the content of one RISC core register to another.
The TFR RD,PC instruction can be used to implement relative subroutine calls.
Example:
RETADDR
SUBR
TFR
BRA
...
...
JAL
R7,PC
SUBR
;Return address (RETADDR) is stored in R7
;Relative branch to subroutine (SUBR)
R7
;Jump to return address (RETADDR)
CCR Effects
TFR RD,CCR, TFR RD,PC:
TFR CCR,RS:
N
Z
V
C
N
Z
V
C
—
—
—
—
∆
∆
∆
∆
Not affected.
Not affected.
Not affected.
Not affected.
N:
Z:
V:
C:
N:
Z:
V:
C:
RS[3].
RS[2].
RS[1].
RS[0].
Code and CPU Cycles
Source Form
Address
Mode
Machine Code
Cycles
TFR RD,CCR CCR ⇒ RD
MON
0
0
0
0
0
RD
1
1
1
1
1
0
0
0
P
TFR CCR,RS RS ⇒ CCR
MON
0
0
0
0
0
RS
1
1
1
1
1
0
0
1
P
TFR RD,PCPC+4 ⇒ RD
MON
0
0
0
0
0
RD
1
1
1
1
1
0
1
0
P
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TST
TST
Test Register
Operation
RS – 0 ⇒ NONE (translates to SUB R0, RS, R0)
Subtracts zero from the content of register RS using binary subtraction and discards the result.
CCR Effects
N
Z
V
C
∆
∆
∆
∆
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & result[15]
Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & result[15]
Code and CPU Cycles
Source Form
TST RS
Address
Mode
TRI
Machine Code
0
0
0
1
1
0
0
0
RS1
Cycles
0
0
0
0
0
P
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Chapter 10 XGATE (S12XGATEV3)
XNOR
XNOR
Logical Exclusive NOR
Operation
~(RS1 ^ RS2) ⇒ RD
~(RD ^ IMM16)⇒ RD
(translates to XNOR RD, #IMM16{15:8]; XNOR RD, #IMM16[7:0])
Performs a bit wise logical exclusive NOR between two 16 bit values and stores the result in the destination
register RD.
Remark: Using R0 as a source registers will calculate the one’s complement of the other source register.
Using R0 as both source operands will fill RD with $FFFF.
NOTE
When using immediate addressing mode (XNOR RD, #IMM16), the Z-flag
of the first instruction (XNORL RD, #IMM16[7:0]) is not considered by the
second instruction (XNORH RD, #IMM16[15:8]).
⇒ Don’t rely on the Z-Flag.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Refer to XNORH instruction for #IMM16 operations.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
XNOR RD, RS1, RS2
XNOR RD, #IMM16
Address
Mode
Machine Code
RS1
Cycles
TRI
0
0
0
1
0
RD
RS2
1
1
P
IMM8
1
0
1
1
0
RD
IMM16[7:0]
P
IMM8
1
0
1
1
1
RD
IMM16[15:8]
P
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Chapter 10 XGATE (S12XGATEV3)
XNORH
Logical Exclusive NOR Immediate
8 bit Constant (High Byte)
XNORH
Operation
~(RD.H ^ IMM8) ⇒ RD.H
Performs a bit wise logical exclusive NOR between the high byte of register RD and an immediate 8 bit
constant and stores the result in the destination register RD.H. The low byte of RD is not affected.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 15 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
XNORH RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
1
1
1
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
XNORL
Logical Exclusive NOR Immediate
8 bit Constant (Low Byte)
XNORL
Operation
~(RD.L ^ IMM8) ⇒ RD.L
Performs a bit wise logical exclusive NOR between the low byte of register RD and an immediate 8 bit
constant and stores the result in the destination register RD.L. The high byte of RD is not affected.
CCR Effects
N
Z
V
C
∆
∆
0
—
N:
Z:
V:
C:
Set if bit 7 of the result is set; cleared otherwise.
Set if the 8 bit result is $00; cleared otherwise.
0; cleared.
Not affected.
Code and CPU Cycles
Source Form
XNORL RD, #IMM8
Address
Mode
IMM8
Machine Code
1
0
1
1
0
RD
Cycles
IMM8
P
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Chapter 10 XGATE (S12XGATEV3)
10.8.6
Instruction Coding
Table 10-23 summarizes all XGATE instructions in the order of their machine coding.
Table 10-23. Instruction Set Summary (Sheet 1 of 3)
Functionality
Return to Scheduler and Others
BRK
NOP
RTS
SIF
Semaphore Instructions
CSEM IMM3
CSEM RS
SSEM IMM3
SSEM RS
Single Register Instructions
SEX RD
PAR RD
JAL RD
SIF RS
Special Move instructions
TFR RD,CCR
TFR CCR,RS
TFR RD,PC
Shift instructions Dyadic
BFFO RD, RS
ASR RD, RS
CSL RD, RS
CSR RD, RS
LSL RD, RS
LSR RD, RS
ROL RD, RS
ROR RD, RS
Shift instructions immediate
ASR RD, #IMM4
CSL RD, #IMM4
CSR RD, #IMM4
LSL RD, #IMM4
LSR RD, #IMM4
ROL RD, #IMM4
ROR RD, #IMM4
Logical Triadic
AND RD, RS1, RS2
OR RD, RS1, RS2
XNOR RD, RS1, RS2
Arithmetic Triadic
SUB RD, RS1, RS2
SBC RD, RS1, RS2
ADD RD, RS1, RS2
ADC RD, RS1, RS2
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IMM3
RS
IMM3
RS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RD
RD
RD
RS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RD
RS
RD
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RD
RD
RD
RD
RD
RD
RD
RD
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
RD
RD
RD
RD
RD
RD
RD
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RD
RS1
RS2
RD
RS1
RS2
RD
RS1
RS2
For compare use SUB R0,Rs1,Rs2
RD
RS1
RS2
RD
RS1
RS2
RD
RS1
RS2
RD
RS1
RS2
0
0
1
1
0
1
0
1
RS
RS
RS
RS
RS
RS
RS
RS
IMM4
IMM4
IMM4
IMM4
IMM4
IMM4
IMM4
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Chapter 10 XGATE (S12XGATEV3)
Table 10-23. Instruction Set Summary (Sheet 2 of 3)
Functionality
Branches
BCC REL9
BCS REL9
BNE REL9
BEQ REL9
BPL REL9
BMI REL9
BVC REL9
BVS REL9
BHI REL9
BLS REL9
BGE REL9
BLT REL9
BGT REL9
BLE REL9
BRA REL10
Load and Store Instructions
LDB RD, (RB, #OFFS5)
LDW RD, (RB, #OFFS5)
STB RS, (RB, #OFFS5)
STW RS, (RB, #OFFS5)
LDB RD, (RB, RI)
LDW RD, (RB, RI)
STB RS, (RB, RI)
STW RS, (RB, RI)
LDB RD, (RB, RI+)
LDW RD, (RB, RI+)
STB RS, (RB, RI+)
STW RS, (RB, RI+)
LDB RD, (RB, –RI)
LDW RD, (RB, –RI)
STB RS, (RB, –RI)
STW RS, (RB, –RI)
Bit Field Instructions
BFEXT RD, RS1, RS2
BFINS RD, RS1, RS2
BFINSI RD, RS1, RS2
BFINSX RD, RS1, RS2
Logic Immediate Instructions
ANDL RD, #IMM8
ANDH RD, #IMM8
BITL RD, #IMM8
BITH RD, #IMM8
ORL RD, #IMM8
ORH RD, #IMM8
XNORL RD, #IMM8
XNORH RD, #IMM8
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RD
RD
RS
RS
RD
RD
RS
RS
RD
RD
RS
RS
RD
RD
RS
RS
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
RB
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
RD
RD
RD
RD
RS1
RS1
RS1
RS1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RD
RD
RD
RD
RD
RD
RD
RD
5
4
3
2
1
0
RI
RI
RI
RI
RI
RI
RI
RI
RI
RI
RI
RI
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
RS2
RS2
RS2
RS2
1
1
1
1
1
1
1
1
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL9
REL10
OFFS5
OFFS5
OFFS5
OFFS5
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
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Chapter 10 XGATE (S12XGATEV3)
Table 10-23. Instruction Set Summary (Sheet 3 of 3)
Functionality
Arithmetic Immediate Instructions
SUBL RD, #IMM8
SUBH RD, #IMM8
CMPL RS, #IMM8
CPCH RS, #IMM8
ADDL RD, #IMM8
ADDH RD, #IMM8
LDL RD, #IMM8
LDH RD, #IMM8
10.9
10.9.1
15
14
13
12
11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
9
8
7
6
RD
RD
RS
RS
RD
RD
RD
RD
5
4
3
2
1
0
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
IMM8
Initialization and Application Information
Initialization
The recommended initialization of the XGATE is as follows:
1. Clear the XGE bit to suppress any incoming service requests.
2. Make sure that no thread is running on the XGATE. This can be done in several ways:
a) Poll the XGCHID register until it reads $00. Also poll XGDBG and XGSWEF to make sure
that the XGATE has not been stopped.
b) Enter Debug Mode by setting the XGDBG bit. Clear the XGCHID register. Clear the XGDBG
bit.
The recommended method is a).
3. Set the XGVBR register to the lowest address of the XGATE vector space.
4. Clear all Channel ID flags.
5. Copy XGATE vectors and code into the RAM.
6. Initialize the S12X_INT module.
7. Enable the XGATE by setting the XGE bit.
The following code example implements the XGATE initialization sequence.
10.9.2
Code Example (Transmit "Hello World!" on SCI)
SCI_REGS
SCIBDH
SCIBDL
SCICR2
SCISR1
SCIDRL
TIE
TE
RE
CPU S12X
;###########################################
;#
SYMBOLS
#
;###########################################
EQU $00C8
;SCI register space
EQU SCI_REGS+$00;
;SCI Baud Rate Register
EQU SCI_REGS+$00
;SCI Baud Rate Register
EQU SCI_REGS+$03
;SCI Control Register 2
EQU SCI_REGS+$04
;SCI Status Register 1
EQU SCI_REGS+$07
;SCI Control Register 2
EQU $80
;TIE bit mask
EQU $08
;TE bit mask
EQU $04
;RE bit mask
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Chapter 10 XGATE (S12XGATEV3)
SCI_VEC
EQU
$D6
;SCI vector number
INT_REGS
INT_CFADDR
INT_CFDATA
RQST
EQU
EQU
EQU
EQU
$0120
INT_REGS+$07
INT_REGS+$08
$80
;S12X_INT register space
;Interrupt Configuration Address Register
;Interrupt Configuration Data Registers
;RQST bit mask
XGATE_REGS
XGMCTL
XGMCTL_CLEAR
XGMCTL_ENABLE
XGCHID
XGISPSEL
XGVBR
XGIF
XGSWT
XGSEM
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$0380
XGATE_REGS+$00
$FA02
$8282
XGATE_REGS+$02
XGATE_REGS+$05
XGATE_REGS+$06
XGATE_REGS+$08
XGATE_REGS+$18
XGATE_REGS+$1A
;XGATE register space
;XGATE Module Control Register
;Clear all XGMCTL bits
;Enable XGATE
;XGATE Channel ID Register
;XGATE Channel ID Register
;XGATE ISP Select Register
;XGATE Interrupt Flag Vector
;XGATE Software Trigger Register
;XGATE Semaphore Register
RPAGE
EQU
$0016
RAM_SIZE
EQU
32*$400
RAM_START
RAM_START_XG
RAM_START_GLOB
EQU
EQU
EQU
$1000
$10000-RAM_SIZE
$100000-RAM_SIZE
XGATE_VECTORS
XGATE_VECTORS_XG
EQU
EQU
RAM_START
RAM_START_XG
XGATE_DATA
XGATE_DATA_XG
EQU
EQU
RAM_START+(4*128)
RAM_START_XG+(4*128)
XGATE_CODE
XGATE_CODE_XG
EQU
EQU
XGATE_DATA+(XGATE_CODE_FLASH-XGATE_DATA_FLASH)
XGATE_DATA_XG+(XGATE_CODE_FLASH-XGATE_DATA_FLASH)
BUS_FREQ_HZ
EQU
40000000
;32k RAM
;###########################################
;#
S12XE VECTOR TABLE
#
;###########################################
ORG $FF10
;non-maskable interrupts
DW
DUMMY_ISR DUMMY_ISR DUMMY_ISR DUMMY_ISR
ORG
DW
$FFF4
;non-maskable interrupts
DUMMY_ISR DUMMY_ISR DUMMY_ISR
ORG
DW
$FFFA
;resets
START_OF_CODE START_OF_CODE START_OF_CODE
;###########################################
;#
DISABLE COP
#
;###########################################
ORG $FF0E
DW
$FFFE
ORG
$C000
START_OF_CODE
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Chapter 10 XGATE (S12XGATEV3)
;###########################################
;#
INITIALIZE S12XE CORE
#
;###########################################
SEI
MOVB #(RAM_START_GLOB>>12), RPAGE
;set RAM page
INIT_SCI
INIT_INT
INIT_XGATE
INIT_XGATE_BUSY_LOOP
;###########################################
;#
INITIALIZE SCI
#
;###########################################
MOVW #(BUS_FREQ_HZ/(16*9600)), SCIBDH;set baud rate
MOVB #(TIE|TE), SCICR2;enable tx buffer empty interrupt
;###########################################
;#
INITIALIZE S12X_INT
#
;###########################################
MOVB #(SCI_VEC&$F0), INT_CFADDR
;switch SCI interrupts to XGATE
MOVB #RQST|$01, INT_CFDATA+((SCI_VEC&$0F)>>1)
;###########################################
;#
INITIALIZE XGATE
#
;###########################################
MOVW #XGMCTL_CLEAR, XGMCTL
;clear all XGMCTL bits
TST
BNE
XGCHID
;wait until current thread is finished
INIT_XGATE_BUSY_LOOP
LDX
LDD
STD
STD
STD
STD
STD
STD
STD
STD
#XGIF
#$FFFF
2,X+
2,X+
2,X+
2,X+
2,X+
2,X+
2,X+
2,X+
;clear all channel interrupt flags
CLR XGISPSEL
;set vector base register
MOVW #XGATE_VECTORS_XG, XGVBR
MOVW #$FF00, XGSWT
;clear all software triggers
INIT_XGATE_VECTAB_LOOP
;###########################################
;#
INITIALIZE XGATE VECTOR TABLE
#
;###########################################
LDAA #128
;build XGATE vector table
LDY #XGATE_VECTORS
MOVW #XGATE_DUMMY_ISR_XG, 4,Y+
DBNE A, INIT_XGATE_VECTAB_LOOP
MOVW #XGATE_CODE_XG, RAM_START+(2*SCI_VEC)
MOVW #XGATE_DATA_XG, RAM_START+(2*SCI_VEC)+2
COPY_XGATE_CODE
COPY_XGATE_CODE_LOOP
;###########################################
;#
COPY XGATE CODE
#
;###########################################
LDX #XGATE_DATA_FLASH
MOVW 2,X+, 2,Y+
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Chapter 10 XGATE (S12XGATEV3)
MOVW
MOVW
MOVW
CPX
BLS
START_XGATE
;###########################################
;#
START XGATE
#
;###########################################
MOVW #XGMCTL_ENABLE, XGMCTL
;enable XGATE
BRA *
;###########################################
;#
DUMMY INTERRUPT SERVICE ROUTINE
#
;###########################################
RTI
DUMMY_ISR
XGATE_DATA_FLASH
XGATE_DATA_SCI
XGATE_DATA_IDX
XGATE_DATA_MSG
XGATE_CODE_FLASH
XGATE_CODE_DONE
XGATE_CODE_FLASH_END
XGATE_DUMMY_ISR_XG
10.9.3
2,X+, 2,Y+
2,X+, 2,Y+
2,X+, 2,Y+
#XGATE_CODE_FLASH_END
COPY_XGATE_CODE_LOOP
CPU XGATE
;###########################################
;#
XGATE DATA
#
;###########################################
ALIGN 1
EQU *
EQU *-XGATE_DATA_FLASH
DW
SCI_REGS
;pointer to SCI register space
EQU *-XGATE_DATA_FLASH
DB
XGATE_DATA_MSG
;string pointer
EQU *-XGATE_DATA_FLASH
FCC "Hello World!
;ASCII string
DB
$0D
;CR
;###########################################
;#
XGATE CODE
#
;###########################################
ALIGN 1
LDW R2,(R1,#XGATE_DATA_SCI)
;SCI -> R2
LDB R3,(R1,#XGATE_DATA_IDX)
;msg -> R3
LDB R4,(R1,R3+)
;curr. char -> R4
STB R3,(R1,#XGATE_DATA_IDX)
;R3 -> idx
LDB R0,(R2,#(SCISR1-SCI_REGS))
;initiate SCI transmit
STB R4,(R2,#(SCIDRL-SCI_REGS))
;initiate SCI transmit
CMPL R4,#$0D
BEQ XGATE_CODE_DONE
RTS
LDL R4,#$00
;disable SCI interrupts
STB R4,(R2,#(SCICR2-SCI_REGS))
LDL R3,#XGATE_DATA_MSG;reset R3
STB R3,(R1,#XGATE_DATA_IDX)
RTS
EQU (XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
Stack Support
To simplify the implementation of a program stack the XGATE can be configured to set RISC core register
R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be defined:
One for threads of priority level 7 to 4 (refer to Section 10.3.1.5, “XGATE Initial Stack Pointer for
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Chapter 10 XGATE (S12XGATEV3)
Interrupt Priorities 7 to 4 (XGISP74)”) and one for threads of priority level 3 to 1 (refer to Section 10.3.1.6,
“XGATE Initial Stack Pointer for Interrupt Priorities 3 to 1 (XGISP31)”).
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Chapter 10 XGATE (S12XGATEV3)
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Chapter 11
S12XE Clocks and Reset Generator (S12XECRGV1) Block
Description
Revision History
Version Revision Effective
Number
Date
Date
Author
Description of Changes
V01.00
26 Oct. 05 26 Oct. 05
Initial release
V01.01
2 Nov. 06
Tabe “Examples of IPLL Divider settings”: corrected $32 to $31
11.1
2 Nov. 06
Introduction
This specification describes the function of the Clocks and Reset Generator (S12XECRG).
11.1.1
Features
The main features of this block are:
• Phase Locked Loop (IPLL) frequency multiplier with internal filter
— Reference divider
— Post divider
— Configurable internal filter (no external pin)
— Optional frequency modulation for defined jitter and reduced emission
— Automatic frequency lock detector
— Interrupt request on entry or exit from locked condition
— Self Clock Mode in absence of reference clock
• System Clock Generator
— Clock Quality Check
— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate
program execution
— Clock switch for either Oscillator or PLL based system clocks
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
•
•
•
Computer Operating Properly (COP) watchdog timer with time-out clear window.
System Reset generation from the following possible sources:
— Power on reset
— Low voltage reset
— Illegal address reset
— COP reset
— Loss of clock reset
— External pin reset
Real-Time Interrupt (RTI)
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.1.2
Modes of Operation
This subsection lists and briefly describes all operating modes supported by the S12XECRG.
• Run Mode
All functional parts of the S12XECRG are running during normal Run Mode. If RTI or COP
functionality is required the individual bits of the associated rate select registers (COPCTL,
RTICTL) have to be set to a non zero value.
• Wait Mode
In this mode the IPLL can be disabled automatically depending on the PLLWAI bit.
• Stop Mode
Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode
(PSTP = 0) and Pseudo Stop Mode (PSTP = 1).
— Full Stop Mode
The oscillator is disabled and thus all system and core clocks are stopped. The COP and the
RTI remain frozen.
— Pseudo Stop Mode
The oscillator continues to run and most of the system and core clocks are stopped. If the
respective enable bits are set the COP and RTI will continue to run, else they remain frozen.
• Self Clock Mode
Self Clock Mode will be entered if the Clock Monitor Enable Bit (CME) and the Self Clock Mode
Enable Bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of
clock. As soon as Self Clock Mode is entered the S12XECRG starts to perform a clock quality
check. Self Clock Mode remains active until the clock quality check indicates that the required
quality of the incoming clock signal is met (frequency and amplitude). Self Clock Mode should be
used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock
is causing severe system conditions.
11.1.3
Block Diagram
Figure 11-1 shows a block diagram of the S12XECRG.
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
Illegal Address Reset
S12X_MMC
Power on Reset
Voltage
Regulator
Low Voltage Reset
ICRG
RESET
CM Fail
Clock
Monitor
OSCCLK
EXTAL
Oscillator
XTAL
COP Timeout
XCLKS
Reset
Generator
Clock Quality
Checker
System Reset
Bus Clock
Core Clock
COP
RTI
Oscillator Clock
Registers
PLLCLK
VDDPLL
IPLL
VSSPLL
Real Time Interrupt
Clock and Reset Control
PLL Lock Interrupt
Self Clock Mode
Interrupt
Figure 11-1. Block diagram of S12XECRG
11.2
Signal Description
This section lists and describes the signals that connect off chip.
11.2.1
VDDPLL, VSSPLL
These pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the IPLL circuitry. This allows
the supply voltage to the IPLL to be independently bypassed. Even if IPLL usage is not required VDDPLL
and VSSPLL must be connected to properly.
11.2.2
RESET
RESET is an active low bidirectional reset pin. As an input it initializes the MCU asynchronously to a
known start-up state. As an open-drain output it indicates that an system reset (internal to MCU) has been
triggered.
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3
Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12XECRG.
11.3.1
Module Memory Map
Figure 11-2 gives an overview on all S12XECRG registers.
Address
Name
0x0000
SYNR
0x0001
REFDV
0x0002
POSTDIV
0x0003
CRGFLG
0x0004
CRGINT
0x0005
CLKSEL
0x0006
PLLCTL
0x0007
RTICTL
0x0008
COPCTL
0x0009
FORBYP2
0x000A
CTCTL2
0x000B
ARMCOP
Bit 7
R
W
R
W
R
6
5
4
3
VCOFRQ[1:0]
SYNDIV[5:0]
REFFRQ[1:0]
REFDIV[5:0]
0
0
0
RTIF
PORF
LVRF
W
R
W
0
0
R
RTIE
LOCKIF
LOCKIE
LOCK
0
XCLKS
0
PLLON
FM1
FM0
FSTWKP
RTDEC
RTR6
RTR5
RTR4
RTR3
WCOP
RSBCK
0
0
0
0
0
0
0
0
0
0
R
0
0
W
Bit 7
Bit 6
W
R
W
R
W
R
W
R
PLLSEL
PSTP
CME
1
Bit 0
POSTDIV[4:0]
W
R
2
PLLWAI
ILAF
0
0
SCMIF
SCMIE
SCM
0
RTIWAI
COPWAI
PRE
PCE
SCME
RTR2
RTR1
RTR0
CR2
CR1
CR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WRTMASK
W
R
W
2. FORBYP and CTCTL are intended for factory test purposes only.
= Unimplemented or Reserved
Figure 11-2. CRG Register Summary
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3.2
Register Descriptions
This section describes in address order all the S12XECRG registers and their individual bits.
11.3.2.1
S12XECRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the IPLL and selects the VCO frequency range.
Module Base + 0x0000
7
6
5
4
3
2
1
0
0
0
0
R
VCOFRQ[1:0]
SYNDIV[5:0]
W
Reset
0
0
0
0
0
Figure 11-3. S12XECRG Synthesizer Register (SYNR)
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
( SYNDIV + 1 )
f VCO = 2 × f OSC × ------------------------------------( REFDIV + 1 )
f VCO
f PLL = -----------------------------------2 × POSTDIV
f PLL
f BUS = ------------2
NOTE
fVCO must be within the specified VCO frequency lock range. F.BUS (Bus
Clock) must not exceed the specified maximum. If POSTDIV = $00 then
fPLL is same as fVCO (divide by one).
The VCOFRQ[1:0] bit are used to configure the VCO gain for optimal stability and lock time. For correct
IPLL operation the VCOFRQ[1:0] bits have to be selected according to the actual target VCOCLK
frequency as shown in Table 11-1. Setting the VCOFRQ[1:0] bits wrong can result in a non functional
IPLL (no locking and/or insufficient stability).
Table 11-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
VCOFRQ[1:0]
32MHz <= fVCO<= 48MHz
00
48MHz < fVCO<= 80MHz
01
Reserved
10
80MHz < fVCO <= 120MHz
11
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3.2.2
S12XECRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the IPLL multiplier steps.
Module Base + 0x0001
7
6
5
4
3
2
1
0
0
0
0
R
REFFRQ[1:0]
REFDIV[5:0]
W
Reset
0
0
0
0
0
Figure 11-4. S12XECRG Reference Divider Register (REFDV)
Read: Anytime
Write: Anytime except when PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit.
f OSC
f REF = -----------------------------------( REFDIV + 1 )
The REFFRQ[1:0] bit are used to configure the internal PLL filter for optimal stability and lock time. For
correct IPLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in Figure 11-2. Setting the REFFRQ[1:0] bits wrong can result in a non functional
IPLL (no locking and/or insufficient stability).
Table 11-2. Reference Clock Frequency Selection
REFCLK Frequency Ranges
REFFRQ[1:0]
1MHz <= fREF <= 2MHz
00
2MHz < fREF <= 6MHz
01
6MHz < fREF <= 12MHz
10
fREF >12MHz
11
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3.2.3
S12XECRG Post Divider Register (POSTDIV)
The POSTDIV register controls the frequency ratio between the VCOCLK and PLLCLK. The count in the
final divider divides VCOCLK frequency by 1 or 2*POSTDIV. Note that if POSTDIV = $00 fPLL= fVCO
(divide by one).
Module Base + 0x0002
R
7
6
5
0
0
0
4
3
2
1
0
0
0
2
1
0
ILAF
SCMIF
0
0
POSTDIV[4:0]
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-5. S12XECRG Post Divider Register (POSTDIV)
Read: Anytime
Write: Anytime except if PLLSEL = 1
f VCO
f PLL = -------------------------------------( 2xPOSTDIV )
NOTE
If POSTDIV = $00 then fPLL is identical to fVCO (divide by one).
11.3.2.4
S12XECRG Flags Register (CRGFLG)
This register provides S12XECRG status bits and flags.
Module Base + 0x0002
7
6
5
4
RTIF
PORF
LVRF
LOCKIF
0
Note 1
Note 2
Note 3
R
3
LOCK
SCM
W
Reset
0
0
1. PORF is set to 1 when a power on reset occurs. Unaffected by system reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by system reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low voltage reset.
= Unimplemented or Reserved
Figure 11-6. S12XECRG Flags Register (CRGFLG)
Read: Anytime
Write: Refer to each bit for individual write conditions
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
Table 11-3. CRGFLG Field Descriptions
Field
Description
7
RTIF
Real Time Interrupt Flag — RTIF is set to 1 at the end of the RTI period. This flag can only be cleared by writing
a 1. Writing a 0 has no effect. If enabled (RTIE=1), RTIF causes an interrupt request.
0 RTI time-out has not yet occurred.
1 RTI time-out has occurred.
6
PORF
Power on Reset Flag — PORF is set to 1 when a power on reset occurs. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 Power on reset has not occurred.
1 Power on reset has occurred.
5
LVRF
Low Voltage Reset Flag — LVRF is set to 1 when a low voltage reset occurs. This flag can only be cleared by
writing a 1. Writing a 0 has no effect.
0 Low voltage reset has not occurred.
1 Low voltage reset has occurred.
4
LOCKIF
IPLL Lock Interrupt Flag — LOCKIF is set to 1 when LOCK status bit changes. This flag can only be cleared
by writing a 1. Writing a 0 has no effect.If enabled (LOCKIE=1), LOCKIF causes an interrupt request.
0 No change in LOCK bit.
1 LOCK bit has changed.
3
LOCK
Lock Status Bit — LOCK reflects the current state of IPLL lock condition. This bit is cleared in Self Clock Mode.
Writes have no effect.
0 VCOCLK is not within the desired tolerance of the target frequency.
1 VCOCLK is within the desired tolerance of the target frequency.
2
ILAF
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block
Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
1
SCMIF
0
SCM
Self Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in Self Clock Mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
running at its minimum frequency fSCM.
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3.2.5
S12XECRG Interrupt Enable Register (CRGINT)
This register enables S12XECRG interrupt requests.
Module Base + 0x0004
7
R
6
5
0
0
RTIE
4
3
2
0
0
LOCKIE
1
0
0
SCMIE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-7. S12XECRG Interrupt Enable Register (CRGINT)
Read: Anytime
Write: Anytime
Table 11-4. CRGINT Field Descriptions
Field
7
RTIE
Description
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
4
LOCKIE
Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
1
SCMIE
Self Clock Mode Interrupt Enable Bit
0 SCM interrupt requests are disabled.
1 Interrupt will be requested whenever SCMIF is set.
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3.2.6
S12XECRG Clock Select Register (CLKSEL)
This register controls S12XECRG clock selection. Refer toFigure 11-16 for more details on the effect of
each bit.
Module Base + 0x0005
7
6
PLLSEL
PSTP
0
0
R
5
4
XCLKS
0
3
2
1
0
RTIWAI
COPWAI
0
0
0
PLLWAI
W
Reset
0
0
0
0
= Unimplemented or Reserved
Figure 11-8. S12XECRG Clock Select Register (CLKSEL)
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 11-5. CLKSEL Field Descriptions
Field
7
PLLSEL
6
PSTP
Description
PLL Select Bit
Write: Anytime.
Writing a one when LOCK=0 has no effect. This prevents the selection of an unstable PLLCLK as SYSCLK.
PLLSEL bit is cleared when the MCU enters Self Clock Mode, Stop Mode or Wait Mode with PLLWAI bit set.
It is recommended to read back the PLLSEL bit to make sure PLLCLK has really been selected as
SYSCLK, as LOCK status bit could theoretically change at the very moment writing the PLLSEL bit.
0 System clocks are derived from OSCCLK (fBUS = fOSC / 2).
1 System clocks are derived from PLLCLK (fBUS = fPLL / 2).
Pseudo Stop Bit
Write: Anytime
This bit controls the functionality of the oscillator during Stop Mode.
0 Oscillator is disabled in Stop Mode.
1 Oscillator continues to run in Stop Mode (Pseudo Stop).
Note: Pseudo Stop Mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
5
XCLKS
Oscillator Configuration Status Bit — This read-only bit shows the oscillator configuration status.
0 Loop controlled Pierce Oscillator is selected.
1 External clock / full swing Pierce Oscillator is selected.
3
PLLWAI
PLL Stops in Wait Mode Bit
Write: Anytime
If PLLWAI is set, the S12XECRG will clear the PLLSEL bit before entering Wait Mode. The PLLON bit remains
set during Wait Mode but the IPLL is powered down. Upon exiting Wait Mode, the PLLSEL bit has to be set
manually if PLL clock is required.
0 IPLL keeps running in Wait Mode.
1 IPLL stops in Wait Mode.
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Table 11-5. CLKSEL Field Descriptions (continued)
Field
Description
1
RTIWAI
RTI Stops in Wait Mode Bit
Write: Anytime
0 RTI keeps running in Wait Mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode.
0
COPWAI
COP Stops in Wait Mode Bit
Normal modes: Write once
Special modes: Write anytime
0 COP keeps running in Wait Mode.
1 COP stops and initializes the COP counter whenever the part goes into Wait Mode.
11.3.2.7
S12XECRG IPLL Control Register (PLLCTL)
This register controls the IPLL functionality.
Module Base + 0x0006
7
6
5
4
3
2
1
0
CME
PLLON
FM1
FM0
FSTWKP
PRE
PCE
SCME
1
1
0
0
0
0
0
1
R
W
Reset
Figure 11-9. S12XECRG IPLL Control Register (PLLCTL)
Read: Anytime
Write: Refer to each bit for individual write conditions
Table 11-6. PLLCTL Field Descriptions
Field
Description
7
CME
Clock Monitor Enable Bit — CME enables the clock monitor. Write anytime except when SCM = 1.
0 Clock monitor is disabled.
1 Clock monitor is enabled. Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock
Mode.
Note: Operating with CME=0 will not detect any loss of clock. In case of poor clock quality this could cause
unpredictable operation of the MCU!
In Stop Mode (PSTP=0) the clock monitor is disabled independently of the CME bit setting and any loss
of external clock will not be detected.
Also after wake-up from stop mode (PSTP = 0) with fast wake-up enabled (FSTWKP = 1) the clock monitor
is disabled independently of the CME bit setting and any loss of external clock will not be detected.
6
PLLON
Phase Lock Loop On Bit — PLLON turns on the IPLL circuitry. In Self Clock Mode, the IPLL is turned on, but
the PLLON bit reads the last written value. Write anytime except when PLLSEL = 1.
0 IPLL is turned off.
1 IPLL is turned on.
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Table 11-6. PLLCTL Field Descriptions (continued)
Field
Description
5, 4
FM1, FM0
IPLL Frequency Modulation Enable Bit — FM1 and FM0 enable additional frequency modulation on the
VCOCLK. This is to reduce noise emission. The modulation frequency is fref divided by 16. Write anytime except
when PLLSEL = 1. See Table 11-7 for coding.
3
FSTWKP
Fast Wake-up from Full Stop Bit — FSTWKP enables fast wake-up from full stop mode. Write anytime. If
Self-Clock Mode is disabled (SCME = 0) this bit has no effect.
0 Fast wake-up from full stop mode is disabled.
1 Fast wake-up from full stop mode is enabled. When waking up from full stop mode the system will immediately
resume operation in Self-Clock Mode (see Section 11.4.1.4, “Clock Quality Checker”). The SCMIF flag will not
be set. The system will remain in Self-Clock Mode with oscillator and clock monitor disabled until FSTWKP bit
is cleared. The clearing of FSTWKP will start the oscillator, the clock monitor and the clock quality check. If
the clock quality check is successful, the S12XECRG will switch all system clocks to OSCCLK. The SCMIF
flag will be set. See application examples in Figure 11-19 and Figure 11-20.
2
PRE
RTI Enable During Pseudo Stop Bit — PRE enables the RTI during Pseudo Stop Mode.
Write anytime.
0 RTI stops running during Pseudo Stop Mode.
1 RTI continues running during Pseudo Stop Mode.
Note: If the PRE bit is cleared the RTI dividers will go static while Pseudo Stop Mode is active. The RTI dividers
will not initialize like in Wait Mode with RTIWAI bit set.
1
PCE
COP Enable During Pseudo Stop Bit — PCE enables the COP during Pseudo Stop Mode.
Write anytime.
0 COP stops running during Pseudo Stop Mode
1 COP continues running during Pseudo Stop Mode
Note: If the PCE bit is cleared the COP dividers will go static while Pseudo Stop Mode is active. The COP
dividers will not initialize like in Wait Mode with COPWAI bit set.
0
SCME
Self Clock Mode Enable Bit
Normal modes: Write once
Special modes: Write anytime
SCME can not be cleared while operating in Self Clock Mode (SCM = 1).
0 Detection of crystal clock failure causes clock monitor reset (see Section 11.5.1.1, “Clock Monitor Reset”).
1 Detection of crystal clock failure forces the MCU in Self Clock Mode (see Section 11.4.2.2, “Self Clock Mode”).
Table 11-7. FM Amplitude selection
FM1
FM0
FM Amplitude /
fVCO Variation
0
0
FM off
0
1
±1%
1
0
±2%
1
1
±4%
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3.2.8
S12XECRG RTI Control Register (RTICTL)
This register selects the timeout period for the Real Time Interrupt.
Module Base + 0x0007
7
6
5
4
3
2
1
0
RTDEC
RTR6
RTR5
RTR4
RTR3
RTR2
RTR1
RTR0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 11-10. S12XECRG RTI Control Register (RTICTL)
Read: Anytime
Write: Anytime
NOTE
A write to this register initializes the RTI counter.
Table 11-8. RTICTL Field Descriptions
Field
Description
7
RTDEC
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 11-9
1 Decimal based divider value. See Table 11-10
6–4
RTR[6:4]
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
Table 11-9 and Table 11-10.
3–0
RTR[3:0]
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 11-9 and Table 11-10 show all possible divide values selectable by the
RTICTL register. The source clock for the RTI is OSCCLK.
Table 11-9. RTI Frequency Divide Rates for RTDEC = 0
RTR[6:4] =
RTR[3:0]
000
(OFF)
001
(210)
010
(211)
011
(212)
100
(213)
101
(214)
110
(215)
111
(216)
0000 (÷1)
OFF1
210
211
212
213
214
215
216
0001 (÷2)
OFF
2x210
2x211
2x212
2x213
2x214
2x215
2x216
0010 (÷3)
OFF
3x210
3x211
3x212
3x213
3x214
3x215
3x216
0011 (÷4)
OFF
4x210
4x211
4x212
4x213
4x214
4x215
4x216
0100 (÷5)
OFF
5x210
5x211
5x212
5x213
5x214
5x215
5x216
0101 (÷6)
OFF
6x210
6x211
6x212
6x213
6x214
6x215
6x216
0110 (÷7)
OFF
7x210
7x211
7x212
7x213
7x214
7x215
7x216
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Table 11-9. RTI Frequency Divide Rates for RTDEC = 0
RTR[6:4] =
RTR[3:0]
1
000
(OFF)
001
(210)
010
(211)
011
(212)
100
(213)
101
(214)
110
(215)
111
(216)
0111 (÷8)
OFF
8x210
8x211
8x212
8x213
8x214
8x215
8x216
1000 (÷9)
OFF
9x210
9x211
9x212
9x213
9x214
9x215
9x216
1001 (÷10)
OFF
10x210
10x211
10x212
10x213
10x214
10x215
10x216
1010 (÷11)
OFF
11x210
11x211
11x212
11x213
11x214
11x215
11x216
1011 (÷12)
OFF
12x210
12x211
12x212
12x213
12x214
12x215
12x216
1100 (÷13)
OFF
13x210
13x211
13x212
13x213
13x214
13x215
13x216
1101 (÷14)
OFF
14x210
14x211
14x212
14x213
14x214
14x215
14x216
1110 (÷15)
OFF
15x210
15x211
15x212
15x213
15x214
15x215
15x216
1111 (÷16)
OFF
16x210
16x211
16x212
16x213
16x214
16x215
16x216
Denotes the default value out of reset.This value should be used to disable the RTI to ensure future backwards compatibility.
Table 11-10. RTI Frequency Divide Rates for RTDEC=1
RTR[6:4] =
RTR[3:0]
000
(1x103)
001
(2x103)
010
(5x103)
011
(10x103)
100
(20x103)
101
(50x103)
110
(100x103)
111
(200x103)
0000 (÷1)
1x103
2x103
5x103
10x103
20x103
50x103
100x103
200x103
0001 (÷2)
2x103
4x103
10x103
20x103
40x103
100x103
200x103
400x103
0010 (÷3)
3x103
6x103
15x103
30x103
60x103
150x103
300x103
600x103
0011 (÷4)
4x103
8x103
20x103
40x103
80x103
200x103
400x103
800x103
0100 (÷5)
5x103
10x103
25x103
50x103
100x103
250x103
500x103
1x106
0101 (÷6)
6x103
12x103
30x103
60x103
120x103
300x103
600x103
1.2x106
0110 (÷7)
7x103
14x103
35x103
70x103
140x103
350x103
700x103
1.4x106
0111 (÷8)
8x103
16x103
40x103
80x103
160x103
400x103
800x103
1.6x106
1000 (÷9)
9x103
18x103
45x103
90x103
180x103
450x103
900x103
1.8x106
1001 (÷10)
10 x103
20x103
50x103
100x103
200x103
500x103
1x106
2x106
1010 (÷11)
11 x103
22x103
55x103
110x103
220x103
550x103
1.1x106
2.2x106
1011 (÷12)
12x103
24x103
60x103
120x103
240x103
600x103
1.2x106
2.4x106
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
Table 11-10. RTI Frequency Divide Rates for RTDEC=1
RTR[6:4] =
RTR[3:0]
000
(1x103)
001
(2x103)
010
(5x103)
011
(10x103)
100
(20x103)
101
(50x103)
110
(100x103)
111
(200x103)
1100 (÷13)
13x103
26x103
65x103
130x103
260x103
650x103
1.3x106
2.6x106
1101 (÷14)
14x103
28x103
70x103
140x103
280x103
700x103
1.4x106
2.8x106
1110 (÷15)
15x103
30x103
75x103
150x103
300x103
750x103
1.5x106
3x106
1111 (÷16)
16x103
32x103
80x103
160x103
320x103
800x103
1.6x106
3.2x106
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11.3.2.9
S12XECRG COP Control Register (COPCTL)
This register controls the COP (Computer Operating Properly) watchdog.
Module Base + 0x0008
7
6
WCOP
RSBCK
R
W
Reset1
5
4
3
0
0
0
2
1
0
CR2
CR1
CR0
0
0
0
WRTMASK
0
0
0
0
0
1. Refer to Device User Guide (Section: S12XECRG) for reset values of WCOP, CR2, CR1 and CR0.
= Unimplemented or Reserved
Figure 11-11. S12XECRG COP Control Register (COPCTL)
Read: Anytime
Write:
1. RSBCK: anytime in special modes; write to “1” but not to “0” in all other modes
2. WCOP, CR2, CR1, CR0:
— Anytime in special modes
— Write once in all other modes
– Writing CR[2:0] to “000” has no effect, but counts for the “write once” condition.
– Writing WCOP to “0” has no effect, but counts for the “write once” condition.
The COP time-out period is restarted if one these two conditions is true:
1. Writing a non zero value to CR[2:0] (anytime in special modes, once in all other modes) with
WRTMASK = 0.
or
2. Changing RSBCK bit from “0” to “1”.
Table 11-11. COPCTL Field Descriptions
Field
Description
7
WCOP
Window COP Mode Bit — When set, a write to the ARMCOP register must occur in the last 25% of the selected
period. A write during the first 75% of the selected period will reset the part. As long as all writes occur during
this window, $55 can be written as often as desired. Once $AA is written after the $55, the time-out logic restarts
and the user must wait until the next window before writing to ARMCOP. Table 11-12 shows the duration of this
window for the seven available COP rates.
0 Normal COP operation
1 Window COP operation
6
RSBCK
COP and RTI Stop in Active BDM Mode Bit
0 Allows the COP and RTI to keep running in Active BDM mode.
1 Stops the COP and RTI counters whenever the part is in Active BDM mode.
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
Table 11-11. COPCTL Field Descriptions (continued)
Field
Description
5
Write Mask for WCOP and CR[2:0] Bit — This write-only bit serves as a mask for the WCOP and CR[2:0] bits
WRTMASK while writing the COPCTL register. It is intended for BDM writing the RSBCK without touching the contents of
WCOP and CR[2:0].
0 Write of WCOP and CR[2:0] has an effect with this write of COPCTL
1 Write of WCOP and CR[2:0] has no effect with this write of COPCTL.
(Does not count for “write once”.)
2–0
CR[2:0]
COP Watchdog Timer Rate Select — These bits select the COP time-out rate (see Table 11-12). Writing a
nonzero value to CR[2:0] enables the COP counter and starts the time-out period. A COP counter time-out
causes a system reset. This can be avoided by periodically (before time-out) reinitialize the COP counter via the
ARMCOP register.
While all of the following four conditions are true the CR[2:0], WCOP bits are ignored and the COP operates at
highest time-out period (2 24 cycles) in normal COP mode (Window COP mode disabled):
1) COP is enabled (CR[2:0] is not 000)
2) BDM mode active
3) RSBCK = 0
4) Operation in emulation or special modes
Table 11-12. COP Watchdog Rates1
1
CR2
CR1
CR0
OSCCLK
Cycles to Timeout
0
0
0
COP disabled
0
0
1
2 14
0
1
0
2 16
0
1
1
2 18
1
0
0
2 20
1
0
1
2 22
1
1
0
2 23
1
1
1
2 24
OSCCLK cycles are referenced from the previous COP time-out reset
(writing $55/$AA to the ARMCOP register)
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1) Block Description
11.3.2.10 Reserved Register (FORBYP)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special
modes can alter the S12XECRG’s functionality.
Module Base + 0x0009
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 11-12. Reserved Register (FORBYP)
Read: Always read $00 except in special modes
Write: Only in special modes
11.3.2.11 Reserved Register (CTCTL)
NOTE
This reserved register is designed for factory test purposes only, and is not
intended for general user access. Writing to this register when in special test
modes can alter the S12XECRG’s functionality.
Module Base + 0x000A
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 11-13. Reserved Register (CTCTL)
Read: Always read $00 except in special modes
Write: Only in special modes
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11.3.2.12 S12XECRG COP Timer Arm/Reset Register (ARMCOP)
This register is used to restart the COP time-out period.
Module Base + 0x000B
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Reset
Figure 11-14. S12XECRG ARMCOP Register Diagram
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
you must write $55 followed by a write of $AA. Other instructions may be executed between these
writes but the sequence ($55, $AA) must be completed prior to COP end of time-out period to
avoid a COP reset. Sequences of $55 writes or sequences of $AA writes are allowed. When the
WCOP bit is set, $55 and $AA writes must be done in the last 25% of the selected time-out period;
writing any value in the first 75% of the selected period will cause a COP reset.
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11.4
Functional Description
11.4.1
11.4.1.1
Functional Blocks
Phase Locked Loop with Internal Filter (IPLL)
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK. Figure 11-15
shows a block diagram of the IPLL.
REFCLK
REFDIV[5:0]
EXTAL
REDUCED
CONSUMPTION
OSCILLATOR
OSCCLK
REFERENCE
PROGRAMMABLE
DIVIDER
XTAL
CLOCK
MONITOR
Supplied by:
FBCLK
LOCK
LOCK
DETECTOR
VDDPLL/VSSPLL
PDET
PHASE
DETECTOR
UP
CPUMP
AND
FILTER
DOWN
VCO
VCOCLK
LOOP
PROGRAMMABLE
DIVIDER
POST
PROGRAMMABLE
DIVIDER
PLLCLK
SYNDIV[5:0]
VDDPLL/VSSPLL
POSTDIV[4:0]
VDD/VSS
Figure 11-15. IPLL Functional Diagram
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of
2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,...
to 62 to generate the PLLCLK.
.
SYNDIV + 1
f PLL = 2 × f OSC × -----------------------------------------------------------------------------[ REFDIV + 1 ] [ 2 × POSTDIV ]
NOTE
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1) then fBUS = fPLL / 2.
IF POSTDIV = $00 the fPLL is identical to fVCO (divide by one)
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Several examples of IPLL divider settings are shown in Table 11-13. Shaded rows indicated that these
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
• Use lowest possible fVCO / fREF ratio (SYNDIV value).
• Use highest possible REFCLK frequency fREF.
Table 11-13. Examples of IPLL Divider Settings
fOSC
REFDIV[5:0]
fREF
4MHz
$00
4MHz
01
$09
80MHz
01
8MHz
$00
8MHz
10
$04
80MHz
4MHz
$00
4MHz
01
$03
4MHz
$01
2MHz
00
4MHz
$03
1MHz
4MHz
$03
1MHz
11.4.1.1.1
REFFRQ[1:0] SYNDIV[5:0]
fVCO
VCOFRQ[1:0] POSTDIV[4:0]
fPLL
fBUS
$00
80MHz
40MHz
01
$00
80MHz
40MHz
32MHz
00
$01
16MHz
8MHz
$18
100MHz
11
$01
50MHz
25MHz
00
$18
50MHz
01
$00
50MHz
25MHz
00
$31
100MHz
11
$01
50MHz
25MHz
IPLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 64 (REFDIV+1) to output the REFCLK. The VCO output clock, (VCOCLK) is
fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of [2
x (SYNDIV +1)] to output the FBCLK. The VCOCLK is fed to the final programmable divider and is
divided in a range of 1,2,4,6,8,... to 62 (2*POSTDIV) to output the PLLCLK. See Figure 11-15.
The phase detector then compares the FBCLK, with the REFCLK. Correction pulses are generated based
on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the
internal filter capacitor, based on the width and direction of the correction pulse.
The user must select the range of the REFCLK frequency and the range of the VCOCLK frequency to
ensure that the correct IPLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK, and the REFCLK. Therefore, the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If IPLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and then check
the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously (during
IPLL start-up, usually) or at periodic intervals. In either case, only when the LOCK bit is set, the PLLCLK
can be selected as the source for the system and core clocks. If the IPLL is selected as the source for the
system and core clocks and the LOCK bit is clear, the IPLL has suffered a severe noise hit and the software
must take appropriate action, depending on the application.
• The LOCK bit is a read-only indicator of the locked state of the IPLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆unl.
• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
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11.4.1.2
System Clocks Generator
PLLSEL or SCM
PLLCLK
PHASE
LOCK
LOOP (IIPLL)
STOP
1
SYSCLK
÷2
SCM
EXTAL
1
OSCILLATOR
Core Clock
0
WAIT(RTIWAI),
STOP(PSTP, PRE),
RTI ENABLE
CLOCK PHASE
GENERATOR
Bus Clock
RTI
OSCCLK
0
WAIT(COPWAI),
STOP(PSTP, PCE),
COP ENABLE
XTAL
COP
Clock
Monitor
STOP
Oscillator
Clock
Gating
Condition
= Clock Gate
Figure 11-16. System Clocks Generator
The clock generator creates the clocks used in the MCU (see Figure 11-16). The gating condition placed
on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see Section 11.4.2.2, “Self Clock Mode”) Oscillator clock source is
switched to PLLCLK running at its minimum frequency fSCM. The Bus Clock is used to generate the clock
visible at the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus
Clock. But note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned
off by clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a
maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks
freeze and CPU activity ceases.
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11.4.1.3
Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system
reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is
detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by
the CME control bit.
11.4.1.4
Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
• Power on reset (POR)
• Low voltage reset (LVR)
• Wake-up from Full Stop Mode (exit full stop)
• Clock Monitor fail indication (CM fail)
A time window of 50000 PLLCLK cycles1 is called check window.
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See Figure 11-17 as an example.
CHECK WINDOW
1
3
2
49999
50000
PLLCLK
1
2
3
4
5
4096
OSCCLK
4095
OSC OK
Figure 11-17. Check Window Example
1. IPLL is running at self clock mode frequency fSCM.
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The Sequence for clock quality check is shown in Figure 11-18.
CM FAIL
CLOCK OK
NO
EXIT FULL STOP
POR
YES
SCME=1 &
FSTWKP=1
?
NO
LVR
NUM = 0
FSTWKP = 0
?
ENTER SCM
YES
CLOCK MONITOR RESET
ENTER SCM
NUM = 50
YES
CHECK WINDOW
SCM
ACTIVE?
NUM = NUM-1
YES
OSC OK
?
NUM = 0
NO
NO
NUM > 0
?
YES
NO
SCME = 1
?
NO
YES
SCM
ACTIVE?
YES
SWITCH TO OSCCLK
NO
EXIT SCM
Figure 11-18. Sequence for Clock Quality Check
NOTE
Remember that in parallel to additional actions caused by Self Clock Mode
or Clock Monitor Reset1 handling the clock quality checker continues to
check the OSCCLK signal.
NOTE
The Clock Quality Checker enables the IPLL and the voltage regulator
(VREG) anytime a clock check has to be performed. An ongoing clock
quality check could also cause a running IPLL (fSCM) and an active VREG
during Pseudo Stop Mode or Wait Mode.
1. A Clock Monitor Reset will always set the SCME bit to logical’1’.
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11.4.1.5
Computer Operating Properly Watchdog (COP)
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus a system reset is initiated (see Section 11.4.1.5, “Computer Operating Properly
Watchdog (COP)”). The COP runs with a gated OSCCLK. Three control bits in the COPCTL register
allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the ARMCOP register
during the selected time-out period. Once this is done, the COP time-out period is restarted. If the program
fails to do this and the COP times out, the part will reset. Also, if any value other than $55 or $AA is
written, the part is immediately reset.
Windowed COP operation is enabled by setting WCOP in the COPCTL register. In this mode, writes to
the ARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out period.
A premature write will immediately reset the part.
If PCE bit is set, the COP will continue to run in Pseudo Stop Mode.
11.4.1.6
Real Time Interrupt (RTI)
The RTI can be used to generate a hardware interrupt at a fixed periodic rate. If enabled (by setting
RTIE=1), this interrupt will occur at the rate selected by the RTICTL register. The RTI runs with a gated
OSCCLK. At the end of the RTI time-out period the RTIF flag is set to one and a new RTI time-out period
starts immediately.
A write to the RTICTL register restarts the RTI time-out period.
If the PRE bit is set, the RTI will continue to run in Pseudo Stop Mode.
11.4.2
11.4.2.1
Operation Modes
Normal Mode
The S12XECRG block behaves as described within this specification in all normal modes.
11.4.2.2
Self Clock Mode
If the external clock frequency is not available due to a failure or due to long crystal start-up time, the Bus
Clock and the Core Clock are derived from the PLLCLK running at self clock mode frequency fSCM; this
mode of operation is called Self Clock Mode. This requires CME = 1 and SCME = 1, which is the default
after reset. If the MCU was clocked by the PLLCLK prior to entering Self Clock Mode, the PLLSEL bit
will be cleared. If the external clock signal has stabilized again, the S12XECRG will automatically select
OSCCLK to be the system clock and return to normal mode. See Section 11.4.1.4, “Clock Quality
Checker” for more information on entering and leaving Self Clock Mode.
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NOTE
In order to detect a potential clock loss the CME bit should always be
enabled (CME = 1).
If CME bit is disabled and the MCU is configured to run on PLLCLK, a loss
of external clock (OSCCLK) will not be detected and will cause the system
clock to drift towards lower frequencies. As soon as the external clock is
available again the system clock ramps up to its IPLL target frequency. If
the MCU is running on external clock any loss of clock will cause the
system to go static.
11.4.3
Low Power Options
This section summarizes the low power options available in the S12XECRG.
11.4.3.1
Run Mode
This is the default mode after reset.
The RTI can be stopped by setting the associated rate select bits to zero.
The COP can be stopped by setting the associated rate select bits to zero.
11.4.3.2
Wait Mode
The WAI instruction puts the MCU in a low power consumption stand-by mode depending on setting of
the individual bits in the CLKSEL register. All individual Wait Mode configuration bits can be superposed.
This provides enhanced granularity in reducing the level of power consumption during Wait Mode.
Table 11-14 lists the individual configuration bits and the parts of the MCU that are affected in Wait Mode.
Table 11-14. MCU Configuration During Wait Mode
PLLWAI
RTIWAI
COPWAI
IPLL
Stopped
—
—
RTI
—
Stopped
—
COP
—
—
Stopped
After executing the WAI instruction the core requests the S12XECRG to switch MCU into Wait Mode.
The S12XECRG then checks whether the PLLWAI bit is asserted. Depending on the configuration the
S12XECRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit and disables
the IPLL.
There are two ways to restart the MCU from Wait Mode:
1. Any reset
2. Any interrupt
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11.4.3.3
Stop Mode
All clocks are stopped in STOP mode, dependent of the setting of the PCE, PRE and PSTP bit. The
oscillator is disabled in STOP mode unless the PSTP bit is set. If the PRE or PCE bits are set, the RTI or
COP continues to run in Pseudo Stop Mode. In addition to disabling system and core clocks the
S12XECRG requests other functional units of the MCU (e.g. voltage-regulator) to enter their individual
power saving modes (if available).
If the PLLSEL bit is still set when entering Stop Mode, the S12XECRG will switch the system and core
clocks to OSCCLK by clearing the PLLSEL bit. Then the S12XECRG disables the IPLL, disables the core
clock and finally disables the remaining system clocks.
If Pseudo Stop Mode (PSTP = 1) is entered from Self-Clock Mode the S12XECRG will continue to check
the clock quality until clock check is successful. The IPLL and the voltage regulator (VREG) will remain
enabled. If Full Stop Mode (PSTP = 0) is entered from Self-Clock Mode the ongoing clock quality check
will be stopped. A complete timeout window check will be started when Stop Mode is left again.
There are two ways to restart the MCU from Stop Mode:
1. Any reset
2. Any interrupt
If the MCU is woken-up from Full Stop Mode by an interrupt and the fast wake-up feature is enabled
(FSTWKP=1 and SCME=1), the system will immediately (no clock quality check) resume operation in
Self-Clock Mode (see Section 11.4.1.4, “Clock Quality Checker”). The SCMIF flag will not be set for this
special case. The system will remain in Self-Clock Mode with oscillator disabled until FSTWKP bit is
cleared. The clearing of FSTWKP will start the oscillator and the clock quality check. If the clock quality
check is successful, the S12XECRG will switch all system clocks to oscillator clock. The SCMIF flag will
be set. See application examples in Figure 11-19 and Figure 11-20.
Because the IPLL has been powered-down during Stop Mode the PLLSEL bit is cleared and the MCU runs
on OSCCLK after leaving Stop-Mode. The software must manually set the PLLSEL bit again, in order to
switch system and core clocks to the PLLCLK.
NOTE
In Full Stop Mode or Self-Clock Mode caused by the fast wake-up feature
the clock monitor and the oscillator are disabled.
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CPU resumes program execution immediately
Instruction
STOP
STOP
FSTWKP=1 SCME=1
STOP
Interrupt
IRQ service
IRQ service
IRQ service
Interrupt
Interrupt
Power Saving
Oscillator Clock
Oscillator Disabled
PLL Clock
Core Clock
Self-Clock Mode
Figure 11-19. Fast Wake-up from Full Stop Mode: Example 1
.
CPU resumes program execution immediately
Instruction
Frequent Uncritical
Frequent Critical
Instructions
Instructions Possible
IRQ Service
STOP
FSTWKP=1 SCME=1
IRQ Interrupt FSTWKP=0 SCMIE=1
SCM Interrupt
Clock Quality Check
Oscillator Clock
Oscillator Disabled Osc Startup
PLL Clock
Self-Clock Mode
Core Clock
Figure 11-20. Fast Wake-up from Full Stop Mode: Example 2
11.5
Resets
All reset sources are listed in Table 11-15. Refer to MCU specification for related vector addresses and
priorities.
Table 11-15. Reset Summary
Reset Source
Local Enable
Power on Reset
None
Low Voltage Reset
None
External Reset
None
Illegal Address Reset
None
Clock Monitor Reset
PLLCTL (CME=1, SCME=0)
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Table 11-15. Reset Summary
11.5.1
Reset Source
Local Enable
COP Watchdog Reset
COPCTL (CR[2:0] nonzero)
Description of Reset Operation
The reset sequence is initiated by any of the following events:
• Low level is detected at the RESET pin (External Reset).
• Power on is detected.
• Low voltage is detected.
• Illegal Address Reset is detected (see S12XMMC Block Guide for details).
• COP watchdog times out.
• Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see Figure 11-21). Since entry into reset is asynchronous it does not require a running SYSCLK.
However, the internal reset circuit of the S12XECRG cannot sequence out of current reset condition
without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6
additional SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK
cycles the RESET pin is released. The reset generator of the S12XECRG waits for additional 64 SYSCLK
cycles and then samples the RESET pin to determine the originating source. Table 11-16 shows which
vector will be fetched.
Table 11-16. Reset Vector Selection
Sampled RESET Pin
Clock Monitor
COP
(64 cycles after release) Reset Pending Reset Pending
Vector Fetch
1
0
0
POR / LVR /
Illegal Address Reset/
External Reset
1
1
X
Clock Monitor Reset
1
0
1
COP Reset
0
X
X
POR / LVR /
Illegal Address Reset/ External Reset
with rise of RESET pin
NOTE
External circuitry connected to the RESET pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within 64 SYSCLK cycles after the low drive is released.
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The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long
reset sequence. In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles
(External Reset), the internal reset remains asserted longer.
Figure 11-21. RESET Timing
RESET
)(
)(
ICRG drives RESET pin low
)
)
SYSCLK
(
128+n cycles
possibly
SYSCLK
not
running
11.5.1.1
RESET pin
released
)
(
(
64 cycles
with n being
min 3 / max 6
cycles depending
on internal
synchronization
delay
possibly
RESET
driven low
externally
Clock Monitor Reset
The S12XECRG generates a Clock Monitor Reset in case all of the following conditions are true:
• Clock monitor is enabled (CME = 1)
• Loss of clock is detected
• Self-Clock Mode is disabled (SCME = 0).
The reset event asynchronously forces the configuration registers to their default settings. In detail the
CME and the SCME are reset to logical ‘1’ (which changes the state of the SCME bit. As a consequence
the S12XECRG immediately enters Self Clock Mode and starts its internal reset sequence. In parallel the
clock quality check starts. As soon as clock quality check indicates a valid Oscillator Clock the
S12XECRG switches to OSCCLK and leaves Self Clock Mode. Since the clock quality checker is running
in parallel to the reset generator, the S12XECRG may leave Self Clock Mode while still completing the
internal reset sequence.
11.5.1.2
Computer Operating Properly Watchdog (COP) Reset
When COP is enabled, the S12XECRG expects sequential write of $55 and $AA (in this order) to the
ARMCOP register during the selected time-out period. Once this is done, the COP time-out period restarts.
If the program fails to do this the S12XECRG will generate a reset.
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11.5.1.3
Power On Reset, Low Voltage Reset
The on-chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power
on reset or low voltage reset or both. As soon as a power on reset or low voltage reset is triggered the
S12XECRG performs a quality check on the incoming clock signal. As soon as clock quality check
indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock. If after 50
check windows the clock quality check indicated a non-valid Oscillator Clock the reset sequence starts
using Self-Clock Mode.
Figure 11-22 and Figure 11-23 show the power-up sequence for cases when the RESET pin is tied to VDD
and when the RESET pin is held low.
Clock Quality Check
(no Self-Clock Mode)
RESET
)(
Internal POR
)(
128 SYSCLK
Internal RESET
64 SYSCLK
)(
Figure 11-22. RESET Pin Tied to VDD (by a Pull-up Resistor)
Clock Quality Check
(no Self Clock Mode)
)(
RESET
Internal POR
)(
128 SYSCLK
Internal RESET
)(
64 SYSCLK
Figure 11-23. RESET Pin Held Low Externally
11.6
Interrupts
The interrupts/reset vectors requested by the S12XECRG are listed in Table 11-17. Refer to MCU
specification for related vector addresses and priorities.
Table 11-17. S12XECRG Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
Real time interrupt
I bit
CRGINT (RTIE)
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Table 11-17. S12XECRG Interrupt Vectors
11.6.1
11.6.1.1
Interrupt Source
CCR
Mask
Local Enable
LOCK interrupt
I bit
CRGINT (LOCKIE)
SCM interrupt
I bit
CRGINT (SCMIE)
Description of Interrupt Operation
Real Time Interrupt
The S12XECRG generates a real time interrupt when the selected interrupt time period elapses. RTI
interrupts are locally disabled by setting the RTIE bit to zero. The real time interrupt flag (RTIF) is set to1
when a timeout occurs, and is cleared to 0 by writing a 1 to the RTIF bit.
The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1. This feature can be used for
periodic wakeup from Pseudo Stop if the RTI interrupt is enabled.
11.6.1.2
IPLL Lock Interrupt
The S12XECRG generates a IPLL Lock interrupt when the LOCK condition of the IPLL has changed,
either from a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting
the LOCKIE bit to zero. The IPLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
11.6.1.3
Self Clock Mode Interrupt
The S12XECRG generates a Self Clock Mode interrupt when the SCM condition of the system has
changed, either entered or exited Self Clock Mode. SCM conditions are caused by a failing clock quality
check after power on reset (POR) or low voltage reset (LVR) or recovery from Full Stop Mode (PSTP =
0) or Clock Monitor failure. For details on the clock quality check refer to Section 11.4.1.4, “Clock Quality
Checker”. If the clock monitor is enabled (CME = 1) a loss of external clock will also cause a SCM
condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to zero. The SCM interrupt flag (SCMIF) is
set to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
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Chapter 12
Pierce Oscillator (S12XOSCLCPV2)
Revision History
Revision
Number
Revision
Date
Author
Description of Changes
01.05
19-Jul-06
All xclks info was removed
02.00
04-Aug-06
incremented revision to match the design system spec revision
12.1
Introduction
The Pierce oscillator (XOSC) module provides a robust, low-noise and low-power clock source. The
module will be operated from the VDDPLL supply rail (1.8 V nominal) and require the minimum number
of external components. It is designed for optimal start-up margin with typical crystal oscillators.
12.1.1
Features
The XOSC will contain circuitry to dynamically control current gain in the output amplitude. This ensures
a signal with low harmonic distortion, low power and good noise immunity.
• High noise immunity due to input hysteresis
• Low RF emissions with peak-to-peak swing limited dynamically
• Transconductance (gm) sized for optimum start-up margin for typical oscillators
• Dynamic gain control eliminates the need for external current limiting resistor
• Integrated resistor eliminates the need for external bias resistor in loop controlled Pierce mode.
• Low power consumption:
— Operates from 1.8 V (nominal) supply
— Amplitude control limits power
• Clock monitor
12.1.2
Modes of Operation
Two modes of operation exist:
1. Loop controlled Pierce (LCP) oscillator
2. External square wave mode featuring also full swing Pierce (FSP) without internal bias resistor
The oscillator mode selection is described in the Device Overview section, subsection Oscillator
Configuration.
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Chapter 12 Pierce Oscillator (S12XOSCLCPV2)
12.1.3
Block Diagram
Figure 12-1 shows a block diagram of the XOSC.
Monitor_Failure
Clock
Monitor
OSCCLK
Peak
Detector
Gain Control
VDDPLL = 1.8 V
Rf
XTAL
EXTAL
Figure 12-1. XOSC Block Diagram
12.2
External Signal Description
This section lists and describes the signals that connect off chip
12.2.1
VDDPLL and VSSPLL — Operating and Ground Voltage Pins
Theses pins provides operating voltage (VDDPLL) and ground (VSSPLL) for the XOSC circuitry. This
allows the supply voltage to the XOSC to use an independent bypass capacitor.
12.2.2
EXTAL and XTAL — Input and Output Pins
These pins provide the interface for either a crystal or a 1.8V CMOS compatible clock to control the
internal clock generator circuitry. EXTAL is the external clock input or the input to the crystal oscillator
amplifier. XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived
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Chapter 12 Pierce Oscillator (S12XOSCLCPV2)
from the EXTAL input frequency. In full stop mode (PSTP = 0), the EXTAL pin is pulled down by an
internal resistor of typical 200 kΩ.
NOTE
Freescale recommends an evaluation of the application board and chosen
resonator or crystal by the resonator or crystal supplier.
Loop controlled circuit is not suited for overtone resonators and crystals.
EXTAL
C1
MCU
Crystal or
Ceramic Resonator
XTAL
C2
VSSPLL
Figure 12-2. Loop Controlled Pierce Oscillator Connections (LCP mode selected)
NOTE
Full swing Pierce circuit is not suited for overtone resonators and crystals
without a careful component selection.
EXTAL
C1
MCU
RB
Crystal or
Ceramic Resonator
RS*
XTAL
C2
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
Figure 12-3. Full Swing Pierce Oscillator Connections (FSP mode selected)
EXTAL
CMOS Compatible
External Oscillator
(VDDPLL Level)
MCU
XTAL
Not Connected
Figure 12-4. External Clock Connections (FSP mode selected)
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12.3
Memory Map and Register Definition
The CRG contains the registers and associated bits for controlling and monitoring the oscillator module.
12.4
Functional Description
The XOSC module has control circuitry to maintain the crystal oscillator circuit voltage level to an optimal
level which is determined by the amount of hysteresis being used and the maximum oscillation range.
The oscillator block has two external pins, EXTAL and XTAL. The oscillator input pin, EXTAL, is
intended to be connected to either a crystal or an external clock source. The XTAL pin is an output signal
that provides crystal circuit feedback.
A buffered EXTAL signal becomes the internal clock. To improve noise immunity, the oscillator is
powered by the VDDPLL and VSSPLL power supply pins.
12.4.1
Gain Control
In LCP mode a closed loop control system will be utilized whereby the amplifier is modulated to keep the
output waveform sinusoidal and to limit the oscillation amplitude. The output peak to peak voltage will be
kept above twice the maximum hysteresis level of the input buffer. Electrical specification details are
provided in the Electrical Characteristics appendix.
12.4.2
Clock Monitor
The clock monitor circuit is based on an internal RC time delay so that it can operate without any MCU
clocks. If no OSCCLK edges are detected within this RC time delay, the clock monitor indicates failure
which asserts self-clock mode or generates a system reset depending on the state of SCME bit. If the clock
monitor is disabled or the presence of clocks is detected no failure is indicated.The clock monitor function
is enabled/disabled by the CME control bit, described in the CRG block description chapter.
12.4.3
Wait Mode Operation
During wait mode, XOSC is not impacted.
12.4.4
Stop Mode Operation
XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled.
During pseudo-stop mode, XOSC is not impacted.
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Chapter 13
Analog-to-Digital Converter (ADC12B16CV1)
Block Description
Revision History
Version
Number
Revision
Date
Effective
Date
V01.00
13 Oct. 2005
13 Oct. 2005
13.1
Author
Description of Changes
Initial version
Introduction
The ADC12B16C is a 16-channel, 12-bit, multiplexed input successive approximation analog-to-digital
converter. Refer to device electrical specifications for ATD accuracy.
13.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Features
8-, 10-, or 12-bit resolution.
Conversion in Stop Mode using internally generated clock
Automatic return to low power after conversion sequence
Automatic compare with interrupt for higher than or less/equal than programmable value
Programmable sample time.
Left/right justified result data.
External trigger control.
Sequence complete interrupt.
Analog input multiplexer for 16 analog input channels.
Special conversions for VRH, VRL, (VRL+VRH)/2.
1-to-16 conversion sequence lengths.
Continuous conversion mode.
Multiple channel scans.
Configurable external trigger functionality on any AD channel or any of four additional trigger
inputs. The four additional trigger inputs can be chip external or internal. Refer to device
specification for availability and connectivity.
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
•
Configurable location for channel wrap around (when converting multiple channels in a sequence).
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.1.2
13.1.2.1
Modes of Operation
Conversion Modes
There is software programmable selection between performing single or continuous conversion on a
single channel or multiple channels.
13.1.2.2
•
•
•
MCU Operating Modes
Stop Mode
— ICLKSTP=0 (in ATDCTL2 register)
Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted
restarts it after exiting stop mode. This has the same effect/consequences as starting a
conversion sequence with write to ATDCTL5. So after exiting from stop mode with a
previously aborted sequence all flags are cleared etc.
— ICLKSTP=1 (in ATDCTL2 register)
A/D conversion sequence seamless continues in Stop Mode based on the internally generated
clock ICLK as ATD clock. For conversions during transition from Run to Stop Mode or vice
versa the result is not written to the results register, no CCF flag is set and no compare is done.
When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is
required to switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access
ATD registers during this time.
Wait Mode
ADC12B16C behaves same in Run and Wait Mode. For reduced power consumption continuos
conversions should be aborted before entering Wait mode.
Freeze Mode
In Freeze Mode the ADC12B16C will either continue or finish or stop converting according to the
FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
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13.1.3
Block Diagram
Bus Clock
ICLK
Clock
Prescaler
Internal
Clock
ATD Clock
ETRIG0
ETRIG1
ETRIG2
Trigger
Mux
Mode and
ATD_12B16C
Sequence Complete
Interrupt
Compare Interrupt
Timing Control
ETRIG3
(See device specification for availability
and connectivity)
ATDCTL1
ATDDIEN
VDDA
VSSA
Successive
Approximation
Register (SAR)
and DAC
VRH
VRL
AN15
AN14
AN13
Results
ATD 0
ATD 1
ATD 2
ATD 3
ATD 4
ATD 5
ATD 6
ATD 7
ATD 8
ATD 9
ATD 10
ATD 11
ATD 12
ATD 13
ATD 14
ATD 15
AN12
AN11
+
AN10
Sample & Hold
AN9
-
AN8
AN7
Analog
MUX
Comparator
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Figure 13-1. ADC12B16C Block Diagram
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.2
Signal Description
This section lists all inputs to the ADC12B16C block.
13.2.1
Detailed Signal Descriptions
13.2.1.1
ANx (x = 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
13.2.1.2
ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connection of these inputs!
13.2.1.3
VRH, VRL
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
13.2.1.4
VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC12B16C block.
13.3
Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC12B16C.
13.3.1
Module Memory Map
Figure 13-2 gives an overview on all ADC12B16C registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address
Name
0x0000
ATDCTL0
0x0001
ATDCTL1
0x0002
ATDCTL2
Bit 7
R
Reserved
W
R
ETRIGSEL
W
R
0
W
6
0
5
0
SRES1
SRES0
AFFC
4
0
3
2
1
Bit 0
WRAP3
WRAP2
WRAP1
WRAP0
SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
ICLKSTP ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACMPIE
= Unimplemented or Reserved
Figure 13-2. ADC12B16C Register Summary (Sheet 1 of 3)
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Address
Name
0x0003
ATDCTL3
0x0004
ATDCTL4
0x0005
ATDCTL5
0x0006
ATDSTAT0
0x0007
Unimplemented
0x0008
ATDCMPEH
0x0009
ATDCMPEL
0x000A
ATDSTAT2H
0x000B
ATDSTAT2L
0x000C
ATDDIENH
0x000D
ATDDIENL
0x000E ATDCMPHTH
0x000F ATDCMPHTL
0x0010
ATDDR0
0x0012
ATDDR1
0x0014
ATDDR2
0x0016
ATDDR3
0x0018
ATDDR4
0x001A
ATDDR5
0x001C
ATDDR6
0x001E
ATDDR7
0x0020
ATDDR8
0x0022
ATDDR9
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
Bit 7
6
5
4
3
2
1
Bit 0
DJM
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
SMP2
SMP1
SMP0
SC
SCAN
MULT
ETORF
FIFOR
0
0
0
SCF
0
0
0
PRS[4:0]
CD
CC
CB
CA
CC3
CC2
CC1
CC0
0
0
0
0
CMPE[15:8]
CMPE[7:0]
CCF[15:8]
CCF[7:0]
IEN[15:8]
IEN[7:0]
CMPHT[15:8]
CMPHT[7:0]
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
= Unimplemented or Reserved
Figure 13-2. ADC12B16C Register Summary (Sheet 2 of 3)
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Address
Name
0x0024
ATDDR10
0x0026
ATDDR11
0x0028
ATDDR12
0x002A
ATDDR13
0x002C
ATDDR14
0x002E
ATDDR15
Bit 7
R
W
R
W
R
W
R
W
R
W
R
W
6
5
4
3
2
1
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
Bit 0
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
See Section 13.3.2.12.1, “Left Justified Result Data (DJM=0)”
and Section 13.3.2.12.2, “Right Justified Result Data (DJM=1)”
= Unimplemented or Reserved
Figure 13-2. ADC12B16C Register Summary (Sheet 3 of 3)
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.3.2
Register Descriptions
This section describes in address order all the ADC12B16C registers and their individual bits.
13.3.2.1
ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence.
Module Base + 0x0000
7
R
W
Reserved
Reset
0
6
5
4
0
0
0
0
0
0
3
2
1
0
WRAP3
WRAP2
WRAP1
WRAP0
1
1
1
1
= Unimplemented or Reserved
Figure 13-3. ATD Control Register 0 (ATDCTL0)
Read: Anytime
Write: Anytime, in special modes always write 0 to Reserved Bit 7.
Table 13-1. ATDCTL0 Field Descriptions
Field
3-0
WRAP[3-0]
Description
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
multi-channel conversions. The coding is summarized in Table 13-2.
Table 13-2. Multi-Channel Wrap Around Coding
WRAP3 WRAP2 WRAP1 WRAP0
Multiple Channel Conversions (MULT = 1)
Wraparound to AN0 after Converting
0
0
0
0
Reserved1
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
AN8
1
0
0
1
AN9
1
0
1
0
AN10
1
0
1
1
AN11
1
1
0
0
AN12
1
1
0
1
AN13
1
1
1
0
AN14
1
1
1
1
AN15
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1
If only AN0 should be converted use MULT=0.
13.3.2.2
ATD Control Register 1 (ATDCTL1)
Writes to this register will abort current conversion sequence.
Module Base + 0x0001
7
6
5
4
3
2
1
0
ETRIGSEL
SRES1
SRES0
SMP_DIS
ETRIGCH3
ETRIGCH2
ETRIGCH1
ETRIGCH0
0
0
1
0
1
1
1
1
R
W
Reset
Figure 13-4. ATD Control Register 1 (ATDCTL1)
Read: Anytime
Write: Anytime
Table 13-3. ATDCTL1 Field Descriptions
Field
Description
7
ETRIGSEL
External Trigger Source Select — This bit selects the external trigger source to be either one of the AD
channels or one of the ETRIG3-0 inputs. See device specification for availability and connectivity of ETRIG3-0
inputs. If a particular ETRIG3-0 input option is not available, writing a 1 to ETRISEL only sets the bit but has
not effect, this means that one of the AD channels (selected by ETRIGCH3-0) is configured as the source for
external trigger. The coding is summarized in Table 13-5.
6–5
SRES[1:0]
A/D Resolution Select — These bits select the resolution of A/D conversion results. See Table 13-4 for
coding.
4
SMP_DIS
Discharge Before Sampling Bit
0 No discharge before sampling.
1 The internal sample capacitor is discharged before sampling the channel. This adds 2 ATD clock cycles to
the sampling time. This can help to detect an open circuit instead of measuring the previous sampled
channel.
3–0
External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG3-0 inputs
ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Table 13-5.
Table 13-4. A/D Resolution Coding
SRES1
SRES0
A/D Resolution
0
0
8-bit data
0
1
10-bit data
1
0
12-bit data
1
1
Reserved
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Table 13-5. External Trigger Channel Select Coding
1
ETRIGSEL
ETRIGCH3
ETRIGCH2
ETRIGCH1
ETRIGCH0
External trigger source is
0
0
0
0
0
AN0
0
0
0
0
1
AN1
0
0
0
1
0
AN2
0
0
0
1
1
AN3
0
0
1
0
0
AN4
0
0
1
0
1
AN5
0
0
1
1
0
AN6
0
0
1
1
1
AN7
0
1
0
0
0
AN8
0
1
0
0
1
AN9
0
1
0
1
0
AN10
0
1
0
1
1
AN11
0
1
1
0
0
AN12
0
1
1
0
1
AN13
0
1
1
1
0
AN14
0
1
1
1
1
AN15
1
0
0
0
0
ETRIG01
1
0
0
0
1
ETRIG11
1
0
0
1
0
ETRIG21
1
0
0
1
1
ETRIG31
1
0
1
X
X
Reserved
1
1
X
X
X
Reserved
Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
13.3.2.3
ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Module Base + 0x0002
7
R
6
5
4
3
2
1
0
AFFC
ICLKSTP
ETRIGLE
ETRIGP
ETRIGE
ASCIE
ACMPIE
0
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 13-5. ATD Control Register 2 (ATDCTL2)
Read: Anytime
Write: Anytime
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Table 13-6. ATDCTL2 Field Descriptions
Field
Description
6
AFFC
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
5
ICLKSTP
Internal Clock in Stop Mode Bit — This bit enables A/D conversions in stop mode. When going into stop mode
and ICLKSTP=1 the ATD conversion clock is automatically switched to the internally generated clock ICLK.
Current conversion sequence will seamless continue. Conversion speed will change from prescaled bus
frequency to the ICLK frequency (see ATD Electrical Characteristics in device description). The prescaler bits
PRS4-0 in ATDCTL4 have no effect on the ICLK frequency. For conversions during stop mode the automatic
compare interrupt or the sequence complete interrupt can be used to inform software handler about changing
A/D values. External trigger will not work while converting in stop mode. For conversions during transition from
Run to Stop Mode or vice versa the result is not written to the results register, no CCF flag is set and no compare
is done. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to
switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
0 If A/D conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be
aborted and automatically restarted when exiting stop mode.
1 A/D continues to convert in stop mode using internally generated clock (ICLK)
4
ETRIGLE
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 13-7 for details.
3
ETRIGP
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 13-7 for details.
2
ETRIGE
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in Table 13-5. If external trigger source is one of the AD channels, the digital input
buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external
events. External trigger will not work while converting in stop mode.
0 Disable external trigger
1 Enable external trigger
1
ASCIE
0
ACMPIE
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare
Interrupt will be requested whenever any of the respective CCF flags is set.
Table 13-7. External Trigger Configurations
ETRIGLE
ETRIGP
External Trigger Sensitivity
0
0
Falling edge
0
1
Rising edge
1
0
Low level
1
1
High level
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.3.2.4
ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Module Base + 0x0003
7
6
5
4
3
2
1
0
DJM
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
0
0
1
0
0
0
0
0
R
W
Reset
= Unimplemented or Reserved
Figure 13-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime
Write: Anytime
Table 13-8. ATDCTL3 Field Descriptions
Field
Description
7
DJM
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 13-9 gives examples ATD results for an input signal range between 0 and 5.12 Volts.
6–3
S8C, S4C,
S2C, S1C
Conversion Sequence Length — These bits control the number of conversions per sequence. Table 13-10
shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
to HC12 family.
2
FIFO
Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first conversion appears in the first result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
file, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the first
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode
may or may not be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC12B16C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
1–0
FRZ[1:0]
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in Table 13-11. Leakage onto the storage node and comparator reference capacitors
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Table 13-9. Examples of ideal decimal ATD Results
Input Signal
VRL = 0 Volts
VRH = 5.12 Volts
8-Bit
Codes
(resolution=20mV)
10-Bit
Codes
(resolution=5mV)
12-Bit
Codes
(transfer curve has
1.25mV offset)
(resolution=1.25mV)
5.120 Volts
...
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.003
0.002
0.000
255
...
1
1
1
1
1
1
1
0
0
0
0
0
0
1023
...
4
4
4
3
3
2
2
2
1
1
0
0
0
4095
...
17
16
14
12
11
9
8
6
4
3
2
1
0
Table 13-10. Conversion Sequence Length Coding
S8C
S4C
S2C
S1C
Number of Conversions
per Sequence
0
0
0
0
16
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Table 13-11. ATD Behavior in Freeze Mode (Breakpoint)
13.3.2.5
FRZ1
FRZ0
Behavior in Freeze Mode
0
0
Continue conversion
0
1
Reserved
1
0
Finish current conversion, then freeze
1
1
Freeze Immediately
ATD Control Register 4 (ATDCTL4)
Writes to this register will abort current conversion sequence.
Module Base + 0x0004
7
6
5
SMP2
SMP1
SMP0
0
0
0
4
3
2
1
0
0
1
R
PRS[4:0]
W
Reset
0
0
1
Figure 13-7. ATD Control Register 4 (ATDCTL4)
Read: Anytime
Write: Anytime
Table 13-12. ATDCTL4 Field Descriptions
Field
Description
7–5
SMP[2:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 13-13 lists the available sample time lengths.
4–0
PRS[4:0]
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
f BUS
f ATDCLK = ------------------------------------2 × ( PRS + 1 )
Refer to Device Specification for allowed frequency range of fATDCLK.
Table 13-13. Sample Time Select
SMP2
SMP1
SMP0
Sample Time
in Number of
ATD Clock Cycles
0
0
0
4
0
0
1
6
0
1
0
8
0
1
1
10
1
0
0
12
1
0
1
16
1
1
0
20
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Table 13-13. Sample Time Select
13.3.2.6
SMP2
SMP1
SMP0
Sample Time
in Number of
ATD Clock Cycles
1
1
1
24
ATD Control Register 5 (ATDCTL5)
Writes to this register will abort current conversion sequence and start a new conversion sequence. If
external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a
conversion sequence which will then occur on each trigger event. Start of conversion means the beginning
of the sampling phase.
Module Base + 0x0005
7
R
6
5
4
3
2
1
0
SC
SCAN
MULT
CD
CC
CB
CA
0
0
0
0
0
0
0
0
W
Reset
0
Figure 13-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime
Write: Anytime
Table 13-14. ATDCTL5 Field Descriptions
Field
Description
6
SC
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,
CC, CB and CA of ATDCTL5. Table 13-15 lists the coding.
0 Special channel conversions disabled
1 Special channel conversions enabled
5
SCAN
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means
external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Table 13-14. ATDCTL5 Field Descriptions (continued)
Field
Description
4
MULT
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0).
0 Sample only one channel
1 Sample across several channels
3–0
CD, CC,
CB, CA
Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are
sampled and converted to digital codes. Table 13-15 lists the coding used to select the various analog input
channels.
In the case of single channel conversions (MULT=0), this selection code specifies the channel to be examined.
In the case of multiple channel conversions (MULT=1), this selection code specifies the first channel to be
examined in the conversion sequence. Subsequent channels are determined by incrementing the channel
selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel
Select Bits WRAP3-0 in ATDCTL0). In case of starting with a channel number higher than the one defined by
WRAP3-0 the first wrap around will be AN15 to AN0.
Table 13-15. Analog Input Channel Select Coding
SC
CD
CC
CB
CA
Analog Input
Channel
0
0
0
0
0
AN0
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
AN8
1
0
0
1
AN9
1
0
1
0
AN10
1
0
1
1
AN11
1
1
0
0
AN12
1
1
0
1
AN13
1
1
1
0
AN14
1
1
1
1
AN15
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Table 13-15. Analog Input Channel Select Coding
SC
CD
CC
CB
CA
Analog Input
Channel
1
0
0
0
0
Reserved
0
0
0
1
Reserved
0
0
1
X
Reserved
0
1
0
0
VRH
0
1
0
1
VRL
0
1
1
0
(VRH+VRL) / 2
0
1
1
1
Reserved
1
X
X
X
Reserved
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.3.2.7
ATD Status Register 0 (ATDSTAT0)
This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and
the conversion counter.
Module Base + 0x0006
7
R
6
5
4
ETORF
FIFOR
0
0
0
SCF
3
2
1
0
CC3
CC2
CC1
CC0
0
0
0
0
W
Reset
0
0
= Unimplemented or Reserved
Figure 13-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime
Write: Anytime (No effect on (CC3, CC2, CC1, CC0))
Table 13-16. ATDSTAT0 Field Descriptions
Field
Description
7
SCF
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared
when one of the following occurs:
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and read of a result register
0 Conversion sequence not completed
1 Conversion sequence has completed
5
ETORF
External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE=0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
A) Write “1” to ETORF
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No External trigger over run error has occurred
1 External trigger over run error has occurred
4
FIFOR
Result Register Over Run Flag — This bit indicates that a result register has been written to before its
associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode
because the flag potentially indicates that result registers are out of sync with the input channels. However, it is
also practical for non-FIFO modes, and indicates that a result register has been over written before it has been
read (i.e. the old data has been lost). This flag is cleared when one of the following occurs:
A) Write “1” to FIFOR
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No over run has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag was still set)
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Table 13-16. ATDSTAT0 Field Descriptions (continued)
Field
Description
3–0
CC[3:0]
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,
CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO
mode (FIFO=0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If
in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counters wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.
13.3.2.8
ATD Compare Enable Register (ATDCMPE)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x0008
15
14
13
12
11
10
9
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CMPE[15:0]
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-10. ATD Compare Enable Register (ATDCMPE)
Table 13-17. ATDCMPE Field Descriptions
Field
Description
15–0
Compare Enable for Conversion Number n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence
CMPE[15:0] — These bits enable automatic compare of conversion results individually for conversions of a sequence. The
sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT register.
For each conversion number with CMPE[n]=1 do the following:
1) Write compare value to ATDDRn result register
2) Write compare operator with CMPHT[n] in ATDCPMHT register
CCF[n] in ATDSTAT2 register will flag individual success of any comparison.
0 No automatic compare
1 Automatic compare of results for conversion n of a sequence is enabled.
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.3.2.9
ATD Status Register 2 (ATDSTAT2)
This read-only register contains the Conversion Complete Flags CCF[15:0].
Module Base + 0x000A
15
14
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CCF[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-11. ATD Status Register 2 (ATDSTAT2)
Read: Anytime
Write: Anytime, no effect
Table 13-18. ATDSTAT2 Field Descriptions
Field
Description
15–0
CCF[15:0]
Conversion Complete Flag n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete
flag is set at the end of each conversion in a sequence. The flags are associated with the conversion position in
a sequence (and also the result register number). Therefore in non-fifo mode, CCF[8] is set when the ninth
conversion in a sequence is complete and the result is available in result register ATDDR8; CCF[9] is set when
the tenth conversion in a sequence is complete and the result is available in ATDDR9, and so forth.
If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete flag
is only set if comparison with ATDDRn is true and if ACMPIE=1 a compare interrupt will be requested. In this
case, as the ATDDRn result register is used to hold the compare value, the result will not be stored there at the
end of the conversion but is lost.
A flag CCF[n] is cleared when one of the following occurs:
A) Write to ATDCTL5 (a new conversion sequence is started)
B) If AFFC=0, write “1” to CCF[n]
C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn
D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn
In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing
by methods B) or C) or D) will be overwritten by the set.
0 Conversion number n not completed or successfully compared
1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn.
If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare
operator CMPGT[n] is true. (No result available in ATDDRn)
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.3.2.10 ATD Input Enable Register (ATDDIEN)
Module Base + 0x000C
15
14
13
12
11
10
9
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
IEN[15:0]
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-12. ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
Table 13-19. ATDDIEN Field Descriptions
Field
Description
15–0
IEN[15:0]
ATD Digital Input Enable on channel x (x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls
the digital input buffer from the analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
13.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x000E
15
14
13
12
11
10
9
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
CMPHT[15:0]
W
Reset
8
0
0
0
0
0
0
0
0
0
Figure 13-13. ATD Compare Higher Than Register (ATDCMPHT)
Table 13-20. ATDCMPHT Field Descriptions
Field
Description
15–0
Compare Operation Higher Than Enable for conversion number n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5,
CMPHT[15:0] 4, 3, 2, 1, 0) of a Sequence — This bit selects the operator for comparison of conversion results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.3.2.12 ATD Conversion Result Registers (ATDDRn)
The A/D conversion results are stored in 16 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL5.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Read: Anytime
Write: Anytime
NOTE
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
13.3.2.12.1 Left Justified Result Data (DJM=0)
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15
15
R
W
Reset
14
13
Bit 11 Bit 10 Bit 9
0
0
0
12
11
10
9
8
7
6
5
4
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
3
2
1
0
0
0
0
0
0
0
0
0
Figure 13-14. Left justified ATD conversion result register (ATDDRn)
13.3.2.12.2 Right Justified Result Data (DJM=1)
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15
R
15
14
13
12
0
0
0
0
0
0
0
0
W
Reset
11
10
9
Bit 11 Bit 10 Bit 9
0
0
0
8
7
6
5
4
3
2
1
0
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bi1 1
Bit 0
0
0
0
0
0
0
0
0
0
Figure 13-15. Right justified ATD conversion result register (ATDDRn)
Table 13-15 shows how depending on the A/D resolution the conversion result is transferred to the ATD
result registers. Compare is always done using all 12 bits of both the conversion result and the compare
value in ATDDRn.
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
Table 13-21. Conversion result mapping to ATDDRn
A/D
resolution
DJM
conversion result mapping to
ATDDRn
8-bit data
0
Bit[11:4] = result, Bit[3:0]=0000
8-bit data
1
Bit[7:0] = result, Bit[11:8]=0000
10-bit data
0
Bit[11:2] = result, Bit[1:0]=00
10-bit data
1
Bit[9:0] = result, Bit[11:10]=00
12-bit data
X
Bit[11:0] = result
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.4
Functional Description
The ADC12B16C is structured into an analog sub-block and a digital sub-block.
13.4.1
Analog Sub-Block
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.
13.4.1.1
Sample and Hold Machine
The Sample and Hold (S/H) Machine accepts analog signals from the external world and stores them as
capacitor charge on a storage node.
During the sample process the analog input connects directly to the storage node.
The input analog signals are unipolar and must fall within the potential range of VSSA to VDDA.
During the hold process the analog input is disconnected from the storage node.
13.4.1.2
Analog Input Multiplexer
The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold
machine.
13.4.1.3
Analog-to-Digital (A/D) Machine
The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8
or 10 or 12 bits. The A/D machine uses a successive approximation architecture. It functions by comparing
the stored analog sample potential with a series of digitally generated analog potentials. By following a
binary search algorithm, the A/D machine locates the approximating potential that is nearest to the
sampled potential.
When not converting the A/D machine is automatically powered down.
Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result
in a non-railed digital output code.
13.4.2
Digital Sub-Block
This subsection explains some of the digital features in more detail. See Section 13.3.2, “Register
Descriptions” for all details.
13.4.2.1
External Trigger Input
The external trigger feature allows the user to synchronize ATD conversions to the external environment
events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
be edge or level sensitive with polarity control. Table 13-22 gives a brief description of the different
combinations of control bits and their effect on the external trigger function.
Table 13-22. External Trigger Control Bits
ETRIGLE
ETRIGP
ETRIGE
SCAN
Description
X
X
0
0
Ignores external trigger. Performs one
conversion sequence and stops.
X
X
0
1
Ignores external trigger. Performs
continuous conversion sequences.
0
0
1
X
Falling edge triggered. Performs one
conversion sequence per trigger.
0
1
1
X
Rising edge triggered. Performs one
conversion sequence per trigger.
1
0
1
X
Trigger active low. Performs continuous
conversions while trigger is active.
1
1
1
X
Trigger active high. Performs continuous
conversions while trigger is active.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
In either level or edge triggered modes, the first conversion begins when the trigger is received.
Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be
triggered externally.
If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion
sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left asserted in
level mode while a sequence is completing, another sequence will be triggered immediately.
13.4.2.2
General-Purpose Digital Port Operation
The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are
multiplexed and sampled as analog channels to the A/D converter. The analog/digital multiplex operation
is performed in the input pads. The input pad is always connected to the analog input channels of the
ADC12B16C. The input pad signal is buffered to the digital port registers. This buffer can be turned on or
off with the ATDDIEN register. This is important so that the buffer does not draw excess current when
analog potentials are presented at its input.
13.5
Resets
At reset the ADC12B16C is in a power down state. The reset state of each individual bit is listed within
the Register Description section (see Section 13.3.2, “Register Descriptions”) which details the registers
and their bit-field.
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Chapter 13 Analog-to-Digital Converter (ADC12B16CV1) Block Description
13.6
Interrupts
The interrupts requested by the ADC12B16C are listed in Table 13-23. Refer to MCU specification for
related vector address and priority.
Table 13-23. ATD Interrupt Vectors
Interrupt Source
CCR
Mask
Local Enable
Sequence Complete Interrupt
I bit
ASCIE in ATDCTL2
Compare Interrupt
I bit
ACMPIE in ATDCTL2
See Section 13.3.2, “Register Descriptions” for further details.
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Chapter 14
Enhanced Capture Timer (ECT16B8CV3)
14.1
Revision History
Version
Number
Revision
Date
Effective
Date
02.03
12-Aug-04
12-Aug-04
• Included OC initialization description in section 4.2.2 and
updated version on cover sheet.
03.00
15-Oct-05
15-Oct-05
• Added register OCPD(1.4.2.25) to isolate OCx from pin logic and
also updated the information of OC initialization in section 4.2.2.
03.01
21 Nov 05
21 Nov 05
• Verbage modified for OCPD and 1.4.1.2 sections
12 Apr 07
• Removed redundant memory map table, corrected MCCNT[9] to
MCCNT[0] in register summary sheet (5 of 6), Removed Memory
Map table (since the information is redundant) in register
summary figure.
03.01
03 Apr 07
14.2
Author
Description of Changes
Introduction
The HCS12 enhanced capture timer module has the features of the HCS12 standard timer module
enhanced by additional features in order to enlarge the field of applications, in particular for automotive
ABS applications.
This design specification describes the standard timer as well as the additional features.
The basic timer consists of a 16-bit, software-programmable counter driven by a prescaler. This timer can
be used for many purposes, including input waveform measurements while simultaneously generating an
output waveform. Pulse widths can vary from microseconds to many seconds.
A full access for the counter registers or the input capture/output compare registers will take place in one
clock cycle. Accessing high byte and low byte separately for all of these registers will not yield the same
result as accessing them in one word.
14.2.1
•
•
•
•
Features
16-bit buffer register for four input capture (IC) channels.
Four 8-bit pulse accumulators with 8-bit buffer registers associated with the four buffered IC
channels. Configurable also as two 16-bit pulse accumulators.
16-bit modulus down-counter with 8-bit prescaler.
Four user-selectable delay counters for input noise immunity increase.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.2.2
•
•
•
•
Modes of Operation
Stop — Timer and modulus counter are off since clocks are stopped.
Freeze — Timer and modulus counter keep on running, unless the TSFRZ bit in the TSCR1 register
is set to one.
Wait — Counters keep on running, unless the TSWAI bit in the TSCR1 register is set to one.
Normal — Timer and modulus counter keep on running, unless the TEN bit in the TSCR1 register
or the MCEN bit in the MCCTL register are cleared.
14.2.3
Block Diagram
Bus Clock
Prescaler
Channel 0
Input Capture
16-bit Counter
Output Compare
Channel 1
Input Capture
Modulus Counter
Interrupt
16-Bit Modulus Counter
Output Compare
IOC0
IOC1
Channel 2
Input Capture
Output Compare
Timer Overflow
Interrupt
Timer Channel 0
Interrupt
Channel 3
Input Capture
Output Compare
Registers
Channel 4
Input Capture
Output Compare
Channel 5
Input Capture
Output Compare
Timer Channel 7
Interrupt
PA Overflow
Interrupt
PA Input
Interrupt
PB Overflow
Interrupt
16-Bit
Pulse Accumulator A
16-Bit
Pulse Accumulator B
Channel 6
Input Capture
Output Compare
Channel 7
Input Capture
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
Output Compare
Figure 14-1. ECT Block Diagram
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14.3
External Signal Description
The ECT module has a total of eight external pins.
14.3.1
IOC7 — Input Capture and Output Compare Channel 7
This pin serves as input capture or output compare for channel 7.
14.3.2
IOC6 — Input Capture and Output Compare Channel 6
This pin serves as input capture or output compare for channel 6.
14.3.3
IOC5 — Input Capture and Output Compare Channel 5
This pin serves as input capture or output compare for channel 5.
14.3.4
IOC4 — Input Capture and Output Compare Channel 4
This pin serves as input capture or output compare for channel 4.
14.3.5
IOC3 — Input Capture and Output Compare Channel 3
This pin serves as input capture or output compare for channel 3.
14.3.6
IOC2 — Input Capture and Output Compare Channel 2
This pin serves as input capture or output compare for channel 2.
14.3.7
IOC1 — Input Capture and Output Compare Channel 1
This pin serves as input capture or output compare for channel 1.
14.3.8
IOC0 — Input Capture and Output Compare Channel 0
This pin serves as input capture or output compare for channel 0.
NOTE
For the description of interrupts see Section 14.5.3, “Interrupts”.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4
Memory Map and Register Definition
This section provides a detailed description of all memory and registers.
14.4.1
Module Memory Map
The memory map for the ECT module is given below in the Table 14-2. The address listed for each register
is the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
14.4.2
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
R
0
0
0
0
0
0
0
0
W
FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
0x0004
R
TCNT (High) W
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
0x0005
R
TCNT (Low) W
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
TEN
TSWAI
TSFRZ
TFFCA
PRNT
0
0
0
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
0x0000
TIOS
0x0001
CFORC
0x0002
OC7M
0x0003
OC7D
0x0006
TSCR1
0x0007
TTOF
0x0008
TCTL1
R
W
R
W
R
W
R
W
R
W
R
W
= Unimplemented or Reserved
Figure 14-2. ECT Register Summary (Sheet 1 of 6)
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Register
Name
0x0009
TCTL2
W
0x000A
TCTL3
W
0x000B
TCTL4
0x000C
TIE
R
R
R
W
R
W
Bit 7
6
5
4
3
2
1
Bit 0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
= Unimplemented or Reserved
Figure 14-2. ECT Register Summary (Sheet 2 of 6)
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Register
Name
Bit 7
0x000D
TSCR2
W
0x000E
TFLG1
W
0x000F
TFLG2
R
R
R
W
TOI
C7F
TOF
6
5
4
3
2
1
Bit 0
0
0
0
TCRE
PR2
PR1
PR0
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
0x0010
R
TC0 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x0011
TC0 (Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0012
R
TC1 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x0013
TC1 (Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0014
R
TC2 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x0015
TC2 (Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0016
R
TC3 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x0017
TC3 (Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0018
R
TC4 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x0019
TC4 (Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x001A
R
TC5 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x001B
TC5 (Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
W
R
W
R
W
R
W
R
W
R
W
= Unimplemented or Reserved
Figure 14-2. ECT Register Summary (Sheet 3 of 6)
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x001C
R
TC6 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x001D
TC6 (Low)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x001E
R
TC7 (High) W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0x001F
TC7 (Low)
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0020
PACTL
W
PAEN
PAMOD
PEDGE
CLK1
CLK0
PA0VI
PAI
0
0
0
0
0
PA0VF
PAIF
0x0021
PAFLG
0x0022
PACN3
0x0023
PACN2
0x0024
PACN1
0x0025
PACN0
R
W
R
R
R
0
W
R
W
R
W
R
W
R
W
0x0026
MCCTL
W
0x0027
MCFLG
W
0x0028
ICPAR
0
R
R
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)
PACNT7
PACNT6
PACNT5
PACNT4
R
W
0x002A
ICOVW
W
R
PACNT2
PACNT1
PACNT0
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10) PACNT1(9) PACNT0(8)
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
MCZI
MODMC
RDMCL
0
0
ICLAT
FLMC
0
0
0
0
0
0
0
DLY7
DLY6
DLY5
NOVW7
NOVW6
NOVW5
MCZF
PACNT2
PACNT1
PACNT0
MCEN
MCPR1
MCPR0
POLF3
POLF2
POLF1
POLF0
PA3EN
PA2EN
PA1EN
PA0EN
DLY4
DLY3
DLY2
DLY1
DLY0
NOVW4
NOVW3
NOVW2
NOVW1
NOVW0
W
0x0029
DLYCT
PACNT3
= Unimplemented or Reserved
Figure 14-2. ECT Register Summary (Sheet 4 of 6)
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Register
Name
0x002B
ICSYS
W
0x002C
OCPD
W
0x002D
TIMTST
0x002E
PTPSR
R
R
0x0031
PBFLG
6
5
4
3
2
1
Bit 0
SH37
SH26
SH15
SH04
TFMOD
PACMX
BUFEN
LATQ
OCPD7
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
R
Timer Test Register
W
R
W
0x002F
R
PTMCPSR W
0x0030
PBCTL
Bit 7
R
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
PTMPS7
PTMPS6
PTMPS5
PTMPS4
PTMPS3
PTMPS2
PTMPS1
PTMPS0
0
0
0
0
0
W
PBOVI
0
0
0
0
0
0
0
PA3H7
PA3H6
PA3H5
PA3H4
PA3H3
PA3H2
PA3H1
PA3H0
PA2H7
PA2H6
PA2H5
PA2H4
PA2H3
PA2H2
PA2H1
PA2H0
PA1H7
PA1H6
PA1H5
PA1H4
PA1H3
PA1H2
PA1H1
PA1H0
PA0H7
PA0H6
PA0H5
PA0H4
PA0H3
PA0H2
PA0H1
PA0H0
MCCNT14
MCCNT13
MCCNT12
MCCNT11
MCCNT10
MCCNT9
MCCNT8
MCCNT7
MCCNT6
MCCNT5
MCCNT4
MCCNT3
MCCNT2
MCCNT1
MCCNT0
0x0038
R
TC0H (High) W
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0x0039
R
TC0H (Low)
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0x0032
PA3H
0x0033
PA2H
0x0034
PA1H
0x0035
PA0H
R
PBEN
W
R
PBOVF
0
W
R
W
R
W
R
W
0x0036
MCCNT
(High)
R
W MCCNT15
0x0037
MCCNT
(Low)
W
R
= Unimplemented or Reserved
Figure 14-2. ECT Register Summary (Sheet 5 of 6)
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Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x003A
R
TC1H (High) W
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0x003B
R
TC1H (Low) W
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0x003C
R
TC2H (High) W
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0x003D
R
TC2H (Low) W
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0x003E
R
TC3H (High) W
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0x003F
R
TC3H (Low) W
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
= Unimplemented or Reserved
Figure 14-2. ECT Register Summary (Sheet 6 of 6)
14.4.2.1
Timer Input Capture/Output Compare Select Register (TIOS)
Module Base + 0x0000
R
W
Reset
7
6
5
4
3
2
1
0
IOS7
IOS6
IOS5
IOS4
IOS3
IOS2
IOS1
IOS0
0
0
0
0
0
0
0
0
Figure 14-3. Timer Input Capture/Output Compare Register (TIOS)
Read or write: Anytime
All bits reset to zero.
Table 14-1. TIOS Field Descriptions
Field
7:0
IOS[7:0]
Description
Input Capture or Output Compare Channel Configuration
0 The corresponding channel acts as an input capture.
1 The corresponding channel acts as an output compare.
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14.4.2.2
Timer Compare Force Register (CFORC)
Module Base + 0x0001
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
FOC7
FOC6
FOC5
FOC4
FOC3
FOC2
FOC1
FOC0
0
0
0
0
0
0
0
0
Reset
Figure 14-4. Timer Compare Force Register (CFORC)
Read or write: Anytime but reads will always return 0x0000 (1 state is transient).
All bits reset to zero.
Table 14-2. CFORC Field Descriptions
Field
Description
7:0
FOC[7:0]
Force Output Compare Action for Channel 7:0 — A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare “x” to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not
get set.
Note: A successful channel 7 output compare overrides any channel 6:0 compares. If a forced output compare
on any channel occurs at the same time as the successful output compare, then the forced output compare
action will take precedence and the interrupt flag will not get set.
14.4.2.3
Output Compare 7 Mask Register (OC7M)
Module Base + 0x0002
R
W
Reset
7
6
5
4
3
2
1
0
OC7M7
OC7M6
OC7M5
OC7M4
OC7M3
OC7M2
OC7M1
OC7M0
0
0
0
0
0
0
0
0
Figure 14-5. Output Compare 7 Mask Register (OC7M)
Read or write: Anytime
All bits reset to zero.
Table 14-3. OC7M Field Descriptions
Field
Description
7:0
OC7M[7:0]
Output Compare Mask Action for Channel 7:0
0 The corresponding OC7Dx bit in the output compare 7 data register will not be transferred to the timer port on
a successful channel 7 output compare, even if the corresponding pin is setup for output compare.
1 The corresponding OC7Dx bit in the output compare 7 data register will be transferred to the timer port on a
successful channel 7 output compare.
Note: The corresponding channel must also be setup for output compare (IOSx = 1) for data to be transferred
from the output compare 7 data register to the timer port.
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14.4.2.4
Output Compare 7 Data Register (OC7D)
Module Base + 0x0003
R
W
Reset
7
6
5
4
3
2
1
0
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
0
0
0
0
0
0
0
0
Figure 14-6. Output Compare 7 Data Register (OC7D)
Read or write: Anytime
All bits reset to zero.
Table 14-4. OC7D Field Descriptions
Field
7:0
OC7D[7:0]
Description
Output Compare 7 Data Bits — A channel 7 output compare can cause bits in the output compare 7 data
register to transfer to the timer port data register depending on the output compare 7 mask register.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.5
Timer Count Register (TCNT)
Module Base + 0x0004
R
W
Reset
15
14
13
12
11
10
9
8
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
0
0
0
0
0
0
0
0
Figure 14-7. Timer Count Register High (TCNT)
Module Base + 0x0005
R
W
Reset
7
6
5
4
3
2
1
0
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
0
0
0
0
0
0
0
0
Figure 14-8. Timer Count Register Low (TCNT)
Read: Anytime
Write: Writable in special modes.
All bits reset to zero.
Table 14-5. TCNT Field Descriptions
Field
Description
15:0
Timer Counter Bits — The 16-bit main timer is an up counter. A read to this register will return the current value
TCNT[15:0] of the counter. Access to the counter register will take place in one clock cycle.
Note: A separate read/write for high byte and low byte in test mode will give a different result than accessing
them as a word. The period of the first count after a write to the TCNT registers may be a different size
because the write is not synchronized with the prescaler clock.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.6
Timer System Control Register 1 (TSCR1)
Module Base + 0x0006
7
R
W
Reset
6
5
4
3
TEN
TSWAI
TSFRZ
TFFCA
PRNT
0
0
0
0
0
2
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-9. Timer System Control Register 1 (TSCR1)
Read or write: Anytime except PRNT bit is write once
All bits reset to zero.
Table 14-6. TSCR1 Field Descriptions
Field
Description
7
TEN
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
Note: If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is
generated by the timer prescaler.
6
TSWAI
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode.
Timer interrupts cannot be used to get the MCU out of wait.
5
TSFRZ
Timer and Modulus Counter Stop While in Freeze Mode
0 Allows the timer and modulus counter to continue running while in freeze mode.
1 Disables the timer and modulus counter whenever the MCU is in freeze mode. This is useful for emulation.
The pulse accumulators do not stop in freeze mode.
4
TFFCA
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 A read from an input capture or a write to the output compare channel registers causes the corresponding
channel flag, CxF, to be cleared in the TFLG1 register. Any access to the TCNT register clears the TOF flag
in the TFLG2 register. Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the
PAFLG register. Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.
Any access to the MCCNT register clears the MCZF flag in the MCFLG register. This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag
clearing due to unintended accesses.
Note: The flags cannot be cleared via the normal flag clearing mechanism (writing a one to the flag) when
TFFCA = 1.
3
PRNT
Precision Timer
0 Enables legacy timer. Only bits DLY0 and DLY1 of the DLYCT register are used for the delay selection of the
delay counter. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler selection.
MCPR0 and MCPR1 bits of the MCCTL register are used for modulus down counter prescaler selection.
1 Enables precision timer. All bits in the DLYCT register are used for the delay selection, all bits of the PTPSR
register are used for Precision Timer Prescaler Selection, and all bits of PTMCPSR register are used for the
prescaler Precision Timer Modulus Counter Prescaler selection.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.7
Timer Toggle On Overflow Register 1 (TTOV)
Module Base + 0x0007
R
W
Reset
7
6
5
4
3
2
1
0
TOV7
TOV6
TOV5
TOV4
TOV3
TOV2
TOV1
TOV0
0
0
0
0
0
0
0
0
Figure 14-10. Timer Toggle On Overflow Register 1 (TTOV)
Read or write: Anytime
All bits reset to zero.
Table 14-7. TTOV Field Descriptions
Field
Description
7:0
TOV[7:0]
Toggle On Overflow Bits — TOV97:0] toggles output compare pin on timer counter overflow. This feature only
takes effect when in output compare mode. When set, it takes precedence over forced output compare but not
channel 7 override events.
0 Toggle output compare pin on overflow feature disabled.
1 Toggle output compare pin on overflow feature enabled.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.8
Timer Control Register 1/Timer Control Register 2 (TCTL1/TCTL2)
Module Base + 0x0008
R
W
Reset
7
6
5
4
3
2
1
0
OM7
OL7
OM6
OL6
OM5
OL5
OM4
OL4
0
0
0
0
0
0
0
0
Figure 14-11. Timer Control Register 1 (TCTL1)
Module Base + 0x0009
R
W
Reset
7
6
5
4
3
2
1
0
OM3
OL3
OM2
OL2
OM1
OL1
OM0
OL0
0
0
0
0
0
0
0
0
Figure 14-12. Timer Control Register 2 (TCTL2)
Read or write: Anytime
All bits reset to zero.
Table 14-8. TCTL1/TCTL2 Field Descriptions
Field
Description
OM[7:0]
7, 5, 3, 1
OMx — Output Mode
OLx — Output Level
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful
OCx compare. When either OMx or OLx is one, the pin associated with OCx becomes an output tied to OCx.
See Table 14-9.
OL[7:0]
6, 4, 2, 0
Table 14-9. Compare Result Output Action
OMx
OLx
Action
0
0
No output compare
action on the timer output signal
0
1
Toggle OCx output line
1
0
Clear OCx output line to zero
1
1
Set OCx output line to one
NOTE
To enable output action by OMx and OLx bits on timer port, the
corresponding bit in OC7M should be cleared.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.9
Timer Control Register 3/Timer Control Register 4 (TCTL3/TCTL4)
Module Base + 0x000A
R
W
Reset
7
6
5
4
3
2
1
0
EDG7B
EDG7A
EDG6B
EDG6A
EDG5B
EDG5A
EDG4B
EDG4A
0
0
0
0
0
0
0
0
Figure 14-13. Timer Control Register 3 (TCTL3)
Module Base + 0x000B
R
W
Reset
7
6
5
4
3
2
1
0
EDG3B
EDG3A
EDG2B
EDG2A
EDG1B
EDG1A
EDG0B
EDG0A
0
0
0
0
0
0
0
0
Figure 14-14. Timer Control Register 4 (TCTL4)
Read or write: Anytime
All bits reset to zero.
Table 14-10. TCTL3/TCTL4 Field Descriptions
Field
Description
EDG[7:0]B
7, 5, 3, 1
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits for each input capture channel. The four pairs of control bits in TCTL4 also configure the input capture
edge control for the four 8-bit pulse accumulators PAC0–PAC3.EDG0B and EDG0A in TCTL4 also determine the
active edge for the 16-bit pulse accumulator PACB. See Table 14-11.
EDG[7:0]A
6, 4, 2, 0
Table 14-11. Edge Detector Circuit Configuration
EDGxB
EDGxA
Configuration
0
0
Capture disabled
0
1
Capture on rising edges only
1
0
Capture on falling edges only
1
1
Capture on any edge (rising or falling)
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.10 Timer Interrupt Enable Register (TIE)
Module Base + 0x000C
R
W
Reset
7
6
5
4
3
2
1
0
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
0
0
0
0
0
0
0
0
Figure 14-15. Timer Interrupt Enable Register (TIE)
Read or write: Anytime
All bits reset to zero.
The bits C7I–C0I correspond bit-for-bit with the flags in the TFLG1 status register.
Table 14-12. TIE Field Descriptions
Field
7:0
C[7:0]I
Description
Input Capture/Output Compare “x” Interrupt Enable
0 The corresponding flag is disabled from causing a hardware interrupt.
1 The corresponding flag is enabled to cause an interrupt.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.11 Timer System Control Register 2 (TSCR2)
Module Base + 0x000D
7
R
W
Reset
TOI
0
6
5
4
0
0
0
0
0
0
3
2
1
0
TCRE
PR2
PR1
PR0
0
0
0
0
= Unimplemented or Reserved
Figure 14-16. Timer System Control Register 2 (TSCR2)
Read or write: Anytime
All bits reset to zero.
Table 14-13. TSCR2 Field Descriptions
Field
7
TOI
Description
Timer Overflow Interrupt Enable
0 Timer overflow interrupt disabled.
1 Hardware interrupt requested when TOF flag set.
3
TCRE
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output
compare. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset disabled and counter free runs.
1 Counter reset by a successful output compare on channel 7.
Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register
TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000.
2:0
PR[2:0]
Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT
bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized
edge where all prescale counter stages equal zero. See Table 14-14.
Table 14-14. Prescaler Selection
PR2
PR1
PR0
Prescale Factor
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
R
W
Reset
7
6
5
4
3
2
1
0
C7F
C6F
C5F
C4F
C3F
C2F
C1F
C0F
0
0
0
0
0
0
0
0
Figure 14-17. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.4.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA
bit in Section 14.4.2.6, “Timer System Control Register 1 (TSCR1)”).
Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers, instead of
generating an interrupt for every capture.
Table 14-15. TFLG1 Field Descriptions
Field
Description
7:0
C[7:0]F
Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or
output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be
set by 8-bit pulse accumulators PAC3–PAC0.
If the delay counter is enabled, the CxF flag will not be set until after the delay.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
R
W
Reset
TOF
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-18. Main Timer Interrupt Flag 2 (TFLG2)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.4.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
TFLG2 indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 14.4.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 14-16. TFLG2 Field Descriptions
Field
7
TOF
Description
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.14 Timer Input Capture/Output Compare Registers 0–7
Module Base + 0x0010
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-19. Timer Input Capture/Output Compare Register 0 High (TC0)
Module Base + 0x0011
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-20. Timer Input Capture/Output Compare Register 0 Low (TC0)
Module Base + 0x0012
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-21. Timer Input Capture/Output Compare Register 1 High (TC1)
Module Base + 0x0013
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-22. Timer Input Capture/Output Compare Register 1 Low (TC1)
Module Base + 0x0014
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-23. Timer Input Capture/Output Compare Register 2 High (TC2)
Module Base + 0x0015
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-24. Timer Input Capture/Output Compare Register 2 Low (TC2)
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Module Base + 0x0016
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-25. Timer Input Capture/Output Compare Register 3 High (TC3)
Module Base + 0x0017
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-26. Timer Input Capture/Output Compare Register 3 Low (TC3)
Module Base + 0x0018
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-27. Timer Input Capture/Output Compare Register 4 High (TC4)
Module Base + 0x0019
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-28. Timer Input Capture/Output Compare Register 4 Low (TC4)
Module Base + 0x001A
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-29. Timer Input Capture/Output Compare Register 5 High (TC5)
Module Base + 0x001B
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-30. Timer Input Capture/Output Compare Register 5 Low (TC5)
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Module Base + 0x001C
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-31. Timer Input Capture/Output Compare Register 6 High (TC6)
Module Base + 0x001D
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-32. Timer Input Capture/Output Compare Register 6 Low (TC6)
Module Base + 0x001E
R
W
Reset
15
14
13
12
11
10
9
8
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
0
0
0
0
0
0
0
0
Figure 14-33. Timer Input Capture/Output Compare Register 7 High (TC7)
Module Base + 0x001F
R
W
Reset
7
6
5
4
3
2
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
0
Figure 14-34. Timer Input Capture/Output Compare Register 7 Low (TC7)
Read: Anytime
Write anytime for output compare function. Writes to these registers have no meaning or effect during
input capture.
All bits reset to zero.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.15 16-Bit Pulse Accumulator A Control Register (PACTL)
Module Base + 0x0020
7
R
0
W
Reset
0
6
5
4
3
2
1
0
PAEN
PAMOD
PEDGE
CLK1
CLK0
PAOVI
PAI
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-35. 16-Bit Pulse Accumulator Control Register (PACTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-17. PACTL Field Descriptions
Field
Description
6
PAEN
Pulse Accumulator A System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and PAC2 can be enabled when their related enable
bits in ICPAR are set. Pulse Accumulator Input Edge Flag (PAIF) function is disabled.
1 16-Bit Pulse Accumulator A system enabled. The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded
to form the PACA 16-bit pulse accumulator. When PACA in enabled, the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA. PA3EN and PA2EN control bits in ICPAR have no effect.
Pulse Accumulator Input Edge Flag (PAIF) function is enabled. The PACA shares the input pin with IC7.
5
PAMOD
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator A is enabled (PAEN = 1).
0 Event counter mode
1 Gated time accumulation mode
4
PEDGE
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator A is enabled
(PAEN = 1). Refer to Table 14-18.
For PAMOD bit = 0 (event counter mode).
0 Falling edges on PT7 pin cause the count to be incremented
1 Rising edges on PT7 pin cause the count to be incremented
For PAMOD bit = 1 (gated time accumulation mode).
0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7
sets the PAIF flag.
1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7
sets the PAIF flag.
If the timer is not active (TEN = 0 in TSCR1), there is no divide-by-64 since the ÷64 clock is generated by the
timer prescaler.
3:2
CLK[1:0]
2
PAOVI
Clock Select Bits — For the description of PACLK please refer to Figure 14-71.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an input
clock to the timer counter. The change from one selected clock to the other happens immediately after these bits
are written. Refer to Table 14-19.
Pulse Accumulator A Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAOVF is set
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Table 14-17. PACTL Field Descriptions (continued)
Field
0
PAI
Description
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAIF is set
.
Table 14-18. Pin Action
PAMOD
PEDGE
Pin Action
0
0
Falling edge
0
1
Rising edge
1
0
Divide by 64 clock enabled with pin high level
1
1
Divide by 64 clock enabled with pin low level
Table 14-19. Clock Selection
CLK1
CLK0
Clock Source
0
0
Use timer prescaler clock as timer counter clock
0
1
Use PACLK as input to timer counter clock
1
0
Use PACLK/256 as timer counter clock frequency
1
1
Use PACLK/65536 as timer counter clock frequency
14.4.2.16 Pulse Accumulator A Flag Register (PAFLG)
Module Base + 0x0021
R
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
1
0
PAOVF
PAIF
0
0
= Unimplemented or Reserved
Figure 14-36. Pulse Accumulator A Flag Register (PAFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.4.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 14.4.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 14-20. PAFLG Field Descriptions
Field
1
PAOVF
Description
Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to
0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000.
When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by
an active edge on PT3.
0
PAIF
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the PT7 input pin triggers PAIF.
14.4.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)
Module Base + 0x0022
7
R
W
Reset
6
5
4
3
2
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
0
0
0
0
0
0
1
0
PACNT1(9)
PACNT0(8)
0
0
Figure 14-37. Pulse Accumulators Count Register 3 (PACN3)
Module Base + 0x0023
R
W
Reset
7
6
5
4
3
2
1
0
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
0
0
0
0
0
0
0
0
Figure 14-38. Pulse Accumulators Count Register 2 (PACN2)
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16-bit pulse
accumulator. When PACA in enabled (PAEN = 1 in PACTL), the PACN3 and PACN2 registers contents
are respectively the high and low byte of the PACA.
When PACN3 overflows from 0x00FF to 0x0000, the interrupt flag PAOVF in PAFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
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When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
14.4.2.18 Pulse Accumulators Count Registers (PACN1 and PACN0)
Module Base + 0x0024
7
R
W
Reset
6
5
4
3
2
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
0
0
0
0
0
0
1
0
PACNT1(9)
PACNT0(8)
0
0
Figure 14-39. Pulse Accumulators Count Register 1 (PACN1)
Module Base + 0x0025
R
W
Reset
7
6
5
4
3
2
1
0
PACNT7
PACNT6
PACNT5
PACNT4
PACNT3
PACNT2
PACNT1
PACNT0
0
0
0
0
0
0
0
0
Figure 14-40. Pulse Accumulators Count Register 0 (PACN0)
Read: Anytime
Write: Anytime
All bits reset to zero.
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form the PACB 16-bit pulse
accumulator. When PACB in enabled, (PBEN = 1 in PBCTL) the PACN1 and PACN0 registers contents
are respectively the high and low byte of the PACB.
When PACN1 overflows from 0x00FF to 0x0000, the interrupt flag PBOVF in PBFLG is set.
Full count register access will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
When clocking pulse and write to the registers occurs simultaneously, write
takes priority and the register is not incremented.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.19 16-Bit Modulus Down-Counter Control Register (MCCTL)
Module Base + 0x0026
7
R
W
Reset
6
5
MCZI
MODMC
RDMCL
0
0
0
4
3
0
0
ICLAT
FLMC
0
0
2
1
0
MCEN
MCPR1
MCPR0
0
0
0
Figure 14-41. 16-Bit Modulus Down-Counter Control Register (MCCTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-21. MCCTL Field Descriptions
Field
7
MCZI
Description
Modulus Counter Underflow Interrupt Enable
0 Modulus counter interrupt is disabled.
1 Modulus counter interrupt is enabled.
6
MODMC
Modulus Mode Enable
0 The modulus counter counts down from the value written to it and will stop at 0x0000.
1 Modulus mode is enabled. When the modulus counter reaches 0x0000, the counter is loaded with the latest
value written to the modulus count register.
Note: For proper operation, the MCEN bit should be cleared before modifying the MODMC bit in order to reset
the modulus counter to 0xFFFF.
5
RDMCL
Read Modulus Down-Counter Load
0 Reads of the modulus count register (MCCNT) will return the present value of the count register.
1 Reads of the modulus count register (MCCNT) will return the contents of the load register.
4
ICLAT
Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3
and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse
accumulators will be automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will always return zero.
3
FLMC
Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus
down-counter is enabled (MCEN = 1).
A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets
the modulus counter prescaler.
Write zero to this bit has no effect. Read of this bit will return always zero.
2
MCEN
1:0
MCPR[1:0]
Modulus Down-Counter Enable
0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early
interrupt flag when the modulus down-counter is enabled.
1 Modulus counter is enabled.
Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler
when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of
the load register into the modulus counter count register occurs.
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Table 14-22. Modulus Counter Prescaler Select
MCPR1
MCPR0
Prescaler Division
0
0
1
0
1
4
1
0
8
1
1
16
14.4.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Module Base + 0x0027
7
R
W
Reset
MCZF
0
6
5
4
3
2
1
0
0
0
0
POLF3
POLF2
POLF1
POLF0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-42. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime
Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a
zero will not affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.4.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
Table 14-23. MCFLG Field Descriptions
Field
7
MCZF
3:0
POLF[3:0]
Description
Modulus Counter Underflow Flag — The flag is set when the modulus down-counter reaches 0x0000.
The flag indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag clearing
mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA bit in
Section 14.4.2.6, “Timer System Control Register 1 (TSCR1)”).
First Input Capture Polarity Status — These are read only bits. Writes to these bits have no effect.
Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch
has been read.
Each POLFx corresponds to a timer PORTx input.
0 The first input capture has been caused by a falling edge.
1 The first input capture has been caused by a rising edge.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.21 ICPAR — Input Control Pulse Accumulators Register (ICPAR)
Module Base + 0x0028
R
7
6
5
4
0
0
0
0
0
0
0
0
W
Reset
3
2
1
0
PA3EN
PA2EN
PA1EN
PA0EN
0
0
0
0
= Unimplemented or Reserved
Figure 14-43. Input Control Pulse Accumulators Register (ICPAR)
Read: Anytime
Write: Anytime.
All bits reset to zero.
The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PACTL is cleared. If PAEN
is set, PA3EN and PA2EN have no effect.
The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if PBEN in PBCTL is cleared. If PBEN
is set, PA1EN and PA0EN have no effect.
Table 14-24. ICPAR Field Descriptions
Field
3:0
PA[3:0]EN
Description
8-Bit Pulse Accumulator ‘x’ Enable
0 8-Bit Pulse Accumulator is disabled.
1 8-Bit Pulse Accumulator is enabled.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.22 Delay Counter Control Register (DLYCT)
Module Base + 0x0029
R
W
Reset
7
6
5
4
3
2
1
0
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
0
0
0
0
0
0
0
0
Figure 14-44. Delay Counter Control Register (DLYCT)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-25. DLYCT Field Descriptions
Field
7:0
DLY[7:0]
Description
Delay Counter Select — When the PRNT bit of TSCR1 register is set to 0, only bits DLY0, DLY1 are used to
calculate the delay.Table 14-26 shows the delay settings in this case.
When the PRNT bit of TSCR1 register is set to 1, all bits are used to set a more precise delay. Table 14-27 shows
the delay settings in this case. After detection of a valid edge on an input capture pin, the delay counter counts
the pre-selected number of [(dly_cnt + 1)*4]bus clock cycles, then it will generate a pulse on its output if the level
of input signal, after the preset delay, is the opposite of the level before the transition.This will avoid reaction to
narrow input pulses.
Delay between two active edges of the input signal period should be longer than the selected counter delay.
Note: It is recommended to not write to this register while the timer is enabled, that is when TEN is set in register
TSCR1.
Table 14-26. Delay Counter Select when PRNT = 0
DLY1
DLY0
Delay
0
0
1
1
0
1
0
1
Disabled
256 bus clock cycles
512 bus clock cycles
1024 bus clock cycles
Table 14-27. Delay Counter Select Examples when PRNT = 1
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
Delay
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
1
1
1
1
Disabled (bypassed)
8 bus clock cycles
12 bus clock cycles
16 bus clock cycles
20 bus clock cycles
24 bus clock cycles
28 bus clock cycles
32 bus clock cycles
64 bus clock cycles
128 bus clock cycles
256 bus clock cycles
512 bus clock cycles
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Table 14-27. Delay Counter Select Examples when PRNT = 1
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
DLY0
Delay
1
1
1
1
1
1
1
1
1024 bus clock cycles
14.4.2.23 Input Control Overwrite Register (ICOVW)
Module Base + 0x002A
R
W
Reset
7
6
5
4
3
2
1
0
NOVW7
NOVW6
NOVW5
NOVW4
NOVW3
NOVW2
NOVW1
NOVW0
0
0
0
0
0
0
0
0
Figure 14-45. Input Control Overwrite Register (ICOVW)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-28. ICOVW Field Descriptions
Field
Description
7:0
NOVW[7:0]
No Input Capture Overwrite
0 The contents of the related capture register or holding register can be overwritten when a new input capture
or latch occurs.
1 The related capture register or holding register cannot be written by an event unless they are empty (see
Section 14.5.1.1, “IC Channels”). This will prevent the captured value being overwritten until it is read or
latched in the holding register.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.24 Input Control System Control Register (ICSYS)
Module Base + 0x002B
R
W
Reset
7
6
5
4
3
2
1
0
SH37
SH26
SH15
SH04
TFMOD
PACMX
BUFEN
LATQ
0
0
0
0
0
0
0
0
Figure 14-46. Input Control System Register (ICSYS)
Read: Anytime
Write: Once in normal modes
All bits reset to zero.
Table 14-29. ICSYS Field Descriptions
Field
Description
7:4
SHxy
Share Input action of Input Capture Channels x and y
0 Normal operation
1 The channel input ‘x’ causes the same action on the channel ‘y’. The port pin ‘x’ and the corresponding edge
detector is used to be active on the channel ‘y’.
3
TFMOD
Timer Flag Setting Mode — Use of the TFMOD bit in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers instead of
generating an interrupt for every capture.
By setting TFMOD in queue mode, when NOVWx bit is set and the corresponding capture and holding registers
are emptied, an input capture event will first update the related input capture register with the main timer
contents. At the next event, the TCx data is transferred to the TCxH register, the TCx is updated and the CxF
interrupt flag is set. In all other input capture cases the interrupt flag is set by a valid external event on PTx.
0 The timer flags C3F–C0F in TFLG1 are set when a valid input capture transition on the corresponding port pin
occurs.
1 If in queue mode (BUFEN = 1 and LATQ = 0), the timer flags C3F–C0F in TFLG1 are set only when a latch
on the corresponding holding register occurs. If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD = 0.
2
PACMX
8-Bit Pulse Accumulators Maximum Count
0 Normal operation. When the 8-bit pulse accumulator has reached the value 0x00FF, with the next active edge,
it will be incremented to 0x0000.
1 When the 8-bit pulse accumulator has reached the value 0x00FF, it will not be incremented further. The value
0x00FF indicates a count of 255 or more.
1
BUFFEN
IC Buffer Enable
0 Input capture and pulse accumulator holding registers are disabled.
1 Input capture and pulse accumulator holding registers are enabled. The latching mode is defined by LATQ
control bit.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Table 14-29. ICSYS Field Descriptions (continued)
Field
Description
0
LATQ
Input Control Latch or Queue Mode Enable — The BUFEN control bit should be set in order to enable the IC
and pulse accumulators holding registers. Otherwise LATQ latching modes are disabled.
Write one into ICLAT bit in MCCTL, when LATQ and BUFEN are set will produce latching of input capture and
pulse accumulators registers into their holding registers.
0 Queue mode of Input Capture is enabled. The main timer value is memorized in the IC register by a valid input
pin transition. With a new occurrence of a capture, the value of the IC register will be transferred to its holding
register and the IC register memorizes the new timer value.
1 Latch mode is enabled. Latching function occurs when modulus down-counter reaches zero or a zero is
written into the count register MCCNT (see Section 14.5.1.1.2, “Buffered IC Channels”). With a latching event
the contents of IC registers and 8-bit pulse accumulators are transferred to their holding registers. 8-bit pulse
accumulators are cleared.
14.4.2.25 Output Compare Pin Disconnect Register (OCPD)
Module Base + 0x002C
R
W
Reset
7
6
5
4
3
2
1
0
OCPD7
OCPD6
OCPD5
OCPD4
OCPD3
OCPD2
OCPD1
OCPD0
0
0
0
0
0
0
0
0
Figure 14-47. Output Compare Pin Disconnect Register (OCPD)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-30. OCPD Field Descriptions
Field
Description
7:0
OCPD[7:0]
Output Compare Pin Disconnect Bits
0 Enables the timer channel IO port. Output Compare actions will occur on the channel pin. These bits do not
affect the input capture or pulse accumulator functions.
1 Disables the timer channel IO port. Output Compare actions will not affect on the channel pin; the output
compare flag will still be set on an Output Compare event.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.26 Precision Timer Prescaler Select Register (PTPSR)
Module Base + 0x002E
R
W
Reset
7
6
5
4
3
2
1
0
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
0
0
0
0
0
0
0
0
Figure 14-48. Precision Timer Prescaler Select Register (PTPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-31. PTPSR Field Descriptions
Field
Description
7:0
PTPS[7:0]
Precision Timer Prescaler Select Bits — These eight bits specify the division rate of the main Timer prescaler.
These are effective only when the PRNT bit of TSCR1 is set to 1. Table 14-32 shows some selection examples
in this case.
The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter
stages equal zero.
Table 14-32. Precision Timer Prescaler Selection Examples when PRNT = 1
PTPS7
PTPS6
PTPS5
PTPS4
PTPS3
PTPS2
PTPS1
PTPS0
Prescale
Factor
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
1
1
4
0
0
0
0
0
1
0
0
5
0
0
0
0
0
1
0
1
6
0
0
0
0
0
1
1
0
7
0
0
0
0
0
1
1
1
8
0
0
0
0
1
1
1
1
16
0
0
0
1
1
1
1
1
32
0
0
1
1
1
1
1
1
64
0
1
1
1
1
1
1
1
128
1
1
1
1
1
1
1
1
256
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.27 Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)
Module Base + 0x002F
R
W
Reset
7
6
5
4
3
2
1
0
PTMPS7
PTMPS6
PTMPS5
PTMPS4
PTMPS3
PTMPS2
PTMPS1
PTMPS0
0
0
0
0
0
0
0
0
Figure 14-49. Precision Timer Modulus Counter Prescaler Select Register (PTMCPSR)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-33. PTMCPSR Field Descriptions
Field
Description
7:0
Precision Timer Modulus Counter Prescaler Select Bits — These eight bits specify the division rate of the
PTMPS[7:0] modulus counter prescaler. These are effective only when the PRNT bit of TSCR1 is set to 1. Table 14-34 shows
some possible division rates.
The newly selected prescaler division rate will not be effective until a load of the load register into the modulus
counter count register occurs.
Table 14-34. Precision Timer Modulus Counter Prescaler Select Examples when PRNT = 1
PTMPS7
PTMPS6
PTMPS5
PTMPS4
PTMPS3
PTMPS2
PTMPS1
PTMPS0
Prescaler
Division
Rate
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
1
1
4
0
0
0
0
0
1
0
0
5
0
0
0
0
0
1
0
1
6
0
0
0
0
0
1
1
0
7
0
0
0
0
0
1
1
1
8
0
0
0
0
1
1
1
1
16
0
0
0
1
1
1
1
1
32
0
0
1
1
1
1
1
1
64
0
1
1
1
1
1
1
1
128
1
1
1
1
1
1
1
1
256
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.28 16-Bit Pulse Accumulator B Control Register (PBCTL)
Module Base + 0x0030
7
R
6
0
PBEN
W
Reset
0
0
5
4
3
2
0
0
0
0
0
0
0
0
1
PBOVI
0
0
0
0
= Unimplemented or Reserved
Figure 14-50. 16-Bit Pulse Accumulator B Control Register (PBCTL)
Read: Anytime
Write: Anytime
All bits reset to zero.
Table 14-35. PBCTL Field Descriptions
Field
Description
6
PBEN
Pulse Accumulator B System Enable — PBEN is independent from TEN. With timer disabled, the pulse
accumulator can still function unless pulse accumulator is disabled.
0 16-bit pulse accumulator system disabled. 8-bit PAC1 and PAC0 can be enabled when their related enable
bits in ICPAR are set.
1 Pulse accumulator B system enabled. The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator B. When PACB is enabled, the PACN1 and PACN0 registers contents are
respectively the high and low byte of the PACB.
PA1EN and PA0EN control bits in ICPAR have no effect.
The PACB shares the input pin with IC0.
1
PBOVI
Pulse Accumulator B Overflow Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PBOVF is set
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.29 Pulse Accumulator B Flag Register (PBFLG)
Module Base + 0x0031
R
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
1
PBOVF
0
0
0
0
= Unimplemented or Reserved
Figure 14-51. Pulse Accumulator B Flag Register (PBFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flag cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 14.4.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
PBFLG indicates when interrupt conditions have occurred. The flag can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in Section 14.4.2.6, “Timer System Control Register 1 (TSCR1)”).
Table 14-36. PBFLG Field Descriptions
Field
1
PBOVF
Description
Pulse Accumulator B Overflow Flag — This bit is set when the 16-bit pulse accumulator B overflows from
0xFFFF to 0x0000, or when 8-bit pulse accumulator 1 (PAC1) overflows from 0x00FF to 0x0000.
When PACMX = 1, PBOVF bit can also be set if 8-bit pulse accumulator 1 (PAC1) reaches 0x00FF and an active
edge follows on PT1.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.30 8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H)
Module Base + 0x0032
R
7
6
5
4
3
2
1
0
PA3H7
PA3H6
PA3H5
PA3H4
PA3H3
PA3H2
PA3H1
PA3H0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-52. 8-Bit Pulse Accumulators Holding Register 3 (PA3H)
Module Base + 0x0033
R
7
6
5
4
3
2
1
0
PA2H7
PA2H6
PA2H5
PA2H4
PA2H3
PA2H2
PA2H1
PA2H0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-53. 8-Bit Pulse Accumulators Holding Register 2 (PA2H)
Module Base + 0x0034
R
7
6
5
4
3
2
1
0
PA1H7
PA1H6
PA1H5
PA1H4
PA1H3
PA1H2
PA1H1
PA1H0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-54. 8-Bit Pulse Accumulators Holding Register 1 (PA1H)
Module Base + 0x0035
R
7
6
5
4
3
2
1
0
PA0H7
PA0H6
PA0H5
PA0H4
PA0H3
PA0H2
PA0H1
PA0H0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-55. 8-Bit Pulse Accumulators Holding Register 0 (PA0H)
Read: Anytime.
Write: Has no effect.
All bits reset to zero.
These registers are used to latch the value of the corresponding pulse accumulator when the related bits in
register ICPAR are enabled (see Section 14.5.1.3, “Pulse Accumulators”).
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.31 Modulus Down-Counter Count Register (MCCNT)
Module Base + 0x0036
R
W
Reset
15
14
13
12
11
10
9
8
MCCNT15
MCCNT14
MCCNT13
MCCNT12
MCCNT11
MCCNT10
MCCNT9
MCCNT8
1
1
1
1
1
1
1
1
Figure 14-56. Modulus Down-Counter Count Register High (MCCNT)
Module Base + 0x0037
R
W
Reset
7
6
5
4
3
2
1
0
MCCNT7
MCCNT6
MCCNT5
MCCNT4
MCCNT3
MCCNT2
MCCNT1
MCCNT0
1
1
1
1
1
1
1
1
Figure 14-57. Modulus Down-Counter Count Register Low (MCCNT)
Read: Anytime
Write: Anytime.
All bits reset to one.
A full access for the counter register will take place in one clock cycle.
NOTE
A separate read/write for high byte and low byte will give different results
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT register will return the present value
of the count register. If the RDMCL bit is set, reads of the MCCNT will return the contents of the load
register.
If a 0x0000 is written into MCCNT when LATQ and BUFEN in ICSYS register are set, the input capture
and pulse accumulator registers will be latched.
With a 0x0000 write to the MCCNT, the modulus counter will stay at zero and does not set the MCZF flag
in MCFLG register.
If the modulus down counter is enabled (MCEN = 1) and modulus mode is enabled (MODMC = 1), a write
to MCCNT will update the load register with the value written to it. The count register will not be updated
with the new value until the next counter underflow.
If modulus mode is not enabled (MODMC = 0), a write to MCCNT will clear the modulus prescaler and
will immediately update the counter register with the value written to it and down-counts to 0x0000 and
stops.
The FLMC bit in MCCTL can be used to immediately update the count register with the new value if an
immediate load is desired.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.4.2.32 Timer Input Capture Holding Registers 0–3 (TCxH)
Module Base + 0x0038
R
15
14
13
12
11
10
9
8
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-58. Timer Input Capture Holding Register 0 High (TC0H)
Module Base + 0x0039
R
7
6
5
4
3
2
1
0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-59. Timer Input Capture Holding Register 0 Low (TC0H)
Module Base + 0x003A
R
15
14
13
12
11
10
9
8
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-60. Timer Input Capture Holding Register 1 High (TC1H)
Module Base + 0x003B
R
7
6
5
4
3
2
1
0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-61. Timer Input Capture Holding Register 1 Low (TC1H)
Module Base + 0x003C
R
15
14
13
12
11
10
9
8
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0
0
0
0
0
0
0
0
W
Reset
= Unimplemented or Reserved
Figure 14-62. Timer Input Capture Holding Register 2 High (TC2H)
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Module Base + 0x003D
R
7
6
5
4
3
2
1
0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 14-63. Timer Input Capture Holding Register 2 Low (TC2H)
Module Base + 0x003E
R
15
14
13
12
11
10
9
8
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 14-64. Timer Input Capture Holding Register 3 High (TC3H)
Module Base + 0x003F
R
7
6
5
4
3
2
1
0
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
0
0
0
0
0
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 14-65. Timer Input Capture Holding Register 3 Low (TC3H)
Read: Anytime
Write: Has no effect.
All bits reset to zero.
These registers are used to latch the value of the input capture registers TC0–TC3. The corresponding
IOSx bits in TIOS should be cleared (see Section 14.5.1.1, “IC Channels”).
14.5
Functional Description
This section provides a complete functional description of the ECT block, detailing the operation of the
design from the end user perspective in a number of subsections.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Bus Clock
÷ 1, 4, 8, 16
Bus Clock
Timer Prescaler
16-Bit Load Register
16-Bit Modulus
Down Counter
Modulus Prescaler
0
P0
Comparator
Pin Logic
Delay
Counter
EDG0
TC0 Capture/Compare Reg.
PAC0
TC0H Hold Reg.
PA0H Hold Reg.
0
P1
Pin Logic
Delay
Counter
EDG1
TC1 Capture/Compare Reg.
PAC1
TC1H Hold Reg.
PA1H Hold Reg.
Pin Logic
Delay
Counter
EDG2
TC2 Capture/Compare Reg.
PAC2
TC2H Hold Reg.
PA2H Hold Reg.
Pin Logic
Pin Logic
RESET
Comparator
Delay
Counter
EDG3
TC3 Capture/Compare Reg.
PAC3
TC3H Hold Reg.
PA3H Hold Reg.
LATCH
P4
RESET
Comparator
0
P3
RESET
Comparator
0
P2
RESET
Underflow
16-Bit Free-Running
16 BITMain
MAIN
TIMER
Timer
÷ 1, 2, ..., 128
Comparator
EDG4
EDG0
TC4 Capture/Compare Reg.
MUX
ICLAT, LATQ, BUFEN
(Force Latch)
SH04
P5
Pin Logic
Comparator
EDG5
EDG1
TC5 Capture/Compare Reg.
MUX
Write 0x0000
to Modulus Counter
SH15
P6
Pin Logic
Comparator
EDG6
EDG2
LATQ
(MDC Latch Enable)
TC6 Capture/Compare Reg.
MUX
SH26
P7
Pin Logic
Comparator
EDG7
EDG3
TC7 Capture/Compare Reg.
MUX
SH37
Figure 14-66. Detailed Timer Block Diagram in Latch Mode when PRNT = 0
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Bus Clock
÷ 1, 2,3, ..., 256
Bus Clock
Timer Prescaler
16-Bit Load Register
16-Bit Modulus
Down Counter
Modulus Prescaler
0
P0
RESET
Underflow
16-Bit Free-Running
16 BITMain
MAINTimer
TIMER
÷ 1, 2,3, ..., 256
Comparator
Pin Logic
Delay
Counter
EDG0
TC0 Capture/Compare Reg.
PAC0
TC0H Hold Reg.
PA0H Hold Reg.
8, 12, 16, ..., 1024
0
P1
RESET
Comparator
Pin Logic
Delay
Counter
EDG1
TC1 Capture/Compare Reg.
PAC1
TC1H Hold Reg.
PA1H Hold Reg.
8, 12, 16, ..., 1024
0
P2
RESET
Comparator
Pin Logic
Delay
Counter
EDG2
TC2 Capture/Compare Reg.
PAC2
TC2H Hold Reg.
PA2H Hold Reg.
8, 12, 16, ..., 1024
0
P3
RESET
Comparator
Pin Logic
Delay
Counter
EDG3
TC3 Capture/Compare Reg.
PAC3
TC3H Hold Reg.
PA3H Hold Reg.
P4
Pin Logic
LATCH
8, 12, 16, ..., 1024
Comparator
EDG4
EDG0
TC4 Capture/Compare Reg.
MUX
ICLAT, LATQ, BUFEN
(Force Latch)
SH04
P5
Pin Logic
Comparator
EDG5
EDG1
TC5 Capture/Compare Reg.
MUX
Write 0x0000
to Modulus Counter
SH15
P6
Pin Logic
Comparator
EDG6
EDG2
LATQ
(MDC Latch Enable)
TC6 Capture/Compare Reg.
MUX
SH26
P7
Pin Logic
Comparator
EDG7
EDG3
TC7 Capture/Compare Reg.
MUX
SH37
Figure 14-67. Detailed Timer Block Diagram in Latch Mode when PRNT = 1
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
16-Bit Free-Running
16 BITMain
MAIN
TIMER
Timer
÷ 1, 4, 8, 16
Bus Clock
16-Bit Load Register
16-Bit Modulus
Down Counter
Modulus
Prescaler
0
Delay
Counter
EDG0
TC0 Capture/Compare Reg.
PAC0
TC0H Hold Reg.
PA0H Hold Reg.
0
Pin Logic
Delay
Counter
EDG1
TC1 Capture/Compare Reg.
PAC1
TC1H Hold Reg.
PA1H Hold Reg.
0
P2
P4
Pin Logic
Delay
Counter
EDG2
TC2 Capture/Compare Reg.
PAC2
TC2H Hold Reg.
PA2H Hold Reg.
Delay
Counter
EDG3
TC3 Capture/Compare Reg.
PAC3
TC3H Hold Reg.
PA3H Hold Reg.
Comparator
EDG4
TC4 Capture/Compare Reg.
LATQ, BUFEN
(Queue Mode)
Comparator
Read TC3H
Hold Reg.
MUX
EDG0
SH04
P5
Pin Logic
EDG5
TC5 Capture/Compare Reg.
MUX
EDG1
Read TC2H
Hold Reg.
SH15
P6
Pin Logic
RESET
Comparator
Pin Logic
Pin Logic
RESET
Comparator
0
P3
RESET
Comparator
LATCH1
P1
LATCH0
Pin Logic
LATCH2
P0
RESET
Comparator
LATCH3
Bus Clock
÷1, 2, ..., 128
Timer
Prescaler
Comparator
EDG6
TC6 Capture/Compare Reg.
MUX
EDG2
Read TC1H
Hold Reg.
SH26
P7
Pin Logic
Comparator
EDG7
TC7 Capture/Compare Reg.
EDG3
SH37
Read TC0H
Hold Reg.
MUX
Figure 14-68. Detailed Timer Block Diagram in Queue Mode when PRNT = 0
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
÷1, 2, 3, ... 256
Bus Clock
16-Bit Free-Running
16 BITMain
MAIN
TIMER
Timer
Timer
Prescaler
÷ 1, 2, 3, ... 256
16-Bit Load Register
Modulus
Prescaler
16-Bit Modulus
Down Counter
Bus Clock
0
P0
RESET
Comparator
Pin Logic
Delay
Counter
EDG0
TC0 Capture/Compare Reg.
PAC0
TC0H Hold Reg.
PA0H Hold Reg.
0
P1
LATCH0
8, 12, 16, ... 1024
RESET
Comparator
Pin Logic
Delay
Counter
EDG1
TC1 Capture/Compare Reg.
PAC1
TC1H Hold Reg.
PA1H Hold Reg.
0
P2
LATCH1
8, 12, 16, ... 1024
RESET
Comparator
Pin Logic
Delay
Counter
EDG2
TC2 Capture/Compare Reg.
PAC2
TC2H Hold Reg.
PA2H Hold Reg.
0
RESET
Comparator
Pin Logic
Delay
Counter
EDG3
TC3 Capture/Compare Reg.
PAC3
TC3H Hold Reg.
PA3H Hold Reg.
8, 12, 16, ... 1024
P4
Pin Logic
Comparator
EDG4
TC4 Capture/Compare Reg.
LATQ, BUFEN
(Queue Mode)
Comparator
Read TC3H
Hold Reg.
MUX
EDG0
SH04
P5
Pin Logic
EDG5
TC5 Capture/Compare Reg.
MUX
EDG1
Read TC2H
Hold Reg.
SH15
P6
Pin Logic
LATCH3
P3
LATCH2
8, 12, 16, ... 1024
Comparator
EDG6
TC6 Capture/Compare Reg.
MUX
EDG2
Read TC1H
Hold Reg.
SH26
P7
Pin Logic
Comparator
EDG7
TC7 Capture/Compare Reg.
EDG3
SH37
Read TC0H
Hold Reg.
MUX
Figure 14-69. Detailed Timer Block Diagram in Queue Mode when PRNT = 1
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Load Holding Register and Reset Pulse Accumulator
0
8, 12,16, ..., 1024
8-Bit PAC0 (PACN0)
EDG0
P0
Edge Detector
Delay Counter
PA0H Holding
Register
Interrupt
0
8, 12,16, ..., 1024
EDG1
P1
Edge Detector
8-Bit PAC1 (PACN1)
Delay Counter
PA1H Holding
Register
0
8, 12,16, ..., 1024
EDG2
P2
Edge Detector
8-Bit PAC2 (PACN2)
Delay Counter
PA2H Holding
Register
Interrupt
8, 12,16, ..., 1024
P3
Edge Detector
0
EDG3
8-Bit PAC3 (PACN3)
Delay Counter
PA3H Holding
Register
Figure 14-70. 8-Bit Pulse Accumulators Block Diagram
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
TIMCLK (Timer Clock)
CLK1
CLK0
PACLK / 256
Clock Select
(PAMOD)
PACLK
PACLK / 65536
Prescaled Clock
(PCLK)
4:1 MUX
Edge Detector
P7
Interrupt
8-Bit PAC3
(PACN3)
8-Bit PAC2
(PACN2)
MUX
PACA
Bus Clock
Divide by 64
Interrupt
8-Bit PAC1
(PACN1)
8-Bit PAC0
(PACN0)
Delay Counter
PACB
Edge Detector
P0
Figure 14-71. 16-Bit Pulse Accumulators Block Diagram
16-Bit Main Timer
Px
Edge
Detector
Delay
Counter
Set CxF
Interrupt
TCx Input
Capture Register
TCxH I.C.
Holding Register
BUFEN • LATQ • TFMOD
Figure 14-72. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.5.1
Enhanced Capture Timer Modes of Operation
The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12
standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the
IOSx bit in TIOS register, they are called input capture (IC) channels.
Four IC channels (channels 7–4) are the same as on the standard timer with one capture register each that
memorizes the timer value captured by an action on the associated input pin.
Four other IC channels (channels 3–0), in addition to the capture register, also have one buffer each called
a holding register. This allows two different timer values to be saved without generating any interrupts.
Four 8-bit pulse accumulators are associated with the four buffered IC channels (channels 3–0). Each pulse
accumulator has a holding register to memorize their value by an action on its external input. Each pair of
pulse accumulators can be used as a 16-bit pulse accumulator.
The 16-bit modulus down-counter can control the transfer of the IC registers and the pulse accumulators
contents to the respective holding registers for a given period, every time the count reaches zero.
The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability.
14.5.1.1
IC Channels
The IC channels are composed of four standard IC registers and four buffered IC channels.
• An IC register is empty when it has been read or latched into the holding register.
• A holding register is empty when it has been read.
14.5.1.1.1
Non-Buffered IC Channels
The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding
NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC
register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set,
the capture register cannot be written unless it is empty. This will prevent the captured value from being
overwritten until it is read.
14.5.1.1.2
Buffered IC Channels
There are two modes of operations for the buffered IC channels:
1. IC latch mode (LATQ = 1)
The main timer value is memorized in the IC register by a valid input pin transition (see
Figure 14-66 and Figure 14-67).
The value of the buffered IC register is latched to its holding register by the modulus counter for a
given period when the count reaches zero, by a write 0x0000 to the modulus counter or by a write
to ICLAT in the MCCTL register.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the contents of IC register are overwritten by the new value. In case of latching, the
contents of its holding register are overwritten.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see Section 14.5.1.1, “IC Channels”).
This will prevent the captured value from being overwritten until it is read or latched in the holding
register.
2. IC Queue Mode (LATQ = 0)
The main timer value is memorized in the IC register by a valid input pin transition (see
Figure 14-68 and Figure 14-69).
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the value of the IC register will be transferred to its holding register and the IC register
memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see Section 14.5.1.1, “IC Channels”).
In queue mode, reads of the holding register will latch the corresponding pulse accumulator value
to its holding register.
14.5.1.1.3
Delayed IC Channels
There are four delay counters in this module associated with IC channels 0–3. The use of this feature is
explained in the diagram and notes below.
BUS CLOCK
DLY_CNT
0
1
2
3
INPUT ON
CH0–3
255 Cycles
INPUT ON
CH0–3
255.5 Cycles
INPUT ON
CH0–3
255.5 Cycles
INPUT ON
CH0–3
256 Cycles
253
254
255
256
Rejected
Rejected
Accepted
Accepted
Figure 14-73. Channel Input Validity with Delay Counter Feature
In Figure 14-73 a delay counter value of 256 bus cycles is considered.
1. Input pulses with a duration of (DLY_CNT – 1) cycles or shorter are rejected.
2. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
accepted, depending on their relative alignment with the sample points.
3. Input pulses with a duration between (DLY_CNT – 1) and DLY_CNT cycles may be rejected or
accepted, depending on their relative alignment with the sample points.
4. Input pulses with a duration of DLY_CNT or longer are accepted.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.5.1.2
OC Channel Initialization
An internal compare channel whose output drives OCx may be programmed before the timer drives the
output compare state (OCx). The required output of the compare logic can be disconnected from the pin,
leaving it driven by the GP IO port, by setting the appropriate OCPDx bit before enabling the output
compare channel (by default the OPCD bits are cleared which would enable the output compare logic to
drive the pin as soon as the time output compare channel is enabled). The desired initial state can then be
configured in the internal output compare logic by forcing a compare action with the logic disconnected
from the IO (by writing a one to CFORCx bit with TIOSx, OCPDx and TEN bits set to one). Clearing the
output compare disconnect bit (OCPDx) will then allow the internal compare logic to drive the
programmed state to OCx. This allows a glitch free switch over of the port from general purpose I/O to
timer output.
14.5.1.3
Pulse Accumulators
There are four 8-bit pulse accumulators with four 8-bit holding registers associated with the four IC
buffered channels 3–0. A pulse accumulator counts the number of active edges at the input of its channel.
The minimum pulse width for the PAI input is greater than two bus clocks.The maximum input frequency
on the pulse accumulator channel is one half the bus frequency or Eclk.
The user can prevent the 8-bit pulse accumulators from counting further than 0x00FF by utilizing the
PACMX control bit in the ICSYS register. In this case, a value of 0x00FF means that 255 counts or more
have occurred.
Each pair of pulse accumulators can be used as a 16-bit pulse accumulator (see Figure 14-71).
To operate the 16-bit pulse accumulators A and B (PACA and PACB) independently of input capture or
output compare 7 and 0 respectively, the user must set the corresponding bits: IOSx = 1, OMx = 0, and
OLx = 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
There are two modes of operation for the pulse accumulators:
• Pulse accumulator latch mode
The value of the pulse accumulator is transferred to its holding register when the modulus
down-counter reaches zero, a write 0x0000 to the modulus counter or when the force latch control
bit ICLAT is written.
At the same time the pulse accumulator is cleared.
• Pulse accumulator queue mode
When queue mode is enabled, reads of an input capture holding register will transfer the contents
of the associated pulse accumulator to its holding register.
At the same time the pulse accumulator is cleared.
14.5.1.4
Modulus Down-Counter
The modulus down-counter can be used as a time base to generate a periodic interrupt. It can also be used
to latch the values of the IC registers and the pulse accumulators to their holding registers.
The action of latching can be programmed to be periodic or only once.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.5.1.5
Precision Timer
By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this
case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter
and enhance delay counter settings compared to the settings in the present ECT timer.
14.5.1.6
Flag Clearing Mechanisms
The flags in the ECT can be cleared one of two ways:
1. Normal flag clearing mechanism (TFFCA = 0)
Any of the ECT flags can be cleared by writing a one to the flag.
2. Fast flag clearing mechanism (TFFCA = 1)
With the timer fast flag clear all (TFFCA) enabled, the ECT flags can only be cleared by accessing
the various registers associated with the ECT modes of operation as described below. The flags
cannot be cleared via the normal flag clearing mechanism. This fast flag clearing mechanism has
the advantage of eliminating the software overhead required by a separate clear sequence. Extra
care must be taken to avoid accidental flag clearing due to unintended accesses.
— Input capture
A read from an input capture channel register causes the corresponding channel flag, CxF, to
be cleared in the TFLG1 register.
— Output compare
A write to the output compare channel register causes the corresponding channel flag, CxF, to
be cleared in the TFLG1 register.
— Timer counter
Any access to the TCNT register clears the TOF flag in the TFLG2 register.
— Pulse accumulator A
Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the
PAFLG register.
— Pulse accumulator B
Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.
— Modulus down counter
Any access to the MCCNT register clears the MCZF flag in the MCFLG register.
14.5.2
Reset
The reset state of each individual bit is listed within the register description section (Section 14.4,
“Memory Map and Register Definition”) which details the registers and their bit-fields.
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Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.5.3
Interrupts
This section describes interrupts originated by the ECT block. The MCU must service the interrupt
requests. Table 14-37 lists the interrupts generated by the ECT to communicate with the MCU.
Table 14-37. ECT Interrupts
Interrupt Source
Description
Timer channel 7–0
Active high timer channel interrupts 7–0
Modulus counter underflow
Active high modulus counter interrupt
Pulse accumulator B overflow
Active high pulse accumulator B interrupt
Pulse accumulator A input
Active high pulse accumulator A input interrupt
Pulse accumulator A overflow
Pulse accumulator overflow interrupt
Timer overflow
Timer 0verflow interrupt
The ECT only originates interrupt requests. The following is a description of how the module makes a
request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt
number are chip dependent.
14.5.3.1
Channel [7:0] Interrupt
This active high output will be asserted by the module to request a timer channel 7–0 interrupt to be
serviced by the system controller.
14.5.3.2
Modulus Counter Interrupt
This active high output will be asserted by the module to request a modulus counter underflow interrupt to
be serviced by the system controller.
14.5.3.3
Pulse Accumulator B Overflow Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator B overflow
interrupt to be serviced by the system controller.
14.5.3.4
Pulse Accumulator A Input Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator A input
interrupt to be serviced by the system controller.
14.5.3.5
Pulse Accumulator A Overflow Interrupt
This active high output will be asserted by the module to request a timer pulse accumulator A overflow
interrupt to be serviced by the system controller.
14.5.3.6
Timer Overflow Interrupt
This active high output will be asserted by the module to request a timer overflow interrupt to be serviced
by the system controller.
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Chapter 15
Inter-Integrated Circuit (IICV3) Block Description
Version
Number
Date
1.0
May-20-2005
Initial. Distributed only within Freescale
1.3
Jul-28-2006
Update flow-chart of interrupt routine for 10-bit address
1.4
Nov-17-2006
Revise Table1-5
15.1
Author
Description of Changes
Introduction
The inter-IC bus (IIC) is a two-wire, bidirectional serial bus that provides a simple, efficient method of data
exchange between devices. Being a two-wire device, the IIC bus minimizes the need for large numbers of
connections between devices, and eliminates the need for an address decoder.
This bus is suitable for applications requiring occasional communications over a short distance between a
number of devices. It also provides flexibility, allowing additional devices to be connected to the bus for
further expansion and system development.
The interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
15.1.1
Features
The IIC module has the following key features:
• Compatible with I2C bus standard
• Multi-master operation
• Software programmable for one of 256 different serial clock frequencies
• Software selectable acknowledge bit
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated start signal generation
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
•
•
•
•
Acknowledge bit generation/detection
Bus busy detection
General Call Address detection
Compliant to ten-bit address
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
15.1.2
Modes of Operation
The IIC functions the same in normal, special, and emulation modes. It has two low power modes: wait
and stop modes.
15.1.3
Block Diagram
The block diagram of the IIC module is shown in Figure 15-1.
IIC
Registers
Start
Stop
Arbitration
Control
Clock
Control
In/Out
Data
Shift
Register
Interrupt
bus_clock
SCL
SDA
Address
Compare
Figure 15-1. IIC Block Diagram
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
15.2
External Signal Description
The IICV3 module has two external pins.
15.2.1
IIC_SCL — Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
15.2.2
IIC_SDA — Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
15.3
Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the IIC module.
15.3.1
Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
0x0000
IBAD
R
W
0x0001
IBFD
R
W
0x0002
IBCR
W
R
0x0003
IBSR
W
0x0004
IBDR
W
0x0005
IBCR2
R
R
R
W
Bit 7
6
5
4
3
2
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBEN
IBIE
MS/SL
Tx/Rx
TXAK
0
0
TCF
IAAS
IBB
D7
D6
D5
GCEN
ADTYPE
0
RSTA
Bit 0
0
IBC0
IBSWAI
0
SRW
D4
D3
D2
D1
D0
0
0
AD10
AD9
AD8
IBAL
IBIF
RXAK
= Unimplemented or Reserved
Figure 15-2. IIC Register Summary
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
15.3.1.1
IIC Address Register (IBAD)
Module Base +0x0000
7
6
5
4
3
2
1
AD7
AD6
AD5
AD4
AD3
AD2
AD1
0
0
0
0
0
0
0
R
0
0
W
Reset
0
= Unimplemented or Reserved
Figure 15-3. IIC Bus Address Register (IBAD)
Read and write anytime
This register contains the address the IIC bus will respond to when addressed as a slave; note that it is not
the address sent on the bus during the address transfer.
Table 15-1. IBAD Field Descriptions
Field
Description
7:1
AD[7:1]
Slave Address — Bit 1 to bit 7 contain the specific slave address to be used by the IIC bus module.The default
mode of IIC bus is slave mode for an address match on the bus.
0
Reserved
15.3.1.2
Reserved — Bit 0 of the IBAD is reserved for future compatibility. This bit will always read 0.
IIC Frequency Divider Register (IBFD)
Module Base + 0x0001
7
6
5
4
3
2
1
0
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
0
0
0
0
0
0
0
0
R
W
Reset
= Unimplemented or Reserved
Figure 15-4. IIC Bus Frequency Divider Register (IBFD)
Read and write anytime
Table 15-2. IBFD Field Descriptions
Field
Description
7:0
IBC[7:0]
I Bus Clock Rate 7:0 — This field is used to prescale the clock for bit rate selection. The bit clock generator is
implemented as a prescale divider — IBC7:6, prescaled shift register — IBC5:3 select the prescaler divider and
IBC2-0 select the shift register tap point. The IBC bits are decoded to give the tap and prescale values as shown
in Table 15-3.
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
Table 15-3. I-Bus Tap and Prescale Values
IBC2-0
(bin)
SCL Tap
(clocks)
SDA Tap
(clocks)
000
5
1
001
6
1
010
7
2
011
8
2
100
9
3
101
10
3
110
12
4
111
15
4
IBC5-3
(bin)
scl2start
(clocks)
scl2stop
(clocks)
scl2tap
(clocks)
tap2tap
(clocks)
000
2
7
4
1
001
2
7
4
2
010
2
9
6
4
011
6
9
6
8
100
14
17
14
16
101
30
33
30
32
110
62
65
62
64
111
126
129
126
128
Table 15-4. Multiplier Factor
IBC7-6
MUL
00
01
01
02
10
04
11
RESERVED
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 15-3, all subsequent tap points are separated by 2IBC5-3 as shown in the
tap2tap column in Table 15-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 15-4.
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
SCL Divider
SCL
SDA Hold
SDA
SDA
SCL Hold(stop)
SCL Hold(start)
SCL
START condition
STOP condition
Figure 15-5. SCL Divider and SDA Hold
The equation used to generate the divider values from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table 15-5. The equation used to generate the SDA Hold value from the IBFD bits is:
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
Table 15-5. IIC Divider and Hold Values (Sheet 1 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
MUL=1
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
Table 15-5. IIC Divider and Hold Values (Sheet 2 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20/22
22/24
24/26
26/28
28/30
30/32
34/36
40/42
28/32
32/36
36/40
40/44
44/48
48/52
56/60
68/72
48
56
64
72
80
88
104
128
80
96
112
128
144
160
192
240
160
192
224
256
288
320
384
480
320
384
448
512
576
7
7
8
8
9
9
10
10
7
7
9
9
11
11
13
13
9
9
13
13
17
17
21
21
9
9
17
17
25
25
33
33
17
17
33
33
49
49
65
65
33
33
65
65
97
6
7
8
9
10
11
13
16
10
12
14
16
18
20
24
30
18
22
26
30
34
38
46
58
38
46
54
62
70
78
94
118
78
94
110
126
142
158
190
238
158
190
222
254
286
11
12
13
14
15
16
18
21
15
17
19
21
23
25
29
35
25
29
33
37
41
45
53
65
41
49
57
65
73
81
97
121
81
97
113
129
145
161
193
241
161
193
225
257
289
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
Table 15-5. IIC Divider and Hold Values (Sheet 3 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
640
768
960
640
768
896
1024
1152
1280
1536
1920
1280
1536
1792
2048
2304
2560
3072
3840
97
129
129
65
65
129
129
193
193
257
257
129
129
257
257
385
385
513
513
318
382
478
318
382
446
510
574
638
766
958
638
766
894
1022
1150
1278
1534
1918
321
385
481
321
385
449
513
577
641
769
961
641
769
897
1025
1153
1281
1537
1921
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
40
44
48
52
56
60
68
80
56
64
72
80
88
96
112
136
96
112
128
144
160
176
208
256
160
14
14
16
16
18
18
20
20
14
14
18
18
22
22
26
26
18
18
26
26
34
34
42
42
18
12
14
16
18
20
22
26
32
20
24
28
32
36
40
48
60
36
44
52
60
68
76
92
116
76
22
24
26
28
30
32
36
42
30
34
38
42
46
50
58
70
50
58
66
74
82
90
106
130
82
MUL=2
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
Table 15-5. IIC Divider and Hold Values (Sheet 4 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
192
224
256
288
320
384
480
320
384
448
512
576
640
768
960
640
768
896
1024
1152
1280
1536
1920
1280
1536
1792
2048
2304
2560
3072
3840
2560
3072
3584
4096
4608
5120
6144
7680
18
34
34
50
50
66
66
34
34
66
66
98
98
130
130
66
66
130
130
194
194
258
258
130
130
258
258
386
386
514
514
258
258
514
514
770
770
1026
1026
92
108
124
140
156
188
236
156
188
220
252
284
316
380
476
316
380
444
508
572
636
764
956
636
764
892
1020
1148
1276
1532
1916
1276
1532
1788
2044
2300
2556
3068
3836
98
114
130
146
162
194
242
162
194
226
258
290
322
386
482
322
386
450
514
578
642
770
962
642
770
898
1026
1154
1282
1538
1922
1282
1538
1794
2050
2306
2562
3074
3842
80
81
82
83
84
72
80
88
96
104
28
28
32
32
36
24
28
32
36
40
44
48
52
56
60
MUL=4
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Table 15-5. IIC Divider and Hold Values (Sheet 5 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
112
128
152
112
128
144
160
176
192
224
272
192
224
256
288
320
352
416
512
320
384
448
512
576
640
768
960
640
768
896
1024
1152
1280
1536
1920
1280
1536
1792
2048
2304
2560
3072
3840
2560
3072
36
40
40
28
28
36
36
44
44
52
52
36
36
52
52
68
68
84
84
36
36
68
68
100
100
132
132
68
68
132
132
196
196
260
260
132
132
260
260
388
388
516
516
260
260
44
52
64
40
48
56
64
72
80
96
120
72
88
104
120
136
152
184
232
152
184
216
248
280
312
376
472
312
376
440
504
568
632
760
952
632
760
888
1016
1144
1272
1528
1912
1272
1528
64
72
84
60
68
76
84
92
100
116
140
100
116
132
148
164
180
212
260
164
196
228
260
292
324
388
484
324
388
452
516
580
644
772
964
644
772
900
1028
1156
1284
1540
1924
1284
1540
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Table 15-5. IIC Divider and Hold Values (Sheet 6 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
3584
4096
4608
5120
6144
7680
5120
6144
7168
8192
9216
10240
12288
15360
516
516
772
772
1028
1028
516
516
1028
1028
1540
1540
2052
2052
1784
2040
2296
2552
3064
3832
2552
3064
3576
4088
4600
5112
6136
7672
1796
2052
2308
2564
3076
3844
2564
3076
3588
4100
4612
5124
6148
7684
Note:Since the bus frequency is speeding up,the SCL Divider could be expanded by it.Therefore,in the
table,when IBC[7:0] is from $00 to $0F,the SCL Divider is revised by the format value1/value2.Value1 is
the divider under the low frequency.Value2 is the divider under the high frequency.How to select the
divider depends on the bus frequency.When IBC[7:0] is from $10 to $BF,the divider is not changed.
15.3.1.3
IIC Control Register (IBCR)
Module Base + 0x0002
7
6
5
4
3
IBEN
IBIE
MS/SL
Tx/Rx
TXAK
R
1
0
0
0
IBSWAI
RSTA
W
Reset
2
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-6. IIC Bus Control Register (IBCR)
Read and write anytime
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Table 15-6. IBCR Field Descriptions
Field
Description
7
IBEN
I-Bus Enable — This bit controls the software reset of the entire IIC bus module.
0 The module is reset and disabled. This is the power-on reset situation. When low the interface is held in reset
but registers can be accessed
1 The IIC bus module is enabled.This bit must be set before any other IBCR bits have any effect
If the IIC bus module is enabled in the middle of a byte transfer the interface behaves as follows: slave mode
ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected.
Master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle
may become corrupt. This would ultimately result in either the current bus master or the IIC bus module losing
arbitration, after which bus operation would return to normal.
6
IBIE
I-Bus Interrupt Enable
0 Interrupts from the IIC bus module are disabled. Note that this does not clear any currently pending interrupt
condition
1 Interrupts from the IIC bus module are enabled. An IIC bus interrupt occurs provided the IBIF bit in the status
register is also set.
5
MS/SL
Master/Slave Mode Select Bit — Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START
signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP
signal is generated and the operation mode changes from master to slave.A STOP signal should only be
generated if the IBIF flag is set. MS/SL is cleared without generating a STOP signal when the master loses
arbitration.
0 Slave Mode
1 Master Mode
4
Tx/Rx
Transmit/Receive Mode Select Bit — This bit selects the direction of master and slave transfers. When
addressed as a slave this bit should be set by software according to the SRW bit in the status register. In master
mode this bit should be set according to the type of transfer required. Therefore, for address cycles, this bit will
always be high.
0 Receive
1 Transmit
3
TXAK
Transmit Acknowledge Enable — This bit specifies the value driven onto SDA during data acknowledge cycles
for both master and slave receivers. The IIC module will always acknowledge address matches, provided it is
enabled, regardless of the value of TXAK. Note that values written to this bit are only used when the IIC bus is a
receiver, not a transmitter.
0 An acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte data
1 No acknowledge signal response is sent (i.e., acknowledge bit = 1)
2
RSTA
Repeat Start — Writing a 1 to this bit will generate a repeated START condition on the bus, provided it is the
current bus master. This bit will always be read as a low. Attempting a repeated start at the wrong time, if the bus
is owned by another master, will result in loss of arbitration.
1 Generate repeat start cycle
1
Reserved — Bit 1 of the IBCR is reserved for future compatibility. This bit will always read 0.
RESERVED
0
IBSWAI
I Bus Interface Stop in Wait Mode
0 IIC bus module clock operates normally
1 Halt IIC bus module clock generation in wait mode
Wait mode is entered via execution of a CPU WAI instruction. In the event that the IBSWAI bit is set, all
clocks internal to the IIC will be stopped and any transmission currently in progress will halt.If the CPU
were woken up by a source other than the IIC module, then clocks would restart and the IIC would resume
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from where was during the previous transmission. It is not possible for the IIC to wake up the CPU when
its internal clocks are stopped.
If it were the case that the IBSWAI bit was cleared when the WAI instruction was executed, the IIC internal
clocks and interface would remain alive, continuing the operation which was currently underway. It is also
possible to configure the IIC such that it will wake up the CPU via an interrupt at the conclusion of the
current operation. See the discussion on the IBIF and IBIE bits in the IBSR and IBCR, respectively.
15.3.1.4
IIC Status Register (IBSR)
Module Base + 0x0003
R
7
6
5
TCF
IAAS
IBB
4
3
2
0
SRW
IBAL
1
0
RXAK
IBIF
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-7. IIC Bus Status Register (IBSR)
This status register is read-only with exception of bit 1 (IBIF) and bit 4 (IBAL), which are software
clearable.
Table 15-7. IBSR Field Descriptions
Field
Description
7
TCF
Data Transferring Bit — While one byte of data is being transferred, this bit is cleared. It is set by the falling
edge of the 9th clock of a byte transfer. Note that this bit is only valid during or immediately following a transfer
to the IIC module or from the IIC module.
0 Transfer in progress
1 Transfer complete
6
IAAS
Addressed as a Slave Bit — When its own specific address (I-bus address register) is matched with the calling
address or it receives the general call address with GCEN== 1,this bit is set.The CPU is interrupted provided the
IBIE is set.Then the CPU needs to check the SRW bit and set its Tx/Rx mode accordingly.Writing to the I-bus
control register clears this bit.
0 Not addressed
1 Addressed as a slave
5
IBB
Bus Busy Bit
0 This bit indicates the status of the bus. When a START signal is detected, the IBB is set. If a STOP signal is
detected, IBB is cleared and the bus enters idle state.
1 Bus is busy
4
IBAL
Arbitration Lost — The arbitration lost bit (IBAL) is set by hardware when the arbitration procedure is lost.
Arbitration is lost in the following circumstances:
1. SDA sampled low when the master drives a high during an address or data transmit cycle.
2. SDA sampled low when the master drives a high during the acknowledge bit of a data receive cycle.
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
This bit must be cleared by software, by writing a one to it. A write of 0 has no effect on this bit.
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Table 15-7. IBSR Field Descriptions (continued)
Field
Description
3
Reserved — Bit 3 of IBSR is reserved for future use. A read operation on this bit will return 0.
RESERVED
2
SRW
Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address
sent from the master
This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address
match and no other transfers have been initiated.
Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
1
IBIF
I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs:
— Arbitration lost (IBAL bit set)
— Data transfer complete (TCF bit set)
— Addressed as slave (IAAS bit set)
It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one
to it. A write of 0 has no effect on this bit.
0
RXAK
Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received
acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8
bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock.
0 Acknowledge received
1 No acknowledge received
15.3.1.5
IIC Data I/O Register (IBDR)
Module Base + 0x0004
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
R
W
Reset
Figure 15-8. IIC Bus Data I/O Register (IBDR)
In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave
mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the
IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission
to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then
reading the IBDR will not initiate the receive.
Reading the IBDR will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IBDR correctly by reading it back.
In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for
the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the
required R/W bit (in position D0).
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15.3.1.6
IIC Control Register 2(IBCR2)
Module Base + 0x0005
7
6
GCEN
ADTYPE
0
0
R
5
4
3
0
0
0
2
1
0
AD10
AD9
AD8
0
0
0
W
Reset
0
0
0
Figure 15-9. IIC Bus Control Register 2(IBCR2)
This register contains the variables used in general call and in ten-bit address.
Read and write anytime
Table 15-8. IBCR2 Field Descriptions
Field
Description
General Call Enable.
0 General call is disabled. The module dont receive any general call data and address.
1 enable general call. It indicates that the module can receive address and any data.
7
GCEN
6
ADTYPE
Address Type— This bit selects the address length. The variable must be configured correctly before IIC enters
slave mode.
0 7-bit address
1 10-bit address
5,4,3
Reserved — Bit 5,4 and 3 of the IBCR2 are reserved for future compatibility. These bits will always read 0.
RESERVED
2:0
AD[10:8]
15.4
Slave Address [10:8] —These 3 bits represent the MSB of the 10-bit address when address type is asserted
(ADTYPE = 1).
Functional Description
This section provides a complete functional description of the IICV3.
15.4.1
I-Bus Protocol
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. Logic AND function is exercised on both
lines with external pull-up resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer and STOP signal. They are described briefly in the following sections and illustrated in
Figure 15-10.
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MSB
SCL
SDA
1
LSB
2
3
4
5
6
7
Calling Address
Read/
Write
MSB
SDA
MSB
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
SCL
8
1
XXX
3
4
5
6
7
8
Calling Address
Read/
Write
3
4
5
6
7
8
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte
1
XX
Ack
Bit
9
No Stop
Ack Signal
Bit
MSB
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Start
Signal
2
Ack
Bit
LSB
2
LSB
1
LSB
2
3
4
5
6
7
8
9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
Repeated
Start
Signal
New Calling Address
Read/
Write
No Stop
Ack Signal
Bit
Figure 15-10. IIC-Bus Transmission Signals
15.4.1.1
START Signal
When the bus is free, i.e. no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal.As shown in Figure 15-10, a
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
SDA
SCL
START Condition
STOP Condition
Figure 15-11. Start and Stop Conditions
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15.4.1.2
Slave Address Transmission
The first byte of data transfer immediately after the START signal is the slave address transmitted by the
master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
If the calling address is 10-bit, another byte is followed by the first byte.Only the slave with a calling
address that matches the one transmitted by the master will respond by sending back an acknowledge bit.
This is done by pulling the SDA low at the 9th clock (see Figure 15-10).
No two slaves in the system may have the same address. If the IIC bus is master, it must not transmit an
address that is equal to its own slave address. The IIC bus cannot be master and slave at the same
time.However, if arbitration is lost during an address cycle the IIC bus will revert to slave mode and operate
correctly even if it is being addressed by another master.
15.4.1.3
Data Transfer
As soon as successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a
direction specified by the R/W bit sent by the calling master
All transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address
information for the slave device.
Each data byte is 8 bits long. Data may be changed only while SCL is low and must be held stable while
SCL is high as shown in Figure 15-10. There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte has to be followed by an acknowledge bit, which is signalled from the
receiving device by pulling the SDA low at the ninth clock. So one complete data byte transfer needs nine
clock pulses.
If the slave receiver does not acknowledge the master, the SDA line must be left high by the slave. The
master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to
commence a new calling.
If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means 'end
of data' to the slave, so the slave releases the SDA line for the master to generate STOP or START
signal.Note in order to release the bus correctly,after no-acknowledge to the master,the slave must be
immediately switched to receiver and a following dummy reading of the IBDR is necessary.
15.4.1.4
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the
master may generate a START signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a low-to-high transition of SDA while
SCL at logical 1 (see Figure 15-10).
The master can generate a STOP even if the slave has generated an acknowledge at which point the slave
must release the bus.
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15.4.1.5
Repeated START Signal
As shown in Figure 15-10, a repeated START signal is a START signal generated without first generating
a STOP signal to terminate the communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode) without releasing the bus.
15.4.1.6
Arbitration Procedure
The Inter-IC bus is a true multi-master bus that allows more than one master to be connected on it. If two
or more masters try to control the bus at the same time, a clock synchronization procedure determines the
bus clock, for which the low period is equal to the longest clock low period and the high is equal to the
shortest one among the masters. The relative priority of the contending masters is determined by a data
arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits
logic 0. The losing masters immediately switch over to slave receive mode and stop driving SDA output.
In this case the transition from master to slave mode does not generate a STOP condition. Meanwhile, a
status bit is set by hardware to indicate loss of arbitration.
15.4.1.7
Clock Synchronization
Because wire-AND logic is performed on SCL line, a high-to-low transition on SCL line affects all the
devices connected on the bus. The devices start counting their low period and as soon as a device's clock
has gone low, it holds the SCL line low until the clock high state is reached.However, the change of low to
high in this device clock may not change the state of the SCL line if another device clock is within its low
period. Therefore, synchronized clock SCL is held low by the device with the longest low period. Devices
with shorter low periods enter a high wait state during this time (see Figure 15-11). When all devices
concerned have counted off their low period, the synchronized clock SCL line is released and pulled high.
There is then no difference between the device clocks and the state of the SCL line and all the devices start
counting their high periods.The first device to complete its high period pulls the SCL line low again.
WAIT
Start Counting High Period
SCL1
SCL2
SCL
Internal Counter Reset
Figure 15-12. IIC-Bus Clock Synchronization
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15.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
15.4.1.9
Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it.If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
15.4.1.10 Ten-bit Address
A ten-bit address is indicated if the first 5 bits of the first address byte are 0x11110. The following rules
apply to the first address byte.
SLAVE
ADDRESS
0000000
R/W BIT
DESCRIPTION
0
0000010
x
0000011
11111XX
11110XX
x
x
x
General call address
Reserved for different bus
format
Reserved for future purposes
Reserved for future purposes
10-bit slave addressing
Figure 15-13. Definition
of bits in the first byte.
The address type is identified by ADTYPE. When ADTYPE is 0, 7-bit address is applied. Reversely, the
address is 10-bit address.Generally, there are two cases of 10-bit address.See the Fig.1-14 and 1-15.
S
Slave Add1st 7bits
11110+AD10+AD9
R/W
0
A1
Slave Add 2nd byte
A2
AD[8:1]
Data
A3
Figure 15-14. A master-transmitter addresses a slave-receiver with a 10-bit address
S
Slave Add1st 7bits
11110+AD10+AD9
R/W
0
A1
Slave Add 2nd byte
A2
AD[8:1]
Sr
Slave Add 1st 7bits R/W
A3 Data
11110+AD10+AD9
1
A4
Figure 15-15. A master-receiver addresses a slave-transmitter with a 10-bit address.
In the figure 1-15,the first two bytes are the similar to figure1-14.After the repeated START(Sr),the first
slave address is transmitted again, but the R/W is 1, meaning that the slave is acted as a transmitter.
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15.4.1.11 General Call Address
To broadcast using a general call, a device must first generate the general call address($00), then after
receiving acknowledge, it must transmit data.
In communication, as a slave device, provided the GCEN is asserted, a device acknowledges the broadcast
and receives data until the GCEN is disabled or the master device releases the bus or generates a new
transfer. In the broadcast, slaves always act as receivers. In general call, IAAS is also used to indicate the
address match.
In order to distinguish whether the address match is the normal address match or the general call address
match, IBDR should be read after the address byte has been received. If the data is $00, the match is
general call address match. The meaning of the general call address is always specified in the first data byte
and must be dealt with by S/W, the IIC hardware does not decode and process the first data byte.
When one byte transfer is done, the received data can be read from IBDR. The user can control the
procedure by enabling or disabling GCEN.
15.4.2
Operation in Run Mode
This is the basic mode of operation.
15.4.3
Operation in Wait Mode
IIC operation in wait mode can be configured. Depending on the state of internal bits, the IIC can operate
normally when the CPU is in wait mode or the IIC clock generation can be turned off and the IIC module
enters a power conservation state during wait mode. In the later case, any transmission or reception in
progress stops at wait mode entry.
15.4.4
Operation in Stop Mode
The IIC is inactive in stop mode for reduced power consumption. The STOP instruction does not affect IIC
register states.
15.5
Resets
The reset state of each individual bit is listed in Section 15.3, “Memory Map and Register Definition,”
which details the registers and their bit-fields.
15.6
Interrupts
IICV3 uses only one interrupt vector.
Table 15-9. Interrupt Summary
Interrupt
Offset
Vector
Priority
Source
Description
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IIC
Interrupt
—
—
—
IBAL, TCF, IAAS When either of IBAL, TCF or IAAS bits is set
may cause an interrupt based on arbitration
bits in IBSR
lost, transfer complete or address detect
register
conditions
Internally there are three types of interrupts in IIC. The interrupt service routine can determine the interrupt
type by reading the status register.
IIC Interrupt can be generated on
1. Arbitration lost condition (IBAL bit set)
2. Byte transfer condition (TCF bit set)
3. Address detect condition (IAAS bit set)
The IIC interrupt is enabled by the IBIE bit in the IIC control register. It must be cleared by writing 0 to
the IBF bit in the interrupt service routine.
15.7
Application Information
15.7.1
15.7.1.1
IIC Programming Examples
Initialization Sequence
Reset will put the IIC bus control register to its default status. Before the interface can be used to transfer
serial data, an initialization procedure must be carried out, as follows:
1. Update the frequency divider register (IBFD) and select the required division ratio to obtain SCL
frequency from system clock.
2. Update the ADTYPE of IBCR2 to define the address length, 7 bits or 10 bits.
3. Update the IIC bus address register (IBAD) to define its slave address. If 10-bit address is applied
IBCR2 should be updated to define the rest bits of address.
4. Set the IBEN bit of the IIC bus control register (IBCR) to enable the IIC interface system.
5. Modify the bits of the IIC bus control register (IBCR) to select master/slave mode, transmit/receive
mode and interrupt enable or not.
6. If supported general call, the GCEN in IBCR2 should be asserted.
15.7.1.2
Generation of START
After completion of the initialization procedure, serial data can be transmitted by selecting the 'master
transmitter' mode. If the device is connected to a multi-master bus system, the state of the IIC bus busy bit
(IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave address) can be sent. The data
written to the data register comprises the slave calling address and the LSB set to indicate the direction of
transfer required from the slave.
The bus free time (i.e., the time between a STOP condition and the following START condition) is built
into the hardware that generates the START cycle. Depending on the relative frequencies of the system
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clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address
to the IBDR before proceeding with the following instructions. This is illustrated in the following example.
An example of a program which generates the START signal and transmits the first byte of data (slave
address) is shown below:
CHFLAG
BRSET
IBSR,#$20,*
;WAIT FOR IBB FLAG TO CLEAR
TXSTART
BSET
IBCR,#$30
;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION
MOVB
CALLING,IBDR
;TRANSMIT THE CALLING ADDRESS, D0=R/W
BRCLR
IBSR,#$20,*
;WAIT FOR IBB FLAG TO SET
IBFREE
15.7.1.3
Post-Transfer Software Response
Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte
communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the
interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit
in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register
(IBDR) in receive mode or writing to IBDR in transmit mode.
Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function
is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation
is different when arbitration is lost.
Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit
mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR,
then the Tx/Rx bit should be toggled at this stage.
During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the
direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly.For slave mode data
cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine
the direction of the current transfer.
The following is an example of a software response by a 'master transmitter' in the interrupt routine.
ISR
TRANSMIT
BCLR
BRCLR
BRCLR
BRSET
MOVB
IBSR,#$02
IBCR,#$20,SLAVE
IBCR,#$10,RECEIVE
IBSR,#$01,END
DATABUF,IBDR
15.7.1.4
Generation of STOP
;CLEAR THE IBIF FLAG
;BRANCH IF IN SLAVE MODE
;BRANCH IF IN RECEIVE MODE
;IF NO ACK, END OF TRANSMISSION
;TRANSMIT NEXT BYTE OF DATA
A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply
generate a STOP signal after all the data has been transmitted. The following is an example showing how
a stop condition is generated by a master transmitter.
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Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
MASTX
END
EMASTX
TST
BEQ
BRSET
MOVB
DEC
BRA
BCLR
RTI
TXCNT
END
IBSR,#$01,END
DATABUF,IBDR
TXCNT
EMASTX
IBCR,#$20
;GET VALUE FROM THE TRANSMITING COUNTER
;END IF NO MORE DATA
;END IF NO ACK
;TRANSMIT NEXT BYTE OF DATA
;DECREASE THE TXCNT
;EXIT
;GENERATE A STOP CONDITION
;RETURN FROM INTERRUPT
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not
acknowledging the last byte of data which can be done by setting the transmit acknowledge bit (TXAK)
before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be
generated first. The following is an example showing how a STOP signal is generated by a master receiver.
MASR
DEC
BEQ
MOVB
DEC
BNE
BSET
RXCNT
ENMASR
RXCNT,D1
D1
NXMAR
IBCR,#$08
ENMASR
NXMAR
BRA
BCLR
MOVB
RTI
NXMAR
IBCR,#$20
IBDR,RXBUF
15.7.1.5
Generation of Repeated START
LAMAR
;DECREASE THE RXCNT
;LAST BYTE TO BE READ
;CHECK SECOND LAST BYTE
;TO BE READ
;NOT LAST OR SECOND LAST
;SECOND LAST, DISABLE ACK
;TRANSMITTING
;LAST ONE, GENERATE ‘STOP’ SIGNAL
;READ DATA AND STORE
At the end of data transfer, if the master continues to want to communicate on the bus, it can generate
another START signal followed by another slave address without first generating a STOP signal. A
program example is as shown.
RESTART
BSET
MOVB
IBCR,#$04
CALLING,IBDR
15.7.1.6
Slave Mode
;ANOTHER START (RESTART)
;TRANSMIT THE CALLING ADDRESS;D0=R/W
In the slave interrupt service routine, the module addressed as slave bit (IAAS) should be tested to check
if a calling of its own address has just been received. If IAAS is set, software should set the transmit/receive
mode select bit (Tx/Rx bit of IBCR) according to the R/W command bit (SRW). Writing to the IBCR
clears the IAAS automatically. Note that the only time IAAS is read as set is from the interrupt at the end
of the address cycle where an address match occurred, interrupts resulting from subsequent data transfers
will have IAAS cleared. A data transfer may now be initiated by writing information to IBDR, for slave
transmits, or dummy reading from IBDR, in slave receive mode. The slave will drive SCL low in-between
byte transfers, SCL is released when the IBDR is accessed in the required mode.
In slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the
next byte of data. Setting RXAK means an 'end of data' signal from the master receiver, after which it must
be switched from transmitter mode to receiver mode by software. A dummy read then releases the SCL
line so that the master can generate a STOP signal.
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15.7.1.7
Arbitration Lost
If several masters try to engage the bus simultaneously, only one master wins and the others lose
arbitration. The devices which lost arbitration are immediately switched to slave receive mode by the
hardware. Their data output to the SDA line is stopped, but SCL continues to be generated until the end of
the byte during which arbitration was lost. An interrupt occurs at the falling edge of the ninth clock of this
transfer with IBAL=1 and MS/SL=0. If one master attempts to start transmission while the bus is being
engaged by another master, the hardware will inhibit the transmission; switch the MS/SL bit from 1 to 0
without generating STOP condition; generate an interrupt to CPU and set the IBAL to indicate that the
attempt to engage the bus is failed. When considering these cases, the slave service