Maxim MAX1799EUP Cdma cellular/pcs system power supply Datasheet

19-1655; Rev 1; 2/01
NUAL
KIT MA
ATION
U
L
A
E
V
E
BL
AVAILA
CDMA Cellular/PCS System
Power Supplies
Typical Operating Circuit
Features
♦ One 300mA Low-Noise LDO
♦ Four 150mA Low-Noise LDOs
♦ 45µVRMS Noise from 10Hz to 100kHz
♦ >60dB Crosstalk Isolation Below 10kHz
♦ >60dB PSRR Below 10kHz
♦ 125mV (max) Dropout (OUT1 at 200mA)
♦ 100mV (max) Dropout (OUT2–5 at 100mA)
♦ Programmable Output Voltages
1.8V to 3.3V in 32 Steps
♦ 140ms (min) Reset Timer
♦ SPI- or I2C-Compatible Serial Interface
♦ Push-On/Push-Off Control Logic
♦ Two 150mA General Purpose Open-Drain Outputs
♦ Overcurrent and Thermal Protection (all LDOs)
♦ 1µA Shutdown Current
♦ 20-Pin Thermally-Enhanced TSSOP or QFN
Packages
Applications
CDMA Cellular/PCS Handsets
ONO
IRQ
OFF
WDOUT
IN4/5
2.5V
TO 5.5V
IN2/3
OUT1
VCC
IN1
ON
MAX1798
MAX1798A*
MAX1799
MAX1799A*
CS (AS)
SPI OR I 2C
SCLK (SCK)
RSO
RESET
OUT2
TX
RX
OUT4
BBA
DIN (SDA)
AUDIO OR
PLL + VCO
VIN1
BP
DR1
0.01µF
VIBRATOR
DR2
GND
Single-Cell Li+ Systems
2- or 3-Cell NiMH, NiCd, or Alkaline Systems
Ordering Information
PART
OUT3
OUT5
MSM CONTROLLER
PDAs, Palmtops, and Handy-Terminals
TEMP
RANGE
PINPACKAGE
INTERFACE
MAX1798EGP
-40°C to +85°C
20 QFN
SPI
MAX1798EUP
-40°C to +85°C
20 TSSOP-EP
SPI
MAX1798AEGP
-40°C to +85°C
20 QFN
SPI
MAX1798AEUP
-40°C to +85°C
20 TSSOP-EP
SPI
Ordering Information continued and Pin Configurations
appear at end of data sheet.
PGND
BACKLIGHT
( ) ARE FOR MAX1799/MAX1799A.
*-13% RESET THRESHOLD AND SHUTDOWN RESET TIMER ADDED.
SPI is a trademark of Motorola, Inc.
I2C is a trademark of Philips Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX1798/MAX1798A/MAX1799/MAX1799A
General Description
The MAX1798/MAX1798A/MAX1799/MAX1799A system
power supplies are designed specifically for CDMA cellular/PCS handsets. Each device contains five lowdropout linear regulators (LDOs), a 140ms (min) reset
timer, a serial interface, push-on/push-off control logic,
and two general-purpose open-drain outputs. Only the
serial interface is different between the MAX1798/
MAX1798A/MAX1799/MAX1799A: the MAX1798/
MAX1798A feature an SPI™-compatible serial interface,
and the MAX1799/MAX1799A feature an I2C™-compatible interface. The “A” parts have a -13% reset threshold, the non-A parts have a 9.5% threshold. The “A”
parts have a 175 delay on a reset-triggered shutdown,
the non-A shutdown instantly.
Each linear regulator features extremely low dropout
voltage, specified at two-thirds of the maximum output
current. LDO1 is rated for 300mA, while LDOs 2–5 are
each rated for 150mA. All LDOs are optimized for low
noise and isolation. Each LDO can be individually
enabled and disabled through the serial port, as well as
individually programmed to any of 32 voltages from
1.8V to 3.3V.
The MAX1798/MAX1798A/MAX1799/MAX1799As’ wide
2.5V to 5.5V input voltage range makes them compatible with a wide range of input supplies, including a single lithium-ion (Li+) cell battery. Both devices are
available in thermally-enhanced 20-pin TSSOP and QFN
exposed pad (EP) packages. Evaluation kits in TSSOP
(MAX1798EVKIT and MAX1799EVKIT) are available to
facilitate designs.
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
ABSOLUTE MAXIMUM RATINGS
OFF, DR1, DR2 to GND............................................-0.3V to +6V
IN1, IN2/3, IN4/5, DIN (SDA) to GND .......................-0.3V to +6V
SCLK (SCK), BP, ON to GND...................................-0.3V to +6V
RSO, ONO to GND .................................-0.3V to (VOUT1 + 0.3V)
PGND to GND.....................................................................±0.3V
OUT1, CS (AS) to GND ..............................-0.3V to (VIN1 + 0.3V)
OUT2, OUT3 to GND...............................-0.3V to (VIN2/3 + 0.3V)
OUT4, OUT5 to GND...............................-0.3V to (VIN4/5 + 0.3V)
Continuous Sink Current
DR1, DR2...............................................................100mARMS
RSO................................................................................25mA
Continuous Power Dissipation (TA = +70°C)
20-Pin QFN (derate 20mW/°C above +70°C) .................1.6W
20-Pin TSSOP (derate 26mW/°C above +70°C) .............2.1W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN1 = VIN2/3 = VIN4/5 = VSCLK (SCK) = VDIN (SDA) = V CS (AS) = V OFF = 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
IN1, IN2/3, IN4/5 Operating
Voltage
Undervoltage Lockout IN1
MIN
TYP
2.5
VUVLO-1
MAX
UNITS
5.5
V
IN1 rising edge
2.10
2.30
2.45
V
Undervoltage Lockout IN2/3
VUVLO-2/3
IN2/3 rising edge
2.10
2.30
2.45
V
Undervoltage Lockout IN4/5
VUVLO-4/5
IN4/5 rising edge
2.10
2.30
2.45
V
IN1 falling edge
0.9
Power-On Reset Threshold
Supply Current in Shutdown
Supply Current (Standby)
ISHDN
ION
OFF = 0, ON = IN1
OUT1 ON, other regulators OFF IOUT1 = 0
Supply Current (All Outputs On)
All regulators ON, IOUT_ = 0
BP Voltage
IBP ≤ 1nA
BP Supply Rejection
2.5V ≤ VIN1 ≤ 5.5V
1.231
2.1
V
1
10
µA
113
230
µA
µA
367
680
1.250
1.269
V
0.2
5
mV
OUT1 REGULATOR
Output Accuracy
IOUT1 = 70mA (Note 3)
-2
2
%
Output Accuracy
(Line and Load)
1mA ≤ IOUT1 ≤ 300mA,
2.5V ≤ VIN1 ≤ 5.5V, VOUT1 = 1.8V (Note 3)
-3
3
%
Nominal Voltage Adjust Range
32 steps through serial interface; Tables 2, 3
1.8
3.3
V
Dropout Voltage
IOUT1 = 1mA (Notes 1, 3)
1
IOUT1 = 200mA (Notes 1, 3)
73
Load Regulation
0.1mA ≤ IOUT1 ≤ 300mA
Line Regulation
2.5V ≤ VIN1 ≤ 5.5V, VOUT1 = 1.8V (Note 3)
-0.003
Current Limit
Output-Discharge Switch
Resistance in Shutdown
Regulator output turned off
OUT1 Reset Threshold
OUT1 rising and
falling
Output Voltage Noise
2
125
(MAX1798/MAX1799)
(MAX1798A/MAX1799A)
f = 10Hz to 100kHz, COUT = 4.7µF
mV
%/mA
-0.15
-0.03
0.11
%/V
320
500
850
mA
25
300
Ω
-9.5
-7.5
-5.5
-15
-13
-11
45
_______________________________________________________________________________________
%
µVRMS
CDMA Cellular/PCS System
Power Supplies
(VIN1 = VIN2/3 = VIN4/5 = VSCLK (SCK) = VDIN (SDA) = V CS (AS) = V OFF = 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT2–5 REGULATORS
Output Accuracy
IOUT_ = 50mA (Note 3)
-2
2
%
Output Accuracy
(Line and Load)
1mA ≤ IOUT_ ≤ 150mA,
2.5V ≤ VIN_ ≤ 5.5V, VOUT_ = 1.8V (Note 3)
-3
3
%
Nominal Voltage Adjust Range
32 steps through serial interface; Tables 2, 3
1.8
3.3
V
Dropout Voltage
IOUT_ = 1mA (Notes 1, 3)
1
IOUT_ = 100mA (Notes 1, 3)
50
Load Regulation
1mA ≤ IOUT_ ≤ 150mA
Line Regulation
2.5V ≤ VIN_ ≤ 5.5V, VOUT_ = 1.8V (Note 3)
Current Limit
100
-0.005
mV
%/mA
-0.15
-0.02
0.11
%/V
160
250
500
mA
300
Ω
Output-Discharge Switch
Resistance
Regulator output turned off
110
Output Voltage Noise
f = 10Hz to 100kHz, COUT = 2.2µF
45
µVRMS
LOGIC AND CONTROL INPUTS (ON, OFF, RSO, DIN (SDA), SCLK (SCK), CS (AS))
Reset Timer
Watchdog Timer
140
35
235
60
430
110
ms
ms
OUT1 Shutdown Timer
(MAX1798A/MAX1799A only)
175
295
540
ms
0.4
V
Input Low Level
VIL
Input High Level
VIH
1.6
V
SDA Output Low Level
(MAX1799 only)
IDIN (SDA) = 3mA
0.4
IDIN (SDA) = 6mA
0.6
OFF Pulldown Resistance
OFF = 5.5V
ONO Output Low Level
IONO = 1mA
ONO Output High Level
IONO = -1mA
RSO Output Low Level
IRSO = 1mA, VIN1 = 1V
RSO Output High Level
(Internal Pullup Resistor)
IRSO = 0
RSO Reset Resistance
RSO = 2.48V
DR1, DR2 Output Low Level
IDR1 = IDR2 = 100mA (Note 3)
DR1, DR2 OFF Current
(Leakage)
IOFF
VDR1 = VDR2 = 5.5V
80
155
360
kΩ
0.05
0.5
V
VOUT1 0.5
V
0.5
VOUT1 0.5
9
V
V
V
14
19
kΩ
0.2
0.5
V
1
µA
-1
THERMAL SHUTDOWN
Threshold
160
°C
Hysteresis
10
°C
_______________________________________________________________________________________
3
MAX1798/MAX1798A/MAX1799/MAX1799A
ELECTRICAL CHARACTERISTICS (continued)
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2/3 = VIN4/5 = VSCLK (SCK) = VDIN (SDA) = V CS (AS) = V OFF = 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
I2C (SMB) TIMING (MAX1799/MAX1799A)
Clock Frequency
SCK
Bus-Free Time Between START
and STOP
tBUF
1.3
µs
tHD_STA
0.6
µs
SCK Low Period
tLOW
1.3
µs
SCK High Period
tHIGH
0.6
µs
Setup Time Repeated START
Condition
tSU_STA
0.6
µs
Data Hold Time
tHD_DAT
0
µs
Data Setup Time
tSU_DAT
100
ns
Hold Time Repeated START
Condition
Maximum Pulse Width of Spikes
that Must Be Suppressed by the
Input Filter of Both SDA and
SCK Signals
tSP
Setup Time for STOP Condition
tSU_STO
50
ns
0.6
µs
SPI TIMING (MAX1798/MAX1798A)
SCLK Clock Frequency
fSCLK
2
MHz
SCLK Low Period
tcl
125
ns
SCLK High Period
tch
125
ns
Data Hold Time
tHD_DAT
0
ns
Data Setup Time
tSU_DAT
125
ns
CS Assertion to SCLK Rising
Edge Setup Time
tCSS
200
ns
CS Deassertion to SCLK Rising
Edge Setup Time
tCS1
200
ns
SCLK Rising Edge to CS
Deassertion
tCSH
200
ns
SCLK Rising Edge to CS
Assertion
tCSO
200
ns
CS High Period
tCSW
300
ns
4
_______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
(VIN1 = VIN2/3 = VIN4/5 = VSCLK (SCK) = VDIN (SDA) = V CS (AS) = V OFF = 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
IN1, IN2/3, IN4/5 Operating
Voltage
Undervoltage Lockout IN1
VUVLO-1
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 1)
2.5
5.5
V
IN1 rising edge
2.10
2.45
V
Undervoltage Lockout IN2/3
VUVLO-2/3
IN2/3 rising edge
2.10
2.45
V
Undervoltage Lockout IN4/5
VUVLO-4/5
IN4/5 rising edge
2.10
2.45
V
IN1 falling edge
0.9
2.1
V
Power-On Reset Threshold
OFF = 0, ON = IN1
OUT1 ON, other regulators OFF IOUT1 = 0
10
µA
230
µA
Supply Current (All Outputs On)
All regulators ON, IOUT_ = 0
680
µA
BP Voltage
IBP ≤ 1nA
1.225
1.275
V
OUT1 REGULATOR
Output Accuracy
IOUT1 = 70mA (Note 3)
-2.5
2.5
%
Output Accuracy
(Line and Load)
1mA ≤ IOUT1 ≤ 300mA,
2.5V ≤ VIN1 ≤ 5.5V, VOUT1 = 1.8V (Note 3)
-3.5
3.5
%
Nominal-Voltage Adjust Range
32 steps through serial interface; Tables 2, 3
1.8
3.3
V
Dropout Voltage
IOUT1 = 200mA (Notes 1, 3)
125
mV
Line Regulation
2.5V ≤ VIN1 ≤ 5.5V, VOUT1 = 1.8V (Note 3)
-0.15
0.11
%/V
320
850
mA
300
Ω
Supply Current in Shutdown
Supply Current (Standby)
ISHDN
ION
Current Limit
Output-Discharge Switch
Resistance in Shutdown
Regulator output turned off
OUT1 Reset Threshold
OUT1 rising and
falling
MAX1798/MAX1799
-9.5
-5.5
MAX1798A/MAX1799A
-15
-11
%
OUT2–5 REGULATORS
Output Accuracy
IOUT_ = 50mA (Note 3)
-2.5
2.5
%
Output Accuracy
(Line and Load)
1mA ≤ IOUT_ ≤ 150mA,
2.5V ≤ VIN_ ≤ 5.5V, VOUT_ = 1.8V (Note 3)
-3.5
3.5
%
Nominal-Voltage Adjust Range
32 steps through serial interface; Tables 2, 3
1.8
Dropout Voltage
IOUT_ = 100mA (Notes 1, 3)
Line Regulation
2.5V ≤ VIN_ ≤ 5.5V, VOUT_ = 1.8V (Note 3)
Current Limit
Output-Discharge Switch
Resistance in Shutdown
Regulator output turned off
3.3
V
100
mV
-0.15
0.11
%/V
160
500
mA
300
Ω
_______________________________________________________________________________________
5
MAX1798/MAX1798A/MAX1799/MAX1799A
ELECTRICAL CHARACTERISTICS
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = VIN2/3 = VIN4/5 = VSCLK (SCK) = VDIN (SDA) = V CS (AS) = V OFF = 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC AND CONTROL INPUTS (ON, OFF, RSO DIN (SDA), SCLK (SCK), CS (AS))
Reset Timer
140
430
ms
Watchdog Timer
35
110
ms
OUT1 Shutdown Timer
(MAX1798A/MAX1799A only)
175
540
ms
0.4
V
V
Input Low Level
Input High Level
VIL
VIH
SDA Output Low Level
(MAX1799 only)
1.6
IDIN (SDA) = 3mA
0.4
IDIN (SDA) = 6mA
0.6
V
Logic Input Current
0 ≤ VIN ≤ VIN1; ON, DIN (SDA),
SCLK (SCK), and CS (AS) only
-1
1
µA
OFF Pulldown Resistance
OFF = 5.5V
80
360
kΩ
ONO Output Low Level
IONO = 1mA
0.5
V
ONO Output High Level
IONO = -1mA
RSO Output Low Level
IRSO = 1mA, VIN1 = 1V
RSO Output High Level
(Internal Pullup Resistor)
IRSO = 0
RSO Reset Resistance
RSO = 2.48V
DR1, DR2 Output Low Level
IDR1 = IDR2 = 100mA (Note 3)
DR1, DR2 OFF Current
(Leakage)
IOFF
VDR1 = VDR2 = 5.5V
VOUT1 0.5
V
0.5
VOUT1 0.5
V
V
9
-1
19
kΩ
0.5
V
1
µA
400
kHz
I2C (SMB) TIMING (MAX1799/MAX1799A)
Clock Frequency
SCK
Bus-Free Time Between START
and STOP
tBUF
1.3
µs
tHD_STA
0.6
µs
SCK Low Period
tLOW
1.3
µs
SCK High Period
Hold Time Repeated START
Condition
tHIGH
0.6
µs
Setup Time Repeated START
Condition
tSU_STA
0.6
µs
Data Hold Time
tHD_DAT
0
Data Setup Time
tSU_DAT
100
ns
Setup Time for STOP Condition
tSU_STO
0.6
µs
6
89
_______________________________________________________________________________________
µs
CDMA Cellular/PCS System
Power Supplies
(VIN1 = VIN2/3 = VIN4/5 = VSCLK (SCK) = VDIN (SDA) = V CS (AS) = V OFF = 3.6V; ON = GND = PGND = 0; RSO, ONO, DR1, DR2 =
open; BP bypassed with 0.01µF, OUT1 bypassed with 4.7µF; OUT2, OUT3, OUT4, OUT5 bypassed with 2.2µF; OUT1–5 set to 2.98V,
TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
MHz
SPI TIMING (MAX1798/MAX1798A)
SCLK Clock Frequency
fSCLK
SCLK Low Period
tcl
125
ns
SCLK High Period
tch
125
ns
Data Hold Time
tHD_DAT
0
ns
Data Setup Time
tSU_DAT
125
ns
CS Assertion to SCLK Rising
Edge Setup Time
tCSS
200
ns
CS Deassertion to SCLK Rising
Edge Setup Time
tCS1
200
ns
SCLK Rising Edge to CS
Deassertion
tCSH
200
ns
SCLK Rising Edge to CS
Assertion
tCSO
200
ns
CS High Period
tCSW
300
ns
Note 1: The dropout voltage is defined as (VIN - VOUT) when VOUT is 100mV below the value of VOUT for VIN = VOUT + 1V.
Note 2: Specifications to -40°C are guaranteed by design, not production tested.
Note 3: Specifications are guaranteed by design, not production tested in the EGP (QFN) package.
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
1.5
1.5
1.5
ACCURACY (%)
0.5
VOUT1 = 3.3V
0
-0.5
VOUT1 = 1.8V
-1.0
VOUT1 = 2.98V
-0.5
-2.0
-2.0
50
100
150
200
LOAD CURRENT (mA)
250
VOUT1 = 2.98V
VOUT1 = 1.8V
-1.0
-1.5
0
VOUT1 = 3.3V
0
-1.5
300
ILOAD = 70mA
VOUT1(NOM) = 2.98V
1.0
0.5
ACCURACY (%)
1.0
1.0
ACCURACY (%)
2.0
MAX1798/99-02
2.0
MAX1798/99-01
2.0
OUTPUT VOLTAGE ACCURACY (OUT1)
vs. TEMPERATURE
MAX1798/99-03
OUTPUT VOLTAGE ACCURACY (OUT2–5)
vs. LOAD CURRENT
OUTPUT VOLTAGE ACCURACY (OUT1)
vs. LOAD CURRENT
0.5
0
-0.5
-1.0
-1.5
-2.0
0
25
50
75
100
LOAD CURRENT (mA)
125
150
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX1798/MAX1798A/MAX1799/MAX1799A
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
160
150
140
VOUT1 = 1.8V
VOUT1 = 2.98V
130
120
250
ILOAD = 200mA
200
150
100
ILOAD = 0
50
100
150
200
250
2.5
3.0
3.5
4.0
4.5
5.0
-40
5.5
MAX1798/99-06
35
60
85
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
125
25
70
60
100
TA = +85°C
75
TA = +25°C
100
150
200
250
300
COUT1 = 4.7µF
40
20
TA = -40°C
VOUT_ = 2.98V
ILOAD = 10mA
CBP = 0.01µF
10
0
0
50
50
30
50
25
0
COUT2–5 = 2.2µF
80
PSRR (dB)
DROPOUT VOLTAGE (mV)
TA = -40°C
90
MAX1798/99-09
150
MAX1798/99-07
TA = +25°C
50
0
25
50
75
100
125
0.01
150
0.1
1
10
100
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
FREQUENCY (kHz)
OUTPUT NOISE vs. LOAD CURRENT
OUTPUT NOISE
CHANNEL-TO-CHANNEL ISOLATION
vs. FREQUENCY
40
OUT2–5 = 2.98V
COUT2–5 = 2.2µF
30
20
f = 10Hz TO 100kHz
COUT2 = 2.2µF, ILOAD = 10mA
CBP = 0.01µF
f = 10Hz TO 100kHz
CBP = 0.01µF
10
100
LOAD CURRENT (mA)
1000
100µs/div
VOUT, 50µV/div
MAX1798/99-12
70
CHANNEL-TO-CHANNEL ISOLATION (dB)
MAX1798/99-10
OUT1 = 2.98V
COUT1 = 4.7µF
1
10
DROPOUT VOLTAGE (OUT2–5)
vs. LOAD CURRENT
75
0
-15
DROPOUT VOLTAGE (OUT1)
vs. LOAD CURRENT
TA = +85°C
10
160
TEMPERATURE (°C)
100
50
170
SUPPLY VOLTAGE (V)
125
60
180
LOAD CURRENT (mA)
150
0
190
140
2.0
300
MAX1798/99-08
0
VIN = 3.6V
ILOAD = 200mA
150
0
100
DROPOUT VOLTAGE (mV)
300
200
50
110
8
VOUT1 = 2.98V
350
GROUND-PIN CURRENT (µA)
170
MAX1798/99-05
180
400
MAX1798/99-11
GROUND-PIN CURRENT (µA)
VOUT1 = 3.3V
GROUND-PIN CURRENT (µA)
VIN1 = 3.6V
OUT2–5 OFF
MAX1798/99-04
200
190
GROUND-PIN CURRENT (OUT1)
vs. TEMPERATURE
GROUND-PIN CURRENT (OUT1)
vs. SUPPLY VOLTAGE (VIN1)
GROUND-PIN CURRENT (OUT1)
vs. LOAD CURRENT
OUTPUT NOISE (µVRMS)
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
60
50
40
30
20
10
0
OUT2/3 = 2.98V
COUT2/3 = 2.2µF
ILOAD = 100mA
CBP = 0.01µF
0.1
1
10
FREQUENCY (kHz)
_______________________________________________________________________________________
100
1000
CDMA Cellular/PCS System
Power Supplies
LOAD-TRANSIENT RESPONSE
(NEAR DROPOUT)
LOAD-TRANSIENT RESPONSE
MAX1798/99-13
MAX1798/99-15
VIN = 3.7V TO 4.0V, VOUT = 2.98V
ILOAD = 100mA
ILOAD
100mA/div
VOUT
AC-COUPLED
10mV/div
VIN1 = 3.5V, VOUT1 = 2.98V
ILOAD = 20mA TO 200mA, OUT2/3/4/5 = OFF
20µs/div
VOUT1
AC-COUPLED
50mV/div
VIN
500mV/div
VOUT1
AC-COUPLED
50mV/div
MAX1798/99-14
VIN1 = 3.1V, VOUT1 = 2.98V
ILOAD = 20mA TO 200mA, OUT2/3/4/5 = OFF
ILOAD
100mA/div
LINE-TRANSIENT RESPONSE
2µs/div
2µs/div
ENTERING SHUTDOWN
MAX1798/99-17
MAX1798/99-16
STARTUP
ON
2V/div
OFF
2V/div
VOUT
2V/div
VOUT1
1V/div
RSO
2V/div
40ms/div
TSSOP SAFE OPERATING AREA
(POWER DISSIPATION LIMIT)
QFN SAFE OPERATING AREA
(POWER DISSIPATION LIMIT)
800
700
VOUT = 1.8V
600
VOUT = 2.98V
500
400
300
TA = +25°C
TA = +85°C
200
2.5
3.0
3.5
1000
900
MAX RECOMMENDED OUTPUT CURRENT
800
700
600
VOUT = 1.8V
500
VOUT = 2.98V
400
300
TA = +25°C
TA = +85°C
200
4.0
4.5
5.0
INPUT VOLTAGE (V)
5.5
6.0
MAX RECOMMENDED INPUT VOLTAGE
MAX TOTAL OUTPUT CURRENT
MAXIMUM OUTPUT CURRENT (mA)
900
MAX RECOMMENDED INPUT VOLTAGE
MAXIMUM OUTPUT CURRENT (mA)
1000
MAX1798/99-18
10ms/div
2.5
3.0
3.5
4.0
4.5
5.0
5.5
MAX1798/99-19
ILOAD = 0
6.0
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
MAX1798/MAX1798A/MAX1799/MAX1799A
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
Pin Description
PIN
NAME
FUNCTION
TSSOP
QFN
1
19
CS (AS)
2
20
SCLK
(SCK)
Clock Input for Serial Interface. Data is read on the rising edge of the clock. SCLK for
MAX1798/MAX1798A. SCK for MAX1799/MAX1799A.
3
1
DIN
(SDA)
Data Input for Serial Interface. Data is read on the rising edge of the clock. DIN for
MAX1798/MAX1798A. SDA for MAX1799/MAX1799A.
4
2
ONO
ON Output. Indicates the state of ON. After initial power-up, the logic level of this pin follows that
of ON. Used to signal the microcontroller (µC) for an OFF request (allows push-on/push-off).
5
3
GND
Ground
6
4
BP
7
5
PGND
10
Chip-Select Input for SPI (MAX1798/MAX1798A). Address Select Input for I2C
(MAX1799/MAX1799A).
1.25V Reference Bypass. Connect a 0.01µF bypass capacitor to GND for reduced noise.
Do not load this pin.
Power Ground
8
6
RSO
Reset Output. Holds the µC system reset line low during initial startup and whenever OUT1 falls
out of regulation. RSO has a 140ms (min) timeout period and is an open-drain output with an
internal 14kΩ pullup to OUT1. The RSO line maintains a valid low output level for IN1 as low
as 1V.
9
7
DR1
2Ω Open-Drain Driver Output 1. Maximum sink current is 150mA (100mARMS). Can drive up to
10 LEDs for backlight or a vibrator motor.
10
8
DR2
2Ω Open-Drain Driver Output 2. Maximum sink current is 150mA (100mARMS). Can drive up to
10 LEDs for backlight or a vibrator motor.
11
9
OFF
OFF Input. A low level to this pin when ON is high turns off the IC once the watchdog timer has
timed out. A high-level input keeps the chip on. There is an internal 155kΩ pulldown resistor at
this input.
12
10
OUT5
Output 5, Output of Linear Regulator 5; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND.
13
11
IN4/5
Supply Inputs 4 and 5. Voltage supply for linear regulators 4 and 5.
14
12
OUT4
Output 4, Output of Linear Regulator 4; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND.
15
13
OUT1
Output 1, Output of Linear Regulator 1; 300mA (max) Output Current. Connect a 4.7µF ceramic
bypass capacitor to PGND.
16
14
IN1
17
15
OUT3
Output 3, Output of Linear Regulator 3; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND.
18
16
IN2/3
Supply Inputs 2 and 3. Voltage supply for linear regulators 2 and 3.
19
17
OUT2
Output 2, Output of Linear Regulator 2; 150mA (max) Output Current. Connect a 2.2µF ceramic
bypass capacitor to PGND.
20
18
ON
ON Input. An active-low turns on the device, enabling LDO1, RESET, the ON/OFF logic, and the
serial interface.
Supply Input 1. Voltage supply for linear regulator 1 and serial interface.
______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
COMMAND
DIN (SDA)
FUNCTION
C2
C1
C0
D4
Update DAC Outputs
0
0
0
U5
OUT1 DAC
0
0
1
OUT2 DAC
0
1
0
OUT3 DAC
0
1
1
OUT4 DAC
1
0
0
OUT5 DAC
1
0
1
Driver Outputs
1
1
0
X
X
X
DR2
DR1
ON/OFF Conrol
1
1
1
ON5
ON4
ON3
ON2
ON1
D3
D2
D1
D0
U2
U1
DAC1 (Table 2)
U4
DAC1 (Table 2)
U3
DAC1 (Table 2)
DAC1 (Table 2)
DAC1 (Table 2)
Note: C2 is MSB, and D0 is LSB. X = Don’t care.
Detailed Description
The MAX1798/MAX1798A/MAX1799/MAX1799A drive
CDMA cellular and PCS handsets or systems with
inputs from 2.5V to 5.5V. The devices contain five
LDOs, two open-drain outputs, and a reset output as
shown in Figure 1. All outputs are individually programmable through either an SPI (MAX1798/MAX1798A) or
I2C (MAX1799/MAX1799A) serial-port interface. The
outputs may be turned on or off individually through the
serial interface. Their output voltages are adjustable
from 1.8V to 3.3V in 32 increments. At power-up, all
outputs are at a default value of 2.98V, but only OUT1
is on. OUT1 is rated for 300mA and optimized for low
dropout. OUT2–5 are rated for 150mA. All LDOs are
optimized for low noise, high isolation, and low dropout.
OUT2–5 are set to 2.98V, but turned off. The control
data byte must be used to turn them on. If VIN1 falls
below 1V, a POR circuit resets all LDO voltages to
2.98V and OUT2–5 are turned off. If VIN2/3 or VIN4/5 fall
below 2.15V, the UVLO circuit turns off the corresponding output, but all LDO voltages remain at their prior
settings. OUT2–5 are optimized for low noise and high
isolation.
Open-Drain Outputs
The open-drain N-channel MOSFETs (DR1 and DR2,
Figure 2) have a nominal 2Ω on-resistance and can be
used to drive up to 10 LEDs for backlight or a vibrator
motor. DR1 and DR2 can sink 100mARMS (max). At
power-up, DR1 and DR2 are high impedance and are
commanded on by the control data byte.
Linear Regulator 1
RSO
Regulator 1 is a low-dropout linear regulator that
sources 300mA (max), operating from a 2.5V to 5.5V
input voltage (VIN1). OUT1 is turned on by using the on
button. OUT1 is turned off by using either the off pin or
the serial port. Its output can be adjusted from 1.8V to
3.3V from the SPI or I2C serial-port interface by setting
the control data byte (Table 1). OUT1 is always on
when the MAX1798/MAX1798A/MAX1799/MAX1799A
are on. If OUT1 is turned off, the entire IC shuts down. If
VIN1 falls below 1V, a POR circuit resets all LDO voltages to 2.98V and OUT1 is left on while OUT2–5 are
turned off.
RSO is an open-drain output, connected to OUT1
through an internal 14kΩ resistor. At power-up, OUT1
turns on and RSO is held low for 140ms (min). When RSO
goes high, OFF must be brought high within 35ms to
keep OUT1 on. Otherwise, if OFF is low, the watchdog
timer circuit counts down 35ms (min), and RSO is
actively held low while the entire device turns off.
The MAX1798/MAX1799 RSO goes low when OUT1
droops by more than 7.5% ±2% of its programmed output voltage. The MAX1798A/MAX1799A RSO goes low
when OUT1 droops by more than 13% ±2% of its programmed output voltage. RSO stays low for 140ms
(min) after OUT1 rises above the threshold. During this
time, the watchdog timer circuit is inactive.
The MAX1798A/MAX1799A have an additional timer
circuit to shut down the regulators when the RSO and
watchdog timer time out. If the OUT1 voltage level ever
exceeds the RSO threshold level before the reset and
Linear Regulators 2–5
Regulators 2–5 are LDOs that source 150mA (max)
from input voltages (VIN2/3 and VIN4/5) of 2.5V to 5.5V.
OUT2–5 can be turned on or off and adjusted from 1.8V
to 3.3V through the SPI or I2C serial-port interface by
setting the control data byte (Table 1). At power-up,
______________________________________________________________________________________
11
MAX1798/MAX1798A/MAX1799/MAX1799A
Table 1. Control Data Byte
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
ONO
ON
OFF
100kΩ
ON DETECT
IRQ
WDOUT
ON/OFF
LOGIC
OFF
155kΩ
ON
LDO1
(LOW NOISE, 0.3Ω)
IN1
OUT1
MSM CONTROLLER
THERMAL SHUTDOWN
1.8V TO 3.3V
300mA
VCC
4.7µF
5-BIT DAC
14kΩ
RESET
(140ms)
RSO
ACTIVE-LOW
RESET
THERMAL SHUTDOWN
LDO2
(LOW NOISE, 0.5Ω)
OUT2
5-BIT DAC
1.8V TO 3.3V
150mA
TX
2.2µF
IN2/3
10µF
THERMAL SHUTDOWN
LDO3
(LOW NOISE, 0.5Ω)
OUT3
5-BIT DAC
1.8V TO 3.3V
150mA
RX
2.2µF
THERMAL SHUTDOWN
LDO4
(LOW NOISE, 0.5Ω)
OUT4
5-BIT DAC
1.8V TO 3.3V
150mA
BBA + TCXO
2.2µF
IN4/5
THERMAL SHUTDOWN
LDO5
(LOW NOISE, 0.5Ω)
VBATT
2.5V TO 5.5V
OUT5
5-BIT DAC
1.8V TO 3.3V
150mA
AUDIO OR
PLL + VCO
2.2µF
VBATT
DR1
2Ω
CS (AS)*
SERIAL PORT
SPI OR I 2C
CONTROL
REGISTERS
SCLK (SCK)*
(ON/OFF
AND VOUT
PROGRAMMING)
DIN (SDA)*
VIBRATOR
MOTOR
DR2
2Ω
BP
0.01µF
MAX1798/MAX1798A
MAX1799/MAX1799A GND
PGND
( ) *ARE FOR MAX1799.
Figure 1. Typical Application Circuit/Functional Diagram
12
______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
tLOW
B
C
tHIGH
D
E
F
G
I
H
J
K
L
M
SCL
SDA
tSU:STA tHD:STA
tSU:DAT
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
tHD:DAT
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO SLAVE (OP/SUS BIT)
H = LSB OF DATA CLOCKED INTO SLAVE
I = SLAVE PULLS SMBDATA LINE LOW
tSU:STO tBUF
J = ACKNOWLEDGE CLOCKED INTO MASTER
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION, DATA EXECUTED BY SLAVE
M = NEW START CONDITION
Figure 2. I2C-Compatible Serial-Interface Timing Diagram
ON
(INPUT)
OUT1
RSO
(OUTPUT)
OFF
(INPUT)
140ms min
140ms min
10µs min
35ms max
35ms max
52ms typ
35ms max
ONO
(OUTPUT)
PULSED HIGH
OR CONTINUOUS HIGH
Figure 3. Push-On/Push-Off Startup and Shutdown Timing Diagram
watchdog timers time out, the shutdown timer is reset.
The shutdown timer requires continuous low RSO signal
and continuous nontriggered watchdog timer to shut
down the regulators.
ON and OFF Logic
See Figure 3. The MAX1798/MAX1798A/MAX1799/
MAX1799A power up when VIN1 is greater than 2.5V
and ON is low (ON button is pressed down momentarily). When ON returns high, the device remains on. It
turns on OUT1 and the serial interface port. Once
OUT1 is in regulation, RSO stays low an additional
140ms (min). At this time, OUT1 is on and set to 2.98V,
while OUT2–5 are disabled and set to 2.98V. To stay
on, the OFF pin must be in a high state within 35ms
(min) or the device will shut down and can only be
turned on by pressing the ON button. While ON is held
low, the status of OFF is irrelevant and OUT1 and the
serial port are on.
After initial power-up, the logic level of ONO follows the
logic level of ON but is level-shifted to OUT1 high voltage. This signal can be used to interrupt the system
controller, which can subsequently manage an orderly
shutdown through the serial port by turning off OUT1.
______________________________________________________________________________________
13
MAX1798/MAX1798A/MAX1799/MAX1799A
A
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
Hard Shutdown
To shut down the MAX1798/MAX1798A/MAX1799/
MAX1799A, drive OFF low or allow the internal resistor
to pull down OFF while ON is high. The device shuts
down after the watchdog timer has cleared (35ms min,
52ms typ). During shutdown, all LDO outputs and RSO
are actively pulled to GND, the open-drain drivers are
in a high-impedance state, and the serial port and reset
timer are inactive. Previously programmed output voltage data is retained in the internal registers as long as
VIN1 > 2.1V. If the device is turned back on by the ON
button, OUT1 automatically is enabled with the preshutdown output voltage. OUT2–5 automatically return to
their preshutdown voltages once they are enabled
through the serial interface.
Soft Shutdown
The serial port can also be used to shut down the
MAX1798/MAX1798A/MAX1799/MAX1799A. Using the
control data byte to disable OUT1 will shut down the
entire device. Once shut down, the only means to turn
on the device is through a momentary low on the ON
button.
Control Data Byte
The control data byte is 8 bits long (3 command bits
and 5 data bits). The first 3 bits specify the action to be
taken, while the last 5 bits set the output voltage or
ON/OFF status. Each regulator has an individual DAC
that sets the output voltage. The DAC registers are
double buffered to allow for simultaneous updating of
all outputs. The output voltage is programmed per
Table 2 or Table 3. At power-up, if no specific voltage
is programmed, OUT1–5 will be set for 2.98V. All DAC
programming must be shifted from the double buffer to
the DACs with the update DAC command (Table 1,
000XXXXX) for the programmed voltages to be seen at
the LDO outputs. The DACs can be updated one at a
time or all at once after all desired outputs are programmed. The ON/OFF status of the LDOs and drivers
is not double-buffered and takes immediate effect upon
CS returning high (SPI compatible) or upon the ninth
rising edge of SCK during the command byte (Figure 2,
edge L). A one turns on the LDO output or driver output, and a zero turns it off.
SPI-Compatible Serial Interface
CS along with SCLK and DIN to communicate. The serial port operates when the device is enabled, even when
RSO is low. The MAX1798/MAX1798A can support a
2MHz (max) data rate. This SPI-compatible port uses
the CPOL = CPHA = 0 protocol.
I2C-Compatible Serial Interface
Use an I2C-compatible 2-wire serial interface with the
MAX1799/MAX1799A to control the ON/OFF state and
output voltage of each regulator, the ON/OFF state of
the drivers, and to shut down the device. Use standard
I2C-compatible write-byte commands to program the
IC. Figure 2 is a timing diagram for the I2C protocol.
The MAX1799/MAX1799A is always a slave to the bus
master. The serial port operates when the device is
enabled, even when OUT1 and RSO are low. When AS
is high, the address is 0111111. When AS is low, the
address is 1001111. Two MAX1799/MAX1799A devices
can be controlled by a single bus master.
Output Voltage
The MAX1798/MAX1798A/MAX1799/MAX1799A are
supplied with factory-set output voltages. At power-up,
all DACS are set for 2.98V, while only OUT1 is enabled;
all other LDO outputs and drivers are off. OUT2–5,
DR1, and DR2 must be enabled on with the serial port.
OUT2–5 can be individually programmed through the
serial port from 1.8V to 3.3V in 32 steps, either while on
or off. OUT1 can be programmed in 32 steps from 1.8V
to 3.3V only while on. (If OUT1 is off, the serial port is
also off, and OUT1 cannot be programmed.) If OUT1 is
turned off through the serial port or the OFF pin, the
entire chip, including the serial port, will be shut down.
However, all previously programmed DAC settings will
be retained as long as a valid supply voltage is maintained on IN1 (VIN1 > 2.1V).
Current Limit
The MAX1798/MAX1798A/MAX1799/MAX1799A
include current limiting on each LDO output. OUT1 has
a current limit set at 500mA (320mA min), while
OUT2–5 have current limits set at 250mA (160mA min).
When the LDO output is in current limit, the current-limiter device monitors and controls the pass transistor’s
gate voltage, limiting the output current available from
the LDO. Once the excessive load is removed, normal
function resumes automatically.
Use an SPI-compatible 3-wire serial interface with the
MAX1798/MAX1798A to control the ON/OFF state and
output voltage of each regulator, the ON/OFF state of
the drivers, and to shut down the device. Figures 4a
and 4b are timing diagrams for the SPI protocol. The
MAX1798/MAX1798A is a write-only device and uses
14
______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
REGULATOR
OUTPUT
VOLTAGE (V)
REGULATOR
OUTPUT
VOLTAGE (V)
Table 3. OUT1–5 Output Voltages
(Hexadecimal Format)
DAC_ DATA
DAC_ DATA
OUT1–
OUT5
D4
D3
D2
D1
D0
OUT1–
OUT5
OUT5
OUT4
OUT3
OUT2
OUT1
1.800
0
0
0
0
0
1.800
A0
80
60
40
20
1.827
0
0
0
0
1
1.827
A1
81
61
41
21
1.854
0
0
0
1
0
1.854
A2
82
62
42
22
1.883
0
0
0
1
1
1.883
A3
83
63
43
23
1.912
0
0
1
0
0
1.912
A4
84
64
44
24
1.942
0
0
1
0
1
1.942
A5
85
65
45
25
1.974
0
0
1
1
0
1.974
A6
86
66
46
26
2.006
0
0
1
1
1
2.006
A7
87
67
47
27
2.039
0
1
0
0
0
2.039
A8
88
68
48
28
2.074
0
1
0
0
1
2.074
A9
89
69
49
29
2.109
0
1
0
1
0
2.109
AA
8A
6A
4A
2A
2.146
0
1
0
1
1
2.146
AB
8B
6B
4B
2B
2.184
0
1
1
0
0
2.184
AC
8C
6C
4C
2C
2.224
0
1
1
0
1
2.224
AD
8D
6D
4D
2D
2.265
0
1
1
1
0
2.265
AE
8E
6E
4E
2E
2.308
0
1
1
1
1
2.308
AF
8F
6F
4F
2F
2.352
1
0
0
0
0
2.352
B0
90
70
50
30
2.398
1
0
0
0
1
2.398
B1
91
71
51
31
2.445
1
0
0
1
0
2.445
B2
92
72
52
32
2.495
1
0
0
1
1
2.495
B3
93
73
53
33
2.547
1
0
1
0
0
2.547
B4
94
74
54
34
2.601
1
0
1
0
1
2.601
B5
95
75
55
35
2.657
1
0
1
1
0
2.657
B6
96
76
56
36
2.716
1
0
1
1
1
2.716
B7
97
77
57
37
2.777
1
1
0
0
0
2.777
B8
98
78
58
38
2.842
1
1
0
0
1
2.842
B9
99
79
59
39
2.909
1
1
0
1
0
2.909
BA
9A
7A
5A
3A
2.980
1
1
0
1
1
2.980
BB
9B
7B
5B
3B
3.054
1
1
1
0
0
3.054
BC
9C
7C
5C
3C
3.132
1
1
1
0
1
3.132
BD
9D
7D
5D
3D
3.214
1
1
1
1
0
3.214
BE
9E
7E
5E
3E
3.300
1
1
1
1
1
3.300
BF
9F
7F
5F
3F
______________________________________________________________________________________
15
MAX1798/MAX1798A/MAX1799/MAX1799A
Table 2. OUT1–5 Output Voltages
(Binary Format)
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
INSTRUCTION
EXECUTED
CS
1
8
SCLK
DIN
A2
A1
A0
D4
D3
D2
D1
DO
Figure 4a. Serial-Interface Timing Diagram
CS
tCSW
tCSH0
tCSS0
tCSH1
tCH
SCLK
tCL
tDS
tCSS1
tDH
DIN
Figure 4b. Detailed Serial-Interface Timing Diagram
Thermal-Overload Protection
The MAX1798/MAX1798A/MAX1799/MAX1799A integrate a separate thermal monitor for each linear regulator. When the junction temperature of any LDO exceeds
TJ = +160°C, the specific thermal sensor signals the
shutdown logic, turning off the pass transistor and
allowing that LDO to cool. The thermal sensor turns the
pass transistor on again after the LDO’s junction temperature cools by 10°C, resulting in a pulsed output
during continuous thermal-overload conditions. Due to
the substrate’s thermal conductivity, a thermal overload
on one LDO may possibly affect other LDOs on the
device.
16
Thermal-overload protection is designed to protect the
MAX1798/MAX1798A/MAX1799/MAX1799A in the
event of fault conditions. For continual operation, do not
exceed the absolute maximum junction-temperature
rating of TJ = +150°C.
Noise Reduction
Bypass BP to GND with an external 0.01µF bypass
capacitor. The MAX1798/MAX1798A/MAX1799/
MAX1799A exhibit 45µVRMS of output voltage noise.
Graphs of Output Noise vs. Load Current, Output Noise
(10Hz to 100kHz), PSRR vs. Frequency, and Channelto-Channel Isolation vs. Frequency appear in the
Typical Operating Characteristics.
______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
Capacitor Selection and
Regulator Stability
Use a 10µF low-ESR ceramic capacitor on the
MAX1798/MAX1798A/MAX1799/MAX1799A’s input if all
the supply inputs are connected together. Larger input
capacitance and lower ESR provide better supply noise
rejection and line-transient response. If IN1, IN2/3, and
IN4/5 are connected to different supply voltages,
bypass each input with a 4.7µF low-ESR ceramic
capacitor.
A minimum 4.7µF low-ESR ceramic capacitor is recommended on OUT1, and a minimum 2.2µF low-ESR
ceramic capacitor is recommended on OUT2–5. The
MAX1798/MAX1798A/MAX1799/MAX1799A are stable
with output capacitors in the ESR range of 10mΩ to 1Ω.
Use larger capacitors to reduce noise and improve
load-transient response, stability, and power-supply
rejection.
Note that some ceramic dielectrics exhibit large capacitance and ESR variation with temperature. With
dielectrics such as Z5U and Y5V, it may be necessary
to use a minimum 4.7µF on OUT2–5 to ensure stability
at temperatures below -10°C. With X7R or X5R
dielectrics, 2.2µF should be sufficient at all operating
temperatures. Tantalum capacitors may cause instability with the MAX1798/MAX1798A/MAX1799/MAX1799A
and are not recommended for this application.
Use a 0.01µF bypass capacitor at BP for low outputvoltage noise. Increasing the capacitance will slightly
decrease the output noise but will increase the startup
time. Values above 0.1µF provide no performance
advantage and are not recommended.
Line-Transient Considerations
The MAX1798/MAX1798A/MAX1799/MAX1799A are
designed to deliver low dropout voltages and low quiescent currents in battery-powered systems. Powersupply rejection is >60dB at low frequencies and rolls
off above 10kHz. See the Power-Supply Rejection Ratio
(PSRR) vs. Frequency graph in the Typical Operating
Characteristics.
When operating from sources other than batteries,
improved supply noise rejection and transient response
can be achieved by increasing the values of the input
and output bypass capacitors and through passive filtering techniques. The Typical Operating Characteristics show the MAX1798/MAX1798A/MAX1799/
MAX1799A line- and load-transient responses.
Load-Transient Considerations
The MAX1798/MAX1798A/MAX1799/MAX1799A loadtransient response graphs (see Typical Operating
Characteristics) show three components of the output
response: the output capacitor’s ESR spike, the regulator’s transient settling response, and the DC shift due to
the LDO’s load regulation. Increasing the output capacitor’s value and decreasing the ESR reduce the overshoot.
Dropout Voltage
A regulator’s minimum input-output voltage differential
(dropout voltage) determines the lowest usable supply
voltage. In battery-powered systems, this determines
the useful end-of-life battery voltage. Because the
MAX1798/MAX1798A/MAX1799/MAX1799A use Pchannel MOSFET pass transistors, their dropout voltage is a function of drain-to-source on-resistance
(R DS(ON) ) multiplied by the load current. See the
Dropout Voltage (OUT1) vs. Load Current graph in the
Typical Operating Characteristics.
Ordering Information (continued)
PART
TEMP
RANGE
PINPACKAGE
INTERFACE
MAX1799EGP
-40°C to +85°C
20 QFN
I2C
MAX1799EUP
-40°C to +85°C
20 TSSOP-EP
I2C
MAX1799AEGP
-40°C to +85°C
20 QFN
I2C
MAX1799AEUP
-40°C to +85°C
20 TSSOP-EP
I2C
Chip Information
TRANSISTOR COUNT: 1735
______________________________________________________________________________________
17
MAX1798/MAX1798A/MAX1799/MAX1799A
Applications Information
Pin Configurations
20
DIN (SDA)
19
18
17
IN2/3
OUT2
CS (AS) 1
ON
TOP VIEW
CS (AS)
SCLK (SCK)
TOP VIEW
16
1
19 OUT2
DIN (SDA) 3
18 IN2/3
OUT3
GND 5
BP 6
ON0
GND
2
MAX1798
MAX1798A
MAX1799
MAX1799A
3
BP
4
PGND
5
20 ON
SCLK (SCK) 2
ONO 4
15
14
IN1
13
OUT1
12
OUT4
11
IN4/5
PGND 7
17 OUT3
MAX1798
MAX1798A
MAX1799
MAX1799A
7
8
9
10
DR1
DR2
OFF
OUT5
6
15 OUT1
14 OUT4
13 IN4/5
DR1 9
12 OUT5
DR2 10
11 OFF
( ) ARE FOR MAX1799/MAX1799A ONLY.
QFN
5mm ✕ 5mm ✕ 0.85mm
( ) ARE FOR MAX1799/MAX1799A ONLY.
18
16 IN1
RSO 8
TSSOP
RS0
MAX1798/MAX1798A/MAX1799/MAX1799A
CDMA Cellular/PCS System
Power Supplies
______________________________________________________________________________________
CDMA Cellular/PCS System
Power Supplies
TSSOP, 4.0,EXP PADS.EPS
______________________________________________________________________________________
19
MAX1798/MAX1798A/MAX1799/MAX1799A
Package Information
CDMA Cellular/PCS System
Power Supplies
MAX1798/MAX1798A/MAX1799/MAX1799A
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.