021 CY7C1021 64K x 16 Static RAM Features • High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 1320 mW (max.) • Automatic power-down when deselected • Independent Control of Upper and Lower bits • Available in 44-pin TSOP II and 400-mil SOJ (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Functional Description Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the write enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable The CY7C1021 is available in standard 44-pin TSOP Type II and 400-mil-wide SOJ packages. Logic Block Diagram Pin Configuration SOJ / TSOP II Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 64K x 16 RAM Array 512 X 2048 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC I/O1 – I/O8 I/O9 – I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC 1021-2 Selection Guide 7C1021-10 Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Maximum CMOS Standby Current (mA) Commercial L 7C1021-12 7C1021-15 7C1021-20 10 12 15 20 220 220 220 220 5 5 5 5 0.5 0.5 0.5 0.5 Shaded areas contain preliminary information. Cypress Semiconductor Corporation Document #: 38-05054 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C1021 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Latch-Up Current..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High Z State[1] ......................................–0.5V to VCC+0.5V DC Input Voltage [1] Ambient Temperature[2] VCC 0°C to +70°C 5V ± 10% –40°C to +85°C 5V ± 10% Commercial Industrial ..................................–0.5V to VCC+0.5V Electrical Characteristics Over the Operating Range Test Conditions Parameter Description VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VIH Input HIGH Voltage 7C1021-10 7C1021-12 7C1021-15 7C1021-20 Min. Min. Min. Min. Max. 2.4 VCC = Min., IOL = 8.0 mA Max. 2.4 0.4 Max. 2.4 0.4 Max. 2.4 0.4 Unit V 0.4 V V 2.2 6.0 2.2 6.0 2.2 6.0 2.2 6.0 VIL Input LOW Voltage −0.5 0.8 –0.5 0.8 –0.3 0.8 –0.3 0.8 V IIX Input Load Current GND < VI < VCC −1 +1 –1 +1 –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled −1 +1 –1 +1 –5 +5 –5 +5 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND −300 –300 –300 –300 mA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 220 220 220 200 mA ISB1 Automatic CE Max. VCC, Power-Down Current CE > VIH VIN > VIH or —TTL Inputs VIN < VIL, f = fMAX 40 40 40 40 mA ISB2 Automatic CE Max. VCC, Power-Down Current CE > VCC – 0.3V, —CMOS Inputs VIN > VCC – 0.3V, or VIN < 0.3V, f=0 5 5 5 5 mA 0.5 0.5 0.5 0.5 mA [1] L Shaded areas contain preliminary information. Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 8 pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05054 Rev. ** Page 2 of 9 CY7C1021 AC Test Loads and Waveforms R 481 Ω R 481 Ω 5V ALL INPUT PULSES 5V OUTPUT 3.0V 90% OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE 5 pF INCLUDING JIG AND SCOPE (a) R2 255Ω OUTPUT Equivalent to: THÉVENIN EQUIVALENT 90% 10% GND 10% < 3 ns (b) < 3 ns 1021-3 167 1021-4 1.73V 30 pF Switching Characteristics[5] Over the Operating Range 7C1021-10 Parameter Description Min. Max. 7C1021-12 Min. Max. 7C1021-15 Min. Max. 7C1021-20 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 10 tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[6] 3 OE HIGH to High Z tLZCE CE LOW to Low Z[6] 3 3 5 7 6 5 3 0 3 7 ns ns 9 ns ns 9 3 ns ns tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 10 12 15 20 ns tDBE Byte Enable to Data Valid 5 6 7 9 ns tLZBE Byte Enable to Low Z tHZBE Byte Disable to High Z 0 0 0 0 0 5 7 ns 20 0 3 6 ns 20 15 6 0 3 20 15 12 5 0 [6, 7] 15 12 10 [6, 7] tHZOE 12 10 0 6 9 0 ns 0 7 ns ns 9 ns [8] WRITE CYCLE tWC Write Cycle Time 10 12 15 20 ns tSCE CE LOW to Write End 8 9 10 12 ns tAW Address Set-Up to Write End 7 8 10 12 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 7 8 10 12 ns tSD Data Set-Up to Write End 5 6 8 10 ns tHD Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low Z[6] 3 3 3 3 ns [6, 7] tHZWE WE LOW to High Z tBW Byte Enable to End of Write 5 7 6 8 7 9 9 12 ns ns Shaded areas contain preliminary information. Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 38-05054 Rev. ** Page 3 of 9 CY7C1021 Switching Waveforms Read Cycle No. 1 [9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1021-5 Read Cycle No. 2 (OE Controlled) [10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB 1021-6 Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05054 Rev. ** Page 4 of 9 CY7C1021 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [12, 13] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O 1021-7 Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O 1021-8 Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05054 Rev. ** Page 5 of 9 CY7C1021 Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE 1021-10 Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power-Down Standby (ISB) L L H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L X L I/O1–I/O8 I/O9–I/O16 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05054 Rev. ** Page 6 of 9 CY7C1021 Ordering Information Speed (ns) 10 12 15 20 Ordering Code Package Name Package Type Operating Range CY7C1021-10VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1021-10ZC Z44 44-Lead TSOP Type II Commercial CY7C1021L-10ZC Z44 44-Lead TSOP Type II Commercial CY7C1021-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1021-12VI V34 44-Lead (400-Mil) Molded SOJ Industrial CY7C1021-12ZC Z44 44-Lead TSOP Type II Commercial CY7C1021-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1021-15VI V34 44-Lead (400-Mil) Molded SOJ Industrial CY7C1021-15ZC Z44 44-Lead TSOP Type II Commercial CY7C1021-15ZI Z44 44-Lead TSOP Type II Industrial CY7C1021L-15ZC Z44 44-Lead TSOP Type II Commercial CY7C1021-20VC V34 44-Lead (400-Mil) Molded SOJ Commercial CY7C1021-20ZC Z44 44-Lead TSOP Type II Commercial Shaded areas contain preliminary information. Package Diagrams 44-Lead (400-Mil) Molded SOJ V34 51-85082-B Document #: 38-05054 Rev. ** Page 7 of 9 CY7C1021 Package Diagrams (continued) 44-Pin TSOP II Z44 51-85087-A Document #: 38-05054 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1021 Document Title: CY7C1021 64K x 16 Static RAM Document Number: 38-05054 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107156 09/10/01 SZV Change from Spec number: 38-00224 to 38-05054 Document #: 38-05054 Rev. ** Page 9 of 9