CY7C1069AV33 2 M × 8 Static RAM 2 M × 8 Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns The CY7C1069AV33 is a high performance complementary metal oxide semiconductor (CMOS) static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. ■ Low active power ❐ 990 mW (max) ■ Operating voltages of 3.3 ± 0.3 V ■ 2.0 V data retention ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE1 and CE2 features ■ Available in Pb-free 54-pin thin small outline package (TSOP) II package Reading from the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) as well as forcing the Output Enable (OE) LOW while forcing the WE HIGH. See “Truth Table” on page 8 for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1069AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram 2048K x 8 ARRAY POWER DOWN Cypress Semiconductor Corporation Document Number: 38-05255 Rev. *J • I/O3 I/O4 A17 A18 A19 A20 A16 A13 A14 A15 I/O6 I/O7 WE OE I/O2 I/O5 COLUMN DECODER CE1 CE2 SENSE AMPS I/O1 ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A A98 A10 A11 A12 I/O0 Data in Drivers 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 29, 2010 [+] Feedback CY7C1069AV33 Contents Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 4 AC Switching Characteristics ......................................... 5 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 8 Ordering Information ........................................................ 9 Ordering Code Definition ............................................. 9 Document Number: 38-05255 Rev. *J Package Diagram .............................................................. 9 Acronyms ........................................................................ 10 Document Conventions ................................................. 10 Units of Measure ....................................................... 10 Document History Page ................................................. 11 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support ....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12 Page 2 of 12 [+] Feedback CY7C1069AV33 Selection Guide Description –10 Unit Maximum access time 10 ns Maximum operating current 275 mA Maximum CMOS standby current 50 mA Pin Configuration Figure 1. 54-pin TSOP II [1, 2] Top View NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS DNU A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC VCC NC Notes 1. NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application. Document Number: 38-05255 Rev. *J Page 3 of 12 [+] Feedback CY7C1069AV33 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature ................................ –65 C to +150 C DC input voltage[3] ............................... –0.5 V to VCC + 0.5 V Current into outputs (LOW) ......................................... 20 mA Operating Range Ambient temperature with power applied ........................................... –55 C to +125 C Range Supply voltage on VCC to relative GND[3] .....–0.5 V to +4.6 V Commercial DC voltage applied to outputs in high Z state[3] ................................... –0.5 V to VCC + 0.5 V Industrial Ambient Temperature VCC 0 C to +70 C 3.3 V 0.3 V –40 C to +85 C DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA VOL Output LOW voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH voltage voltage[3] –10 Unit Min Max 2.4 – V – 0.4 V 2.0 VCC + 0.3 V VIL Input LOW –0.3 0.8 V IIX Input leakage current GND < VI < VCC –1 +1 A IOZ Output leakage current GND < VOUT < VCC, Output Disabled –1 +1 A ICC VCC Operating supply current VCC = Max, f = fMAX = 1/tRC – 275 mA ISB1 Automatic CE power down current —TTL Inputs CE2 < VIL, Max VCC, CE1 > VIH VIN > VIH or VIN < VIL, f = fMAX – 70 mA ISB2 Automatic CE power down current —CMOS inputs CE2 < 0.3 V, Max VCC, CE1> VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – 50 mA Capacitance Tested initially and after any design or process changes that may affect these parameters.[4] Parameter CIN COUT Description Input capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V I/O capacitance TSOP II Unit 6 pF 8 pF Notes 3. VIL (min.) = –2.0 V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05255 Rev. *J Page 4 of 12 [+] Feedback CY7C1069AV33 Figure 2. AC Test Loads and Waveforms[5] 50 OUTPUT Z0 = 50 (a) R1 317 VTH = 1.5 V 3.3 V 30 pF* *Capacitive Load consists of all components of the test environment OUTPUT 5 pF* *Including jig and scope (b) All input pulses 3.3V 90% 10% GND R2 351 90% 10% Fall time: > 1 V/ns Rise time > 1 V/ns (c) AC Switching Characteristics Over the Operating Range [6] Parameter –10 Description Unit Min Max – ms Read Cycle tpower VCC(typical) to the first access[7] 1 tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE – 10 ns tDOE CE1 LOW/CE2 HIGH to data valid OE LOW to data valid tLZOE OE LOW to low Z tHZOE tLZCE tHZCE tPU tPD Write Cycle[9, 10] – 5 ns [8] 1 – ns 8 Z[ ] OE HIGH to high [8] CE1 LOW/CE2 HIGH to low Z – 5 ns 3 – ns CE1 HIGH/CE2 LOW to high CE1 LOW/CE2 HIGH to power up[9] – 5 ns 0 – ns – 10 ns 8] Z[ CE1 HIGH/CE2 LOW to power down[9] tWC Write cycle time 10 – ns tSCE CE1 LOW/CE2 HIGH to write end 7 – ns tAW Address setup to write end 7 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns Notes 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 8. tHZOE, tHZCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE1 LOW/CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document Number: 38-05255 Rev. *J Page 5 of 12 [+] Feedback CY7C1069AV33 AC Switching Characteristics Over the Operating Range (continued)[6] Parameter Description tPWE WE pulse width tSD Data setup to write end tHD Data hold from write end tLZWE WE HIGH to low Z tHZWE –10 Min Max Unit 7 – ns 5.5 – ns 0 – ns [8] 3 – ns [8] – 5 ns WE LOW to high Z Figure 3. Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR VDR > 2 V 3.0 V tR CE Document Number: 38-05255 Rev. *J Page 6 of 12 [+] Feedback CY7C1069AV33 Switching Waveforms Figure 4. Read Cycle No. 1[11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE1 CE2 tASCE OE tHZOE tDOE tHZSCE tLZOE DATA OUT HIGH IMPEDANCE tLZSCE VCC SUPPLY CURRENT HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Notes 11. Device is continuously selected. CE1 = VIL, CE2 = VIH. 12. WE is HIGH for Read cycle. 13. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document Number: 38-05255 Rev. *J Page 7 of 12 [+] Feedback CY7C1069AV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (CE1 Controlled)[14, 15, 16] tWC ADDRESS tSA CE tSCE tAW tHA tPWE WE t BW tSD tHD DATAI/O Figure 7. Write Cycle No. 2 (WE Controlled, OE LOW)[14, 15, 16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE1 CE2 OE WE I/O0–I/O7 Mode Power H X X X High Z Power down Standby (ISB) X L X X High Z Power down Standby (ISB) L H L H Data Out Read all bits Active (ICC) L H X L Data In Write all bits Active (ICC) L H H H High Z Selected, outputs disabled Active (ICC) Notes 14. Data I/O is high-impedance if OE = VIH. 15. If CE1 goes HIGH/CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state. 16. CE above is defined as a combination of CE1 and CE2. It is active low. Document Number: 38-05255 Rev. *J Page 8 of 12 [+] Feedback CY7C1069AV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1069AV33-10ZXC Package Diagram 51-85160 Package Type 54-pin TSOP II (Pb-free) Operating Range Commercial Ordering Code Definition CY 7 C 106 9 A V33 Voltage: 3.3 V Technology: 150 nm Bus Width: x8 Density: 16 Mbit Technology: CMOS Marketing Code: 7= SRAM Company ID : CY = Cypress Package Diagram Figure 8. 54-pin TSOP II, 51-85160 51-85160 *A Document Number: 38-05255 Rev. *J Page 9 of 12 [+] Feedback CY7C1069AV33 Acronyms Document Conventions Acronym Description Units of Measure BE Byte Enable CMOS complementary metal oxide semiconductor ns nano seconds I/O Input/output V Volts OE Output Enable µA micro Amperes SRAM static random access memory mA milli Amperes TSOP thin small outline package mV milli Volts TTL transistor-transistor logic mW milli Watts WE Write Enable ms milli seconds Document Number: 38-05255 Rev. *J Symbol Unit of Measure pF pico Farad °C degree Celcius W Watts % percent Page 10 of 12 [+] Feedback CY7C1069AV33 Document History Page Document Title: CY7C1069AV33 2 M × 8 Static RAM Document Number: 38-05255 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 113724 03/27/02 NSL New Data Sheet *A 117060 07/31/02 DFP Removed 15-ns bin *B 117990 08/30/02 DFP Added 8-ns bin Changing ICC for 8, 10, 12 bins tpower changed from 1 s to 1 ms Load Cap Comment changed (for Tx line load) tSD changed to 5.5 ns for the 10-ns bin Changed some 8-ns bin #'s (tHZ, tDOE, tDBE) Removed hz < lz comments *C 120385 11/13/02 DFP Final Data Sheet Added note 4 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin TSOP to 6/8 pf *D 124441 2/25/03 MEG Changed ISB1 from 100 mA to 70 mA Shaded the 48fBGA product offering information *E 403984 See ECN NXR Changed the Logic Block Diagram On page # 1 Added notes under Pin Configuration Changed the Package diagram of 51-85162 from Rev *A to Rev *D Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration Updated the Ordering Information *F 492137 See ECN NXR Removed 8 ns speed bin from product offering Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information *G 2784946 10/12/2009 *H 2897049 03/25/10 AJU Removed inactive parts from the ordering information table. Updated package diagrams. *I 2950666 06/11/2010 VKN Removed 12ns speed bin, Removed 60 Ball FBGA package Updated Ordering Information Added Acronyms and Ordering Code Definition. *J 3096933 11/29/2010 PRAS Document Number: 38-05255 Rev. *J VKN/PYRS Updated template Corrected typo in footnote 9 Updated Ordering Information table Added Units of Measure. Minor edits and updated in new template. Page 11 of 12 [+] Feedback CY7C1069AV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory Optical & Image Sensing cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05255 Rev. *J Revised November 29, 2010 Page 12 of 12 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback