Revised May 2005 74LCX162244 Low Voltage 16-Bit Buffer/Line Driver with 26: Series Resistors in Outputs General Description Features The LCX162244 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The LCX162244 is designed for low voltage (2.5V or 3.3V) VCC applications with capability of interfacing to a 5V signal environment. In addition, the outputs include equivalent 26: (nominal) series resistors to reduce overshoot and undershoot and are designed to sink/source up to 12 mA at VCC 3.0V. ■ 5V tolerant inputs and outputs The LCX162244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. ■ 2.3V–3.6V VCC specifications provided ■ Outputs include equivalent series resistance of 26: to make external termination resistors unnecessary and reduce overshoot and undershoot ■ 5.3 ns tPD max (VCC 3.0V), 20 PA ICC max ■ Power down high impedance inputs and outputs ■ r12 mA output drive (VCC 3.0V) ■ Implements patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model ! 2000V Machine model ! 200V ■ Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA) (Preliminary) Ordering Code: Order Number 74LCX162244GX (Note 1) Package Number BGA54A (Preliminary) Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74LCX162244MEA (Note 2) MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74LCX162244MTD (Note 2) MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Note 1: BGA package available in Tape and Reel only. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 2005 Fairchild Semiconductor Corporation DS500471 www.fairchildsemi.com 74LCX162244 Low Voltage 16-Bit Buffer/Line Driver with 26: Series Resistors in Outputs September 2000 74LCX162244 Connection Diagrams Pin Descriptions Pin Assignment for SSOP and TSSOP Pin Names Description OEn Output Enable Input (Active LOW) I0–I15 Inputs O0–O15 Outputs NC No Connect FBGA Pin Assignments 1 2 3 4 5 6 A O0 NC OE1 OE2 NC I0 B O2 O1 NC NC I1 I2 C O4 O3 VCC VCC I3 I4 D O6 O5 GND GND I5 I6 E O8 O7 GND GND I7 I8 F O10 O9 GND GND I9 I10 I12 G O12 O11 VCC VCC I11 H O14 O13 NC NC I13 I14 J O15 NC OE4 OE3 NC I15 Truth Tables Inputs I0–I3 OE1 Pin Assignment for FBGA Outputs L L L L H H H X Z Inputs Outputs OE2 I4–I7 L L L L H H H X Inputs (Top Thru View) Z Outputs I8–I11 L L L L H H H X Z I12–I15 O12–O15 Inputs O8–O11 Outputs L L L L H H H X Z H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance 2 O4–O7 OE3 OE4 www.fairchildsemi.com O0–O3 can be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by an Output Enable (OEn) input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. The LCX162244 contains sixteen non-inverting buffers with 3-STATE standard outputs. The device is designed with 26: series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceiver/transmitters. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins Logic Diagram 3 www.fairchildsemi.com 74LCX162244 Functional Description 74LCX162244 Absolute Maximum Ratings(Note 3) Symbol Parameter VCC Supply Voltage VI DC Input Voltage VO DC Output Voltage IIK DC Input Diode Current IOK DC Output Diode Current Value IO DC Output Source/Sink Current ICC DC Supply Current per Supply Pin IGND DC Ground Current per Ground Pin TSTG Storage Temperature Conditions 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 0.5 to VCC 0.5 50 50 50 r50 r100 r100 65 to 150 Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI GND V mA VO GND mA VO ! VCC mA mA mA qC Recommended Operating Conditions (Note 5) Symbol VCC Parameter VI Input Voltage VO Output Voltage IOH/IOL Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 Supply Voltage Output Current TA Free-Air Operating Temperature 't/'V Input Edge Rate, VIN 0.8V–2.0V, VCC 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC 3.0V 3.6V VCC 2.7V 3.0V VCC 2.3V 2.7V r12 r8 r4 Units V V V mA 40 85 qC 0 10 ns/V 3.0V Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: IO Absolute Maximum Rating must be observed. Note 5: Unused control inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage TA 40qC to 85qC (V) Min 2.3 2.7 1.7 2.7 3.6 2.0 Max 0.7 2.7 3.6 0.8 100 PA 2.3 3.6 VCC 0.2 IOH 4 mA 2.3 1.8 IOH 4 mA 2.7 2.2 IOH 6 mA 3.0 2.4 IOH 8 mA 2.7 2.0 IOH 12 mA 3.0 2.0 Units V 2.3 2.7 IOH V V IOL 100 PA 2.3 3.6 0.2 IOL 4 mA 2.3 0.6 IOL 4 mA 2.7 0.4 IOL 6 mA 3.0 0.55 IOL 8 mA 2.7 0.6 IOL 12 mA 3.0 0.8 2.3 3.6 r5.0 PA 2.3 3.6 r5.0 PA II Input Leakage Current 0 d VI d 5.5 IOZ 3-STATE Output Leakage 0 d VO d 5.5V VI www.fairchildsemi.com VCC V IH or VIL 4 V Symbol (Continued) Parameter VCC Conditions TA (V) 40qC to 85qC Min Units Max IOFF Power-Off Leakage Current VIN or VO 0 10 PA ICC Quiescent Supply Current VI VCC or GND 2.3 3.6 20 PA 'ICC Increase in ICC per Input VIH V CC 0.6V 2.3 3.6 500 PA 5.5V Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. AC Electrical Characteristics TA Symbol Parameter VCC CL 40qC to 85qC, RL 3.3V r 0.3V VCC 50 pF CL 500 : 2.7V 50 pF VCC CL 2.5V r 0.2V 30 pF Min Max Min Max Min tPHL Propagation Delay 1.0 5.3 1.0 6.0 1.0 6.4 tPLH Data to Output 1.0 5.3 1.0 6.0 1.0 6.4 tPZL Output Enable Time 1.0 6.3 1.0 7.1 1.0 8.2 1.0 6.3 1.0 7.1 1.0 8.2 1.0 5.4 1.0 5.7 1.0 6.5 1.0 5.4 1.0 5.7 1.0 6.5 tPZH tPLZ Output Disable Time tPHZ tOSHL Output to Output Skew (Note 8) Max 1.0 tOSLH Units ns ns ns ns 1.0 Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Dynamic Switching Characteristics Symbol VOLP VOLV Parameter Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL VCC Conditions TA 25qC (V) Typical CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.35 CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.25 CL 50 pF, VIH 3.3V, VIL 0V 3.3 0.35 CL 30 pF, VIH 2.5V, VIL 0V 2.5 0.25 Units V V Capacitance Symbol Parameter Conditions CIN Input Capacitance VCC Open, VI COUT Output Capacitance VCC 3.3V, VI 0V or VCC CPD Power Dissipation Capacitance VCC 3.3V, VI 0V or VCC, f 5 0V or VCC 10 MHz Typical Units 7 pF 8 pF 20 pF www.fairchildsemi.com 74LCX162244 DC Electrical Characteristics 74LCX162244 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) CL VI 6V for VCC 3.3V, 2.7V VCC * 2 for VCC 50 pF 2.5V 30 pF Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol www.fairchildsemi.com VCC 3.3V r 0.3V 2.7V 2.5V r 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL 0.3V VOL 0.3V VOL 0.15V Vy VOH 0.3V VOH 0.3V VOH 0.15V 6 74LCX162244 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com 74LCX162244 Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A Preliminary www.fairchildsemi.com 8 74LCX162244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 9 www.fairchildsemi.com 74LCX162244 Low Voltage 16-Bit Buffer/Line Driver with 26: Series Resistors in Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10