C8051F044 25 MIPS, 64 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU Analog Peripherals High-Speed 8051 µC Core - 10-Bit ADC - ±1 LSB INL; guaranteed monotonic Programmable throughput up to 100 ksps 13 external inputs; programmable as single-ended or differential Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5 Data-dependent windowed interrupt generator Built-in temperature sensor (±3 °C) - Memory - High-Voltage Differential Amplifier - - 60 V common mode input range Offset adjust from –60 to +60 V 16 gain settings from 0.05 to 16 - - - On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required) Provides breakpoints, single stepping, watchpoints, stack monitor, program trace memory Inspect/modify memory and registers Superior performance to emulation systems using ICE-chips, target pods, and sockets IEEE1149.1 compliant boundary scan Supply Voltage: 2.7 to 3.6 V - MONEN XTAL1 XTAL2 Clock Sources - Internal programmable 2% oscillator: up to 25 MHz External oscillator: Crystal, RC, C, or Clock 100-pin TQFP (standard lead and lead-free packages) Ordering Part Numbers Temperature Range: –40 to +85 °C TCK TMS TDI TDO RST - 64 port I/O; all are 5 V tolerant Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial ports available concurrently Programmable 16-bit counter array with 6 capture/compare modules 5 general-purpose 16-bit counter/timers Dedicated watchdog timer; bidirectional reset Real-time clock mode using timer 3 or PCA Package Typical operating current: 10 mA at 25 MHz Multiple power saving sleep and shutdown modes VDD VDD VDD DGND DGND DGND AV+ AV+ AV+ AGND AGND AGND 32 message objects ”Mailbox" implementation only interrupts CPU when needed Digital Peripherals On-Chip JTAG Debug & Boundary Scan - 4352 bytes data RAM 64 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved) External parallel data memory interface CAN Bus 2.0B Three Comparators Internal Voltage Reference Precision VDD Monitor/Brown-out Detector - Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks Up to 25 MIPS throughput with 25 MHz system clock Expanded interrupt handler - Lead-free package: C8051F044-GQ Standard package: C8051F044 Digital Power 8 0 5 1 Analog Power Boundary Scan JTAG Logic Debug HW Reset VDD Monitor WDT External Oscillator Circuit System Clock VREF VREF Internal 2% Oscillator C o r e UART0 UART1 SFR Bus C R O S S B A R SMBus SPI Bus PCA Timers 0,1,2,3,4 64 kB FLASH 32x136 CANRAM Port 0,1,2,3 &4 Latches Prog Gain A M U X HVAIN+ HVAMP P2 Drv P2.0/CPx P3 Drv P3.0/AINAMUX0 P1.7 P2.7/CPx P3.7/AINAMUX7 CANRX 4 kB XRAM + - CP0 + + - P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P4.0 Port 4 <from crossbar> External Data Memory Bus Bus Control Address [15:0] TEMP SENSOR P1.0 CANTX CP1 ADC 100 ksps (10-Bit) P1 Drv P0.7 256 byte RAM VREF0 A M U X P0.0 CAN 2.0B CP2 AIN0.0 AIN0.1 AIN0.2 AIN0.3 P0 Drv Addr [7:0] Addr [15:8] P7 Latch Data [7:0] HVAIN- P4.4 P4.5/ALE P4.6/RD P4.7/WR P5 DRV P5.0/A0 P6 DRV P6.0/A8 P7 DRV P7.0/D0 Ctrl Latch P5 Latch P6 Latch 8:2 P4 DRV Data Latch P5.7/A7 P6.7/A15 P7.7/D7 HVREF HVCAP CAN 2.0B Copyright © 2005 by Silicon Laboratories 5.5.2005 C8051F044 25 MIPS, 64 kB Flash, 10-Bit ADC, 100-Pin Mixed-Signal MCU Selected Electrical Specifications (TA = –40 to +85 C°, VDD = 2.7 V unless otherwise specified) Parameter Conditions Min Typ Max Units 2.7 — 3.6 V — 10 0.5 20 — mA mA µA Global Characteristics Supply Voltage Supply Current with CPU active Clock = 25 MHz Clock = 1 MHz Clock = 32 kHz; VDD Monitor Enabled Supply Current (shutdown) Oscillator off; VDD Monitor Disabled Clock Frequency Range — 0.1 — µA DC — 25 MHz — 10 — bits — — ±1 LSB ±1 LSB — dB A/D Converter Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Signal-to-Noise Plus Distortion 59 — Throughput Rate — — 100 ksps Input Voltage Range 0 — VREF V Comparators Supply Current (each Comparator) — 1.5 — µA Response Time (CP+ – CP-) = 100 mV — 4 — µs C8051F040DK Development Kit Package Information D MIN NOM MAX (mm) (mm) (mm) D1 A - A1 0.05 - 1.20 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 E1 E D - 16.00 - D1 - 14.00 - e - 0.50 - E - 16.00 - E1 - 14.00 - 100 PIN 1 DESIGNATOR 1 e A2 A b CAN 2.0B A1 Copyright © 2005 by Silicon Laboratories Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders 5.5.2005