TI CDCF5801A Clock multiplier with delay control and phase alignment Datasheet

CDCF5801A
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SCAS816 – MARCH 2006
CLOCK MULTIPLIER WITH DELAY CONTROL AND PHASE ALIGNMENT
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-Jitter Clock Multiplier: ×1, ×2, ×4, ×8
Fail-Safe Power Up Initialization
Programmable Bidirectional Delay Steps of
1.3 mUI
Output Frequency Range of 25 MHz to
280 MHz
Input Frequency Range of 12.5 MHz to
240 MHz
Low Jitter Generation
Single-Ended REFCLK Input With Adjustable
Trigger Level (Works With LVTTL, HSTL, and
LVPECL)
Differential/Single-Ended Output
Output Can Drive LVPECL, LVDS, and LVTTL
Three Power Operating Modes to Minimize
Power
Low Power Consumption (< 190 mW at
280 MHz/3.3 V)
Packaged in a Shrink Small-Outline Package
(DBQ)
No External Components Required for PLL
•
Spread Spectrum Clock Tracking Ability to
Reduce EMI (SSC)
APPLICATIONS
•
•
•
•
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Video Graphics
Gaming Products
Datacom
Telecom
Noise Cancellation Created by FPGAs
DBQ PACKAGE
(TOP VIEW)
VDDREF
REFCLK
VDDP
GNDP
GND
LEADLAG
DLYCTRL
GNDPA
VDDPA
VDDPD
STOPB
PWRDNB
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
P0
P1
VDDO
GNDO
CLKOUT
NC
CLKOUTB
GNDO
VDDO
MULT0
MULT1
P2
DESCRIPTION
The CDCF5801A provides clock multiplication from a reference clock (REFCLK) signal with the unique capability
to delay or advance the CLKOUT/CLKOUTB with steps of only 1.3 mUI through a phase aligner. For every rising
edge on the DLYCTRL pin the CLKOUT is delayed by a 1.3-mUI step size as long as the LEADLAG input
detects a low signal at the time of the DLYCTRL rising edge. Similarly for every rising edge on the DLYCTRL pin
the CLKOUT is advanced by a 1.3-mUI step size as long as the LEADLAG pin is high during the transition. This
unique capability allows the device to phase align (zero delay) between CLKOUT/CLKOUTB and any one other
CLK in the system by feeding the clocks that need to be aligned to the DLYCTRL and the LEADLAG pins. Also it
provides the capability to program a fixed delay by providing the proper number of edges on the DLYCTRL pin,
while strapping the LEADLAG pin to dc high or low. Further possible applications are:
• Aligning the rising edge of the output clock signal to the input clock rising edge
• Avoiding PLL instability in applications that require very long PLL feedback lines
• Isolation of jitter and digital switching noise
• Limitation of jitter in systems with good ppm frequency stability
The CDCF5801A has a fail-safe power up initialization state-machine which supports proper operation under all
power up conditions.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
CDCF5801A
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SCAS816 – MARCH 2006
The CDCF5801A provides clock multiplication and division from a reference clock (REFCLK) signal. The device
is optimized to have extremely low jitter impact from input to output. The predivider pins MULT[0:1] and
post-divider pins P[0:2] provide selection for frequency multiplication and division ratios, generating
CLKOUT/CLOUTKB frequencies ranging from 25 MHz to 280 MHz with clock input references (REFCLK) ranging
from 12.5 MHz to 240 MHz. See Table 1 for detailed frequency support. The selection of pins MULT[0:1] and
P[1:2] determines the multiplication value of 1, 2, 4, or 8. The CDCF5801A offers several power-down/
high-impedance modes, selectable by pins P0, STOPB and PWRDN. Another unique capability of the
CDCF5801A is the high sensitivity and wide common-mode range of the clock-input pin REFCLK by varying the
voltage on the VDDREF pin. The clock signal outputs CLKOUT and CLKOUTB can be used independently to
generate single-ended clock signals. The CLKOUT/CLKOUTB outputs can also be combined to generate a
differential output signal suitable for LVDS, LVPECL, or HSTL/SSTL signaling. The CDCF5801A is characterized
for operation over free-air temperatures of -40°C to 85°C.
2
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REFCLK
VDDREF/2
12.5-240 MHz
Control
PWRDNB
P0
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div4
div8
div16
00
11
10
MULT[0:1]
2
div2
PLL
01
VDDP
GNDP
DLY-
div8
div4
div2
GNDPA
LEADLAG
0-280 MHz
VDDPD/2
DLYCTRL
0-240 MHz
DLY+
>CLK
Delay
Phase Aligner
VDDPA
P[1:2]
2
01
10
11
VDDO
25-280 MHz
GNDO
STOPB
CLKOUTB
CLKOUT
CDCF5801A
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FUNCTIONAL BLOCK DIAGRAM
3
CDCF5801A
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SCAS816 – MARCH 2006
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CLKOUT
CLKOUTB
2018
O
Output CLK signal (low-noise CMOS) Complementary output CLK signal (low-noise CMOS)
DLYCTRL
7
I
Every rising edge on this pin delays/advances the CLKOUT/CLKOUTB signal by 1/768th of the
CLKOUT/CLKOUTB period (1.3 mUI). (E.g., for a 90-degree delay or advancement one needs to
provide 192 rising edges). See Table 3.
GND
5
GND for VDDREF and VDDPD
GNDO
17, 21
GND for the output pins (CLKOUT, CLKOUTB)
GNDP
4
GNDPA
8
LEADLAG
6
I
Controls whether the output CLK is delayed or advanced relative to REFCLK. See Table 3.
MULT0
MULT1
15
I
PLL multiplication factor select. See Table 1.
GND for the PLL
GND for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], STOPB, PWRDNB
14
MULT[0:1] = 10: ×16
MULT[0:1] = 11: ×8
MULT[0:1] = 00: ×4
MULT[0:1] = 01: ×2
NC
19
P0
24
Not connected; leave pin floating or tied to GND.
I
Mode control pins (see Table 1)
0 - Normal operation
1 - High-Z outputs and other special settings
P1
23
I
Post divider control (see Table 1)
P[1:2] = 11: div2
P[1:2] = 10: div4
P2
13
PWRDNB
12
P[1:2] = 01: div8
I
Active-low power-down state. CLKOUT/CLKOUTB goes low, See Table 2).
0 - IC in power down
1 - Normal operation
REFCLK
2
I
Reference input clock
STOPB
11
I
Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as
listed in Table 2.
0 - Outputs disabled
1 - Normal operation
VDDO
16, 22
VDDP
3
VDD for PLL and input buffer
VDDPA
9
VDD for phase aligner, digital logic, and inputs P[0:2], MULT[0:1], and STOPB
VDDPD
10
Reference voltage for inputs LEADLAG and DLYCTRL
VDDREF
1
Reference voltage for REFCLK
4
VDD for the output pin (CLKOUT, CLKOUTB) and power down circuit
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Table 1. Input-to-Output Settings
INPUT-TO-OUTPUT
MULTIPLICATION-RATIO
8
4
2
1
INPUT
FREQUENCY (MHz)
OUTPUT
FREQUENCY (MHz)
PREDIVIDER
FROM
TO
FROM
TO
MULT0
MULT1
12.5
35
100
280
1
12.5
39
50
156
1
25
70
100
280
12.5
39
25
25
78
50
P1
P2
0
1
1
0
1
0
1
1
1
1
78
1
0
0
1
50
156
1
1
1
0
140
100
280
0
0
1
1
25
78
25
78
1
1
0
1
50
156
50
156
0
0
1
0
100
240
100
240
0
1
1
1
X
X
0
0
X
X
0
1
X
X
1
X
CLKOUT high-impedance
CLOUOTB high-impedance
CLKOUT = high
CLKOUTB = high
CLKOUT = P2
CLKOUTB = P2
(1)
POST DIVIDER
P0
0
1
NOTE
Normal operation (1)
Special mode of operation
There is some overlapping of the input frequency ranges for multiplication ratios of 1, 2, and 4. For example, an input frequency of 30
MHz for a multiplication ratio of four falls within both the 12.5 to 39-MHz range and the 25 to 70-MHz range. For best device operation in
a case such as this, always select the input frequency range nearer to the top of the table.
PLL DIVIDER/MULITPLIER SELECTION
Table 2. Power Down Modes
STATE
PWRDNB
STOPB
Power down
0
X
CLKOUT and CLKOUTB
GNDO
Clock stop
1
0
VO, STOP
Normal
1
1
See Table 1
Table 3. Programmable Delay and Phase Alignment
DLYCTR
Each rising
edge+
Each rising
edge+
NOTE
LEADLAG
For every 32 edges, there are one or two
edges for which the phase aligner does not
update the phase. Therefore, CLKOUT
phase is not updated for every 32nd edge.
The frequency of the DLYCTRL pin should
always be equal to or less than the
frequency of the LEADLAG pin.
CLKOUT and CLKOUTB
HI
Advanced by one step:
step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11
1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10
1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01
LO
Delayed by one step:
step size: 1/768 of the CLKOUT period (1.3 mUI) at P[1:2] = 11
1/1536 of the CLKOUT period (0.65 mUI) at P[1:2] = 10
1/3072 of the CLKOUT period (0.325 mUI) at P[1:2] = 01
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
VDDx (2)
Tstg
(1)
(2)
Supply voltage range
-0.5 V to 4 V
Voltage range at any output terminal
-0.5 V to VDD + 0.5 V
Voltage range at any input terminal
-0.5 V to VDD + 0.5 V
Storage temperature range
-65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under,, recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND terminals.
POWER DISSIPATION RATING TABLE
PACKA
GE
TA≤ 25°C POWER
RATING
DERATING
FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
830 mW
8.3 mW/°C
332 mW
DBQ
(1)
This is the inverse of the junction-to-ambient thermal resistance
when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
3
3.3
3.6
UNIT
VDDP, VDDPA, VDDO
Supply voltage
VIH
(CMOS)
High-level input voltage
VIL
(CMOS)
Low-level input voltage
0.3 VDD
V
VIL (DLYCTRL, LEADLAG)
Input signal low voltage
VDDPD 0.2
2
V
VIH (DLYCTRL, LEADLAG)
Input signal high voltage
(VDDPD)
Input reference voltage for DLYCNTRL and LEADLAG
IOH
High-level output current
-16
mA
IOL
Low-level output current
16
mA
(VDDREF) (see Application
section)
Input reference voltage for REFCLK
VIL (see Application section)
REFCLK input low voltage
VIH (see Application section)
REFCLK input high voltage
TA
Operating free-air temperature
0.7 VDD
V
V
VDDPD 0.2
2
V
1.2
VDD
1.2
V
VDD
V
VDDREF 0.2
2
V
VDDREF 0.2
2
V
-40
85
°C
TIMING REQUIREMENTS
PARAMETER
Fmod
MIN
Input frequency of modulation, (if driven by SSC CLKIN)
33
Modulation index, nonlinear maximum 0.5%
SR
UNIT
kHz
0.6%
Input slew rate
1
4
Input duty cycle on REFCLK
40%
60%
Input frequency on REFCLK
12.5
240
MHz
25
280
MHz
240
MHz
Output frequency on CLKOUT and CLKOUTB
Allowable frequency on DLYCTRL
6
MAX
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V/ns
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TIMING REQUIREMENTS (continued)
PARAMETER
MIN
MAX
UNIT
280
MHz
25%
75%
Allowable frequency on LEADLAG
Allowable duty cycle on DLYCTRL and LEADLAG pins
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
TEST CONDITIONS (1)
PARAMETER
MIN TYP (2)
VO(STOP)
Output voltage during Clkstop mode
See Figure 1
VO(X)
Output crossing-point voltage
See Figure 1 and Figure 4
VO
Output voltage swing (VOH - VOL)
See Figure 1
VIK
Input clamp voltage
VDD = 3 V,
II = -18 mA
VDD = 3 to 3.6 V,
See Figure 1
2
VDD = 3 V,
IOH = -16 mA
2.2
VDD = 3 to 3.6 V,
See Figure 1
VDD = 3 V,
IOH = 16 mA
VDD = 3.135 V,
VO = 1 V
VDD = 3.3 V,
VO = 1.65 V
VDD = 3.465 V,
VO = 3.135 V
VDD = 3.135 V,
VO = 1.95 V
VDD = 3.3 V,
VO = 1.65 V
VOH
High-level output voltage
VOL
Low-level output voltage
IOH
High-level output current
IOL
Low-level output current
VDD = 3.465 V,
VO = 0.4 V
IOZ
High-impedance-state output current
P0 = 1,
P1 = P2 = 0
IOZ(STOP)
High-impedance-state output current
during Clk Stop
Stop = 0,
VO = GND or VDD
IOZ(PD)
High-impedance-state output current
in power-down state
PWRDNB = 0,
VO = GND or VDD
IIH
High-level
input current
IIL
REFCLK; STOPB;
VDD = 3.6 V,
PWRDNB; P[0:2];
MULT[0:1];
VDD = 3.6 V,
DLYCTRL; LEADLAG
MAX
UNIT
1.1
2
V
VDDO 0.2
2
VDDO 0.2
2
V
1.7
2.9
V
-1.2
V
2.5
0.4
V
0.6
0.5
-32
-52
-51
-14.5
43
V
mA
-21
61.5
65
25.5
-10
VI = VDD
VI =0
mA
40
±10
µA
±100
µA
100
µA
10
µA
-10
µA
ZO
Output
impedance
(single
ended)
High state
RI at IO-14.5 mA to -16.5 mA
15
35
50
Low state
RI at IO 14.5 mA to 16.5 mA
10
17
35
IREF
Reference
current
VDDREF; VDDPD
VDD = 3.6 V
CI
Input capacitance
VI = VDD or GND
2
pF
CO
Output capacitance
VO = GND or VDD
3
pF
IDD(PD)
Supply current in power-down state
REFCLK = 0 MHz to 280 MHz;
PWRDNB = 0; STOPB = 1
IDD(CLKSTOP) Supply current in CLK stop state
IDD(NORMAL)
(1)
(2)
Supply current (normal operation
mode)
PWRDNB = 0
PWRDNB = 1
Ω
50
µA
0.5
mA
4
mA
BUSCLK configured for 280 MHz
44
mA
BUSCLK 280 MHz, MULT[0:1] = 10;
P[0:2] = 011; Load , See Figure 1
75
mA
VDD refers to any of the following; VDDP, VDDREF, VDDO, VDDPD, and VDDPA
All typical values are at VDD = 3.3 V, TA = 25°C.
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JITTER SPECIFICATION
over recommended free-air temperature range and VCC range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
TYP (ps)
MAX (ps)
20
48
Period p-p
120
225
Cycle to cycle +
70
165
Cycle to cycle -
70
165
RMS phase jitter (accumulated,
100 kHz-12.5 MHz)
80
160
7
15
Period p-p
37
75
Cycle to cycle +
27
55
Cycle to cycle -
27
55
27
65
5
14
30
65
24
55
24
55
35
65
4
8
20
40
Cycle to cycle +
17
40
Cycle to cycle -
17
40
RMS phase jitter (accumulated,
100 kHz-40 MHz)
15
35
8
15
38
60
Cycle to cycle +
5
55
Cycle to cycle -
35
55
RMS phase jitter (accumulated,
100 kHz-40 MHz)
30
60
Period rms (1-sigma jitter, full
frequency band)
Period rms (1-sigma jitter, full
frequency band)
REFCLK
(MHz)
CLKOUT
(MHz)
25
25
50
50
MULT[0:1] P[0:2]
11
11
001
001
RMS phase jitter (accumulated,
100 kHz-25 MHz)
Period rms (1-sigma jitter, full
frequency band)
100
100
00
010
Period p-p
t(jitter)
Cycle to cycle +
Cycle to cycle RMS phase jitter (accumulated,
100 kHz-40 MHz)
Period rms (1-sigma jitter, full
frequency band)
156
156
00
010
Period p-p
Period rms (1-sigma jitter, full
frequency band)
200
200
01
Period p-p
8
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NOTES
011
Phase
aligner
running
(CLKOUT
tight to
LEADLAG;
REFCLK
tight to
DLYCTRL).
All typical
values are
at
VDD = 3.3
V,
TA = 25°C.
CDCF5801A
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JITTER SPECIFICATION (continued)
over recommended free-air temperature range and VCC range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
TYP (ps)
MAX (ps)
4
11
Period p-p
20
48
Cycle to cycle +
16
45
Cycle to cycle -
16
45
4
11
Period p-p
22
55
Cycle to cycle +
15
45
Cycle to cycle -
15
45
4
11
18
48
15
45
15
45
6
16
34
75
20
65
20
65
3
11
Period p-p
15
44
Cycle to cycle +
13
40
Cycle to cycle -
13
40
6
20
Period p-p
35
80
Cycle to cycle +
25
75
Cycle to cycle -
25
75
REFCLK
(MHz)
CLKOUT
(MHz)
25
200
Period rms (1-sigma jitter, full
frequency band)
Period rms (1-sigma jitter, full
frequency band)
25
Period rms (1-sigma jitter, full
frequency band)
MULT[0:1] P[0:2]
10
100
70
011
10
280
010
11
011
Period p-p
Cycle to cycle +
t(jitter)
Cycle to cycle Period rms (1-sigma jitter, full
frequency band)
25
50
10
001
Period p-p
Cycle to cycle +
Cycle to cycle Period rms (1-sigma jitter, full
frequency band)
Period rms (1-sigma jitter, full
frequency band)
78
156
62.5
11
125
NOTES
Phase
aligner
not running
(LEADLAG
= 0,
DLYCTRL =
0). All
typical
values are
at
VDD = 3.3
V, TA =
25°C.
010
00
011
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
t(DC)
Output duty cycle over 1000 cycles
See Figure 3
42%
tr, tf
Output rise and fall times (measured at 20%-80% of output voltage
See Figure 5
150
250
350
MIN
TYP
MAX
UNIT
58%
ps
STATE TRANSITION LATENCY SPECIFICATIONS
PARAMETER
t(powerup)
FROM
Delay time, PWRDNB↑ to CLKOUT /
CLKOUTB settled
Delay time, PWRDNB↑ to internal PLL
and clock are on and settled
TO
TEST
CONDITION
UNIT
3
Power down
Normal
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See Figure 6
ms
3
9
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STATE TRANSITION LATENCY SPECIFICATIONS (continued)
PARAMETER
t(VDDpowerup)
FROM
Delay time, power up to CLKOUT
output settled
TO
TEST
CONDITION
MIN
TYP
MAX
UNIT
3
Delay time, power up to internal PLL
and clock are on and settled
VDD
Normal
See Figure 6
ms
3
t(MULT)
MULT0 and MULT1 change to
CLKOUT output resettled
Normal
Normal
See Figure 7
1
ms
t(CLKON)
STOPB↑ to CLKOUT glitch-free clock
edges
CLK stop
Normal
See Figure 8
10
ns
t(CLKSETL)
STOPB↑ to CLKOUT output settled to
within 50 ps of the phase before
STOPB was disabled
CLK stop
Normal
See Figure 8
20
cycles
t(CLKOFF)
STOPB↓ to CLKOUT output disabled
Normal
CLK stop
See Figure 8
5
ns
t(powerdown)
Delay time, PWRDNB↓ to the device in
Normal
the power-down mode
Power down
See Figure 6
1
ms
t(STOP)
Maximum time in CLKSTOP (STOPB =
0) before reentering normal mode
STOPB
(STOPB = 1)
Normal
See Figure 8
100
µs
t(ON)
Minimum time in normal mode (STOPB
= 1) before reentering CLKSTOP
Normal
(STOPB = 0)
CLK stop
See Figure 8
100
ms
PARAMETER MEASUREMENT INFORMATION
TESTING CONDITIONS
CLKOUT
50 Ω
VCM
50 Ω
10 pF
CLKOUTB
Figure 1. Test Load and Voltage Definitions VOH, VOL, VO(STOP)
CLKOUT
CLKOUTB
tCYCLE(i)
tCYCLE(i+1)
Cycle-to-Cycle Jitter (t(jitter)) = | tCYCLE(i) - tCYCLE(i+1) | over 1000 consecutive cycles
Figure 2. Cycle-to-Cycle Jitter
10
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PARAMETER MEASUREMENT INFORMATION (continued)
CLKOUT
CLKOUTB
tPW+
tCYCLE
Duty Cycle = (tPW+/tCYCLE)
Figure 3. Output Duty Cycle
CLKOUT
VO(X)+
VO(X), nom
VO(X)CLKOUTB
Figure 4. Crossing Point Voltage
VOH
80%
20%
VOL
tr
tf
Figure 5. Voltage Waveforms
PWRDNB
CLKOUT
CLKOUTB
t(powerdown)
t(powerup)
Figure 6. PWRDNB Transition Timings
MULT0
and/or
MULT1
CLKOUT
CLKOUTB
t(MULT)
Figure 7. MULT Transition Timings
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PARAMETER MEASUREMENT INFORMATION (continued)
t(ON)
t(STOP)
STOPB
t(CLKSETL)
t(CLKON)
(see Note A)
CLKOUT
CLKOUTB
Output clock
not specified
glitches ok
A.
Clock enabled
and glitch free
Clock output settled
within 50 ps of the
phase before disabled
Vref = VO±200 mV
Figure 8. STOPB Transition Timings
12
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t(CLKOFF)
(see Note A)
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APPLICATION INFORMATION
APPLICATION EXAMPLE
The following figure shows an example of using the CDCF5801A as a phase aligner de-skewing the unknown
buffer delay of the two CDCV304s in the circuit. This circuitry would not be possible with a simple PLL because
the feedback of the PLL would have the second CDCV304 in the loop, causing instability of the PLL due to a
long delay.
Z = 50 Ω; Length = L1
30 Ω
25 MHz
CDCV304
Clock Buffer
25 MHz
Z = 50 Ω
Z = 50 Ω
CLK
Outputs are Phase Aligned
Between the Two Buffers
CDCF5801A
3.3 V
VDDREF
P0
P1
REFCLK
3.3 V
VDDP
VDDO
GNDP
GNDO
GND
CLKOUT
LEADLAG
NC
DLYCTRL
CLKOUTB
GNDPA
3.3 V
CDCV304
Clock Buffer
3.3 V
25 MHz
25 MHz
Z = 50 Ω
35 Ω
CLK
GNDO
VDDPA
VDDO
VDDPD
MULT0
STOPB
MULT1
PWRDNB
3.3 V
P2
Z = 50 Ω; Length = L1
Figure 9. Application Example
NOTE:
If an active element (microcontroller, ASIC, DSP< FPYA, DSP, etc.) is used in the
CDCF5801A CLKOUT to DLYCTRL feedback loop, see application report SCAA075.
SELECTING VDDREF
Generally, VDDREF can be set to any value between 1.2 V and VDD. The setting of VDDREF directly influences
the trigger voltage of the input. Special care must be taken when using small signal swings to drive the
CVDCF5801 input (e.g., PECL). It is recommended to connect VDDREF directly to VDD, ac-couple the REFCLK
input, and rebias the signal.
The following circuit is recommended to drive the CDCF5801A from a differential clock signal like PECL.
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13
CDCF5801A
www.ti.com
SCAS816 – MARCH 2006
APPLICATION INFORMATION (continued)
3.3 V ± 10%
150 Ω
R1
100 Ω
CDCF5801A
VDDREF
Z = 50 Ω
REFCLK
PECL
R2
100 Ω
GND
150 Ω
A.
GNDP
NOTE: If more signal swing is required and an unterminated transmission is on option, then R1 and R2 can both be
replaced with 10-kΩ resistors.
Figure 10. Driving the CDCF5801A From a Differential Clock Signal
14
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CDCF5801A
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SCAS816 – MARCH 2006
Revision History
DATE
REV
PAGE
SECTION
15 MAR
05
*
–
–
DESCRIPTION
Original version
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15
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCF5801ADBQ
ACTIVE
SSOP/
QSOP
DBQ
24
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCF5801ADBQG4
ACTIVE
SSOP/
QSOP
DBQ
24
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCF5801ADBQR
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
CDCF5801ADBQRG4
ACTIVE
SSOP/
QSOP
DBQ
24
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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