Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
P R E L I M I N A R Y
Distinctive Characteristics
8 10Mbps Ethernet Access Ports
9
I N F O R M A T I O N
EA218E – 8-Port Ethernet Access Controller
XpressFlow 2020 Ethernet Routing Switch Chipset
Direct interface with 10BaseT
transceiver
0.5 micron 3.3 Volt CMOS process
XPRESSFLOW BUS
352-BGA package
MANAGEMENT BUS
Operating frequency
-33
33 MHz maximum
9
-40
40 MHz maximum
9
-50
50 MHz maximum
9
-66
mum
66.66 MHz maxi-
16
LOCAL
BUFFER
MEMORY
EA-218E
8-Port Ethernet
Access Controller
Port Port Port Port Port Port Port Port
0
1
2
3
4
5
6
7
32-bit Local Buffer Memory Interface
9
Supports 128k to 1M bytes
9
Utilize high performance 32-bit
Synchronous Burst SRAM
32
32
9
10BaseT
Phyiscal Layer
Transceiver
Hardware assisted Buffer and Queue
Management
16-bit Management Bus I/O Interface
9
Allows host to access Control
Registers & Local Buffer Memory
9
Big and Little Endian CPUs
9
Direct interface to standard microprocessors, including 386, 486
families and Motorola MPC series
embedded processors
32-bit XpressFlow Bus Interface
9
Uses Granule for frame transferring between Access Controllers
Unicast, multicast, and broadcast
frames
9
Also detects IEEE 802.3X MAC
Control frames
Works together with SC-220 XpressFlow Engine
8 10BaseT Ports
Block DiagramEA218E 8-Port Ethernet Access Controller
General Description
The EA-218E provides eight 10Mbps Ethernet network access interface ports.
The EA-218E provides the Ethernet MAC protocols, handles the local buffer memory
interface and management, arbitrates among multiple priority queues, and interfaces
with the XpressFlow Engine and other Access Controllers through the XpressFlow
message passing protocol.
Related Components:
9
Forwards frames at full line-rate
SC220 – XpressFlow Engine
9
Distributed Flow Caching™ to reduce frame forwarding latency
EA218 – 6-port 10 + 2-port 10/100 Ethernet Access Controller
Half and Full Duplex operation
EA234 – 4-port 10/100Mbps Ethernet Access Controller
Programmable Flow Control
9
Jam Collision for Half Duplex
Mode
9
Transmit Flow Control Frame for
IEEE 802.3x Full Duplex Mode
Supports Store-&-Forward frame forward© 1998 Zarlink Semiconductor, Inc.
1
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
ing mode
XPRESSFLOW BUS
Characteristics Continue
MANAGEMENT BUS
32
Automatically selects the optimized mode for forwarding
Local
Buffer
Memory
Multi-Media ready with QoS supports
9
XpressFlow
Bus Interafce
Local
Buffer
Memory
Interface
Automatic
Buffer
Manager
MAC Interface
Four frame transmission priority
queues
32
Complies with IEEE 802.1 Bridge
Standard
9
Management
Bus Interafce
32
9 Allows manual frame forwarding
mode selection override
EA-218E
32
9
16
MAC Port #0 to #7
Assigns one unique MAC Address
for each port
Port 0
1
2
3
4
5
6
7
5
6
7
VLAN ID Tagging & Stripping
9
Auto padding if necessary after
stripping
8-Port
10BaseT PHY
Automatic retry frame transmission
9
Transmit collision
9
Transmit buffer under-run
Port 0
Bad FCS
9
Short events or frames under 64
bytes
9
Long events or frames over
1518/1522 bytes
Automatic statistic collection for
RMON
3
4
Block Diagram –
EA218E 8-Port Ethernet Access Controller
Automatic receive filtering for bad
frames for Store & Forward Mode
9
2
1
Typical Application:
9 A 16-port Ethernet Switch with 4-Fast Ethernet
Address
Mapping
Table
Buffer
RAM
RS232 Local
Control Console
SC220
XpressFlow
Engine
Switch
Manager
CPU
Flash
ROM
DRAM
Management Bus
XpressFlow Bus
Buffer
RAM
EA218E
8-Port
Ethernet
Access
Controller
8 Ethernet ports
Buffer
RAM
EA218E
8-Port
Ethernet
Access
Controller
8 Ethernet ports
Buffer
RAM
EA234
4-Port
Ethernet
Access
Controller
Four 100M
Fast Ethernet ports
System Block Diagram -16-Port Ethernet Switch with 4 Fast Ethernet Up-Links
© 1998 Zarlink Semiconductor, Inc.
2
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
1. PIN ASSIGNMENT
1.1 Logic Symbol
L_A[18:2]
L_BWE[3:0]#
L_WE[3:0]#
L_OE[3:0]#
L_ADSC#
L_CLK
4
4
4
P_CS#
P_ADS#
P_RWC
P_BS16#
P_RDY#
P_INT
P_RST#
P_CLK
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_OVLD#
S_HPREQ#
S_REQ#
S_GNT#
S_CLK
© 1998 Zarlink Semiconductor, Inc.
T_MODE
Tm_RXD
Tm_RXC
Tm_TXC
Tm_TXEN
Tm_TXD
Tm_LPBK
Tm_FD
Tm_COL
Tm_CRS
Tm_LNK
XpressFlow Bus Interface
P_A[11:1]
Management Bus
Interface
P_D[15:0]
Test Pin
Port [7:0]
10M Serial Interface
L_D[31:0]
Control Buffer
Memory Interface
EA-218E
3
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
1.2 Pin Assignment (Preliminary)
Note:
#
Input
In-ST
Output
Out-OD
I/O-TS
I/O-OD
5VT
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Output signal with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
Pin No(s).
Management Bus Interface
J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26, P25
C26,D24,C25,E24,D26,
D25,F24,E26,E25,G24, F26
F25
H25
J24
G25
G26
H26
J26
K24
XpressFlow Bus Interface
C23,A23,B22,C22,A22
B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13
B12
A12
C14
C13
B23
A24
B24
A13
D13
© 1998 Zarlink Semiconductor, Inc.
Symbol
Max
IOL / IOH Name and Functions
Type
P_D[15:0]
TTL I/O-TS (5VT)
16mA
P_A[11:1]
TTL In (5VT)
Management Bus – Address Bit [11:1]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
P_RST#
P_CLK
TTL In (5VT)
TTL In (5VT)
TTL Out-OD
TTL Out-OD
TTL In (5VT)
CMOS Output
TTL In-ST (5VT)
TTL In (5VT)
Management Bus – Address Strobe
Management Bus – Read/Write Control
Management Bus – Data Ready
Management Bus – 16 bit Data Bus
Management Bus – Chip Select
Management Bus – Interrupt Request
Management Bus – Master Reset
Management Bus – Bus Clock
16mA
16mA
4mA
S_D[31:27] /
P_C[0:4]
S_D[26:0]
CMOS I/O-TS
12 mA
CMOS I/O-TS
12mA
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-OD
CMOS I/O-OD
CMOS Output
CMOS Input
CMOS Input
CMOS Input
12 mA
12mA
12 mA
12 mA
12mA
4mA
4
Management Bus – Data Bit [15:0]
XpressFlow Bus – Data Bit [31:27] or Management Bus Interface Configuration bit [0:4]
XpressFlow Bus – Data Bit [26:0]
XpressFlow Bus – Message Envelope
XpressFlow Bus – End of Frame
XpressFlow Bus – Initiator Ready
XpressFlow Bus – Target Abort
XpressFlow Bus – High Priority Request
XpressFlow Bus – Bus Request to SC201
XpressFlow Bus – Bus Grant from SC201
XpressFlow Bus – Bus Overload
XpressFlow Bus – Clock
Rev.2.1 – February, 1999
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Symbol
Control Buffer Memory Interface
L_D[31:0]
M4,N2,L3,M1,M2,L1,K3,
L2,K4,K1,J3,K2,J1,J2,
H3,H1,H2,G3,G1,G2,F1,F3,F
2,E1,E3,E2,D1,D3,D2,C1,C2,
B1
A6,B6,C8,A7,D8,D7,C9,
L_A[18:2]
A8,B8,A9,C10,B9,D10,
A10,C11,B10,A11
C7
L_A[19] /
L_OE[3]#
D5,A5,A3
L_OE[2:0]#
D7,E4,B5,C4
L_WE[3:0]#
C6,B4,A4,C5
L_BWE[3:0]#
B3
L_ADSC#
G4
L_CLK
Ethernet Access Port cont. [7:0]
AF20,AE17,AD12,AD9,
T[7:2]_RXD
AC2,T25
AC25,AF6
T[1:0]_RXD
AD19,AD16,AE14,AF10,AC2 T[7:2]_RXC
1U24
AC24,AE7
T[1:0]_RXC
AF18,AD14,AE12,AF8,
T[7:0]_TXC
W2,AA25,AE22,AD1
AE19,AF15,AF12,AD8,
T[7:2]_TXEN
W1,AA24
AF22,AF2
T[1:0]_TXEN
AE20,AF16,AF13,AE10,
T[7:2]_TXD
Y1,W25
AF23,AE4
T[1:0]_TXD
AD18,AD15,AE13,AF9,
T[7:2]_LPBK
Y2,Y26
AE23,AF3
T[1:0]_LPBK
AF19,AE16,AD11,AE9,
T[7:2]_FD
V3,AA26
AD21,AE3
T[1:0]_FD
AD17,AE15,AF11,AE8,
T[7:2]_COL
V1,AB26
AD20,AC23
T[1:0]_COL
AE18,AD13,AD10,AD7,
T[7:2]_CRS
U3,AB24,
AF21,AD2
T[1:0]_CRS
AF17,AF14,AE11,AF7,
T[7:2]_LNK
V2,AB25,
AE21,AB3
T[1:0]_LNK
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
Pin No(s).
F
Type
TTL I/O-TS
Name and Functions
8mA
Local Memory Bus – Data Bit [31:0]
CMOS Output
8mA
Local Memory Bus – Address Bit [17:2]
CMOS Output
8mA
CMOS Output
CMOS Output
CMOS Output
CMOS Output
CMOS Output
2mA
2mA
8mA
8mA
8mA
Local Memory Bus – Address Bit [19] or Memory
Read Chip Select [3]
Local Memory Read Chip Select [2:0]
Local Memory Write Chip Select [3:0]
Local Memory Byte Write Enable, Byte [3:0]
Local Memory Controller Address Status
Local Memory Clock input
TTL In (5VT)
Receive Data – (one for each 10Mbps Serial Interface Port)
TTL In (5VT)
TTL In (5VT)
Receive Clock – (one for each 10Mbps Serial Interface Port)
TTL In (5VT)
TTL In (5VT)
Transmit Clock – (one for each 10Mbps Serial Interface Port)
Transmit Enable – (one for each 10Mbps Serial
Interface Port)
4mA
CMOS Output
CMOS Out
4mA
Transmit Data – (one for each 10Mbps Serial Interface Port)
CMOS Output
CMOS Out
2mA
Loop Back Enable – (one for each 10Mbps Serial
Interface Port)
CMOS Output
CMOS Out
2mA
Full Duplex Mode – (one for each 10Mbps Serial
Interface Port)
CMOS Out
CMOS Output
TTL In (5VT) Collision Detected – (one for each 10Mbps Serial
Interface Port)
TTL In (5VT)
TTL In (5VT)
Carrier Sense – (one for each 10Mbps Serial Interface Port)
TTL In (5VT)
TTL In (5VT)
Link Status – (one for each 10Mbps Serial Interface Port)
TTL In (5VT)
5
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Pin No(s).
Symbol
T_MODE
N1,M3,P2,P1,N3,R2,P3,R1,T T_D[15:10]
2R3,T1,R4,U2,T3,U1,U4
Pin No(s).
Power Pins
D6,D11,D16,D21,F4,
VDD
F23,L4,L23,T4,T23,AA4,AA23
AC6,AC11,AC16,AC21
VSS
A1,A2,A26,B2,B25,B26,
C3,C24,D4,D9,D14,D19,D23,
H4,J23,N4,P23,V4,W23,AC4,
AC8,AC13,
AC18,AC23,AD3,AD24,
AE1,AE2,AE25,AF1, AF25
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
Test Facility
A25
F
Symbol
Max
IOL / IOH Name & Functions
Type
CMOS I/O-TS CMOS Output
2mA
4mA
Test Pin – Set Test Mode upon Reset, and provides test status output during test mode
Test Pins – Reserved for internal use only
Type
Name & Functions
Power
+3.3 Volt DC Supply
Power
Ground
6
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
1.3 Pin Reference Table: (352 pin BGA)
Pin #
F26
G24
E25
E26
F24
D25
D26
E24
C25
D24
C26
F25
G26
H25
G25
J24
J26
H26
K24
P25
P26
R24
N25
N26
P24
M25
N24
M26
L25
M24
L26
K25
L24
K26
J25
Signal Name
P_A[1]
P_A[2]
P_A[3]
P_A[4]
P_A[5]
P_A[6]
P_A[7]
P_A[8]
P_A[9]
P_A[10]
P_A[11]
P_ADS#
P_CS#
P_RWC
P_BS16#
P_RDY#
P_RST#
P_INT
P_CLK
P_D[0]
P_D[1]
P_D[2]
P_D[3]
P_D[4]
P_D[5]
P_D[6]
P_D[7]
P_D[8]
P_D[9]
P_D[10]
P_D[11]
P_D[12]
P_D[13]
P_D[14]
P_D[15]
D13
A13
B23
A24
B24
B12
A12
C14
C13
B13
C15
A14
D15
B14
C16
A15
B15
A16
C17
B16
D17
A17
S_CLK
S_OVLD#
S_HPREQ#
S_REQ#
S_GNT#
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_D[0]
S_D[1]
S_D[2]
S_D[3]
S_D[4]
S_D[5]
S_D[6]
S_D[7]
S_D[8]
S_D[9]
S_D[10]
S_D[11]
S_D[12]
Note:
Pin #
C18
B17
A18
B18
C19
A19
B19
C20
A20
B20
A21
C21
D20
B21
A22
C22
B22
A23
C23
Signal Name
S_D[13]
S_D[14]
S_D[15]
S_D[16]
S_D[17]
S_D[18]
S_D[19]
S_D[20]
S_D[21]
S_D[22]
S_D[23]
S_D[24]
S_D[25]
S_D[26]
S_D[27] / P_C[4]
S_D[28] / P_C[3]
S_D[29] / P_C[2]
S_D[30] / P_C[1]
S_D[31] / P_C[0]
A11
B10
C11
A10
D10
B9
C10
A9
B8
A8
C9
B7
D8
A7
C8
B6
A6
C7
D5
A5
A3
D7
E4
B5
C4
C6
B4
A4
C5
B3
G4
B1
C2
C1
D2
D3
D1
E2
L_A[2]
L_A[3]
L_A[4]
L_A[5]
L_A[6]
L_A[7]
L_A[8]
L_A[9]
L_A[10]
L_A[11]
L_A[12]
L_A[13]
L_A[14]
L_A[15]
L_A[16]
L_A[17]
L_A[18]
L_A[19] / OE[3]#
L_OE[2]#
L_OE[1]#
L_OE[0]
L_WE[3]#
L_WE[2]#
L_WE[1]#
L_WE[0]#
L_BWE[3]#
L_BWE[2]#
L_BWE[1]#
L_BWE[0]#
L_ADSC#
L_CLK
L_D[0]
L_D[1]
L_D[2]
L_D[3]
L_D[4]
L_D[5]
L_D[6]
Pin #
E3
E1
F2
F3
F1
G2
G1
G3
H2
H1
H3
J2
J1
K2
J3
K1
K4
L2
K3
L1
M2
M1
L3
N2
M4
Signal Name
L_D[7]
L_D[8]
L_D[9]
L_D[10]
L_D[11]
L_D[12]
L_D[13]
L_D[14]
L_D[15]
L_D[16]
L_D[17]
L_D[18]
L_D[19]
L_D[20]
L_D[21]
L_D[22]
L_D[23]
L_D[24]
L_D[25]
L_D[26]
L_D[27]
L_D[28]
L_D[29]
L_D[30]
L_D[31]
AB3 T0_LNK
AD2 T0_CRS
AC3 T0_COL
AE3 T0_FD
AF3 T0_LPBK
AE4 T0_TXD
AF2 T0_TXEN
AD1 T0_TXC
AE7 T0_RXC
AF6 T0_RXD
AE21 T1_LNK
AF21 T1_CRS
AD20 T1_COL
AD21 T1_FD
AE23 T1_LPBK
AF23 T1_TXD
AF22 T1_TXEN
AE22 T1_TXC
AC24 T1_RXC
AC25 T1_RXD
AB25 T2_LNK
AB24 T2_CRS
AB26 T2_COL
AA26 T2_FD
Y26 T2_LPBK
W25 T2_TXD
AA24 T2_TXEN
AA25 T2_TXC
U24 T2_RXC
T25 T2_RXD
V2
T3_LNK
U3
T3_CRS
Pin #
V1
V3
Y2
Y1
W1
W2
AC1
AC2
AF7
AD7
AE8
AE9
AF9
AE10
AD8
AF8
AF10
AD9
AE11
AD10
AF11
AD11
AE13
AF13
AF12
AE12
AE14
AD12
AF14
AD13
AE15
AE16
AD15
AF16
AF15
AD14
AD16
AE17
AF17
AE18
AD17
AF19
AD18
AE20
AE19
AF18
AD19
AF20
Signal Name
T3_COL
T3_FD
T3_LPBK
T3_TXD
T3_TXEN
T3_TXC
T3_RXC
T3_RXD
T4_LNK
T4_CRS
T4_COL
T4_FD
T4_LPBK
T4_TXD
T4_TXEN
T4_TXC
T4_RXC
T4_RXD
T5_LNK
T5_CRS
T5_COL
T5_FD
T5_LPBK
T5_TXD
T5_TXEN
T5_TXC
T5_RXC
T5_RXD
T6_LNK
T6_CRS
T6_COL
T6_FD
T6_LPBK
T6_TXD
T6_TXEN
T6_TXC
T6_RXC
T6_RXD
T7_LNK
T7_CRS
T7_COL
T7_FD
T7_LPBK
T7_TXD
T7_TXEN
T7_TXC
T7_RXC
T7_RXD
A25
T_MODE
U4
U1
T3
U2
R4
T1
R3
T_D[0]
T_D[1]
T_D[2]
T_D[3]
T_D[4]
T_D[5]
T_D[6]
Pin #
T2
R1
P3
R2
N3
P1
P2
M3
N1
Signal Name
T_D[7]
T_D[8]
T_D[9]
T_D[10]
T_D[11]
T_D[12]
T_D[13]
T_D[14]
T_D[15]
D6
D11
D16
D21
F4
F23
L4
L23
T4
T23
AA4
AA23
AC6
AC11
AC16
AC21
A1
A2
A26
B2
B25
B26
C3
C24
D4
D9
D14
D19
D23
H4
J23
N4
P23
V4
W23
AC4
AC8
AC13
AC18
AC23
AD3
AD24
AE1
AE2
AE25
AF1
AF25
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Output signals with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2. FUNCTIONAL DESCRIPTION
2.1 Local Memory (Local Buffer Memory) Interface
Uses industry standard Synchronous Burst Mode SRAM up to 1M bytes
9
32k x 32, 64k x 32, 128k x 32, or 256k x 32
Provides separate Read and Write Chip Selects ( L_OE[3:0]# and L_WE[3:0]# ) for each memory chip
Supports back to back Read or Write operations across memory chips
2.1.1 Pin Description
Symbol
Type
L_D[31:0]
TTL I/O-TS
L_A[18:2]
CMOS Output
L_A[19] /
L_OE[3]#
CMOS Output
L_OE[2:0]#
CMOS Output
L_WE[3:0]#
CMOS Output
L_BWE[3:0]#
L_ADSC#
L_CLK
L_D[31:0]
L_A[18:2]
CMOS Output
CMOS Output
CMOS Output
TTL I/O-TS
CMOS Output
L_A[19] /
L_WE[3]#
CMOS Output
L_WE[2:0]#
CMOS Output
L_OE[3:0]#
CMOS Output
L_BWE[3:0]#
L_ADSC#
L_CLK
CMOS Output
CMOS Output
CMOS Output
Note:
Name and Functions
Local Memory Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Local Memory Address Bus Bit [18:2] – Bit [18:2] of a synchronous address bus. The
memory address is sampled when L_CS# is enabled and L_ADSC# is asserted.
Local Memory Address Bus Bit [19] or Local Memory Read Chip Select [3] – Depends on memory configuration, this pin can be used as the Local Memory Address Bit
[19] or as the Local Memory Read Chip Select [3].
Local Memory Read Chip Select [2:0] – allows up to read one of the 4 banks of memory.
Local Memory Write Chip Select [3:0] – allows up to write one of the 4 banks of memory.
Local Memory Byte Write Enable [3:0] – use to write individual bytes.
Local Memory Controller Address Status – to load a new address.
Local Memory Clock – a synchronous clock to memory devices.
Local Memory Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Local Memory Address Bus Bit [18:2] – Bit [17:2] of a synchronous address bus. The
memory address is sampled when L_CS# is enabled and L_ADSC# is asserted.
Local Memory Address Bus Bit [19] or Local Memory Write Chip Select [3] – Depends on memory configuration, this pin can be used as the Local Memory Address Bit
[19] or as the Local Memory Write Chip Select [3].
Local Memory Write Chip Select [2:0] – allows up to write one of the 4 banks of memory.
Local Memory Read Chip Select [3:0] – allows up to read one of the 4 banks of memory.
Local Memory Byte Write Enable [3:0] – use to write individual bytes.
Local Memory Controller Address Status – to load a new address.
Local Memory Clock – a synchronous clock to memory devices.
These pins have weak internal pull up resistors (50k to 100k Ohms each).
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.1.2 Supported Memory Configurations
Read/Write Chip Select and High Address Bits
Chip #3
Chip #2
Chip #1
Chip #0
L_A[19] /
RAM Chip # of RAM Total Buffer
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
Size
Chips Memory Size
32k x 32
64k x 32
128k x32
256k x32
1
128k bytes
----
----
----
----
2
256k bytes
----
----
----
----
4
512k bytes
1
256k bytes
2
512k bytes
4
1M bytes
1
512k bytes
----
----
----
----
2
1M bytes
----
----
----
----
1
1M bytes
----
L_A[19]
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
----
----
----
----
----
----
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
L_WE[3]# L_OE[3]# L_WE[2]# L_OE[2]# L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
L_WE[0]# L_OE[0]#
L_WE[1]# L_OE[1]# L_WE[0]# L_OE[0]#
----
----
L_WE[0]# L_OE[0]#
2.1.3 Bus Cycle Waveforms
L_CLK
L_ADSC#
L_CS#
L_A[19:2]
A1
A2
A3
A3+1
A3+2
A3+3
A4
A4+1
A4+2
A4+3
A5
A6
L_WE[3:0]#
L_BWE[3:0]#
L_OE[3:0]#
L_D[31:0] (Wr)
D1
L_D[31:0] (Rd)
D3
D3+1
D3+2
D3+3
D2
D6
D4
D4+1
D4+2
D4+3
D5
Typical Local Memory Access Operations
© 1998 Zarlink Semiconductor, Inc.
9
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.2 Processor Bus Interface
Supports various industry standard micro-processors including:
9
Intel 186, 386, and 486 family or equivalent
9
Motorola MPC series embedded processors
Supports 16-bit Data Bus
Supports early RDY cycle
9
Easily adapts to other industry standard CPUs
Meets timing requirement for Intel/AMD 186 family processors
Supports 1X or 2X CPU Clock
Provides separate Address and Data bus
9
Supports Big & Little Endian byte ordering
2X CPU Clock for 386 family processors
Provides a single interrupt signal to Switch Manager CPU
2.2.1 Pin Description
Symbol
P_C[4:0]
Type
CMOS Input
Name and Functions
Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the
processor configuration. By using external weak pull-up or -down resistors, they define the External Management Bus Interface Configuration. These inputs are sampled at the trailing edge of
the Reset cycle.
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU Bus interface, and
the setting of this bit is ignored.
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
Lo
Hi
P_A[11:1]
P_D[15:0]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
P_RST#
P_CLK
C[0]
CPU Clock
C[1]
Byte Order
C[2]
RWC
C[3]
Bus Size
C[4]
RDY Timing
1X Clock
2x Clock
Little Endian
Big Endian
P_R/W#
P_W/R#
n/a
n/a
Normal
Early
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
TTL In (5VT)
Address Bus Bit [11:1] – I/O port address
TTL I/O-TS (5VT) Data Bus Bit [15:0] – a 16-bit synchronous data bus.
TTL In (5VT)
Address Strobe – indicates valid address is on the bus
TTL Input (5VT) Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
C[1]=Low
P_R/W# is used for PowerPC or other similar processors.
C[1]=High
P_W/R# is used for 386, 486 or other similar processors
TTL Out-OD
Data Ready – timing indicates for bus data valid
TTL Out-OD
Bus Size 16 – response to bus master that the EA208 only supports 16-bit data bus width.
TTL Input (5VT) Chip Select – indicates the XpressFlow Engine is the target for the current bus operation.
CMOS Output
Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable
via chip configuration register.
TTL In-ST (5VT) CPU Reset – Synchronous reset Input from Switch Manager CPU
TTL In (5VT)
CPU Clock – 2X Clock for 386 family, and 1X Clock for the others
© 1998 Zarlink Semiconductor, Inc.
10
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.2.2 Motorola MPC801 Processor Interface
P_CLK
{CLKOUT}
P_ADS#
{TS#}
P_A[11:1]
{A[20:30]}
P_CS#
P_RWC
{RD/WR#}
P_RDY#
{TA#}
P_D[15:0]
{D[0:15]} (in)
P_D[15:0]
{D[0:15]} (out)
Note: Mnemonics with in {} are the equivalent signals defined by MPC801
Typical Motorola MPC801 CPU I/O Access Operations
2.2.3 Intel 486 Processor Interface
P_CLK
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D[15:0] (out)
Typical 486 CPU I/O Access Operations
© 1998 Zarlink Semiconductor, Inc.
11
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.2.4 Intel 386 Processor Interface
P_CLK
PH2 (internal)
PH2
P_ADS#
P_A[11:1]
P_CS#
P_W/R#
P_RDY#
P_D[15:0] (in)
P_D15:0] (out)
Typical 386 CPU I/O Access Operations
P_CLK
PH2 (internal)
PH2
PH1
PH2
PH2 or PH1
P_RST#
Internal PH2 Clock Synchronization **
Note: ** See Intel 386 Processor Data Book for more details
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.2.5 Register Map
Note:
All 32-bit registers are D-word aligned.
All 16-bit registers are also D-word aligned and right justified.
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
Register
This is a Global Register. CPU is allowed to write the Global Register of all devices by a single operation.
These registers are reserved for system diagnostic usage only.
I/O Offset
Little
Big
Endian Endian
Description
Device Configuration Registers (DCR)
GCR
Global Control Register
DCR0
DCR1
DCR2
DCR3
DCR4
DTSR
Device Status Register
Signature & Revision Register
ID Register
Device Configuration Register
Interfaces Status Register
Test Register
Interrupt Controls
ISR
Interrupt Status Register – Unmasked
ISRM
Interrupt Status Register – Masked
IMSK
Interrupt Mask Register
IAR
Interrupt Acknowledgment Register
Buffer Memory Interface
MWAR
Memory Write Address Reg. – Single Cycle
MRAR
Memory Read Address Reg. – Single Cycle
MBAR
Memory Address Register – Burst Mode
MWBS
Memory Write Burst Size (in D-words)
MRBS
Memory Read Burst Size (in D-words)
MWDR
Memory Write Data Register
MWDX
Memory Write Data Reg. – Byte Swapping
MRDR
Memory Read Data Register
MRDX
Memory Read Data Reg. – Byte Swapping
FCB Buffer & Stack Management
FCBBA
Frame Control Buffer – Base Address
FCBAG
Frame Control Buffer – Buffer Aging Status
FCBSL
FCBST
FCBSS
Frame Ctrl Buffer Stack – Size Limit
Frame Ctrl Buffer Stack – Buffer Low Threshold
Frame Ctrl Buffer Stack – Allocation Status
© 1998 Zarlink Semiconductor, Inc.
13
Reg.
Size
W/R
Note:
hF00
hF02
16-bit
W/--
hF00
hF10
hF20
hF30
hF40
hF70
hF02
hF12
hF22
hF32
hF42
hF72
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
--/R
--/R
W/R
W/R
--/R
W/R
hF80
hF90
hFA0
hFB0
hF82
hF92
hFA2
hFB2
16-bit
16-bit
16-bit
16-bit
--/R
--/R
W/R
W/--
hE08
hE18
hE28
hE40
hE50
hE68
hE6C
hE68
hE6C
hE08
hE18
hE28
hE42
hE52
hE68
hE6C
hE68
hE6C
32-bit
32-bit
32-bit
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
W/R
W/R
W/R
W/R
W/R
W/-W/---/R
--/R
hD00
hD30
hD02
hD32
16-bit
16-bit
W/R
--/R
hD90
hDA0
hDB0
hD92
hDA2
hDB2
16-bit
16-bit
16-bit
W/R
W/R
--/R
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I/O Offset
Little
Big
Endian Endian
Description
Access Control Function (Chip Level controls)
AVXR
VLAN Control Table (VCT) Index Register
AVDR
VCT Data Register
AVTC
VLAN Type Code
AXSC
Transmission Scheduling Control Register
AMIIC
MII Command Register
AMIIS
MII Status Register
AFCR
Flow Control Register
AMAR0
Multicast Address. for MAC Control Frames
AMAR1
Byte [3,2]
AMAR2
Byte [5,4]
AMCT
MAC Control FrameType Code Register
ADAR0
Base MAC Address Register – Byte [1,0]
ADAR1
Base MAC Address Register – Byte [3,2]
ADAR2
Base MAC Address Register – Byte [5,4]
F
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
Register
N
Reg.
Size
W/R
hC00
hC10
hC20
hC30
hC40
hC40
hC70
hC80
hC90
hCA0
hCB0
hCC0
hCD0
hCE0
hC02
hC12
hC22
hC32
hC40
hC40
hC72
hC82
hC92
hCA2
hCB2
hCC2
hCD2
hCE2
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
W/-W/R
W/R
W/R
W/---/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
Ethernet MAC Port Control Registers – (substitute [n] with Port Number, n = {0..3] )
ECR0
MAC Port Control Register
hn00
ECR1
MAC Port Configuration Register
hn10
ECR2
MAC Port Interrupt Mask Register
hn20
ECR3
MAC Port Interrupt Status Register
hn30
EXSR
MAC Tx Status Register
hn40
hn02
hn12
hn22
hn32
hn42
16-bit
16-bit
16-bit
16-bit
16-bit
W/R
W/R
W/R
--/R
--/R
Byte [1,0]
EXEC
MAC Tx Error Counters
hn50
hn52
16-bit
--/R
ERSR
MAC Rx Status Register
hn68
hn68
32-bit
--/R
EREC
MAC Rx Error Counters
hn78
hn78
32-bit
--/R
© 1998 Zarlink Semiconductor, Inc.
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Note:
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.3 XpressFlow Bus Operation
Zarlink’s optimized XpressFlow Bus architecture
Provides 1.6G bps switching bandwidth
9
Command Messages for passing control information between devices
9
Data Messages for forwarding an Ethernet frame from receiving port to transmission port
9 -33
1.07G bps
9 -40
1.28G bps
Built-in intelligent bus load regulator for data traffic balancing
9 -50
1.6G bps
Provides centralized bus arbitration with two level request priorities
Full multi bus master structure
Allows XpressFlow Engine to communicate with Access Controllers via a message passing protocol
9
High priority for Data Messages
9
Low priority for Command Messages
2.3.1 Pin Description
Symbol
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
Type
Name and Functions
CMOS
I/O-TS
Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Note:
During the system RESET period, Data Bit [31:28] are used as Processor Interface
Configuration bit [0:3]
CMOS Message Envelope – encompasses the entire period of a message transfer. Targets use the
I/O-TS leading edge of this signal to detect the beginning of a message transfer, and to decode the
message header for the intended target(s).
CMOS End of Frame – only used by frame data transfer messages to identify the end of frame condiI/O-TS tion. This signal is synchronous with the Rx Frame Status word appended to the end of the
message.
CMOS Initiator Ready – a normal true signal. When negated, it indicates the initiator had asserted wait
I/O-TS state(s) in between command words. Target should use this signal as enable signal for latching
the data from the bus.
CMOS Target Abort – when asserted, the target had aborted the reception of current message on the
I/O-OD bus.
CMOS High Priority Request – indicates one or more Bus Requester is requesting for high priority
I/O-OD message transfer.
CMOS Bus Request –Bus Request signals from Access Controller to Bus Access Arbitrator in XpressOutput Flow Engine
CMOS In- Bus Grant –Bus Grant signals from Bus Arbitrator to Bus Requester
put
CMOS Bus Overload – when asserted, all data forwarding bus bandwidth has been allocated. Cannot
Output support additional load for data forwarding traffic.
CMOS XpressFlow Bus Clock – 33MHz system clock
Input
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.3.2 Bus Cycle Waveforms
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
D0
D1
D2
D3
D4
D5
EoF
S_EOF#
S_IRDY
XpressFlow Bus Data Transfer Cycle
S_CLK
S_MSGEN#
S_D[31:0]
C0
C1
C0
C1
EOF
C0
C1
S_EOF#
S_TABT#
Command Cycle
Data Xfer w/o Data
Aborted Command
Other XpressFlow Bus Cycles
S_CLK
S_REQ[k]#
S_REQ[j]#
S_HPREQ#
High Priority Request pre-empts the low priority request.
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
S_CLK
S_MSGEN#
S_REQ[j]#
S_GNT[j]#
S_HPREQ#
S_REQ[I]#
S_GNT[I]#
XpressFlow Bus arbitration
S_CLK
S_REQ[k]#
S_OVLD#
Bus Overload pre-empts the data transfer request
© 1998 Zarlink Semiconductor, Inc.
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Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
2.4 10Mb Serial Interface for Port 0 through 7
Fully compliant with IEEE 802.3 10M bit Serial Interface Standard for connecting with external 10Mbps Ethernet Physical
Layer Transceiver
Supports 10Mbps 10BaseT serial interface
Supports both half and full duplex operation
2.4.1 Pin Description
Symbol
Tn_RXD
Tn_RXC
Tn_TXC
Tn_TXEN
Tn_TXD
Tn_LPBK
Tn_FD
Tn_COL
Tn_CRS
Tn_LNK
Note:
Type
Name and Functions
TTL In
(5VT)
TTL In
(5VT)
TTL In
(5VT)
CMOS
Output
CMOS
Output
CMOS
Output
CMOS
Output
TTL In
(5VT)
TTL In
(5VT)
TTL In
(5VT)
Receive Data – (one for each 10M bit Serial Interface Port) a receive data stream.
Receive Clock – (one for each 10M bit Serial Interface Port) from external phy for sampling the
receive data from Tn_RXD input
Transmit Clock – (one for each 10M bit Serial Interface Port) a continuous clock input with
35% to 65% duty cycles.
Transmit Enable – (one for each 10M bit Serial Interface Port)
Transmit Data – (one for each 10M bit Serial Interface Port) a transmit data stream.
Loop Back Enable – (one for each 10M bit Serial Interface Port) The polarity of this signal is
programmable via Port Configuration Register
Full Duplex Mode – (one for each 10M bit Serial Interface Port) The polarity of this signal is
programmable via Port Configuration Register
Collision Detected – (one for each 10M bit Serial Interface Port)
Carrier Sense – (one for each 10M bit Serial Interface Port)
Link Status – (one for each 10M bit Serial Interface Port) The polarity of this signal is programmable via Port Configuration Register
“n” is the port number [7:0]
These signals have programmable output polarity.
100 nsec
TXC
TXEN
TXD
10M bit Serial Interface – Transmit Timing
© 1998 Zarlink Semiconductor, Inc.
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
CRS
100 nsec
RXC
RXD
10M bit Serial Interface – Receive Timing
2.5 Test Pins
Symbol
T_MODE
Type
Name and Functions
CMOS
I/O-TS
Test Mode Selection & Test Output – Set Test Mode upon Reset, and provides test status
output during test mode
© 1998 Zarlink Semiconductor, Inc.
19
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
3. DC SPECIFICATION
3.1 ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Operating Temperature
-50°C to +125°C
0°C to +70°C
Supply Voltage VDD with Respect to VSS
Voltage on 5V Tolerant Input Pins
Voltage on Other Input Pins
+3.0 V to +3.6 V
-0.5 V to (VDD + 1.8 V)
-0.5 V to (VDD + 10%)
Stresses above those listed may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability.
3.2 DC CHARACTERISTICS
VDD = +3.0 V to +3.6 V
TAMBIENT = 0°C to +70°C
Preliminary
Symbol
fosc
IDD
VOH-CMOS
VOL-CMOS
VOH-TTL
VOL-TTL
VIH-CMOS
VIL-CMOS
VIH-TTL
VIL-TTL
VIH-5VT
VIL-5VT
ILI
ILO
IIH
IIL
CIN
COUT
CI/O
Parameter Description
Min
Type
Max
Unit
Frequency of Operation (-40)
Frequency of Operation (-50)
Frequency of Operation (-66)
Supply Power – @ 40 MHz (VDD =3.3 V)
Supply Power – @ 50 MHz (VDD =3.3 V)
Supply Power – @ 66.67 MHz (VDD =3.3 V)
Output High Voltage (CMOS) IOH = maximum
Output Low Voltage (CMOS) IOL = maximum
Output High Voltage (TTL) IOH = maximum
Output Low Voltage (TTL) IOL = maximum
Input High Voltage (CMOS)
Input Low Voltage (CMOS)
Input High Voltage (TTL)
Input Low Voltage (TTL)
Input High Voltage (TTL 5V tolerant)
Input Low Voltage (TTL 5V tolerant)
20
20
20
300
300
360
40.0000
50.0000
66.6667
500
500
600
0.45
VDD + 10%
VDD x 30%
VDD + 10%
+0.8
VDD + 1.8
+0.8
MHz
MHz
MHz
mA
mA
mA
V
V
V
V
V
V
V
V
V
V
Input Leakage Current (0.1 V ) VIN ) VDD)
(all pins except those with internal pull-up/pull-down resistors)
±10
µA
Output Leakage Current (0.1 V ) VOUT ) VDD)
Input Leakage Current VIH = VDD - 0.1 V
(pins with internal pull-down resistors)
Input Leakage Current VIL = 0.1 V
(pins with internal pull-up resistors)
Input Capacitance
Output Capacitance
I/O Capacitance
±15
60
µA
µA
-60
µA
VDD - 0.5
0.45
2.4
VDD x 70%
-0.5
2.0
-0.3
2.0
-0.3
8
8
10
pF
pF
pF
Notes:
© 1998 Zarlink Semiconductor, Inc.
20
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
4. AC SPECIFICATION
4.1 XpressFlow Bus Interface:
S_CLK
S12
S1-min
S_CLK
S_D[31:0]
S17
S18
S13
S2-min
S_D[31:0]
S_MSGEN#
S19
S20
S14
S3-min
S_MSGEN#
S_EOF#
S21
S22
S15
S4-min
S_EOF#
S_IRDY
S23
S24
S_IRDY
XpressFlow Bus Interface –
Output float delay timing
S27
S28
S_TABT#
S_CLK
S29
S30
S1-max
S1-min
S_HPREQ#
S_D[31:0]
S31
S32
S2-max
S2-min
S_GNT#
S_MSGEN#
S33
S34
S3-max
S3-min
S_OVLD#
S_EOF#
XpressFlow Bus Interface –
Input setup and hold timing
S4-max
S4-min
S_IRDY
S6-max
S6-min
S_TABT#
S7-max
S7-min
S_HPREQ#
S8-max
S8-min
S_REQ#
XpressFlow Bus Interface –
Output valid delay timing
© 1998 Zarlink Semiconductor, Inc.
21
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
-40
Symbol
R
Parameter
-50
-66
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Min
(ns)
Max
(ns)
Note:
S1
S_D[31:0] output valid delay
6
14
5
11
4
8.5
CL = 50pf
S2
S_MSGEN# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S3
S_EOF# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S4
S_IRDY output valid delay
6
14
5
11
4
8.5
CL = 50pf
S6
S_TABT# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S7
S_HPREQ# output valid delay
6
14
5
11
4
8.5
CL = 50pf
S8
S_REQ# output valid delay
6
14
5
11
4
8.5
CL = 20pf
S12
S_D[31:0] output float delay
18
15
12
S13
S_MSGEN# output float delay
18
15
12
S14
S_EOF# output float delay
18
15
12
S15
S_IRDY output float delay
18
15
12
S17
S_D[31:0] input set-up time
S18
S_D[31:0] input hold time
S19
S_MSGEN# input set-up time
S20
S_MSGEN# input hold time
S21
S_EOF# input set-up time
S22
2
1.5
1
5.5
4.5
3.5
2
1.5
1
5.5
4.5
3.5
2
1.5
1
S_EOF# input hold time
5.5
4.5
3.5
S23
S_IRDY input set-up time
2
1.5
1
S24
S_IRDY input hold time
5.5
4.5
3.5
S27
S_TABT# input set-up time
13
10
8
S28
S_TABT# input hold time
5.5
4.5
3.5
S29
S_HPREQ# input set-up time
2
1.5
1
S30
S_HPREQ# input hold time
5.5
4.5
3.5
S31
S_GNT# input set-up time
13
10
8
S32
S_GNT# input hold time
5.5
4.5
3.5
S33
S_OVLD# input set-up time
15
12
9
S34
S_OVLD# input hold time
5.5
4.5
3.5
AC Characteristics – XpressFlow Bus Interface
© 1998 Zarlink Semiconductor, Inc.
22
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
4.2 CPU Bus Interface:
P_CLK
P_CLK
P_D[31:0]
P15
P16-min
P1
P2
P_RST#
P3
P4
CPU Bus Interface –
Output float delay timing
P_ADS#
P5
P6
P_W/R#
P_CLK
P7
P16-max
P16-min
P8
P_CS#
P_D[15:0]
P9
P17-max
P17-min
P10
P_A[11:1]
P_RDY#
P11
P18-max
P18-min
P12
P_D[15:0]
P_INT
CPU Bus Interface –
Input setup and hold timing
CPU Bus Interface –
Output valid delay timing
-40
Symbol
Parameter
Min
(ns)
-50
Max
(ns)
Min
(ns)
-66
Max
(ns)
Min
(ns)
P1
P_RST# input setup time
13
10
8
P2
P_RST# input hold time
3.5
2.5
2
P3
P_ADS# input set-up time
13
10
8
P4
P_ADS# input hold time
3.5
2.5
2
P5
P_W/R# input set-up time
13
10
8
P6
P_W/R# input hold time
3.5
2.5
2
P7
P_CS# input set-up time
13
10
8
P8
P_CS# input hold time
3.5
2.5
2
P9
P_A[11:1] input set-up time
13
10
8
P10
P_A[11:1] input hold time
3.5
2.5
2
Max
(ns)
Note:
P11
P_D[31:0]# input set-up time
13
10
8
P12
P_D[31:0]# input hold time
3.5
2.5
2
P15
P_D[31:0]# output float delay
17
13
10
P16
P_D[31:0]# # output valid delay
8.5
6.5
5
CL = 60pf
P17
P_RDY# output valid delay
8.5
6.5
5
CL = 60pf
P18
P_INT# output valid delay
17
13
10
CL = 20pf
AC Characteristics -- CPU Bus Interface
© 1998 Zarlink Semiconductor, Inc.
23
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
4.3 Local Memory Interface:
L_CLK
L_CLK
L1
L3-max
L3-min
L2
L_D[31:0]
L_D[31:0]
L4-max
L4-min
Local Memory Interface –
Input setup and hold timing
L_A[19:2]
L5-max
L5-min
L_CS[3:0]#
L_CLK
L6-max
L6-min
L10
L3-min
L_ADSC#
L_D[31:0]
L7-max
L7-min
L_BWE[3:0]#
Local Memory Interface –
Output float delay timing
L8-max
L8-min
L_WE#]
L9-max
L9-min
L_OE#
Local Memory Interface –
Output valid delay timing
-40
Symbol
-50
Max
(ns)
Min
(ns)
-66
Max
(ns)
Min
(ns)
Max
(ns)
Note:
Parameter
Min
(ns)
L1
L_D[31:0]# input set-up time
6.5
5.5
4
L2
L_D[31:0]# input hold time
3
2.5
2
L3
L_D[31:0]# output valid delay
17
13
10
CL = 30pf
L4
L_A[19:2] output valid delay
17
13
10
CL = 30pf
L6
L_ADSC# output valid delay
17
13
10
CL = 30pf
L7
L_BWE[3:0]# output valid delay
17
13
10
CL = 30pf
L8
L_WE# output valid delay
17
13
10
CL = 10pf
L9
L_OE# output valid delay
17
13
10
CL = 10pf
L10
L_D[31:0]# output float delay
22
18
14
AC Characteristics – Local Memory Interface
© 1998 Zarlink Semiconductor, Inc.
24
Rev.2.1 – February, 1999
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EA218E
8-Port 10Mb Ethernet Access Controller
XpressFlow-2020 Series –
Ethernet Switch Chipset
5. PACKAGING INFORMATION
352-PIN BGA
(35x35x2.33mm)
Pin 1 I.D.
B
24
26
25
20
22
23
21
18
19
16
17
14
15
12
13
10
11
8
9
6
7
4
5
0.75 DIA
+/- 0.15
(352X)
2
3
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
24.00 Ref
1.27
32.00 Ref
31.75
35.00 +/- 0.20
1.17
Ref
C
0.56 2.33
Ref +/-0.13
0.60 +/-0.10
Ordering Information
Part Number
EA218E
Description
8-port 10Mbps Ethernet network access
Environmental –
C = Commercial
I = Industrial
Speed grade -
0 = 40 MHz
5 = 50 MHz
6 = 66 MHz
Package -
Identification
Zarlink Use
Revision
C 0 B
TAV
rrr
Revision 001 = Rev.1
For latest revision, leave blank
B = BGA
This Document contains preliminary information on a product. Zarlink Semiconductor Inc. reserves the right to make any changes without notice.
400 March Road
Ottawa, Ontario, Canada K2K 3H4
Tel. 613 592 0200, FAX: 613 592 1010
Web Site: www.zarlink.com
Rev. 2.1 February 1999
¶1998 Zarlink Semiconductor Inc.
E1
DIMENSION
A
A1
A2
D
D1
E
E1
b
e
MIN
MAX
2.20
2.46
0.50
0.70
1.17 REF
35.20
34.80
30.00 REF
35.20
34.80
30.00 REF
0.60
0.90
1.27
352
Conforms to JEDEC MS - 034
E
e
D1
A2
D
A1
A
1. CONTROLLING DIMENSIONS ARE IN MM
2. DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER
3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
4. N IS THE NUMBER OF SOLDER BALLS
5. NOT TO SCALE.
6. SUBSTRATE THICKNESS IS 0.56 MM
Package Code
c Zarlink Semiconductor 2002 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes:
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visit our Web Site at
www.zarlink.com
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TECHNICAL DOCUMENTATION - NOT FOR RESALE