AD AD5593R 8-channel, 12-bit, configurable adc/dac Datasheet

8-Channel, 12-Bit, Configurable ADC/DAC
with On-Chip Reference, I2C Interface
AD5593R
Data Sheet
FEATURES
GENERAL DESCRIPTION
8-channel, configurable ADC/DAC/GPIO
Configurable as any combination of
8 12-bit DAC channels
8 12-bit ADC channels
8 general-purpose I/O pins
Integrated temperature sensor
16-lead TSSOP and LFCSP and 16-ball WLCSP packages
I2C interface
The AD5593R has eight input/output (I/O) pins, which can be
independently configured as digital-to-analog converter (DAC)
outputs, analog-to-digital converter (ADC) inputs, digital outputs,
or digital inputs. When an I/O pin is configured as an analog
output, it is driven by a 12-bit DAC. The output range of the
DAC is 0 V to VREF or 0 V to 2 × VREF. When an I/O pin is
configured as an analog input, it is connected to a 12-bit ADC
via an analog multiplexer. The input range of the ADC is 0 V to
VREF or 0 V to 2 × VREF. The I/O pins can also be configured to
be general-purpose, digital input or output (GPIO) pins. The
state of the GPIO pins can be set or read back by accessing the
GPIO write data register and GPIO read configuration registers,
respectively, via an I2C write or read operation.
APPLICATIONS
Control and monitoring
General-purpose analog and digital I/O
The AD5593R has an integrated 2.5 V, 20 ppm/°C reference that
is turned off by default and an integrated temperature indicator
that gives an indication of the die temperature. The temperature
value is read back as part of an ADC read sequence.
The AD5593R is available in 16-lead TSSOP and LFCSP, as well
as a 16-ball WLCSP, and operates over a temperature range of
−40°C to +105°C.
Table 1. Related Products
Product
AD5592R
AD5592R-1
Description
AD5593R equivalent with SPI interface
AD5593R equivalent with SPI interface and VLOGIC pin
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
VREF
AD5593R
2.5V
REFERENCE
POWER-ON
RESET
GPIO0
INPUT
REGISTER
DAC
REGISTER
DAC 0
INPUT
REGISTER
DAC
REGISTER
DAC 7
I/O0
SCL
SDA
A0
GPIO7
I2C
INTERFACE
LOGIC
RESET
I/O7
MUX
SEQUENCER
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
GND
12507-001
TEMPERATURE
INDICATOR
Figure 1.
Rev. C
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AD5593R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ................................................................................ 21
Applications ....................................................................................... 1
Write Operation.......................................................................... 21
General Description ......................................................................... 1
Read Operation........................................................................... 21
Functional Block Diagram .............................................................. 1
Pointer Byte ................................................................................. 23
Revision History ............................................................................... 2
Control Registers ........................................................................ 23
Specifications..................................................................................... 3
General-Purpose Control Register .......................................... 24
Timing Characteristics ................................................................ 6
Configuring the AD5593R ........................................................ 25
Absolute Maximum Ratings ............................................................ 7
DAC Write Operation ................................................................ 26
Thermal Resistance ...................................................................... 7
DAC Readback............................................................................ 26
ESD Caution .................................................................................. 7
ADC Operation .......................................................................... 27
Pin Configuration and Function Descriptions ............................. 8
GPIO Operation ......................................................................... 29
Typical Performance Characteristics ........................................... 11
Power-Down/Reference Control .............................................. 30
Terminology .................................................................................... 16
Reset Function ............................................................................ 30
Theory of Operation ...................................................................... 18
Applications Information .............................................................. 31
DAC Section ................................................................................ 18
Microprocessor Interfacing ....................................................... 31
ADC Section ............................................................................... 18
AD5593R to ADSP-BF537 Interface ........................................ 31
GPIO Section .............................................................................. 20
Layout Guidelines....................................................................... 31
Internal Reference ...................................................................... 20
Outline Dimensions ....................................................................... 32
Reset Function ............................................................................ 20
Ordering Guide............................................................................... 33
Temperature Indicator ............................................................... 20
REVISION HISTORY
4/2017—Rev. B to Rev. C
Changes to Reset Function Section .............................................. 30
Changes to Ordering Guide .......................................................... 33
1/2016—Rev. A to Rev. B
Added 16-Lead LFCSP....................................................... Universal
Added VLOGIC Parameter and ILOGIC Parameter, Table 2 ............... 5
Added Figure 4 and Table 7; Renumbered Sequentially ............. 9
Added Calculating ADC Input Current Section and Figure 33 .... 20
Changes to Temperature Indicator Section................................. 21
Changes to Figure 34 ...................................................................... 22
Changes to Figure 35 and Figure 36............................................. 23
Changes to Figure 37 ...................................................................... 24
Change to DAC Readback Section ............................................... 27
Changes to ADC Operation Section ............................................ 28
Changes to Outline Dimensions................................................... 33
Changes to Ordering Guide .......................................................... 34
10/2014—Rev. 0 to Rev. A
Added 16-Ball WLCSP ...................................................... Universal
Changes to Gain Error Parameter, Table 1.....................................3
Changes to Table 5.............................................................................7
Added Figure 4 and Table 7; Renumbered Sequentially ..............9
Change to ADC Section ................................................................ 17
Changes to Reset Function Section and Temperature
Indicator Section ............................................................................ 19
Changes to Reset Function Section, Table 24, and Table 25 .......... 27
Added Figure 41, Outline Dimensions ........................................ 29
Updated Outline Dimensions ....................................................... 29
Changes to Ordering Guide .......................................................... 29
8/2014—Revision 0: Initial Version
Rev. C | Page 2 of 33
Data Sheet
AD5593R
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, VREF = 2.5 V (internal), TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
ADC PERFORMANCE
Resolution
Input Range 1
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error
Track Time (tTRACK) 2
Conversion Time (tCONV)2
Signal to Noise Ratio (SNR) 3
Min
69
67
61
69
67
60
−91
−89
−72
91
91
72
15
12
50
−95
8.2
1.6
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
ps
dB
MHz
MHz
2
Spurious Free Dynamic Range (SFDR)
Aperture Delay2
Aperture Jitter2
Channel-to-Channel Isolation
Full Power Bandwidth
12
0
0
−1
−1
−3
VREF
2 × VREF
+1
+1
+3
8
Zero Code Error
Total Unadjusted Error (TUE)
0.65
±0.03
±0.015
Capacitive Load Stability
Resistive Load
Short-Circuit Current
DC Crosstalk2
DC Output Impedance
DC Power Supply Rejection Ratio (PSRR)2
Load Impedance at Rails 5
Unit
Bits
V
V
LSB
LSB
mV
% FSR
ns
µs
dB
dB
dB
dB
VREF
2 × VREF
+2
+1
±5
0.3
500
Total Harmonic Distortion (THD)
INL
DNL
Offset Error
Offset Error Drift2
Gain Error
Max
12
0
0
−2
−1
Signal-to-Noise + Distortion (SINAD)
Ratio
DAC PERFORMANCE 4
Resolution
Output Range
Typ
±0.2
±0.1
2
±0.25
±0.1
2
10
1
25
−4
+4
0.2
0.15
25
Bits
V
V
LSB
LSB
mV
µV/°C
% FSR
% FSR
mV
% FSR
% FSR
nF
nF
kΩ
mA
µV
Ω
mV/V
Ω
Rev. C | Page 3 of 33
Test Conditions/Comments
fIN = 10 kHz sine wave
ADC range select bit = 0
ADC range select bit = 1
VDD = 2.7 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 2.7 V, input range = 0 V to VREF
VDD = 3.3 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 2.7 V, input range = 0 V to VREF
VDD = 3.3 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 2.7 V, input range = 0 V to VREF
VDD = 3.3 V, input range = 0 V to VREF
VDD = 5.5 V, input range = 0 V to 2 × VREF
VDD = 3 V
VDD = 5 V
fIN = 5 kHz
At 3 dB
At 0.1 dB
DAC range select bit = 0
DAC range select bit = 1
Output range = 0 V to VREF
Output range = 0 V to 2 × VREF
Output range = 0 V to VREF
Output range = 0 V to 2 × VREF
RLOAD = ∞
RLOAD = 1 kΩ
Single channel, full-scale output change
DAC code = midscale, VDD = 3 V ± 10% or 5 V ± 10%
AD5593R
Parameter
Load Regulation
Data Sheet
Min
Power-Up Time
AC SPECIFICATIONS
Slew Rate
Settling Time
DAC Glitch Impulse
DAC to DAC Crosstalk
Digital Crosstalk
Analog Crosstalk
Digital Feedthrough
Multiplying Bandwidth
Output Voltage Noise Spectral Density
SNR
SFDR
SINAD
Total Harmonic Distortion
REFERENCE INPUT
VREF Input Voltage
DC Leakage Current
VREF Input Impedance
REFERENCE OUTPUT
VREF Output Voltage
VREF Temperature Coefficient
Capacitive Load Stability
Output Impedance
Max
µV/mA
7
µs
1.25
6
2
1
0.1
1
0.1
240
200
V/µs
µs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
nV/√Hz
81
77
74
−76
dB
dB
dB
dB
Test Conditions/Comments
VDD = 5 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤
+10 mA
VDD = 3 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤
+10 mA
Exiting power-down mode, VDD = 5 V
DAC code = full scale, output range = 0 V to 2 × VREF
DAC code = midscale, output range = 0 V to 2 × VREF,
measured at 10 kHz
VDD
+1
V
µA
kΩ
kΩ
No I/Ox pins configured as DACs
DAC output range = 0 V to 2 × VREF
DAC output range = 0 V to VREF
2.505
V
ppm/°C
μF
Ω
Ω
µV p-p
nV/√Hz
µV/V
µV/V
RLOAD = 2 kΩ
VDD = 2.7 V
VDD = 5 V
0.1 Hz to 10 Hz
At ambient, f = 1 kHz, CL = 10 nF
At ambient, sweeping VDD from 2.7 V to 5.5 V
At ambient, sweeping VDD from 2.7 V to 3.3 V
210
120
±5
µV/mA
µV/mA
mA
At ambient, −5 mA ≤ load current ≤ +5 mA
At ambient, −5 mA ≤ load current ≤ +5 mA
VDD ≥ 3 V
1.6
mA
12
24
2.495
Unit
µV/mA
200
1
−1
Output Voltage Noise
Density
Line Regulation
Load Regulation
Sourcing
Sinking
Output Current Load Capability
GPIO OUTPUT
ISOURCE and ISINK
Output Voltage
High, VOH
Low, VOL
GPIO INPUT
Input Voltage
High, VIH
Low, VIL
Input Capacitance
Hysteresis
Input Current
Typ
200
2.5
20
5
0.15
0.7
10
240
20
10
VDD − 0.2
0.4
VDD × 0.7
VDD × 0.3
20
0.2
±1
V
V
V
V
pF
V
µA
Rev. C | Page 4 of 33
ISOURCE = 1 mA
ISOURCE = 1 mA
Data Sheet
Parameter
LOGIC INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUT (SDA)
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Output Capacitance
TEMPERATURE SENSOR2
Resolution
Operating Range
Accuracy
Track Time
POWER REQUIREMENTS
VDD
IDD
Power-Down Mode
Normal Mode
VDD = 5 V
AD5593R
Min
Max
Unit
+0.01
0.3 × VLOGIC
+1
10
V
V
µA
pF
0.7 × VLOGIC
−1
VLOGIC − 0.2
0.4
10
12
−40
+105
±3
5
20
2.7
VDD = 3 V
VLOGIC
ILOGIC
Typ
1.8
5.5
2.7
3.5
V
V
pF
Bits
°C
°C
µs
µs
ISOURCE = 200 µA; VDD = 2.7 V to 5.5 V
ISINK = 200 µA
ADC buffer enabled
ADC buffer disabled
V
Digital inputs = 0 V or VDD
µA
1.6
1
2.4
mA
mA
mA
1.1
mA
1
0.75
0.5
0.5
1.1
1
1.1
mA
mA
mA
mA
mA
mA
mA
0.78
mA
0.75
0.5
0.45
0.45
mA
mA
mA
mA
V
μA
VDD
3.5
Test Conditions/Comments
I/O0 to I/O7 are DACs, internal reference, gain = 2
I/O0 to I/O7 are DACs, external reference, gain = 2
I/O0 to I/O7 are DACs and sampled by the ADC,
internal reference, gain = 2
I/O0 to I/O7 are DACs and sampled by the ADC,
external reference, gain = 2
I/O0 to I/O7 are ADCs, internal reference, gain = 2
I/O0 to I/O7 are ADCs, external reference, gain = 2
I/O0 to I/O7 are general-purpose outputs
I/O0 to I/O7 are general-purpose inputs
I/O0 to I/O7 are DACs, internal reference, gain = 1
I/O0 to I/O7 are DACs, external reference, gain = 1
I/O0 to I/O7 are DACs and sampled by the ADC,
internal reference, gain = 1
I/O0 to I/O7 are DACs and sampled by the ADC,
external reference, gain = 1
I/O0 to I/O7 are ADCs, internal reference, gain = 1
I/O0 to I/O7 are ADCs, external reference, gain = 1
I/O0 to I/O7 are general-purpose outputs
I/O0 to I/O7 are general-purpose inputs
When using the internal ADC buffer, there is a dead band of 0 V to 5 mV.
Guaranteed by design and characterization; not production tested.
All specifications expressed in decibels are referred to full-scale input, FSR, and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4
DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a reduced code range of 8 to 4085. An upper dead band of
10 mV exists when VREF = VDD.
5
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 26 and Figure 27).
1
2
3
Rev. C | Page 5 of 33
AD5593R
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.7 V to
5.5 V, 1.8 V ≤ VLOGIC ≤ VDD; 2.5 V ≤ VREF ≤ VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1
t1
t2
t3
t4
t5
t6 2
t7
t8
t9
t10
Min
2.5
0.6
1.3
0.6
100
Typ
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
pF
0.9
0.6
0.6
1.3
300
0
t11
250
0
300
20 + 0.1CB 3
C B3
400
Conditions/Comments
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
Guaranteed by design and characterization; not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
3
CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD.
1
2
Timing Diagram
SDA
t9
t3
t11
t10
t4
SCL
t6
t2
t5
START
CONDITION
t1
t7
REPEATED
START
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
Rev. C | Page 6 of 33
t8
STOP
CONDITION
12507-002
t4
Data Sheet
AD5593R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Table 4.
Parameter
VDD to GND
VLOGIC to GND
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ max)
Lead Temperature
Soldering
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−0.3 V to VLOGIC +0.3 V
−0.3 V to VDD +0.3 V
−40°C to +105°C
−65°C to +150°C
+150°C
JEDEC industry-standard
J-STD-020
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
16-Lead TSSOP
16-Lead LFCSP
16-ball WLCSP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 7 of 33
θJA
112
137
60
Unit
°C/W
°C/W
°C/W
AD5593R
Data Sheet
RESET 1
16
SCL
A0 2
15
SDA
VDD 3
14
GND
AD5593R
13
I/O7
12
I/O6
I/O2 6
11
I/O5
I/O3 7
10
I/O4
8
9
VLOGIC
I/O0 4
I/O1 5
VREF
TOP VIEW
(Not to Scale)
12507-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. 16-Lead TSSOP Pin Configuration
Table 6. 16-Lead TSSOP Pin Function Descriptions
Pin No.
1
Mnemonic
RESET
2
3
4 to 7,
10 to 13
A0
VDD
I/O0 to I/O7
8
VREF
9
14
15
VLOGIC
GND
SDA
16
SCL
Description
Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is reset
to its default configuration.
Address Input. Sets the LSB of the 7-bit slave address.
Power Supply Input. The AD5593R can operate from 2.7 V to 5.5 V. Decouple the supply with a 0.1 µF capacitor to GND.
Input/Output 0 Through Input/Output 7. These pins can be independently configured as DACs, ADCs, or generalpurpose digital inputs or outputs. The function of each pin is determined by programming the appropriate bits in
the configuration registers.
Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the VREF pin. A
0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the
AD5593R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage
range for the external reference is 1 V to VDD.
Interface Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
Ground Reference Point for All Circuitry.
Serial Data Input. This pin is used in conjunction with the SCL line to clock data in to or out of the input shift register. SDA
is a bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor.
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data in to or out of the 16-bit input register.
Rev. C | Page 8 of 33
13 SDA
14 SCL
16 A0
AD5593R
15 RESET
Data Sheet
V DD 1
12 GND
I/O0 2
AD5593R
11 I/O7
I/O1 3
TOP VIEW
(Not to Scale)
10 I/O6
I/O4 8
VLOGIC 7
I/O3 5
VREF 6
I/O5
12507-004
9
I/O2 4
Figure 4. 16-Lead LFCSP Pin Configuration
Table 7. 16-Ball LFCSP Pin Function Descriptions
Pin No.
1
2 to 5, 8 to 11
Mnemonic
VDD
I/O0 to I/O7
6
VREF
7
12
13
VLOGIC
GND
SDA
14
SCL
15
RESET
16
A0
Description
Power Supply Input. The AD5593R operates from 2.7 V to 5.5 V. Decouple the supply with a 0.1 μF capacitor to GND.
Input/Output 0 through Input/Output 7. These pins can be independently configured as DACs, ADCs, or generalpurpose digital inputs or outputs. The function of each pin is determined by programming the appropriate
bits in the configuration registers.
Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the
pin. A 0.1 μF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance
from the AD5593R. When the internal reference is disabled, an external reference must be applied to this pin.
The voltage range for the external reference is 1 V to VDD.
Interface Power Supply. The voltage ranges from 1.8 V to 5.5 V.
Ground Reference Point for All Circuitry.
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the input shift register.
SDA is a bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor.
Serial Clock Line. This is pin used in conjunction with the SDA line to clock data into or out of the 16-bit input
register.
Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is
reset to its default configuration.
Address Input. This pin sets the LSB of the 7-bit slave address.
Rev. C | Page 9 of 33
AD5593R
Data Sheet
BALL A1
INDICATOR
1
2
3
4
SDA
SCL RESET
A0
GND
I/O7
I/O0
VDD
I/O6
I/O3
I/O2
I/O1
I/O4 VLOGIC VREF
I/O5
A
B
D
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
12507-201
C
Figure 5. 16-Ball WLCSP Pin Configuration
Table 8. 16-Ball WLCSP Pin Function Descriptions
Pin No.
A3
Mnemonic
RESET
A4
B4
B3, C4, C3,
C2, D1, D4,
C1, B2
D3
A0
VDD
I/O0 to I/O7
D2
B1
A1
VLOGIC
GND
SDA
A2
SCL
VREF
Description
Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5593R is
reset to its default configuration.
Address Input. Sets the LSB of the 7-bit slave address.
Power Supply Input. The AD5593R can operate from 2.7 V to 5.5 V. Decouple the supply with a 0.1 μF capacitor to GND.
Input/Output 0 through Input/Output 7. These pins can be independently configured as DACs, ADCs, or generalpurpose digital inputs or outputs. The function of each pin is determined by programming the appropriate bits
in the configuration registers.
Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on the
pin. A 0.1 μF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance
from the AD5593R. When the internal reference is disabled, an external reference must be applied to this pin.
The voltage range for the external reference is 1 V to VDD.
Interface Power Supply. The voltage ranges from 1.8 V to 5.5 V.
Ground Reference Point for All Circuitry.
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the input shift register.
SDA is a bidirectional, open-drain line that must be pulled to the VLOGIC supply with an external pull-up resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register.
Rev. C | Page 10 of 33
Data Sheet
AD5593R
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.5
0.4
0.8
0.3
0.2
DNL (LSB)
INL (LSB)
0.6
0.4
0.2
0.1
0
–0.1
–0.2
–0.3
0
1000
2000
3000
4000
ADC CODE
–0.5
12507-102
0
0
1000
3000
4000
Figure 9. ADC DNL; VDD = 2.7 V
Figure 6. ADC INL; VDD = 5.5 V
35000
0.5
0.4
30000
NUMBER OF OCCURRENCES
0.3
0.2
DNL (LSB)
2000
ADC CODE
12507-105
–0.4
–0.2
0.1
0
–0.1
–0.2
–0.3
25000
VDD = 2.7V
SAMPLES = 60000
VIN = 1.5V
GAIN = 1
EXTERNAL
REFERENCE = 2.5V
20000
15000
10000
5000
–0.4
1000
2000
3000
4000
ADC CODE
0
2528
2530
ADC CODE
Figure 10. Histogram of ADC Codes; VDD = 2.7 V
Figure 7. ADC DNL; VDD = 5.5 V
35000
0.5
0.4
30000
NUMBER OF OCCURRENCES
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
VDD = 5.5V
SAMPLES = 60000
VIN = 1.5V
GAIN = 1
EXTERNAL REFERENCE = 2.5V
25000
20000
15000
10000
5000
–0.5
0
1000
2000
3000
ADC CODE
4000
0
2520
2521
2522
2523
2524
2525
ADC CODE
Figure 11. Histogram of Codes; VDD = 5.5 V
Figure 8. ADC INL; VDD = 2.7 V
Rev. C | Page 11 of 33
2526
12507-101
–0.4
12507-104
INL (LSB)
2529
12507-100
0
12507-103
–0.5
AD5593R
Data Sheet
1
4
VDD = 3V/5V
2
–1
GLITCH (nV-sec)
ADC BANDWIDTH (dB)
0
–2
–3
–4
0
–2
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–4
12507-124
–6
1k
0
0.5
2.505
VOUT (V)
4095
0
2.500
1024
2048
3072
4095
DAC CODE
2.490
–10
12507-130
0
0
10
20
TIME (µs)
Figure 13. DAC INL
12507-115
2.495
Figure 16. DAC Digital to Analog Glitch (Rising)
2.510
0.5
2.505
VOUT (V)
1.0
0
–0.5
2.500
0
1024
2048
DAC CODE
3072
4095
12507-127
2.495
Figure 14. DAC DNL
2.490
–10
0
10
TIME (µs)
Figure 17. DAC Digital to Analog Glitch (Falling)
Rev. C | Page 12 of 33
20
12507-116
INL (LSB)
2.510
–0.5
DNL (LSB)
3072
Figure 15. DAC Adjacent Code Glitch
1.0
–1.0
2048
DAC CODE
Figure 12. ADC Bandwidth
–1.0
1024
12507-126
–5
Data Sheet
AD5593R
2.58
4.0
2.56
3.5
RL = 2kΩ
CL = 200pF
2.54
3.0
VOUT (V)
VOUT (V)
2.52
2.50
2.48
2.5
2.0
2.46
0
5
10
0
2
3
4
5
Figure 21. DAC Settling Time, Output Range = 0 V to 2 × VREF
2.58
4.0
2.56
3.5
2.54
3.0
2.52
2.5
VOUT (V)
Figure 18. DAC Settling Time (100 Code Change, Rising Edge)
2.50
2.0
2.48
1.5
2.46
1.0
2.44
0.5
2.42
–10
–5
0
5
10
TIME (µs)
0nF LOAD
10nF LOAD
22nF LOAD
47nF LOAD
0
–5
0
5
10
15
TIME (µs)
Figure 19. DAC Settling Time (100 Code Change, Falling Edge)
Figure 22. DAC Settling Time vs. Capacitive Load
2.00
200
150
1.75
RL = 2kΩ
CL = 200pF
100
VOUT (µV p-p)
1.50
1.25
1.00
50
0
–50
–100
0.75
0
1
2
3
4
TIME (µs)
5
Figure 20. DAC Settling Time, Output Range = 0 V to VREF
–200
0
2
4
6
8
TIME (Seconds)
Figure 23. DAC 1/f Noise with External Reference
Rev. C | Page 13 of 33
10
12507-109
0.50
–150
12507-131
VOUT (V)
1
TIME (µs)
12507-120
VOUT (V)
TIME (µs)
1.0
12507-121
–5
12507-119
2.42
–10
12507-132
1.5
2.44
AD5593R
Data Sheet
5
200
150
4
OUTPUT VOLTAGE (V)
VOUT (µV p-p)
100
50
0
–50
–100
3
FULL-SCALE
2
3/4 SCALE
1/2 SCALE
1
1/4 SCALE
–150
2
4
6
8
10
TIME (Seconds)
0
–30
10
20
30
6
FULL-SCALE
OUTPUT VOLTAGE (V)
5
1500
1000
3/4 SCALE
4
3
1/2 SCALE
2
1/4 SCALE
1
ZERO SCALE
500
0
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 25. DAC Output Noise Spectral Density
–1
–30
–20
–10
0
10
20
LOAD CURRENT (mA)
Figure 27. DAC Output Sink and Source Capability,
Output Range = 0 V to 2 × VREF
Rev. C | Page 14 of 33
30
12507-134
0
12507-112
NSD (nV/√Hz)
0
Figure 26. DAC Output Sink and Source Capability,
Output Range = 0 V to VREF
FULL-SCALE
3/4 SCALE
MID-SCALE
1/4 SCALE
ZERO SCALE
2000
–10
LOAD CURRENT (mA)
Figure 24. DAC 1/f Noise with Internal Reference
2500
ZERO SCALE
–20
12507-133
0
12507-110
–200
Data Sheet
AD5593R
20
2.5005
15
2.5003
5
VREF (V)
VOUT (µV p-p)
10
0
–5
2.5001
2.4999
–10
2.4997
0
2
4
6
8
10
TIME (Seconds)
Figure 28. Internal Reference 1/f Noise
1000
600
400
200
1k
10k
100k
FREQUENCY (Hz)
1M
12507-113
NSD (nV/√Hz)
800
100
3.0
3.3
3.6
3.9
4.2
4.5
4.8
VDD (V)
Figure 30. Reference Line Regulation
1200
0
10
2.4995
2.7
Figure 29. Reference Noise Spectral Density
Rev. C | Page 15 of 33
5.1
5.4
12507-200
–20
12507-111
–15
AD5593R
Data Sheet
TERMINOLOGY
ADC Integral Nonlinearity (INL)
For the ADC, INL is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The end points of the transfer function are zero scale, a point
that is 1 LSB below the first code transition, and full scale, a
point that is 1 LSB above the last code transition.
ADC Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD5593R, it is defined as
ADC Differential Nonlinearity (DNL)
For the ADC, DNL is the difference between the measured and the
ideal 1 LSB change between any two adjacent codes in the ADC.
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Offset Error
Offset error is the deviation of the first code transition (00 …
000) to (00 … 001) from the ideal, that is, AGND + 1 LSB.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Gain Error
Gain error is the deviation of the last code transition (111 …
110) to (111 … 111) from the ideal (that is, VREF − 1 LSB) after
the offset error has been adjusted out.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of
crosstalk between channels. It is measured by applying a fullscale 5 kHz sine wave signal to all nonselected ADC input
channels and determining how much that signal is attenuated in
the selected channel. This specification is the worst case across
all ADC channels for the AD5593R.
ADC Power Supply Rejection Ratio (PSRR)
For the ADC, variations in power supply affect the full-scale
transition, but not the converter linearity. Power supply rejection is
the maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
Track-and-Hold Acquisition Time
The track-and-hold amplifier goes into track mode when the
ADC sequence register has been written to. The track and hold
amplifier goes into hold mode when the conversion starts (see
Figure 37). Track-and-hold acquisition time is the minimum time
required for the track-and-hold amplifier to remain in track
mode for its output to reach and settle to within ±1 LSB of the
applied input signal, given a step change to the input signal.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal to (noise + distortion) at
the output of the analog-to-digital converter. The signal is the
rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2),
excluding dc. The ratio is dependent on the number of quantization
levels in the digitization process; the more levels, the smaller the
quantization noise. The theoretical SINAD for an ideal N-bit
converter with a sine wave input is given by
Signal-to-(Noise + Distortion) (dB) = 6.02N + 1.76
Thus, for a 12-bit converter, this is 74 dB.
THD ( dB ) = 20 × log
V 2 +V3 +V4 +V5 +V6
2
2
2
2
2
V1
DAC Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 13.
DAC Differential Nonlinearity (DNL)
For the DAC, differential nonlinearity is the difference between
the measured change and the ideal 1 LSB change between any
two adjacent codes. A specified differential nonlinearity of ±1
LSB maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 14.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x000) is loaded to the DAC register. Ideally, the output is
0 V. The zero code error is always positive in the AD5593R
because the output of the DAC cannot go below 0 V due to a
combination of the offset errors in the DAC and the output
amplifier. Zero code error is expressed in mV.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error can be negative or positive.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Rev. C | Page 16 of 33
Data Sheet
AD5593R
DAC DC Power Supply Rejection Ratio (PSRR)
For the DAC, PSRR indicates how the output of the DAC is
affected by changes in the supply voltage. PSRR is the ratio of
the change in VOUT to a change in VDD for full-scale output of
the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is
varied by ±10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge of
SDA that generates the stop condition.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FF to 0x800) (see Figure 16 and
Figure 17).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Noise Spectral Density (NSD)
NSD is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. A plot
of noise spectral density is shown in Figure 25.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC kept
at midscale. It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
first measured by loading one of the input registers with a fullscale code change (all 0s to all 1s and vice versa). Then it is
measured by executing a software LDAC and monitoring the
output of the DAC whose digital code was not changed. The area of
the glitch is expressed in nV-sec.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by loading
the attack channel with a full-scale code change (all 0s to all 1s
and vice versa), using the write to and update commands while
monitoring the output of the victim channel that is at midscale.
The energy of the glitch is expressed in nV-sec.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this finite bandwidth. A
sine wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying bandwidth is the
frequency at which the output amplitude falls to 3 dB below the
input.
DAC Total Harmonic Distortion (THD)
For the DAC, THD is the difference between an ideal sine wave
and its attenuated version using the DAC. The sine wave is used
as the reference for the DAC, and the THD is a measurement of
the harmonics present on the DAC output. It is measured in dB.
Voltage Reference Temperature Coefficient (TC)
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The voltage
reference TC is calculated using the box method, which defines
the TC as the maximum change in the reference output over a
given temperature range expressed in ppm/°C, as follows:
 VREF(MAX) − VREF(MIN) 
 × 10 6
TC = 
 VREF(NOM) × Temp Range 


where:
VREF(MAX) is the maximum reference output measured over the
total temperature range.
VREF(MIN) is the minimum reference output measured over the
total temperature range.
VREF(NOM) is the nominal reference output voltage, 2.5 V.
Temp Range is the specified temperature range of −40°C to
+105°C.
Rev. C | Page 17 of 33
AD5593R
Data Sheet
THEORY OF OPERATION
The AD5593R is an 8-channel, configurable analog and digital
I/O port. The AD5593R has eight pins that can be independently
configured as a 12-bit DAC output channel, a 12-bit ADC input
channel, a digital input pin, or a digital output pin.
R
R
The function of each pin is determined by programming the
ADC, DAC, or GPIO configuration registers as appropriate.
R
DAC SECTION
TO OUTPUT
AMPLIFIER
The AD5593R contains eight 12-bit DACs. Each DAC consists
of a string of resistors followed by an output buffer amplifier.
Figure 31 shows a block diagram of the DAC architecture.
R
VREF
REF (+)
OUTPUT
AMPLIFIER
GND
12507-012
REF (–)
R
I/Ox
12507-011
DAC REGISTER
RESISTOR
STRING
Figure 32. Resistor String
DAC Output Buffer
Figure 31. DAC Channel Architecture Block Diagram
The DAC channels share a single DAC range bit (see Bit D4 in
Table 13) that sets the output range to 0 V to VREF or 0 V to 2 ×
VREF. Because the range bit is shared by all channels, it is not
possible to set different output ranges on a per channel basis.
The input coding to the DAC is straight binary. Therefore, the
ideal output voltage is given by
D
VOUT = G × VREF ×  N 
2 
where:
G = 1 for an output range of 0 V to VREF or G = 2 for an output
range of 0 V to 2 × VREF.
VREF is the voltage on the VREF pin.
D is the decimal equivalent of the binary code (0 to 4095) that is
loaded to the DAC register.
N = 12.
Resistor String
The simplified segmented resistor string DAC structure is
shown in Figure 32. The code loaded to the DAC register
determines the switch on the string that is connected to the
output buffer.
Because each resistance in the string has the same value, R, the
string DAC is guaranteed monotonic.
The output buffer is designed as an input/output rail-to-rail
buffer. The output buffer can drive 2 nF capacitance with a 1 kΩ
resistor in parallel. The slew rate is 1.25 V/µs with a ¼ to ¾
scale settling time of 6 µs. By default, the DAC outputs update
directly after data has been written to the input register. The
LDAC register delays the updates until additional channels have
been written to if required. See the LDAC Mode Operation
section for more information.
ADC SECTION
The ADC section is a fast, 12-bit, single-supply ADC with a
conversion time of 2 µs. The ADC is preceded by a multiplexer
that switches selected I/O pins to the ADC. A sequencer is
included to switch the multiplexer to the next selected channel
automatically. Channels are selected for conversion by writing
to the ADC sequence register. When the write to the ADC
sequence register has completed, the first channel in the
conversion sequence is put into track mode. Each channel can
track the input signal for a minimum of 500 ns. The conversion is
initiated on the rising edge of the clock for the acknowledge
(ACK) that occurs after the slave address (see Figure 37).
Each conversion takes 2 µs. The ADC has a range bit (ADC
range select in the general-purpose control register, see Bit D5 in
Table 13) that sets the input range as 0 V to VREF or 0 V to 2 ×
VREF. All input channels share the same range. The output
coding of the ADC is straight binary. It is possible to set each
I/Ox pin as both a DAC and an ADC. In this case, the primary
function is that of the DAC. If the pin is selected for inclusion in
an ADC conversion sequence, the voltage on the pin is converted
and made available via the serial interface. This allows the DAC
voltage to be monitored.
Rev. C | Page 18 of 33
Data Sheet
AD5593R
Calculating ADC Input Current
Calculate the input current for buffered mode as follows:
The current flowing into the I/Ox pins configured as ADC inputs
varies with sampling rate (fS), the voltage difference between
successive channels (VDIFF), and whether buffered or unbuffered
mode is used. Figure 33 shows a simplified version of the ADC
input structure. When a new channel is selected for conversion,
5.8 pF must be charged to or discharged from the voltage that
on the previously selected channel. The time required for the
charge or discharge depends on the voltage difference between
the two channels. This dependence affects the input impedance
of the multiplexer and, therefore, the input current flowing into
the I/Ox pins.
fS × C × VDIFF + 1 nA
where:
fS is the ADC sample rate in Hz.
C is the sampling capacitance in farads.
VDIFF is the voltage change between successive channels.
Calculate the input current for buffered mode as follows:
fS × C × VDIFF
where 1 nA is the dc leakage current associated with unbuffered
mode.
The input current for the ADC in buffered mode, where
I/O0 = 0.5 V, I/O1 = 2 V, and fS = 10 kHz, is as follows:
In buffered mode, Switch S1 is open and Switch S2 is closed. In
buffered mode, the U1 buffer directly drives the 23.1 pF capacitor
and the charging time of the capacitors is negligible. In unbuffered
mode, Switch S1 is closed and Switch S2 is closed. In unbuffered
mode, the 23.1 pF capacitor must be charged from the I/Ox
pins; this charging contributes to the input current. For
applications where the ADC input current is too high, an external
input buffer may be required. The choice of buffer is a function
of the particular application.
(10,000 × 5.8 × 10−12 × 1.5) + 1 nA = 88 nA
Under the same conditions, the ADC input current in unbuffered
mode is as follows:
(10,000 × 28.9 × 10−12 × 1.5) = 433.5 nA
S1
MUX
I/O0
U1
300Ω
S3
CONTROL
LOGIC
23.1pF
S4
COMPARATOR
Figure 33. ADC Input Structure
Rev. C | Page 19 of 33
12507-033
I/O7
S2
5.8pF
AD5593R
Data Sheet
GPIO SECTION
Each of the eight I/Ox pins can be configured as a generalpurpose digital input or output pin by programming the GPIO
control register. When an I/Ox pin is configured as an output,
the pin can be set high or low by programming the GPIO write
data register. Logic levels for general-purpose outputs are relative
to VDD and GND. When an I/Ox pin is configured as an input, its
status can be determined by reading the GPIO read configuration
register. When an I/Ox pin is set as an output, it is possible to
read its status by also setting it as an input pin. When reading
the status of the I/Ox pins set as inputs the status of an I/Ox pin
set as both and input and output pin is also returned.
INTERNAL REFERENCE
The AD5593R contains an on-chip 2.5 V reference. The
reference is powered down by default and is enabled by setting
Bit D9 in the power-down/reference control register to 1. When
the on-chip reference is powered up, the reference voltage
appears on the VREF pin and may be used as a reference source
for other components. When the internal reference is used, it is
recommended to decouple VREF to GND using a 100 nF
capacitor. It is recommended that the internal reference be
buffered before using it elsewhere in the system. When the
reference is powered down, an external reference must be
connected to VREF. Suitable external reference sources for the
AD5593R include the AD780, AD1582, ADR431, REF193, and
ADR391.
RESET FUNCTION
The AD5593R has an asynchronous RESET pin. For normal
operation, RESET is tied high. A falling edge on RESET resets
all registers to their default values and reconfigures the I/O pins
to their default values (85 kΩ pull-down resistor to GND). The
reset function takes 250 µs maximum; do not write new data to
the AD5593R during this time. The AD5593R has a software
reset that performs the same function as the RESET pin. The
reset function is activated by writing 0x0F to the pointer byte
and 0x0D and 0xAC to the most significant and least significant
bytes, respectively.
TEMPERATURE INDICATOR
The AD5593R contains an integrated temperature indicator that
can be read to provide an estimation of the die temperature.
This can be used in fault detection where a sudden rise in die
temperature may indicate a fault condition, such as a shorted
output. Temperature readback is enabled by setting Bit D8 in
the ADC sequence register. The temperature result is then
added to the ADC sequence. The temperature result has an
address of 0b1000 and care must be taken that this result is not
confused with the readback from DAC0. The temperature
conversion takes 5 µs with the ADC buffer enabled and 20 µs
when the buffer is disabled. Calculate the temperature using the
following formulae:
For ADC gain = 1,
Temperature (°C) = 25 +
ADC Code − 820
2.654
For ADC gain = 2,
Temperature (°C) = 25 +
ADC Code − 410
2.654
The range of codes returned by the ADC when reading from
the temperature indicator is approximately 645 to 1035,
corresponding to a temperature between −40°C to +105°C. The
accuracy of the temperature indicator is typically 3°C when
averaged over five samples.
Rev. C | Page 20 of 33
Data Sheet
AD5593R
SERIAL INTERFACE
The AD5593R has a 2-wire, I2C-compatible serial interface
(refer to The I2C -Bus Specification, Version 2.1, January 2000).
The AD5593R is connected to an I2C bus as a slave device
under the control of a master device. See Figure 2 for a timing
diagram of a typical write sequence. The AD5593R supports
standard mode (100 kHz) and fast mode (400 kHz). Support is
not provided for 10-bit addressing and general call addressing.
The AD5593R has a 7-bit slave address; its six MSBs are set to
001000. The LSB is set by the state of the A0 address pin, which
determines the state of the A0 bit. The facility to change the
logic level of the A0 pin before a read or write operation allows
the user to incorporate multiple AD5593R devices on one bus.
WRITE OPERATION
When writing to the AD5593R, the user must begin with a start
command followed by an address byte R/W = 0), after which
the AD5593R acknowledges that it is prepared to receive data
by pulling SDA low. The AD5593R requires three bytes of data.
The first byte is the pointer byte. This byte contains information
defining the type of operation that is required of the AD5593R,
such as configuring the I/O pins and writing to a DAC. The pointer
byte is followed by the most significant byte and the least
significant byte, as shown in Figure 34. After these data bytes
are acknowledged by the AD5593R, a stop condition follows.
READ OPERATION
The 2-wire serial bus protocol operates as follows: the master
initiates data transfer by establishing a start condition when a
high-to-low transition on the SDA line occurs while SCL is
high. The following byte is the address byte, which consists of
the 7-bit slave address. The slave address corresponding to the
transmitted address responds by pulling SDA low during the
ninth clock pulse (this is termed the acknowledge bit). At this
stage, all other devices on the bus remain idle while the selected
device waits for data to be written to or read from its shift register.
When reading data back from the AD5593R, the user begins
with a start command followed by an address byte (R/W = 0),
after which the DAC acknowledges that it is prepared to transmit
data by pulling SDA low. The pointer byte is then written to select
what is to be read back. A repeat start or a new I2C transmission
can then follow to read two bytes of data from the AD5593R.
Both bytes are acknowledged by the master, as shown in Figure 35.
It is also possible to perform consecutive readbacks without
having to provide interim start and stop conditions or slave
addresses. This method can be used to read blocks of
conversions from the ADC, as shown in Figure 37.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
When all data bits have been read or written, a stop condition is
established.
In write mode, the master pulls the SDA line high during the
10th clock pulse to establish a stop condition. In read mode, the
master issues a no acknowledge for the ninth clock pulse (that
is, the SDA line remains high). The master brings the SDA line
low before the 10th clock pulse and then high during the 10th
clock pulse to establish a stop condition.
1
9
1
9
SCL
0
SDA
0
START BY
MASTER
1
0
0
0
A0
D7
R/W
D6
D5
ACK. BY
AD5593R
FRAME 1
SLAVE ADDRESS
1
9
D4
D3
D2
D1
D0
ACK. BY
AD5593R
FRAME 2
POINTER BYTE
1
9
SCL
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
FRAME 3
MOST SIGNIFICANT
DATA BYTE
DB8
DB7
DB6
ACK. BY
AD5593R
Figure 34. 4-Byte I2C Write
Rev. C | Page 21 of 33
DB5
DB4
DB3
DB2
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
DB1
DB0
ACK. BY
AD5593R
STOP BY
MASTER
12507-013
SDA
(CONTINUED)
AD5593R
Data Sheet
1
9
1
9
SCL
0
SDA
0
1
0
START BY
MASTER
0
0
A0
W
D7
D6
D5
ACK. BY
AD5593R
FRAME 1
SLAVE ADDRESS
1
D4
D3
D2
D1
D0
ACK. BY
AD5593R
FRAME 2
POINTER BYTE
9
1
STOP BY
MASTER
9
SCL
(CONTINUED)
SDA
(CONTINUED)
0
0
1
0
0
0
A0
START BY
MASTER
R
D15
D14
D13
ACK. BY
AD5593R
D11
D10
D9
D8
ACK. BY
MASTER
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 1
SLAVE ADDRESS
1
D12
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
NACK. BY
MASTER
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
STOP BY
MASTER
12507-014
SDA
(CONTINUED)
Figure 35. Read One 16-Bit Word
1
9
1
9
SCL
0
SDA
0
1
0
0
0
A0
D7
W
START BY
MASTER
D6
D5
D4
D3
D2
D1
D0
ACK. BY
AD5593R
ACK. BY
AD5593R
FRAME 1
SLAVE ADDRESS
FRAME 2
POINTER BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
0
0
1
0
0
0
A0
R
REPEAT START
BY MASTER
D15
ACK. BY
AD5593R
FRAME 1
SLAVE ADDRESS
1
D14
D13
D12
D11
D10
FRAME 2
MOST SIGNIFICANT
DATA BYTE
D9
D8
ACK. BY
MASTER
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
D1
D0
NACK. BY
MASTER
STOP BY
MASTER
Figure 36. Read One 16-Bit Word, Maintain Control of the Bus
Rev. C | Page 22 of 33
12507-015
SDA
(CONTINUED)
Data Sheet
AD5593R
1
9
1
9
SCL
0
SDA
0
1
0
0
0
A0
W
START BY
MASTER
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
AD5593R
ACK. BY
AD5593R
FRAME 1
SLAVE ADDRESS
FRAME 2
POINTER BYTE
START OF ADC
CONVERSION1
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
0
0
1
0
0
0
A0
R
D15
D14
D13
ACK. BY
AD5593R
REPEAT START
BY MASTER
9
D11
D10
D9
D8
ACK. BY
MASTER
FRAME 2
MOST SIGNIFICANT
DATA BYTE
FRAME 1
SLAVE ADDRESS
1
D12
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D15
D0
D14
ACK. BY
MASTER
FRAME 3
LEAST SIGNIFICANT
DATA BYTE
1
D13
D12
D11
D10
FRAME 4
MOST SIGNIFICANT
DATA BYTE
D9
D8
ACK. BY
MASTER
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER
FRAME 5
LEAST SIGNIFICANT
DATA BYTE
1ONLY
STOP BY
MASTER
12507-016
SDA
(CONTINUED)
APPLICABLE IF AN ADC SEQUENCE HAS BEEN SELECTED.
Figure 37. I2C Block Read
POINTER BYTE
CONTROL REGISTERS
The pointer byte contains eight bits. Bits[D7:D4] are mode bits
that select the operation to be executed. The data contained in
Bits[D3:D0] depend on the operation required. Table 9 shows
the configuration of the pointer byte. When Bits[D7:D4] are
0b0000, the mode dependent bits (Bits[D3:D0]) select a control
register to write data to. The data written to a control register is
contained in the MSB and LSB as shown in Figure 34. The mode
dependent data bits also select which DAC is updated during a
DAC write operation and which register is selected for readback.
Table 11 shows the control register map for the AD5593R. The
control registers configure the I/O pins and set various
operating parameters in the AD5593R, such as enabling the
reference, selecting the LDAC mode function, or selecting
power-down modes. The control registers are written to using
the 4-byte I2C write sequence shown in Figure 34. To write to a
control register, the mode bits (Bits[D7:D4]) of the pointer byte
are zeros. The mode dependent data bits (Bits[D3:D0]) of the
pointer byte select which control register is to be accessed. The
data to be written to the control register is contained in the
most significant and least significant data bytes. These contain a
total of 16 bits and are shown as D15 to D0 in Table 12 and
Table 13. The contents of the control registers can be read back
using the read sequence shown in Figure 35 or Figure 36.
Table 9. Pointer Byte Configuration
D7
D6
D5
Mode bits
D4
D3
D2
D1
D0
Mode dependent data bits
Table 10. Mode Bits
D7
0
0
0
0
0
0
D6
0
0
1
1
1
1
D5
0
0
0
0
1
1
D4
0
1
0
1
0
1
Description
Configuration mode
DAC write
ADC readback
DAC readback
GPIO readback
Register readback
Rev. C | Page 23 of 33
AD5593R
Data Sheet
GENERAL-PURPOSE CONTROL REGISTER
The general-purpose control register enables or disables certain
functions associated with the DAC, ADC, and I/O pin configuration (see Table 13). The register sets the output range of the
DAC and input range of the ADC, which sets their transfer
functions, enables/disables the ADC buffer, and enables the
precharge function (see the ADC Section for more details). The
register is also used to lock the I/O pin configuration to prevent
accidental change. When Bit D7 is set to 1, writes to the
configuration registers are ignored.
Table 11. Control Registers
Pointer Byte
[D7:D0]
00000000
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
Register Name
NOP
ADC sequence register
General-purpose control register
ADC pin configuration
DAC pin configuration
Pull-down configuration
LDAC mode
GPIO write configuration
GPIO write data
GPIO read configuration
Power-down/reference control
Open-drain configuration
Three-state pins
Reserved
Software reset
Description
No operation
Selects ADCs for conversion
DAC and ADC control register
Selects which pins are ADC inputs
Selects which pins are DAC outputs
Selects which pins have an 85 kΩ pull-down resistor to GND
Selects the operation of the load DAC
Selects which pins are general-purpose outputs
Writes data to general-purpose outputs
Selects which pins are general-purpose inputs
Powers down the DACs and enables/disables the reference
Selects open-drain or push-pull for general-purpose outputs
Selects which pins are three-stated
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x00FF
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Resets the AD5593R
0x0000
Table 12. General-Purpose Control Register
MSB
D15
D14
D13 D12
Reserved
D11
D10
D9
ADC buffer
precharge
D8
ADC buffer
enable
D7
Lock
configuration
D6
Write all
DACs
D5
ADC
range
select
D4
DAC
range
select
D3
D2 D1
Reserved
LSB
D0
Table 13. General-Purpose Control Register Descriptions
Bits
D15 to D10
D9
D8
D7
D6
D5
D4
D3 to D0
Description
Reserved. Set these bits to 0.
ADC buffer precharge.
0: the ADC buffer is not used to precharge the ADC. If the ADC buffer is enabled, it is always powered up (default).
1: the ADC buffer is used to precharge the ADC. If the ADC buffer is enabled, it is powered up while the conversion takes
place and then powered down until the next conversion takes place.
ADC buffer enable.
0: the ADC buffer is disabled (default).
1: the ADC buffer is enabled.
Lock configuration.
0: the contents of the I/O pin configuration registers can be changed (default).
1: the contents of the I/O pin configuration registers cannot be changed.
Write all DACs.
0: for future DAC writes, the DAC address bits determine which DAC is written to (default).
1: for future DAC writes, the DAC address bits are ignored and all channels configured as DACs are updated with the same data.
ADC range select.
0: the ADC range is 0 to VREF (default).
1: the ADC range is 0 to 2 × VREF.
DAC range select.
0: the DAC range is 0 to VREF (default).
1: the DAC range is 0 to 2 × VREF.
Reserved; set these bits to 0.
Rev. C | Page 24 of 33
Data Sheet
AD5593R
CONFIGURING THE AD5593R
The exceptions to this rule are that an I/Ox pin can be set as
both a DAC and ADC or as a digital input and output. When an
I/Ox pin is configured as a DAC and ADC, the primary
function is as a DAC and the ADC can be used to measure the
voltage being provided by the DAC. This feature can be used to
monitor the output voltage to detect short circuits or overload
conditions. Figure 38 shows an example of how to configure
I/O1 and I/O7 as DACs. When a pin is configured as both a
general-purpose input and output, the primary function is as an
output pin. This configuration allows the status of the output pin
to be determined by reading the GPIO read configuration
register.
The AD5593R I/O pins are configured by writing to a series of
pin configuration registers. The control registers are accessed
when Bits[D7:D4] are 0b0000. Bits[D3:D0] determine which
register is accessed as shown in Table 11.
On power-up, the I/O pins are configured as 85 kΩ resistors
connected to GND. The I/O channels of the AD5593R can be
configured to operate as DAC outputs, ADC inputs, digital
outputs, digital inputs, three-state, or connected to GND with
85 kΩ pull-down resistors. When configured as digital outputs,
the pins have the additional option of being configured as
push/pull or open-drain.
The general-purpose control register contains a lock
configuration bit. When the lock configuration bit is set to 1,
any writes to the pin configuration registers are ignored, thus
preventing the function of the I/O pins from being changed.
The I/O channels are configured by writing to the appropriate
configuration registers, as shown in Table 11. To assign a
particular function for an I/O channel, write to the appropriate
register and set the corresponding bit to 1. For example, setting
Bit D0 in the DAC configuration register configures I/O0 as a
DAC. In the event that the bit for an I/O channel is set in
multiple configuration registers, the I/O channel adopts the
function dictated by the last write operation.
The I/O pins can be reconfigured any time when the AD5593R
is in an idle state, that is, no ADC conversions are taking place
and no registers are being read back. The lock configuration bit
must also be set to 0.
Table 14. I/O Pin Configuration Registers 1
D7
I/O7
D5
I/O5
D4
I/O4
D3
I/O3
D2
I/O2
D1
I/O1
D0
I/O0
Setting an I/O pin configuration bit to 1 after writing to a control register enables that function on the selected I/O pin.
MOST SIGNIFICANT
DATA BYTE
POINTER BYTE
S
SLAVE ADDRESS + W
A
0b00000101
A
0b00000000
LEAST SIGNIFICANT
DATA BYTE
A
0b10000010
A
P
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE
Figure 38. Configuring I/O1 and I/O7 as DACs
Rev. C | Page 25 of 33
12507-017
1
D6
I/O6
AD5593R
Data Sheet
DAC WRITE OPERATION
DAC READBACK
Data is written to a DAC when the mode bits (Bits[D7:D4]) of
the pointer byte are 0b0001 (see Table 10). Bits[D2:D0]
determine which DAC is addressed. Data to be written to the
DAC is contained in the MSB and LSB, as shown in Table 17.
Data is written to the selected DAC input register. Data written
to the input register can be automatically copied to the DAC
register, if required. Data is transferred to the DAC register
based on the setting of the LDAC mode register (see Table 15).
The input register of each DAC can be read back via the I2C
interface. This can be useful to confirm that the data was received
correctly before writing to the LDAC register or simply checking
what value was last loaded to a DAC. Data can be read back
from a DAC only when no ADC conversion sequence is taking
place. A DAC input register can be read back using the sequence
shown in Figure 35 or Figure 36. The mode bits, Bits[D3:D0], of
the pointer register, 0b0101, select which DAC input register is
to be read back. When the DAC register is read back, the MSB
of the most significant data byte is a 1 to indicate that the result
is a DAC register. The next three bits (Bits[D14:D12]) contain
the DAC register address (see Table 17) and Bits[D11:D0]
contain the DAC register value. Figure 39 shows an example of
reading the input register of DAC2.
LDAC Mode Operation
The transfer of data from an input register to a DAC register is
controlled by Bit D1 and Bit D0 of the readback and LDAC
mode register (pointer byte = 0b00000111). When the LDAC
mode bits (Bit D1 and Bit D0) are set to 00, new data is
automatically transferred from the input register to the DAC
register and the analog output updates. When the LDAC mode
bits are set to 01, data remains in the input register. This allows
writes to input registers without affecting the analog outputs.
After loading the input registers with the desired values and
setting the LDAC mode bits to 10, the values in the input
registers transfer to the DAC registers and the analog outputs
update simultaneously. The LDAC mode bits then revert to 01.
Table 16. DAC Pointer Byte Address
DAC Address
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
Table 15. LDAC Mode Register
D1
0
D0
0
0
1
1
0
1
1
LDAC Mode
Data written to an input register is immediately
copied to a DAC register and the DAC output
updates (default).
Data written to an input register is not copied to a
DAC register. The DAC output is not updated.
Data in the input registers is copied to the
corresponding DAC registers. When the data has
been transferred, the DAC outputs are updated
simultaneously.
Reserved.
D7
D6
D5
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D3
0
0
0
0
0
0
0
0
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
Table 17. DAC Data Register
D14
D13
D12
DAC address
D11
D10
D9
D8
D7
D6
D5
12-bit DAC data
D4
D3
D2
D1
POINTER BYTE
S
SLAVE ADDRESS + W
A
0b01010010
DACADDRESS AND
4 MSBs
0b1010XXX
A
RS
SLAVE ADDRESS + R
DAC LSBs
A
0bXXXXXXX
A
P
Figure 39. DAC Input Register Readback
Rev. C | Page 26 of 33
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE
RS = REPEAT START
A
12507-018
MSB
D15
1
LSB
D0
Data Sheet
AD5593R
ADC OPERATION
sequence. If the REP bit is clear, the ADC clocks out the last
result on subsequent I2C reads. When ADC data is clocked out
by the serial interface, D15 = 0 to indicate that the result is ADC
data. D14 to D12 contain a 3-bit address to indicate which ADC
the data is coming from, and D11 to D0 contain the 12-bit ADC
result (see Table 20).
The ADC channels of the AD5593R operate as a traditional
multichannel ADC, where each serial transfer selects the next
channel for conversion. The user must write to the ADC
sequence register (see Table 19) to select the input channels to
be included in the conversion sequence before initiating any
conversions. This is done using the I2C write sequence shown in
Figure 34. When writing to the ADC sequence register, select
which channels are to be converted in sequence. The user can also
set the REP bit to have the ADC repeat conversions in the
sequence.
Figure 40 shows how to configure the AD5593R to perform
ADC conversions. In Step 1, I/O7 and I/O0 are configured as
ADCs. Step 2 writes to the ADC configuration register, sets the
REP bit, and selects ADC7 and ADC0 for inclusion in the
conversion sequence. Step 3 selects the ADCs for reading and
Step 4 begins reading the ADC results. The conversions are
repeated until a stop condition is given by the controller.
When the sequence register has been written to, the ADC begins to
track the first channel in the sequence. ADC data can be read
from the AD5593R using any of the three read operations shown
in Figure 35, Figure 36, and Figure 37, with the I2C block read
(Figure 37) being the most efficient.
The ADC sequence can be changed by writing the new
sequence to the ADC sequence register when conversions are
not taking place. When a new sequence is written, any channels
remaining to be converted from the earlier sequence are
ignored and the ADC starts converting the first channel of the
new sequence.
If more than one channel is selected in the ADC sequence
register, the ADC converts all selected channels sequentially in
ascending order. Conversion is started by the rising edge of SCL
at the acknowledge (ACK) preceding the MSB (see Figure 37).
To stop the ADC conversion sequence, clear the REP, TEMP,
and ADC7 to ADC0 bits in the ADC sequence register to 0.
If the REP bit is set after all of the selected channels in the
sequence register have been converted, the ADC repeats the
Table 18. ADC Sequence Register
MSB
D15
D14
D13
D12
Reserved
D11
D10
D9
REP
D8
TEMP
D7
ADC7
D6
ADC6
D5
ADC5
D4
ADC4
D3
ADC3
D2
ADC2
D1
ADC1
LSB
D0
ADC0
Table 19. ADC Sequence Register Descriptions
Bits
D15 to D10
D9
D8
D7 to D0
Description
Reserved; set this bit to 0
REP: ADC sequence repeat
0 = sequence repetition disabled (default)
1 = sequence repetition enabled
TEMP: include temperature indicator in ADC sequence
0 = disable temperature indicator readback (default)
1 = enable temperature indicator readback
Setting these bits to 1 includes the appropriate ADC in the conversion sequence; by default no channels are included
Table 20. ADC Data Register
MSB
D15
0
D14
D13
D12
ADC address
D11
D10
D9
D8
D7
Rev. C | Page 27 of 33
D6
D5
12-bit ADC data
D4
D3
D2
D1
LSB
D0
AD5593R
Data Sheet
LEAST SIGNIFICANT
DATA BYTE
STEP1
S
SLAVE ADDRESS + W
A
0b00000100
A
0b00000000
A
0b10000001
A P
STEP2
S
SLAVE ADDRESS + W
A
0b00000010
A
0b00000010
A
0b10000001
A P
STEP3
S
SLAVE ADDRESS + W
A
0b01000000
A P
STEP4
S
SLAVE ADDRESS + R
A
ADC7 RESULT (MSB)
A
ADC7 RESULT (LSB)
A
ADC0 RESULT (MSB)
A
ADC0 RESULT (LSB)
A
ADC7 RESULT (MSB)
A
ADC0 RESULT (MSB)
A
ADC0 RESULT (LSB)
A P
Figure 40. Configuring the ADC for Conversion
Rev. C | Page 28 of 33
ADC7 RESULT (LSB)
S = START CONDITION
P = STOP CONDITION
A = ACKNOWLEDGE
A
12507-019
MOST SIGNIFICANT
DATA BYTE
POINTER BYTE
Data Sheet
AD5593R
GPIO OPERATION
Table 23. GPIO Write Data Register Descriptions
Each of the I/Ox pins of the AD5593R can be configured to
operate as a general-purpose, digital input or output pin. The
function of the pins is determined by writing to the appropriate
bit in the GPIO read configuration and GPIO write configuration
registers using the 4-byte I2C write shown in Figure 34.
Bits
D15 to D8
D7 to D0
Setting Pins as Outputs
Setting Pins as Inputs
To set a pin as a general-purpose output, set the appropriate bit
in the GPIO write configuration register to 1. For example,
setting Bit D0 to 1 enables I/O0 as a general-purpose output.
To set an I/Ox pin as a general-purpose input, set the
appropriate bit in the GPIO read configuration register to 1. For
example, setting Bit D0 to 1 enables I/O0 as a general-purpose
input. To read the state of general-purpose inputs, set the
pointer byte to 0b01100000 (see Table 10 ) using any of the read
operations shown in Figure 35, Figure 36, and Figure 37. The
status of any I/O pin set as a general-purpose input appears in
the appropriate bit location in the least significant data byte.
The outputs can be independently configured as push/pull or
open-drain outputs. When in push/pull configuration, the
output is driven to VDD or GND as determined by the data in
the GPIO write data register. When in open-drain configuration,
the output is driven to GND when a data bit in the GPIO write
data register sets the pin low. When the pin is set high, the
output is not driven and must be pulled high by an external
resistor. This allows multiple output pins to be tied together. If
all the pins are normally high, it allows one pin to pull down the
others. This is commonly used where multiple pins are used to
trigger an alarm or interrupt pin. The state of the output pin is
controlled by setting or clearing the bits in the GPIO write data
register (pointer byte = 0b00001001). A data bit is ignored if it is
written to a location that is not configured as an output.
Three-State Pins
The I/Ox pins can be set to three-state by writing to the threestate configuration register (pointer byte = 0b00001101) as
shown in Table 24.
Table 24. Three-State Configuration Register Descriptions
Bits
D15 to D8
D7 to D0
Table 21. GPIO Write Configuration Register Descriptions
Bits
D15 to D8
D7 to D0
Description
Reserved; set these bits to 0
Select pins as GPIO outputs
D[7:0] = 1: I/O[7:0] is a general-purpose output pin
D[7:0] = 0: I/O[7:0] function is determined by the
pin configuration registers (default)
Table 22. GPIO Open-Drain Control Register Descriptions
Bits
D15 to D8
D7 to D0
Description
Reserved; set these bits to 0
Sets output pins as open-drain
D[7:0] = 1: I/O[7:0] is an open-drain output pin
D[7:0] = 0: I/O[7:0] is a push/pull output pin
(default)
Description
Reserved; set these bits to 0
Sets the state of a GPIO output
D[7:0] = 1: I/O[7:0] is a Logic 1
D[7:0] = 0: I/O[7:0] is a Logic 0 (default)
Description
Reserved; set these bits to 0
Set pins as three-state outputs
D[7:0] = 1: I/O[7:0] is a three-state output pin
D[7:0] = 0: I/O[7:0] function is determined by the
pin configuration registers (default)
85 kΩ Pull-Down Pins
The I/Ox pins can be connected to GND via a pull-down
resistor (85 kΩ) by setting the appropriate bits in the pull-down
configuration register (pointer byte = 00000110) as shown in
Table 25.
Table 25. Pull-Down Configuration Register Descriptions
Bits
D15 to D8
D7 to D0
Rev. C | Page 29 of 33
Description
Reserved; set these bits to 0
Set pins as weak pull-down outputs
D[7:0] = 1: I/O[7:0 is connected to GND via an 85 kΩ
pull-down resistor
D[7:0] = 0: I/O[7:0] function is determined by the
pin configuration registers (default)
AD5593R
Data Sheet
POWER-DOWN/REFERENCE CONTROL
RESET FUNCTION
The AD5593R has a power-down/reference control register
(pointer byte = 0b00001011) that reduces the power consumption
when certain functions are not needed. The power-down register
allows any channels set as DACs to be placed in a power-down
state individually. When in power-down, the DAC outputs are
three-stated. When a DAC channel is returned into normal
mode, the DAC output returns to its previous value. The internal
reference and its buffer are powered down by default and are
enabled by setting the EN_REF bit in the power-down register.
The internal reference voltage then appears at the VREF pin.
The AD5593R can be reset to its default conditions by writing
0x0DAC to the reset register (pointer byte = 0b00001111). This
resets all registers to their default values and reconfigures the
I/Ox pins to their default values (85 kΩ pull-down to GND).
The reset function is triggered on the SCL falling edge of the eighth
bit of the least significant byte (DB0 of Frame 4 in Figure 34),
and the AD5593R does not generate an ACK signal for this byte
of data. The AD5593R has a RESET pin that performs the same
function. For normal operation, RESET is tied high. A falling
edge on RESET triggers the reset function. Both the hardware
and the software reset functions take 100 µs maximum and
there must be no activity on the SCL pin of the AD5593R
during this time.
There is no dedicated power-down function for the ADC, but
the ADC is automatically powered down if none of the I/Ox
pins are selected as ADCs. The ADC powers up if a read of the
temperature indicator is initiated. The PD_ALL bit powers down
all the DACs, the reference, its buffer, and the ADC. The
PD_ALL bit also overrides the settings of Bit D9 to Bit D0.
Table 26 shows the power-down register.
Table 26. Power-Down Register
MSB
D15
0
D14
0
D13
0
D12
0
D11
0
D10
PD_ALL
D9
EN_REF
D8
0
D7
PD7
D6
PD6
D5
PD5
D4
PD4
D3
PD3
D2
PD2
D1
PD1
Table 27. LDAC Mode Register Descriptions
Bits
D15 to D11
D10
Bit Name
Reserved
PD_ALL
D9
EN_REF
D7 to D0
PD7 to PD0
Description
Reserved; set these bits to 0
0 = the power-down states of the reference and DACs are determined by D9 and D7 to D0 (default).
1 = the reference, the DACs, and the ADC are powered down.
0 = the reference and its buffer are powered down (default). Set this bit if an external reference is used.
1 = the reference and its buffer are powered up. The reference is available on the VREF pin.
0 = the channel is in normal operating mode (default).
1 = the channel is powered down if it is configured as a DAC.
Rev. C | Page 30 of 33
LSB
D0
PD0
Data Sheet
AD5593R
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
LAYOUT GUIDELINES
Microprocessor interfacing to the AD5593R is via a serial bus using
a standard I2C protocol. The communications channel requires a
2-wire interface consisting of a clock signal and a data signal.
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board (PCB) on
which the AD5593R is mounted must be designed so that the
AD5593R lies on the analog plane.
AD5593R TO ADSP-BF537 INTERFACE
The I2C interface of the AD5593R is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 41 shows the AD5593R connected to the Analog Devices
Blackfin® DSP. The Blackfin has an integrated I2C port that can
be connected directly to the I2C pins of the AD5593R.
AD5593R
SCL
SDA
SCL
SDA
PF8
RESET
12507-164
ADSP-BF537
The AD5593R must have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply, located as close to the package
as possible, ideally right up against the device. The 10 µF capacitors
are the tantalum bead type. The 0.1 µF capacitor must have low
effective series resistance (ESR) and low effective series inductance
(ESI) such as the common ceramic types, which provide a low
impedance path to ground at high frequencies to handle transient
currents due to internal logic switching.
Figure 41. ADSP-BF537 Interface
Rev. C | Page 31 of 33
AD5593R
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 42. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.30
0.25
0.20
0.50
BSC
16
13
12
1
4
9
TOP VIEW
0.80
0.75
0.70
PKG-004132
SEATING
PLANE
0.50
0.40
0.30
8
5
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.152 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-32)
Dimensions shown in millimeters
Rev. C | Page 32 of 33
09-03-2013-A
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
Data Sheet
AD5593R
2.000
1.960 SQ
1.920
3
4
2
1
A
BALL A1
IDENTIFIER
B
1.50
REF
C
TOP VIEW
0.50
BSC
(BALL SIDE DOWN)
BOTTOM VIEW
(BALL SIDE UP)
SIDE VIEW
COPLANARITY
0.05
0.340
0.320
0.300
SEATING
PLANE
0.270
0.240
0.210
10-17-2012-B
0.640
0.595
0.540
D
Figure 44. 16-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5593RBRUZ
AD5593RBRUZ-RL7
AD5593RBCPZ-RL7
AD5593RBCBZ-RL7
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP
16-Ball WLCSP
Package Option
RU-16
RU-16
CP-16-32
CB-16-3
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12507-0-4/17(C)
Rev. C | Page 33 of 33
Branding
DM6