PRELIMINARY CY2XF23 High Performance LVDS Oscillator with Frequency Margining - I2C Control Features Functional Description ■ Low Jitter Crystal Oscillator (XO) The CY2XF23 is a high performance and high frequency Crystal Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed using the I2C Bus serial interface, allowing easy frequency margin testing in applications. ■ Less than 1ps Typical RMS Phase Jitter ■ Differential LVDS Output ■ Output Frequency from 50 MHz to 690 MHz ■ Frequency Margining through I2C Bus ■ Factory Configured or Field Programmable ■ Integrated Phase-Locked Loop (PLL) ■ Pb-Free Package: 5.0 x 3.2 mm LCC ■ Supply Voltage: 3.3V or 2.5V ■ Commercial and Industrial Temperature Ranges The CY2XF23 is available as a factory configured device or as a field programmable device. Logic Block Diagram 4 CRYSTAL OSCILLATOR LOW-NOISE PLL CLK OUTPUT DIVIDER 5 CLK# PROGRAMMABLE CONFIGURATION 1 SDA I 2C INTERFACE 2 SCL Pinouts Figure 1. Pin Diagram - 6 Pin Ceramic LCC SDA 1 6 VDD SCLK 2 5 CLK# VSS 3 4 CLK Table 1. Pin Definitions - 6 Pin Ceramic LCC Pin Name I/O Type Description 1 SDA I/O I2C Serial Data 2 SCLK CMOS Input I2C Serial Clock 4, 5 CLK, CLK# LVDS Output Differential Output Clock 6 VDD Power Supply Voltage: 2.5V or 3.3V 3 VSS Power Ground Cypress Semiconductor Corporation Document Number: 001-53145 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 18, 2009 [+] Feedback PRELIMINARY CY2XF23 Functional Description Configuration Software The CY2XF23 is a phase locked loop (PLL) based high performance clock generator. It uses an internal crystal oscillator as a reference, and outputs one differential LVDS clock. It has an I2C Bus serial interface[1], which is used to change the output frequency. Cypress provides CyberClocks™ Online web-based software that enables users to create data values for shifting into the frequency words. This software is required because the algorithm is too complicated to describe here. The CY2XF23 comes configured for four different frequencies. At power on, the four configurations are transparently loaded into an internal volatile memory which in turn controls the PLL. The user can switch between the four frequencies through the I2C Bus. The user can also configure the CY2XF23 with new output frequencies by shifting new data into the internal memory. The user specifies the output frequency. The software then calculates the bit stream. The bit stream is generic in the sense that it can be shifted into any of the four Frequency Words. This process is repeated for all frequencies of interest. Frequency margining is a common application for this feature. One frequency is used for the standard operating mode of the device, while additional frequencies are available for margin testing, either during product development or in system manufacturing test. Note that all configuration changes made using I2C are temporary and are lost when power is removed from the device. At power on, the device returns to its original state. The configuration for a particular frequency is stored in a 6-byte block of memory, known as a word. The CY2XF23 has four such words, labeled Frequency Word 0 through Frequency Word 3. An additional register byte contains a 2-bit field, which selects one of the four frequency words. By writing to this Select Byte, the user can switch back and forth between the four programmed frequencies. The select byte is always defined to select Frequency Word 0 at power on. When changing the output frequency, the frequency transition is not guaranteed to be smooth. There can be frequency excursions beyond the start frequency and the new frequency. Glitches and runt pulses are possible, and time must be allowed for the PLL to re-lock. I 2C If more than four frequencies are needed, the Bus can be used to change any of the four frequency words. When writing frequency words via I2C, users should not change the currently selected word. Instead, write one of the three unselected words before changing the select byte to select that new word. Figure 2 shows how the frequency words are arranged and selected. The software is located at www.cyberclocksonline.com. Programming Description The CY2XF23 is a programmable device. Before being used in an application, it must be programmed with the output frequencies and other variables described in a later section. Two different device types are available, each with its own programming flow. They are described in the following sections. Field Programmable CY2XF23F Field programmable devices are shipped unprogrammed and must be programmed before being installed on a printed circuit board (PCB). Customers use CyberClocks Online Software to specify the device configuration and generate a JEDEC (extension .jed) programming file. Programming of samples and prototype quantities is available using a Cypress programmer. Third party vendors manufacture programmers for small to large volume applications. Cypress’s value added distribution partners also provide programming services. Field programmable devices are designated with an “F” in the part number. They are intended for quick prototyping and inventory reduction. The CY2XF23 is one time programmable (OTP). Factory Configured CY2XF23 For customers wanting ready-to-use devices, the CY2XF23 is available with no field programming required. All requests are submitted to the local Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, the user receives a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders. Figure 2. Frequency Words Register Address 10h – 15h Frequency Word 0 00 16h – 1Bh Frequency Word 1 01 1Ch – 21h Frequency Word 2 10 22h – 27h Frequency Word 3 11 40h Select Byte Control PLL Sel Bits [1:0] Default = 00 Note 1. The serial interface is I2C Bus compliant, with the following exceptions: SDA input leakage current, SDA input capacitance, SDA and SCLK are clamped to VDD, setup time, and output hold time. Document Number: 001-53145 Rev. *B Page 2 of 11 [+] Feedback CY2XF23 PRELIMINARY Programming Variables Output Frequencies The CY2XF23 is programmed with up to four independent output frequencies, which are then selected using the I2C interface. The device can synthesize frequencies to a resolution of 1 part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. The CY2XF23 has an output frequency range of 50 MHz to 690 MHz, but the range is not continuous. The CY2XF23 cannot generate frequencies in the ranges of 521 MHz to 529 MHz, and 596 MHz to 617 MHz. Industrial Versus Commercial Device Performance Industrial and Commercial devices have different internal crystals. This has a potentially significant impact on performance levels for applications requiring the lowest possible phase noise. CyberClocks Online Software displays expected performance for both options. Table 3. Frequency Words Frequency Word 0 1 2 3 Byte Addresses (hex) 10h to 15h 16h to 1Bh 1Ch to 21h 22h to 27h Table 4. Register 40h: Select Byte 7:2 Default Value Name (binary) 000000 Reserved 1:0 00 Bits Phase Noise Versus Jitter Performance In most cases, the device configuration for optimal phase noise performance is different from the device configuration for optimal cycle to cycle or period jitter. CyberClocks Online Software includes algorithms to optimize performance for either parameter. Table 2. Device Programming Variables Variable Output Frequency 0 Output Frequency 1 Output Frequency 2 Output Frequency 3 Optimization (phase noise or jitter) Temperature range (Commercial or Industrial) Memory Map Word Select (Select Byte 40h) 00 01 10 11 Description Reserved. Always write this value. Word Select Selects the Frequency Word to determine the output frequency. 00 selects Word 0; 01 selects Word 1; 10 selects Word 2; 11 selects Word 3. Serial Interface Protocol and Timing The CY2XF23 uses pins SDA and SCLK for an I2C Bus that operates up to 100 kbits/sec in Read or Write mode. The CY2XF23 is always a slave on this bus, meaning that it never initiates a bus transaction. The basic Write protocol is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in MA+2; ACK; and so on, until STOP Bit. The basic serial format is illustrated in Figure 4 on page 5. Device Address The device address is a 7-bit value. The default serial interface address is 69H. Data Valid I2C Five fields can be written via the Bus. Four frequency words define the output frequency. As shown in Table 3, each of these words is a 6-byte field. When writing to a frequency word, all 6 bytes should be written. They may be written either as individual byte writes, or as a block write. The currently selected frequency word should not be written to. All four words are symmetrical, meaning that a 6-byte value that is valid for one word is also valid for any of the other words, and produces the same frequency. The fifth field is the select byte, located at byte address 40h. The value written into the two least significant bits determines the active frequency word. The other bits of the byte are reserved and should be written with the values indicated in the table. Users should never write to any address other than the 25 bytes described here. Data is valid when the clock is HIGH, and may only be transitioned when the clock is LOW as illustrated in Figure 5 on page 5. Data Frame Every new data frame is indicated by a start and stop sequence, as illustrated in Figure 6 on page 5. START Sequence - Start Frame is indicated by SDA going LOW when SCLK is HIGH. Every time a start signal is given, the next 8-bit data must be the device address (seven bits) and a R/W bit, followed by register address (eight bits) and register data (eight bits). STOP Sequence - Stop Frame is indicated by SDA going HIGH when SCLK is HIGH. A Stop Frame frees the bus for writing to another part on the same bus or writing to another random register address. Acknowledge Pulse During Write Mode, the CY2XF23 responds with an Acknowledge (ACK) pulse after every eight bits. This is accomplished by pulling the SDA line LOW during the N*9th clock cycle as illustrated in Figure 7 on page 6. (N = the number of bytes transmitted). After the data packet is sent during Read Mode, the master generates the acknowledge. Document Number: 001-53145 Rev. *B Page 3 of 11 [+] Feedback CY2XF23 PRELIMINARY Write Operations Writing Individual Bytes A valid write operation must have a full 8-bit register address after the device address word from the master, which is followed by an acknowledge bit from the slave (SDA = 0/LOW). The next eight bits must contain the data word intended for storage. After the data word is received, the slave responds with another acknowledge bit (SDA = 0/LOW), and the master must end the write sequence with a STOP condition. the CY2XF23 receives the slave address with the R/W bit set to a ‘1’, the CY2XF23 issues an acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition, which causes the CY2XF23 to stop transmission. Random Read To write more than one byte at a time, the master does not end the write sequence with a stop condition. Instead, the master can send multiple contiguous bytes of data to be stored. After each byte, the slave responds with an acknowledge bit, just like after the first byte, and accept data until the acknowledge bit is responded to by the STOP condition. When receiving multiple bytes, the CY2XF23 internally increments the register address. Through random read operations, the master may access any memory location. To perform this type of read operation, first the word address must be set. This is accomplished by sending the address to the CY2XF23 as part of a write operation. After the word address is sent, the master generates a START condition following the acknowledge. This terminates the write operation before any data is stored in the address, but not before the internal address pointer is set. Next the master reissues the control byte with the R/W byte set to ‘1’. The CY2XF23 then issues an acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition which causes the CY2XF23 to stop transmission. Read Operations Sequential Read Writing Multiple Bytes Read operations are initiated the same way as Write operations except that the R/W bit of the slave address is set to ‘1’ (HIGH). There are three basic read operations: current address read, random read, and sequential read. Current Address Read The CY2XF23 has an onboard address counter that retains 1 more than the address of the last word access. If the last word written or read was word ‘n’, then a current address read operation would return the value stored in location ‘n+1’. When Sequential read operations follow the same process as random reads except that the master issues an acknowledge instead of a STOP condition after transmission of the first 8-bit data word. This action results in an incrementing of the internal address pointer, and subsequently output of the next 8-bit data word. By continuing to issue acknowledges instead of STOP conditions, the master may serially read the entire contents of the slave device memory. When the internal address pointer points to the FFh register, after the next increment, the pointer will point to the 00h register. Figure 3. Data Transfer Sequence on the Serial Bus SCLK SDA START Condition Address or Acknowledge Valid Document Number: 001-53145 Rev. *B Data may be changed STOP Condition Page 4 of 11 [+] Feedback CY2XF23 PRELIMINARY Figure 4. Data Frame Architecture SDA Write Multiple Contiguous Registers 1 Bit Slave ACK 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 8-bit Register Address (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH) 1 Bit Slave ACK 8-bit Register Data (XXH+1) 1 Bit Slave ACK 8-bit Register Data (XXH+2) 1 Bit Slave ACK 8-bit Register Data (FFH) 1 Bit Slave ACK 1 Bit Slave ACK 8-bit Register Data (00H) Stop Signal Start Signal SDA Read Current Address Read Start Signal SDA Read Multiple Contiguous Registers 1 Bit Slave ACK 1 Bit 1 Bit Slave R/W = 1 ACK 7-bit Device Address 1 Bit Master ACK 8-bit Register Data Stop Signal 1 Bit Slave ACK 1 Bit 1 Bit Slave R/W = 0 ACK 7-bit Device Address 8-bit Register Address (XXH) 1 Bit Master ACK 7-bit Device Address +R/W=1 1 Bit Master ACK 8-bit Register Data (XXH) 1 Bit Master ACK 8-bit Register Data (XXH+1) 1 Bit Master ACK 8-bit Register Data (FFH) 1 Bit Master ACK 1 Bit Master ACK 8-bit Register Data (00H) Stop Signal Start Signal Repeated Start bit Figure 5. Data Valid and Data Transition Periods Data Valid Transition to next Bit SDA tDH VIH SCLK VIL tSU CLKHIGH CLKLOW Figure 6. Start and Stop Frame SDA START Document Number: 001-53145 Rev. *B Transition to next Bit SCLK STOP Page 5 of 11 [+] Feedback CY2XF23 PRELIMINARY Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data) SDA + START DA6 DA5 DA0 + R/W ACK RA7 + RA6 RA1 RA0 ACK D7 + + D6 D1 D0 ACK STOP + SCLK Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Supply Voltage –0.5 4.4 V VIN[2] Input Voltage, DC Relative to VSS –0.5 VDD+0.5 V TS Temperature, Storage Non Operating –55 135 C TJ Temperature, Junction –40 135 C ESDHBM ESD Protection (Human Body Model) JEDEC STD 22-A114-B ΘJA[3] Thermal Resistance, Junction to Ambient 0 m/s airflow 2000 – V 64 C/W Operating Conditions Parameter VDD Min Typ Max Unit 3.3V Supply Voltage Range Description 3.135 3.3 3.465 V 2.5V Supply Voltage Range 2.375 2.5 2.625 V TPU Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp is Monotonic) 0.05 – 500 ms TA Ambient Temperature (Commercial) 0 – 70 C –40 – 85 C Condition Min Typ Max Unit VDD = 3.465V, CLK = 150 MHz, output terminated – – 120 mA VDD = 2.625V, CLK = 150 MHz, output terminated – – 115 mA Ambient Temperature (Industrial) DC Electrical Characteristics Parameter IDD[4] Description Operating Supply Current VOD LVDS Differential Output Voltage VDD = 3.3V or 2.5V, defined in Figure 8 as terminated in Figure 13 247 – 454 mV ΔVOD Change in VOD between Complementary Output States VDD = 3.3V or 2.5V, defined in Figure 8 as terminated in Figure 13 – – 50 mV VOS LVDS Offset Output Voltage VDD = 3.3V or 2.5V, defined in Figure 9 as terminated in Figure 13 1.125 – 1.375 V ΔVOS Change in VOS between Complementary Output States VDD = 3.3V or 2.5V, RTERM = 100Ω between CLK and CLK# – – 50 mV Notes 2. The voltage on any input or I/O pin cannot exceed the power pin during power up. 3. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 4. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors. Document Number: 001-53145 Rev. *B Page 6 of 11 [+] Feedback CY2XF23 PRELIMINARY DC Electrical Characteristics (continued) Parameter Description VOLS Output Low Voltage (SDA) VIH Input High Voltage Condition Min Typ Max – – 0.1*VDD V 0.7*VDD – – V – – 0.3*VDD V – – 115 μA IOL = 4 mA Unit VIL Input Low Voltage IIH0 Input High Current (SDA) Input = VDD IIH1 Input High Current (SCLK) Input = VDD – – 10 μA IIL0 Input Low Current (SDA) Input = VSS –50 – – μA IIL1 Input Low Current (SCLK) Input = VSS –20 – – μA CIN0[5] Input Capacitance (SDA) – 15 – pF CIN1[5] Input Capacitance (SCLK) – 4 – pF AC Electrical Characteristics[5] Parameter Description Min Typ Max Unit 50 – 690 MHz VDD = min to max, TA = 0 C to 70 C – – ±35 ppm VDD = min to max, TA = –40° to 85°C – – ±55 ppm – – ±15 ppm F <= 450 MHz, measured at zero crossing 45 50 55 % F > 450 MHz, measured at zero crossing 40 50 60 % 20% and 80% of full output swing – 0.35 1.0 ns Startup Time Time for CLK to reach valid frequency measured from the time VDD = VDD(min.) – – 5 ms TLSER Relock Time Time for CLK to reach valid frequency from serial bus change to select bits in register 40h, measured from I2C STOP – – 1 ms TJitter(φ) RMS Phase Jitter (Random) fOUT = 106.25 MHz (12 kHz–20 MHz) – 1 – ps FOUT Output Frequency[7] FSC Frequency Stability, commercial devices[6] FSI Frequency Stability, industrial devices[6] AG Aging, 10 years TDC Output Duty Cycle TR, TF Output Rise and Fall Time TLOCK Condition Notes 5. Not 100% tested, guaranteed by design and characterization. 6. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage. 7. This parameter is specified in CyberClocks Online software. Document Number: 001-53145 Rev. *B Page 7 of 11 [+] Feedback CY2XF23 PRELIMINARY I2C Bus Timing Specifications[5] Parameter Description Min Max Unit fSCLK SCLK frequency – 100 kHz tHD:STA Start mode time from SDA LOW to SCLK LOW 4 – μs tLOW SCLK LOW period 4.7 – μs tHIGH SCLK HIGH period 4 – μs tSU:DAT Input data setup (SDA transition to SCLK rising edge) 1000 – ns tHD:DAT Input data hold (SCLK falling edge to SDA transition) 0 – ns tHD:DO Output data hold (SCLK falling edge to SDA transition) tSR Rise time of SCLK and SDA tSF tSU:STO tBUF Stop mode to Start mode 200 – ns – 300 ns Fall time of SCLK and SDA – 300 ns Stop mode time from SCLK HIGH to SDA HIGH 4 – μs 4.7 – μs Switching Waveforms Figure 8. Output Voltage Swing CLK# VOD1 VOD2 CLK ΔVOD = VOD1 - VOD2 Figure 9. Output Offset Voltage CLK 50Ω 50Ω CLK# V OS Figure 10. Duty Cycle Timing CLK TDC = CLK# TPW TPERIOD TPW TPERIOD Document Number: 001-53145 Rev. *B Page 8 of 11 [+] Feedback CY2XF23 PRELIMINARY Figure 11. Output Rise and Fall Time CLK# CLK 80% 80% 20% 20% TR TF Figure 12. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot Termination Circuits Figure 13. LVDS Termination CLK 100Ω CLK# Document Number: 001-53145 Rev. *B Page 9 of 11 [+] Feedback CY2XF23 PRELIMINARY Ordering Information Part Number[8] Configuration Package Description Product Flow Pb-Free CY2XF23FLXCT Field Programmable 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0° to 70°C CY2XF23FLXIT Field Programmable 6-Pin Ceramic LCC SMD - Tape and Reel Industrial, –40° to 85°C CY2XF23LXCxxxT Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0° to 70°C CY2XF23LXIxxxT Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel Industrial, –40° to 85°C Package Drawings and Dimensions Figure 14. 6-Pin 3.2x5.0 mm Ceramic LCC LZ06A 0.50 1.30 Max 2.54 TYP. SIDE VIEW 0.64 TYP. TYP. 0.20 R REF. 5 4 0.32 R INDEX 6 7 9 8 3 2 0.45 REF. TOP VIEW 1 0.10 REF. 3.2 TYP. 1.2 TYP. 10 1.27 5.0 TYP. 0.10 R REF. BOTTOM VIEW Dimensions in mm General Tolerance: ± 0.15MM Kyocera dwg ref KD-VA6432-A 001-10044-** Package Weight ~ 0.12 grams . Note 8. “xxx” is a factory assigned code that identifies the programming option. Document Number: 001-53145 Rev. *B Page 10 of 11 [+] Feedback PRELIMINARY CY2XF23 Document History Page Document Title: CY2XF23 High Performance LVDS Oscillator with Frequency Margining - I2C Control Document Number: 001-53145 REV. ECN NO. Orig. of Change Submission Date Description of Change ** 2704379 KVM/PYRS 05/11/2009 *A 2718898 WWZ 06/15/09 Minor ECN to post data sheet to external web New data sheet *B 2764787 KVM 09/18/09 Change VOD limits from 250/450 mV to 247/454 mV Add max limit for TR, TF: 1.0 ns Change TLOCK max from 10 ms to 5 ms Change TLSER max from 10 ms to 1 ms Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC psoc.cypress.com Clocks & Buffers clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53145 Rev. *B Revised September 18, 2009 Page 11 of 11 CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback