ON FDMF6707B Extra-small, high-performance, high-frequency drmos module Datasheet

Description
Benefits




Ultra-Compact 6x6mm PQFN, 72% Space-Saving
Compared to Conventional Discrete Solutions
Fully Optimized System Efficiency
Clean Sw itching Waveforms w ith Minimal Ringing
High-Current Handling
Features












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
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
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Over 93% Peak-Efficiency
High-Current Handling of 50 A
High-Performance PQFN Copper-Clip Package
3-State 3.3 V PWM Input Driver
Skip-Mode SMOD# (Low -Side Gate Turn Off) Input
Thermal Warning Flag for Over-Temperature
Condition
Driver Output Disable Function (DISB# Pin)
Internal Pull-Up and Pull-Dow n for SMOD# and
DISB# Inputs, Respectively
ON Semiconductor Pow erTrench® Technology
MOSFETs for Clean Voltage Waveforms and
Reduced Ringing
The XS™ DrMOS family is ON Semiconductor’s nextgeneration, fully optimized, ultra-compact, integrated
MOSFET plus driver pow er stage solution for highcurrent, high-frequency, synchronous buck DC-DC
applications. The FDMF6707B integrates a driver IC, tw o
pow er MOSFETs, and a bootstrap Schottky diode into a
thermally enhanced, ultra-compact 6x6 mm PQFN
package.
With an integrated approach, the complete sw itching
pow er stage is optimized for driver and MOSFET
dynamic performance, system inductance, and pow er
XS™
Dr MOS
uses
ON
MOSFET
RDS(ON) .
Semiconductor's
high-performance
Pow erTrench®
MOSFET technology, w hich dramatically reduces sw itch
ringing, eliminating the snubber circuit in most buck
converter applications.
A new driver IC w ith reduced dead times and
propagation delays further enhances performance. A
ther mal w arning function w arns of potential overtemperature situations. FDMF6707B also incorporates
features such as Skip Mode (SMOD) for improved lightload efficiency, along w ith a 3-state 3.3 V PWM input for
compatibility w ith a w ide range of PWM controllers.
Applications
ON Semiconductor SyncFET™ (Integrated
Schottky Diode) Technology in the Low -Side
MOSFET


Integrated Bootstrap Schottky Diode

Adaptive Gate Drive Timing for Shoot-through
Protection
Under-Voltage Lockout (UVLO)


Optimized for Sw itching Frequencies up to 1 MHz
Low -Profile SMD Package

ON Semiconductor Green Packaging and RoHS
Compliant

High-Performance Gaming Motherboards
Compact Blade Servers, V-Core and Non-V-Core
DC-DC Converters
Desktop Computers, V-Core and Non-V-Core
DC-DC Converters
Workstations
High-Current DC-DC Point-of-Load (POL)
Converters
Netw orking and Telecom Microprocessor Voltage
Regulators
Small Form-Factor Voltage Regulator Modules
Based on the Intel® 4.0 DrMOS Standard
Ordering Information
Part Number
Current Rating
Package
Top Mark
FDMF6707B
50 A
40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package
FDMF6707B
© 2011 Semiconductor Components Industries, LLC.
December-2017, Rev. 2
Publication Order Number:
FDMF6707B/D
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
FDMF6707B - Extra-Small, High-Performance, HighFrequency DrMOS Module
V5V
VIN
3V ~ 15V
RVCIN
C VCIN
C VDRV
VDRV
DISB
VCIN
C VIN
VIN
RBOOT
DISB#
BOOT
PWM
Input
PWM
C BOOT
FDMF6707B
OFF
PHASE
SMOD#
ON
OpenDrain
Output
VSWH
THWN#
VOUT
L OUT
CGND
Figure 1.
COUT
PGND
Typical Application Circuit
DrMOS Block Diagram
VDRV
VIN
BOOT
UVLO
VCIN
Q1
HS Power
MOSFET
DBoot
DISB#
GH
Logic
GH
Lev el Shift
10µA
30kΩ
PHASE
VCIN
Dead-Time
Control
R UP_PWM
Input
3-State
Logic
PWM
VSWH
VDRV
R DN_PWM
GL
Logic
THWN#
GL
30kΩ
VCIN
Temp.
Sense
Q2
LS Power
MOSFET
10µA
CGND
PGND
SMOD#
Figure 2.
DrMOS Block Diagram
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2
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Typical Application Circuit
40
39
38
37
36
35
34
33
VIN
VSWH
PGND
VSWH
PGND
VSWH
PGND
28
29
30
VSWH
PGND
27
VSWH
PGND
26
PGND
PGND
25
PGND
PGND
24
PGND
PGND
23
PGND
PGND
22
PGND
PGND
21
PGND
VSWH
VSWH
43
PGND
Bottom View
CGND
41
VIN
42
PGND
VSWH
18
VSWH
PGND
19
PGND
20
VSWH
PGND
32
VIN
PGND
31
NC
11
PHASE
12
GH
13
CGND
14
BOOT
15
VDRV
16
VCIN
GL
PGND
17
SMOD#
VSWH
20
21
SMOD#
CGND
VSWH
19
22
VCIN
VIN
18
23
VDRV
THWN
VIN
31
DISB#
32
Figure 3.
24
1
VIN
PGND
25
2
VIN
VSWH
26
3
PWM
PGND
27
4
VIN
VSWH
28
5
VIN
PGND
29
6
VIN
VSWH
30
7
VIN
33
VSWH
43
8
17
34
VIN
42
9
16
35
CGND
41
BOOT
10
CGND
10
GH
9
PHASE
8
NC
7
VIN
6
15
36
VSWH
5
14
37
VSWH
4
13
38
GL
3
12
39
CGND
2
11
40
THWN
VIN
PWM
DISB#
1
Figure 4.
Top View
Pin Definitions
Pin #
1
Name
Description
When SMOD#=HIGH, the low -side driver is the inverse of PWM input. When SMOD#=LOW,
SMOD# the low -side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add
a noise filter capacitor.
2
VCIN
IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.
3
VDRV
Pow er for gate driver. Minimum 1 µF ceramic capacitor is recommended connected as close as
possible from this pin to CGND.
4
BOOT
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
5, 37, 41
CGND
IC ground. Ground return for driver IC.
6
GH
7
For manufacturing test only. This pin must float. It must not be connected to any pin.
PHASE Sw itch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
8
NC
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
9 - 14, 42
VIN
Pow er input. Output stage supply voltage.
15, 29 35, 43
VSWH
Sw itch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
16 – 28
PGND
Pow er ground. Output stage ground. Source pin of the low -side MOSFET.
36
GL
38
THWN#
Thermal w arning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
39
DISB#
Output disable. When LOW, this pin disables the pow er MOSFET sw itching (GH and GL are
held LOW). This pin has a 10 µA internal pull-dow n current source. Do not add a noise filter
capacitor.
40
PWM
PWM signal input. This pin accepts a 3-state 3.3 V PWM signal from the controller.
For manufacturing test only. This pin must float. It must not be connected to any pin.
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FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
VCIN, VDRV, DISB#, PWM, SMOD#, GL, THWN# to CGND Pins
-0.3
6.0
VIN to PGND, CGND Pins
-0.3
25.0
BOOT, GH to VSWH, PHASE Pins
-0.3
6.0
BOOT, PHASE, GH to CGND Pins
-0.3
25.0
VSWH to CGND/PGND (DC Only)
-0.3
25.0
VSWH to PGND (< 20 ns)
-8.0
25.0
BOOT to VDRV
ITHWN#
Unit
V
22.0
THWN# Sink Current
-0.1
(
IO(AV) Error!
Reference
V IN=12V, V O=1.0V
source not
)
found.
θJPCB
Max.
50
f SW=1 MHz
45
Junction-to-PCB Thermal Resistance
TA
Ambient Temperature Range
TJ
Maximum Junction Temperature
TSTG
Storage Temperature Range
ESD
Electrostatic Discharge Protection
7.0
f SW=300 kHz
-40
-55
Human Body Model, JESD22-A114
2000
Charged Device Model, JESD22-C101
1000
mA
A
3.5
°C/W
+125
°C
+150
°C
+150
°C
V
Note:
1. IO(AV) is rated using ON Semiconductor’s DrMOS evaluation board, at TA = 25°C, w ith natural convection cooling.
This rating is limited by the peak DrMOS temperature, TJ = 150°C, and varies depending on operating conditions
and PCB layout. This rating can be changed w ith different application settings.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet spec ifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V CIN
Control Circuit Supply Voltage
4.5
5.0
5.5
V
V DRV
Gate Drive Circuit Supply Voltage
4.5
5.0
5.5
V
3.0
12.0
15.0
V
V IN
(2)
Output Stage Supply Voltage
Note:
2. Operating at high V IN can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes
during MOSFET sw itching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must
remain at or below the Absolute Maximum Ratings show n in the table above. Refer to the “Application
Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.
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FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Absolute Maximum Ratings
Typical values are V IN = 12 V, V CIN = 5 V, V DRV = 5 V, and TA = +25°C unless otherw ise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Basic Operation
IQ
Quiescent Current
IQ=IVCIN+IVDRV, PWM=LOW or HIGH or Float
UVLO
UVLO Threshold
V CIN Rising
UVLO_Hyst
UVLO Hysteresis
2.9
3.1
2
mA
3.3
V
0.4
V
PWM Input (VCIN = VDRV = 5 V +/- 10%)
RUP_PWM
Pull-Up Impedance
26
kΩ
RDN_PWM
Pull-Dow n Impedance
12
kΩ
V IH_PWM
PWM High Level Voltage
1.88
2.25
2.61
V
V TRI_HI
3-State Upper Threshold
1.84
2.20
2.56
V
V TRI_LO
3-State Low er Threshold
0.70
0.95
1.19
V
V IL_PWM
PWM Low Level Voltage
0.62
0.85
1.13
V
160
200
ns
1.60
1.90
V
tD_HOLD-OFF 3-State Shutoff Time
V HiZ_PWM
3-State Open Voltage
1.40
PWM Input (VCIN = VDRV = 5 V ±5%)
RUP_PWM
Pull-Up Impedance
26
kΩ
RDN_PWM
Pull-Dow n Impedance
12
kΩ
V IH_PWM
PWM High Level Voltage
2.00
2.25
2.50
V
V TRI_HI
3-State Upper Threshold
1.94
2.20
2.46
V
V TRI_LO
3-State Low er Threshold
0.75
0.95
1.15
V
V IL_PWM
PWM Low Level Voltage
0.66
0.85
1.09
V
160
200
ns
1.60
1.80
V
tD_HOLD-OFF 3-State Shutoff Time
V HiZ_PWM
3-State Open Voltage
1.45
DISB# Input
V IH_DISB
High-Level Input Voltage
V IL_DISB
Low -Level Input Voltage
IPLD
Pull-Dow n Current
tPD_DISBL
Propagation Delay
tPD_DISBH
Propagation Delay
2
V
0.8
V
10
µA
PWM=GND, Delay Betw een DISB# from
HIGH to LOW to GL from HIGH to LOW
25
ns
PWM=GND, Delay Betw een DISB# from
LOW to HIGH to GL from LOW to HIGH
25
ns
SMOD# Input
V IH_SMOD
High-Level Input Voltage
V IL_SMOD
Low -Level Input Voltage
IPLU
2
V
0.8
Pull-Up Current
V
10
µA
tPD_SLGLL
Propagation Delay
PWM=GND, Delay Betw een SMOD# from
HIGH to LOW to GL from HIGH to LOW
10
ns
tPD_SHGLH
Propagation Delay
PWM=GND, Delay Betw een SMOD# from
LOW to HIGH to GL from LOW to HIGH
10
Ns
Continued on the following page…
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5
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Electrical Characteristics
Typical values are V IN = 12 V, V CIN = 5 V, V DRV = 5 V, and TA = +25°C unless otherw ise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Therm al Warning Flag
TACT
Activation Temperature
150
°C
TRST
Reset Temperature
135
°C
IPLD=5 mA
30
Ω
SW=0 V, Delay Betw een GH from HIGH to
LOW and GL from LOW to HIGH
250
ns
1
Ω
RTHWN
Pull-Dow n Resistance
250ns Tim eout Circuit
tD_TIMEOUT
Timeout Delay
High-Side Driver
RSOURCE_GH Output Impedance, Sourcing Source Current=100 mA
Output Impedance, Sinking
Sink Current=100 mA
0.8
Ω
tR_GH
Rise Time
GH=10% to 90%, CLOAD=1.1 nF
6
ns
tF_GH
Fall Time
GH=90% to 10%, CLOAD=1.1 nF
5
ns
tD_DEADON
LS to HS Deadband Time
GL going LOW to GH going HIGH,
1 V GL to 10 % GH
10
ns
tPD_PLGHL
PWM LOW Propagation
Delay
PWM going LOW to GH going LOW,
V IL_PWM to 90% GH
16
tPD_PHGHH
PWM HIGH Propagation
Delay (SMOD# Held LOW)
PWM going HIGH to GH going HIGH,
V IH_PWM to 10% GH (SMOD# =LOW)
30
ns
tPD_TSGHH
Exiting 3-State Propagation
Delay
PWM (from 3-State) going HIGH to GH
going HIGH, V IH_PWM to 10% GH
30
ns
RSINK_GH
30
ns
Low -Side Driver
1
Ω
Output Impedance, Sinking
Sink Current=100 mA
0.5
Ω
tR_GL
Rise Time
GL=10% to 90%, CLOAD=5.9 nF
20
ns
tF_GL
Fall Time
GL=90% to 10%, CLOAD=5.9 nF
13
ns
SW going LOW to GL going HIGH,
2.2 V SW to 10% GL
12
ns
RSOURCE_GL Output Impedance, Sourcing Source Current=100 mA
RSINK_GL
tD_DEADOFF HS to LS Deadband Time
tPD_PHGLL
PWM-HIGH Propagation
Delay
PWM going HIGH to GL going LOW,
V IH_PWM to 90% GL
9
tPD_TSGLH
Exiting 3-State Propagation
Delay
PWM (from 3-State) going LOW to GL
going HIGH, V IL_PWM to 10% GL
20
ns
VF
Forw ard-Voltage Drop
IF=10 mA
0.35
V
VR
Breakdow n Voltage
IR=1 mA
25
ns
Boot Diode
22
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6
V
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Electrical Characteristics
V IH_PWM
V IL_PWM
PWM
90%
GL
1.0V
10%
90%
GH
to
VSWH
10%
1.2V
t D_TIMEOUT
(250ns Timeout)
2.2V
VSWH
tPD_PLGHL
tPD_PHGLL
tD_DEADOFF
t D_DEADON
Figure 5.
PWM Tim ing Diagram
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7
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Timing Diagram
55
11
50
10
300kHz
45
9
500kHz
8
800kHz
7
1MHz
40
Module Power Loss (W)
Module Output current, IOUT (A)
Test Conditions: V IN=12 V, V OUT=1.0 V, V CIN=5 V, V DRV=5 V, LOUT=320 nH, TA=25°C, and natural convection cooling,
unless otherw ise specified.
fSW = 1MHz
35
30
fSW = 300kHz
25
20
15
VIN = 12V, VOUT = 1.0V
10
Θ JPCB = 3.5°C/W
5
6
5
4
3
2
1
0
0
25
0
50
75
100
125
150
0
5
10
PCB Temperature (°C)
Figure 6.
Safe Operating Area
Figure 7.
Normalized Module Power Loss
IOUT = 30A
Normalized Module Power Loss
20
25
30
35
40
45
Module Pow er Loss vs. Output Current
1.3
1.5
1.4
1.3
1.2
1.1
1
IOUT = 30A, fSW = 300kHz
1.2
1.1
1.0
0.9
0.9
200
300
400
500
600
700
800
900
4
1000
6
Figure 8.
Pow er Loss vs. Sw itching Frequency
Figure 9.
IOUT = 30A, fSW = 300kHz
12
14
16
Pow er Loss vs. Input Voltage
IOUT = 30A, fSW = 300kHz
Normalized Module Power Loss
2.0
1.05
1.00
0.95
1.8
1.6
1.4
1.2
1.0
0.8
0.6
4.75
5.00
5.25
0.6
5.50
1.0
1.4
1.8
2.2
2.6
3.0
Output Voltage, VOUT (V)
Driver Supply Voltage, VDRV and VCIN (V)
Figure 10.
10
2.2
1.10
0.90
4.50
8
Module Input Voltage, VIN (V)
Module Switching Frequency, fSW (kHz)
Normalized Module Power Loss
15
Module Output Current, IOUT (A)
Pow er Loss vs. Driver Supply Voltage
Figure 11.
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8
Pow er Loss vs. Output Voltage
3.4
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics
Test Conditions: V IN=12 V, V OUT=1.0 V, V CIN=5 V, VDRV=5 V, LOUT=320 nH, TA =25°C, and natural convection cooling,
unless otherw ise specified.
50
IOUT = 30A, fSW = 300kHz
1.05
Driver Supply Current, IVDRV + IVCIN (mA)
Normalized Module Power Loss
1.06
1.04
1.03
1.02
1.01
1.00
0.99
IOUT = 0A
45
40
35
30
25
20
15
10
0.98
5
225
275
325
375
200
425
300
Output Inductance, LOUT (nH)
Figure 12.
Pow er Loss vs. Output Inductance
Figure 13.
Normalized Driver Supply Current
IOUT = 0A, fSW = 300kHz
16
15
14
13
12
4.50
4.75
Figure 14.
5.00
5.25
800
900
1000
1.06
1.04
1.02
300kHz
1.00
1MHz
0.98
0.96
0.94
0
5
10
15
20
25
30
35
40
45
Module Output Current, IOUT (A)
Driver Supply Current vs. Driver
Supply Voltage
Figure 15.
Driver Supply Current vs. Output Current
3.0
TA = 25°C
VCIN = 5V
PWM Threshold Voltage (V)
PWM Threshold Voltage (V)
700
1.08
5.50
3.0
VIH_PWM
2.0
VTRI_HI
VHiZ_PWM
1.5
VTRI_LO
1.0
VIL_PWM
0.5
0.0
4.50
600
Driver Supply Current vs. Frequency
Driver Supply Voltage, VDRV and VCIN (V)
2.5
500
1.10
17
Driver Supply Current, IVDRV + IVCIN (mA)
400
Module Switching Frequency, fSW (kHz)
2.5
VIH_PWM
2.0
VTRI_HI
1.5
VTRI_LO
1.0
VIL_PWM
0.5
0.0
4.75
5.00
5.25
5.50
-50
-25
Driver Supply Voltage, VCIN (V)
0
25
50
75
100
125
Driver IC Junction Temperature, TJ (oC)
Figure 16. PWM Thresholds vs. Driver Supply Voltage
Figure 17.
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9
PWM Thresholds vs. Tem perature
150
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics (Continued)
Test Conditions: V IN=12 V, V OUT=1.0 V, V CIN=5 V, VDRV=5 V, LOUT=320 nH, TA =25°C, and natural convection cooling,
unless otherw ise specified.
2.2
2.0
VCIN = 5V
SMOD Threshold Voltage (V)
SMOD# Threshold Voltage (V)
TA = 25°C
2.0
VIH_SMOD
1.8
1.6
VIL_SMOD
1.4
1.9
1.8
VIH_SMOD
1.7
1.6
VIL_SMOD
1.5
1.4
1.3
1.2
4.50
4.75
5.00
5.25
-50
5.50
-25
0
Figure 18.
Figure 19.
SMOD# Thresholds vs. Driver
Supply Voltage
75
100
125
150
SMOD# Thresholds vs. Tem perature
VCIN = 5V
DISB Threshold Voltage (V)
SMOD# Pull-up Current, IPLU (uA)
VCIN = 5V
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
1.90
1.80
VIH_DISB
1.70
1.60
VIL_DISB
1.50
1.40
-50
-25
0
25
50
75
100
125
150
-50
Driver IC Junction Temperature, TJ (oC)
Figure 20.
-25
0
25
50
75
100
125
150
Driver IC Junction Temperature, TJ (°C)
SMOD# Pull-Up Current vs. Tem perature
Figure 21.
Disable Thresholds vs. Driver
Supply Voltage
12.0
2.1
TA = 25oC
DISB # Pull-Down Current , I PLD (µA)
DISB# Threshold Voltage (V)
50
2.00
-9.0
2.0
25
Driver IC Junction Temperature (oC)
Driver Supply Voltage, VCIN (V)
VIH_DISB
1.9
1.8
1.7
VIL_DISB
1.6
1.5
1.4
1.3
4.50
11.0
10.5
10.0
9.5
9.0
8.5
8.0
4.75
5.00
5.25
5.50
Driver Supply Voltage, VCIN (V)
Figure 22.
VCI = 5V
11.5
- 50
- 25
0
25
50
75
100
125
Driver IC Junction Temperature ( o C)
Disable Thresholds vs. Tem perature
www.onsemi.com
10
Figure 23.
Disable Pull-Dow n Current
vs. Tem perature
150
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Typical Performance Characteristics (Continued)
The FDMF6707B is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low -side MOSFETs. Each part is
capable of driving speeds up to 1 MHz.
VCIN and Disable (DISB#)
The VCIN pin is monitored by an under-voltage loc kout
(UVLO) circuit. When V CIN rises above ~3.1 V, the dr iver
is enabled for operation. When V CIN falls below ~2.7 V,
the driver is disabled (GH, GL=0). The driver can also
be disabled by pulling the DISB# pin LOW ( DISB# <
V IL_DISB), w hich holds both GL and GH LOW regardless
of the PWM input state. The driver can be enabled by
raising the DISB# pin voltage HIGH (DISB# > V IH_DISB).
Table 1. UVLO and Disable Logic
UVLO
DISB#
Driver State
0
X
Disabled (GH, GL=0)
1
0
Disabled (GH, GL=0)
1
1
Enabled (See Table 2)
1
Open
Disabled (GH, GL=0)
Thermal Warning Flag (THWN#)
The FDMF6707B provides a ther mal w arning flag
(THWN#) to advise of over-temperature conditions. The
ther mal w arning flag uses an open-drain output that
pulls to CGND w hen the activation temperature (150°C)
is reached. The THWN# output returns to highimpedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN# output
requires a pull-up resistor, w hich can be connected to
VCIN. THWN# does NOT disable the DrMOS module.
HIGH
THWN#
Logic
State
Nor mal
Operation
Ther mal
Warning
LOW
TJ_driver
Figure 24.
IC
The FDMF6707B incorporates a 3-state 3.3 V PWM
input gate drive design. The 3-state gate dr ive has both
logic HIGH level and LOW level, along w ith a 3-state
shutdow n w indow . When the PWM input signal enters
and remains w ithin the 3-state w indow for a defined
hold-off time (tD_HOLD-OFF), both GL and GH are pulled
LOW. This feature enables the gate drive to shut dow n
both high-and low -side MOSFETs to support features
such as phase shedding, a common feature on multiphase voltage regulators.
Exiting 3-State Condition
When exiting a valid 3-state condition, the FDMF6707B
design follow s the PWM input command. If the PWM
input goes from 3-state to LOW, the low -side MOSFET
is turned on. If the PWM input goes from 3-state to
HIGH, the high-side MOSFET is turned on, as illustrated
in Figure 25. The FDMF6707B des ign allows for short
propagation delays w hen exiting the 3-state w indow
(see Electrical Characteristics).
Low-Side Driver
Note:
3. DISB# internal pull-dow n current source is 10 µA.
135°C Reset 150°C
Activation
Temperature
Temperature
3-State PWM Input
The low -side driver (GL) is designed to drive a groundreferenced low RDS(ON) N-channel MOSFET. The bias
for GL is internally connected betw een VDRV and
CGND. When the dr iver is enabled, the driver's output is
180° out of phase w ith the PWM input. When the dr iver
is disabled (DISB#=0 V), GL is held LOW.
High-Side Driver
The high-side driv er is des igned to dr ive a floating Nchannel MOSFET. The bias voltage for the high-side
driver is dev eloped by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstr ap capac itor ( CBOOT). Dur ing startup, V SWH is
held at PGND, allow ing CBOOT to charge to V DRV
through the internal diode. When the PWM input goes
HIGH, GH begins to charge the gate of the high-side
MOSFET ( Q1). During this transition, the charge is
removed from CBOOT and deliver ed to the gate of Q1.
As Q1 turns on, V SWH rises to V IN, forcing the BOOT
pin to V IN + V BOOT, w hich provides sufficient V GS
enhancement for Q1. To complete the sw itching cycle,
Q1 is tur ned off by pulling GH to V SWH. CBOOT is then
recharged to V DRV w hen V SWH falls to PGND. GH
output is in-phase w ith the PWM input. The high-side
gate is held LOW w hen the dr iver is disabled or the
PWM s ignal is held w ithin the 3-state w indow for
longer than the 3-state hold-off time, tD_HOLD-OFF.
THWN Operation
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11
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Functional Description
The driver IC design ensures minimum MOSFET dead
time w hile eliminating potential shoot-through (crossconduction) currents. It senses the state of the
MOSFETs and adjusts the gate drive adaptively to
prevent simultaneous conduction. Figure 25 provides
the relevant timing w aveforms. To prevent overlap
during the LOW-to-HIGH sw itching transition (Q2 off to
Q1 on), the adaptive circuitry monitors the voltage at the
GL pin. When the PWM signal goes HIGH, Q2 begins to
turn off after a propagation delay (tPD_PHGLL). Once the
GL pin is discharged below ~1 V, Q1 begins to turn on
after adaptive delay tD_DEADON.
V IH_PWM
V IH_PWM
V IL_PWM
To prevent overlap dur ing the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive c ircuitry monitors the
voltage at the VSWH pin. When the PWM signal goes
LOW, Q1 begins to turn off after a propagation delay
(tPD_PLGHL). Once the VSWH pin falls below ~2.2 V, Q2
begins to turn on after adaptive delay tD_DEADOFF.
Additionally, V GS(Q1) is monitored. When V GS(Q1) is
discharged below ~1.2 V, a secondary adaptive delay is
initiated that results in Q2 being dr iven on after
tD_TIMEOUT, regardless of VSWH state. This function is
implemented to ensure CBOOT is recharged each
sw itching cycle in the event that the VSWH voltage does
not fall below the 2.2 V adaptive threshold. Secondary
delay tD_TIMEOUT is longer than tD_DEADOFF.
t R_GH
PWM
less than
tD_HOLD - OFF
GH
to
V IH_PWM
V TRI_HI
V IH PWM
V TRI_HI
V TRI_LO
VIL_PWM
t F_GH
90%
tD_HOLD -OFF
10%
VSWH
V IN
CCM
DCM
DCM
V OUT
2.2V
VSWH
GL
90%
9 0%
1.0V
tPD_PHGLL
t D_DEADON
10%
1 0%
t PD_PLGHL t R_GL
tF_GL
tD_DEADOFF
t PD_TSGHH
Enter
3- State
Exit
3-State
tD_HOLD -OFF
Enter
3 -State
t PD_TSGHH
Exit
3 State
less than
tD_HOLD - OFF
t D_HOLD-OFF t PD_TSGLH
Enter
3 -State
Exit
3- State
Notes:
tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
Example (tPD_PHGLL – PWM going HIGH to LS V GS (GL) going LOW)
tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS V GS (GL) LOW to HS VGS (GH) HIGH)
PWM
tPD_PHGLL = PWM rise to LS VGS fall, V IH_PWM to 90% LS V GS
tPD_PLGHL = PWM fall to HS VGS fall, V IL_PWM to 90% HS VGS
tPD_PHGHH = PWM rise to HS VGS rise, V IH_PWM to 10% HS VGS (SMOD# held LOW)
Exiting 3-state
tPD_TSGHH = PWM 3-state to HIGH to HS V GS rise, VIH_PWM to 10% HS VGS
tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, V IL_PWM to 10% LS V GS
SMOD#
tPD_SLGLL = SMOD# fall to LS V GS fall, VIL_SMOD to 90% LS V GS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS
Dead Times
tD_DEADON = LS V GS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS
tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS
Figure 25.
PWM and 3-StateTim ing Diagram
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12
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Adaptive Gate Drive Circuit
The SMOD function allow s for higher converter
efficiency under light-load conditions. During SMOD, the
low -side FET gate signal is disabled (held LOW),
preventing discharging of the output capacitors as the
filter inductor current attempts reverse current flow –
also know n as “Diode Emulation” Mode.
When the SMOD# pin is pulled HIGH, the synchronous
buck converter w orks in Synchronous Mode. This mode
allows for gating on the low -side FET. When the
SMOD# pin is pulled LOW, the low -side FET is gated
off. If the SMOD# pin is connected to the PWM
controller, the controller can actively enable or disable
SMOD w hen the controller detects light-load condition
from output current sensing. This pin is active LOW.
See Figure 26 for timing delays.
Table 2. SMOD# Logic
DISB#
PWM
SMOD#
GH
GL
0
X
X
0
0
1
3-State
X
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
Note:
4. The SMOD feature is intended to have low
propagation delay betw een the SMOD signal and
the low -side FET VGS response time to control
diode emulation on a cycle-by-cycle basis.
SMOD#
V IH_SMOD
V IL_SMOD
V IH_PWM
V IH_PWM
V IL_PWM
PWM
90%
GH
to
VSWH
10%
1 0%
CCM
2.2V
DCM
CCM
V OUT
VSWH
GL
90%
1.0V
t PD_PHGLL
t D_DEADON
1 0%
10%
tPD_PLGHL
tPD_SLGLL
tD_DEADOFF
tPD_PHGHH
Delay from SMOD# going
LOW to LS VGS LOW
HS turn - on with SMOD# LOW
Figure 26.
SMOD# Tim ing Diagram
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13
tPD_SHGLH
Delay from SMOD# going
HIGH to LS V GS HIGH
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Skip Mode (SMOD#)
Supply Capacitor Selection
VCIN Filter
For the supply inputs (V DRV & V CIN), a local ceramic
bypass capacitor is required to reduce noise and to
supply peak transient currents during gate drive
sw itching action. It is recommended to use a minimum
capacitor value of 1 µF X7R or X5R. Keep this capacitor
close to the V CIN and VDRV pins and connect it to the
GND plane w ith vias.
The V DRV pin provides pow er to the gate drive of the
high-side and low-side pow er MOSFETs. In most cases,
VDRV can be connected directly to VCIN, w hich supplies
pow er to the logic circuitry of the gate driver. For
additional noise immunity, an RC filter can be inserted
betw een VDRV and VCIN. Recommended values w ould
be 10 Ω (RVCIN) placed betw een VDRV and VCIN and
1µF (CVCIN) from VCIN to CGND (see Figure 28).
Bootstrap Circuit
Power Loss and Efficiency
The bootstrap circuit uses a charge storage capacitor
(CBOOT), as show n in Figure 27. A bootstrap capacitance
of 100 nF X7R or X5R capacitor is typically adequate. A
series bootstrap resistor may be needed for specific
applications to improve sw itching noise immunity. The
boot resistor may be required w hen operating near the
maximum rated V IN and is effective at controlling the
high-side MOSFET turn-on slew rate and V SHW
overshoot. Typical RBOOT values from 0.5 Ω to 2.0 Ω are
effective in reducing V SWH overshoot.
V5V
A
PIN=(V IN x IIN) + (V 5V x I5V) (W)
PSW=V SW x IOUT (W)
POUT=V OUT x IOUT (W)
PLOSS_MODULE=PIN - PSW (W)
PLOSS_BOARD=PIN - POUT (W)
EFFMODULE=100 x PSW/PIN (%)
EFFBOARD=100 x POUT/PIN (%)
A
R VCIN
I5V
VCIN
VDRV
C VIN
VIN
DISB#
PWM
Input
VIN
I IN
CVCIN
C VDRV
DISB
Measurement and Calculation
Refer to Figure 27 for pow er loss testing method. Pow er
loss calculations are:
RBOOT
BOOT
PWM
FDMF6707B
CBOOT
OFF
IOUT
VSWH
SMOD#
ON
A
OpenDrain
Output
V VSW
PGND
Pow er Loss Measurem ent Block Diagram
A
A
R VCIN
I5V
VCIN
VDRV
DISB
DISB#
PWM
Input
PWM
VIN
I IN
C VCIN
C VDRV
C VIN
VIN
RBOOT
BOOT
FDMF6707B
OFF
CBOOT
IOUT
VSWH
ON
OpenDrain
Output
VOUT
COUT
CGND
Figure 27.
V5V
L OUT
PHASE
THWN#
SMOD#
A
L OUT
PHASE
COUT
THWN#
CGND
Figure 28.
PGND
V VSW
Block Diagram Show ing V CIN Filter
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14
VOUT
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Application Information
Figure 29 provides an example of a proper layout for the
FDMF6707B and critical components. All of the highcurrent paths, such as V IN, V SWH, VOUT, and GND
copper, should be short and w ide for low inductance
and resistance. This technique achieves a more stable
and evenly distributed current flow , along w ith enhanced
heat radiation and system performance.
The follow ing guidelines are recommendations for the
PCB designer:
1. Input ceramic bypass capacitors must be placed
close to the VIN and PGND pins. This helps reduce
the high-current pow er loop inductance and the input
current ripple induced by the pow er MOSFET
sw itching operation.
2. The V SWH copper trace serves tw o purposes. In
addition to being the high-frequency current path
from the Dr MOS package to the output inductor, it
also serves as a heat sink for the low -side MOSFET
in the Dr MOS package. The trace should be short
and w ide enough to present a low -impedance path
for the high-frequency, high-current flow betw een the
Dr MOS and inductor to minimize losses and
temperature rise. Note that the VSWH node is a
high-voltage and high-frequency sw itching node w ith
high noise potential. Care should be taken to
minimize coupling to adjacent traces. Since this
copper trace also acts as a heat sink for the low er
FET, balance using the largest area possible to
improve
Dr MOS
cooling
w hile
maintaining
acceptable noise emission.
3. An output inductor should be located close to the
FDMF6707B to minimize the pow er loss due to the
VSWH copper trace. Care should also be taken so
the inductor dissipation does not heat the DrMOS.
4. Pow erTrench® MOSFETs are used in the output
stage. The pow er MOSFETs are effective at
minimiz ing ringing due to fast sw itching. In most
cases, no VSWH snubber is required. If a snubber is
used, it should be placed close to the VSWH and
PGND pins. The resistor and capacitor need to be of
proper size for the pow er dissipation.
5. VCIN, VDRV, and BOOT capacitors should be
placed as close as possible to the VCIN to CGND,
VDRV to CGND, and BOOT to PHASE pins to
ensure clean and stable pow er. Routing w idth and
length should be considered as w ell.
6. Inc lude a trace from PHA SE to VSWH to improve
noise margin. Keep the trace as short as possible.
7. The layout should include a placeholder to insert a
small-value series boot resistor (RBOOT) betw een the
boot capacitor (CBOOT) and Dr MOS BOOT pin. The
BOOT-to-VSWH loop size, including RBOOT and
CBOOT, should be as s mall as possible. The boot
resistor may be required w hen operating near the
maximum rated V IN. The boot resistor is effective at
controlling the high-side MOSFET turn-on slew rate
and VSHW overshoot. RBOOT can improve noise
operating margin in synchronous buck des igns that
may have noise issues due to ground bounce or high
positive and negative VSWH ringing. How ever,
inserting a boot resistance low ers the Dr MOS
efficiency. Efficiency versus noise trade-offs must be
considered. RBOOT values from 0.5 Ω to 2.0 Ω are
typically effective in reducing VSWH overshoot.
8. The V IN and PGND pins handle large current
transients w ith frequency components greater than
100 MHz. If possible, these pins should be
connected directly to the VIN and board GND
planes. The use of ther mal relief traces in series w ith
these pins is discouraged since this adds
inductance to the pow er path. Added inductance in
series w ith the VIN or PGND pin degrades system
noise immunity by increasing pos itive and negative
VSWH ringing.
9. CGND pad and PGND pins should be connected to
the GND plane copper w ith multiple vias for stable
grounding. Poor grounding can create a noise
transient offset voltage level betw een CGND and
PGND. This could lead to faulty operation of the gate
driver and MOSFETs.
10. Ringing at the BOOT pin is most effectively
controlled by close placement of the boot capacitor.
Do not add an additional BOOT to the PGND
capacitor: this may lead to excess current flow
through the BOOT diode.
11. The SMOD# and DISB# pins have w eak internal
pull-up and pull-dow n current sources, respectively.
These pins should not have any noise filter
capacitors. Do not to float these pins unless
absolutely necessary.
12. Use multiple vias on each copper area to
interconnect top, inner, and bottom layers to help
distribute current flow and heat conduction. Vias
should be relatively large and of reasonably low
inductance. Critical high-frequency components,
such as RBOOT, CBOOT, the RC snubber, and bypass
capacitors should be located as close to the
respective Dr MOS module pins as possible on the
top layer of the PCB. If this is not feasible, they
should be connected from the backside through a
netw ork of low -inductance vias.
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15
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
PCB Layout Guidelines
Figure 29.
PCB Layout Exam ple
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16
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Bottom View
Top View
B
0.10 C
PIN#1
INDICATOR
6.00
2X
5.80
A
4.50
30
21
31
6.00
20
0.40
2.50
0.65
0.25
1.60
0.10 C
11
40
2X
1
SEE 0.60
DETAIL 'A' 0.50 TYP
TOP VIEW
10
0.35
0.15
2.10
0.40 21
FRONT VIEW
4.40±0.10
(2.20)
0.10
C A B
0.05
C
0.30
30 0.20 (40X)
31
20
0.50
2.40±0.10
(0.70)
1.50±0.10
11
10
0.40
2.00±0.10
(0.20)
40
0.50 (40X)
0.30
2.00±0.10
0.50
NOTES: UNLESS OTHERWISE SPECIFIED
(0.20)
1.10
0.90
0.10 C
0.30
0.20
PIN #1 INDICATOR
0.20 MAY APPEAR AS
OPTIONAL
1
BOTTOM VIEW
0.08 C
2.10
LAND PATTERN
RECOMMENDATION
0.05
0.00
DETAIL 'A'
C
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-220, DATED
MAY/2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: PQFN40AREV3
SEATING
PLANE
SCALE: 2:1
Figure 30.
40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 m m Package
Package drawings are provided as a service to customers considering ON Semiconductor components. Drawings may change in
any manner without notice. Please note the revision and/or date on the drawing and contact an ON Semiconductor representative to
verify or obtain the most recent revision. Package specifications do not expand the terms of ON Semiconductor’s worldwide terms and
conditions, specifically the warranty therein, which covers ON Semiconductor products.
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17
FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
Physical Dimensions
PUBLICATION ORDERING INFORMATION
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FDMF6707B - Extra-Small High-Performance, High-Frequency DrMOS Module
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