AD AD9411BSV-170 10-bit, 170/200 msps 3.3 v a/d converter Datasheet

10-Bit, 170/200 MSPS
3.3 V A/D Converter
AD9411
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SENSE VREF AGND DRGND DRVDD AVDD
SCALABLE
REFERENCE
VIN+
VIN–
CLK+
CLK–
TRACK
AND
HOLD
AD9411
ADC
10
10-BIT
PIPELINE /
CORE
CLOCK
MANAGEMENT
LVDS
OUTPUTS
LVDS TIMING
DATA,
OVERRANGE
IN LVDS
DCO+
DCO–
APPLICATIONS
S1
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
S5
04530-0-001
SNR = 60 dB @ fIN up to 70 MHz @ 200 MSPS
ENOB of 9.8 @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN up to 70 MHz @ 200 MSPS (–0.5 dBFS)
Excellent linearity:
DNL = ±0.15 LSB (typical)
INL = ±0.25 LSB (typical)
LVDS output levels
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.25 W typical @ 200 MSPS
1.5 V input voltage range
3.3 V supply operation
Output data format option
Clock duty cycle stabilizer
Pin compatible to LVDS mode AD9430
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9411 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 200 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including track-and-hold (T/H) and reference, are
included on the chip to provide a complete conversion solution.
1.
High performance.
Maintains 60 dB SNR @ 200 MSPS with a 70 MHz input.
2.
Low power.
Consumes only 1.25 W @ 200 MSPS.
3.
Ease of use.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold function provide flexibility in system
design. Use of a single 3.3 V supply simplifies system
power supply design.
4.
Out-of-range (OR).
The OR output bit indicates when the input signal is
beyond the selected input range.
The ADC requires a 3.3 V power supply and a differential
sample clock for full performance operation. The digital outputs
are LVDS compatible and support both twos complement and
offset binary format. A data clock output is available to ease
data capture.
Fabricated on an advanced BiCMOS process, the AD9411 is
available in a 100-lead surface-mount plastic package (e-PAD
TQFP-100) specified over the industrial temperature range
(–40°C to +85°C).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9411
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
Clock Outputs (DCO+, DCO–)............................................... 19
AC Specifications.............................................................................. 4
Voltage Reference ....................................................................... 19
Digital Specifications........................................................................ 5
Noise Power Ratio Testing (NPR)............................................ 19
Switching Specifications .................................................................. 6
Evaluation Board ............................................................................ 21
Explanation of Test Levels ........................................................... 6
Power Connector........................................................................ 21
Absolute Maximum Ratings............................................................ 7
Analog Inputs ............................................................................. 21
ESD Caution.................................................................................. 7
Gain.............................................................................................. 21
Pin Configuration and Function Descriptions............................. 8
Clock ............................................................................................ 21
Terminology .................................................................................... 10
Voltage Reference ....................................................................... 21
Equivalent Circuits ......................................................................... 12
Data Format Select ..................................................................... 21
Typical Performance Characteristics ........................................... 13
Data Outputs............................................................................... 21
Application Notes ........................................................................... 18
Clock XTAL................................................................................. 21
Clock Input.................................................................................. 18
Outline Dimensions ....................................................................... 27
Analog Input ............................................................................... 18
Ordering Guide .......................................................................... 27
LVDS Outputs............................................................................. 19
REVISION HISTORY
7/04—Data Sheet Changed from Rev. 0 to Rev. A
Added 200 MSPS Grade ....................................................Universal
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 27
Rev 0 : Initial Version
Rev. A | Page 2 of 28
AD9411
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
otherwise noted.
Table 1.
AD9411-170
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Out (VREF)
REFERENCE
Reference Out (VREF)
Output Current1
IVREF Input Current2
ISENSE Input Current
ANALOG INPUTS (VIN+, VIN–)3
Differential Input Voltage Range
(S5 = GND)
Differential Input Voltage Range
(S5 = AVDD)
Input Common-Mode Voltage
Input Resistance
Input Capacitance
POWER SUPPLY (LVDS Mode)
AVDD
DRVDD
Supply Currents
IANALOG (AVDD = 3.3 V)4
IDIGITAL (DRVDD = 3.3 V)
Power Dissipation
Power Supply Rejection
2
4
4
AD9411-200
Temp
Test
Level
Min
Full
25°C
25°C
25°C
Full
25°C
Full
VI
I
I
I
VI
I
VI
Guaranteed
–3
–5
–0.5
± 0.15
–0.6
± 0.25
–0.8
± 0.5
–1
± 0.5
Full
Full
Full
V
V
V
58
0.02
+0.12/
–0.24
25°C
25°C
25°C
25°C
I
IV
I
I
Full
V
1.536
1.536
V
Full
V
0.766
0.766
V
Full
Full
25°C
VI
VI
V
2.65
2.2
2.8
3
5
2.9
3.8
2.65
2.2
2.8
3
5
2.9
3.8
V
kΩ
pF
Full
Full
IV
IV
3.1
3.0
3.3
3.3
3.6
3.6
3.2
3.0
3.3
3.3
3.6
3.6
V
V
Full
Full
Full
25°C
VI
VI
VI
V
335
49
1.27
–7.5
372
57
1.42
385
49
1.43
–7.5
425
57
1.59
mA
mA
W
mV/V
1.15
Typ
12
1.235
1.6
1
Max
Min
Typ
12
+3
+5
+0.5
+0.6
+0.8
+1
Guaranteed
–3
–5
–0.5
± 0.15
–0.6
± 0.25
–0.8
± 0.5
–1
± 0.5
Max
Unit
Bits
+3
+5
+0.5
+0.6
+0.8
+1
mV
% FS
LSB
LSB
LSB
LSB
58
0.02
+0.12/
–0.24
1.3
3.0
20
5.0
1.15
1.235
1.6
µV/°C
%/°C
mV/°C
1.3
3.0
20
5.0
Internal reference mode; SENSE = floats.
External reference mode; SENSE = DRVDD; VREF driven by external 1.23 V reference.
3
S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc, ac tests, unless otherwise specified
4
IAVDD and IDRVDD are measured with an analog input of 10.3 MHz, –0.5 dBFS, sine wave, rated clock rate, and in LVDS output mode. See the Typical Performance
Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated clock rate in LVDS output mode.
2
Rev. A | Page 3 of 28
V
mA
mA
mA
AD9411
AC SPECIFICATIONS1
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, unless
otherwise noted.
Table 2.
AD9411-170
Parameter
SNR
Analog Input @ –0.5 dBFS
10 MHz
70 MHz
100 MHz
240 MHz
SINAD
Analog Input @ –0.5 dBFS
10 MHz
70 MHz
100 MHz
240 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
10 MHz
70 MHz
100 MHz
240 MHz
WORST HARMONIC (Second or Third)
Analog Input @ –0.5 dBFS 10 MHz
10 MHz
70 MHz
100 MHz
240 MHz
WORST HARMONIC (Fourth or Higher)
Analog Input @ –0.5 dBFS 10 MHz
10 MHz
70 MHz
100 MHz
240 MHz
TWO-TONE IMD2
F1, F2 @ –7 dBFS
ANALOG INPUT BANDWIDTH
1
2
Temp
Test
Level
25°C
25°C
25°C
25°C
AD9411-200
Min
Typ
Min
Typ
I
I
V
V
59
59
60.2
60.1
60
59.1
59
59
60.2
60.1
60
59.1
dB
dB
dB
dB
25°C
25°C
25°C
25°C
I
I
V
V
58.5
58.5
60
60
59.5
57.5
58.5
58.5
60
60
59.5
57.5
dB
dB
dB
dB
25°C
25°C
25°C
25°C
I
I
V
V
9.5
9.5
9.8
9.8
9.7
9.3
9.5
9.5
9.8
9.8
9.7
9.3
Bits
Bits
Bits
Bits
25°C
25°C
25°C
25°C
I
I
V
V
–80
–80
−74
−69
–73
–73
–80
–80
−74
−69
–70
–70
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
I
I
V
V
–82
–82
−76
−70
–75
–75
–82
–82
−76
−70
–75
–75
dBc
dBc
dBc
dBc
25°C
25°C
V
V
70
700
All ac specifications tested by driving CLK+ and CLK– differentially.
F1 = 30.5 MHz, F2 = 31 MHz.
Rev. A | Page 4 of 28
Max
70
700
Max
Unit
dBc
MHz
AD9411
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS
(CLK+, CLK–)1
Differential Input Voltage2
Common-Mode Voltage3
Input Resistance
Input Capacitance
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
Input Resistance
Input Capacitance
LVDS LOGIC OUTPUTS4
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
AD9411-170
Typ
Max
Temp
Test Level
Min
Full
Full
Full
25°C
IV
VI
VI
V
0.2
1.375
3.2
Full
Full
Full
Full
25°C
25°C
IV
IV
VI
VI
V
V
2.0
Full
Full
VI
VI
247
454
1.125
1.375
Twos Complement or Binary
1.5
5.5
4
1.575
6.5
Min
0.2
1.375
3.2
AD9411-200
Typ
1.5
5.5
4
Max
Unit
1.575
6.5
V
V
kΩ
pF
2.0
0.8
190
10
30
4
1
See the Equivalent Circuits section.
All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 200 mV.
3
Clock inputs’ common mode can be externally set, such that 0.9 V < CLK± < 2.6 V.
4
LVDS RTERM = 100 Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).
2
Rev. A | Page 5 of 28
0.8
190
10
30
4
247
454
1.125
1.375
Twos Complement or Binary
V
V
µA
µA
kΩ
pF
mV
V
AD9411
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
Parameter (Conditions)
Temp
Maximum Conversion Rate1
Minimum Conversion Rate
CLK+ Pulse Width High (tEH)
CLK+ Pulse Width Low (tEL)
OUTPUT (LVDS Mode)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD–tCPD)
Latency
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Full
Full
Full
Full
Test
Level
VI
V
IV
IV
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
VI
VI
V
V
VI
IV
IV
V
V
Out-of-Range Recovery Time
25°C
V
1
1
1
1
Min
AD9411-170
Typ
Max
170
Min
AD9411-200
Typ
Max
Unit
200
40
12.5
12.5
2
2
2.0
MSPS
MSPS
ns
ns
40
12.5
12.5
2
2
2.0
3.2
0.5
0.5
2.7
0.5
14
1.2
0.25
1.8
0.2
4.3
3.8
0.8
1
1.8
0.2
3.2
0.5
0.5
2.7
0.5
14
1.2
0.25
ns
ns
ns
ns
ns
ns
Cycles
ns
ps
rms
Cycles
4.3
3.8
0.8
1
All ac specifications tested by driving CLK+ and CLK– differentially.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
N–1
N
N+1
AIN
tEL
tEH
1/fS
CLK+
CLK–
tPD
N–14
DATA OUT
N–13
N
N+1
14 CYCLES
DCO+
04530-0-002
DCO–
tCPD
Figure 2. LVDS Timing Diagram
Rev. A | Page 6 of 28
AD9411
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
AVDD, DRVDD
Analog Inputs
Digital Inputs
REFIN Inputs
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction Temperature
Maximum Case Temperature
θJA1
1
Rating
4V
–0.5 V to AVDD +0.5 V
–0.5 V to DRVDD +0.5 V
–0.5 V to AVDD +0.5 V
20 mA
–55ºC to +125°C
–65ºC to +150°C
150°C
150°C
25°C/W, 32°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions outside of those indicated in the operation
section of this specification is not implied. Exposure to absolute
maximum ratings conditions for extended periods may affect
device reliability.
Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
soldered) for multilayer board in still air with solid ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 7 of 28
AD9411
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AGND
AVDD
AVDD
AVDD
AGND
AGND
OR+
OR–
DVRDD
DRGND
D9+
D9–
D8+
D8–
D7+
D7–
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
S5
1
75
DRVDD
DNC
AGND
2
74
3
73
DRGND
D6+
AGND
4
72
D6–
AVDD
5
71
D5+
S1
6
70
D5–
LVDSBIAS
7
69
D4+
AVDD
8
68
D4–
AGND
9
67
DRGND
SENSE 10
66
D3+
VREF 11
65
D3–
D1+
D1–
AGND 20
56
D0+
VIN+ 21
55
D0–
VIN– 22
54
DRVDD
AGND 23
53
DRGND
AVDD 24
52
DNC
AGND 25
51
DNC
AVDD 34
AVDD 33
AGND 32
AGND 31
AGND 30
AVDD 29
AVDD 28
AVDD 27
AGND 26
AGND 35
Figure 3. TQFP/EP Pinout
Rev. A | Page 8 of 28
DNC 50
57
DNC 49
58
DRGND 48
D2–
AVDD 18
AVDD 19
DRVDD 47
D2+
59
DNC 46
60
AGND 17
DNC 45
AGND 16
DNC 44
DRVDD
DRGND
DNC 43
61
DNC 42
DCO–
62
AVDD 14
AVDD 15
AGND 41
63
AVDD 40
TOP VIEW
(Not to Scale)
AVDD 39
DCO+
AGND 13
AGND 38
64
CLK– 37
AD9411
CLK+ 36
AGND 12
04530-0-003
AGND
100
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9411
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
S5
2, 42–46,49–52
3, 4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31,
32, 35, 38, 41, 86, 87, 91, 92, 93, 96, 97, 100
5, 8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34,
39, 40, 88, 89, 90, 94, 95, 98, 99
6
7
DNC
AGND
10
11
21
22
36
37
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
SENSE
VREF
VIN+
VIN–
CLK+
CLK–
DRVDD
DRGND
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
D0+
D1–
D1+
D2–
D2+
DCO–
DCO+
D3–
D3+
D4–
D4+
D5–
D5+
D6–
D6+
D7–
D7+
D8–
D8+
D9–
D9+
OR–
OR+
AVDD
S1
LVDSBIAS
Function
Full-Scale Adjust Pin. AVDD sets FS = 0.768 V p-p differential;
GND sets FS = 1.536 V p-p differential.
Do Not Connect.
Analog Ground. AGND and DRGND should be tied together to a common
ground plane.
3.3 V Analog Supply.
Data Format Select. GND = binary; AVDD = twos complement.
Set Pin for LVDS Output Current. Place a 3.74 kΩ resistor terminated to
ground.
Reference Mode Select Pin. Float for internal reference operation.
1.235 V Reference Input/Output. Function depends on SENSE.
Analog Input. True.
Analog Input. Complement.
Clock Input. True (LVPECL levels).
Clock Input. Complement (LVPECL levels).
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground. AGND and DRGND should be tied together to a
common ground plane.
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
Data Clock Output. Complement.
Data Clock Output. True.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
Overrange Complement Output Bit.
Overrange True Output Bit.
Rev. A | Page 9 of 28
AD9411
TERMINOLOGY
Analog Bandwidth
Clock Pulse Width/Duty Cycle
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
The delay between the 50% point of the rising edge of the clock
command and the instant at which the analog input is sampled.
Pulse width high is the minimum amount of time the clock
pulse should be left in the Logic 1 state to achieve rated
performance; pulse width low is the minimum time the clock
pulse should be left in the low state. Refer to the timing
implications of changing tENCH in the Application Notes, Clock
Input section. At a given clock rate, these specifications define
an acceptable CLOCK duty cycle.
Aperture Uncertainty (Jitter)
Full-Scale Input Power
The sample-to-sample variation in aperture delay.
Expressed in dBm. Computed using the following equation:
Aperture Delay
Crosstalk
Coupling onto one channel being driven by a low level (–40 dBFS)
signal when the adjacent interfering channel is driven by a fullscale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input’s phase 180° and again taking the peak measurement.
The difference is then computed between both peak
measurements.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
SNRMEASURED − 1.76 dB
ENOB =
6.02
Gain Error
Harmonic Distortion, Second
Differential Analog Input Voltage Range
The deviation of any code width from an ideal 1 LSB step.
⎞
⎟
⎟
⎟
⎟
⎠
The difference between the measured and ideal full-scale input
voltage range of the ADC.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Nonlinearity
PowerFULLSCALE
⎛
⎜V 2
FULLSCALE RMS
= 10 log⎜
Z INPUT
⎜
⎜
0.001
⎝
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The CLOCK rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The CLOCK rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK–
and the time when all output data bits are within valid logic
levels.
Rev. A | Page 10 of 28
AD9411
Noise (for Any Range within the ADC)
Two-Tone Intermodulation Distortion Rejection
Calculated as follows:
The ratio of the rms value of either input tone to the rms value of
the worst third-order intermodulation product, reported in dBc.
− SNRdBc − Signal dBFS ⎞
⎛ FS
V NOISE = Z × 0.001 × 10⎜ dBM
⎟
10
⎠
⎝
Two-Tone SFDR
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value of the particular
input level, and Signal is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Power Supply Rejection Ratio (PSRR)
Worst Other Spur
The ratio of a change in input offset voltage to a change in
power supply voltage.
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonics) reported in dBc.
Signal-to-Noise-and-Distortion (SINAD)
Transient Response Time
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Signal-to-Noise Ratio (without Harmonics)
Out-of-Range Recovery Time
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc
(i.e., degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Rev. A | Page 11 of 28
AD9411
EQUIVALENT CIRCUITS
AVDD
FULL
SCALE
K
12kΩ
12kΩ
0.1µF
CLK+
VREF
CLK–
150Ω
150Ω
A1
1V
10kΩ
200Ω
04530-0-004
SENSE
1kΩ
DISABLE
A1
Figure 4. Clock Inputs
04530-0-007
10kΩ
VDD
AVDD
Figure 7. VREF, SENSE I/O
3.5kΩ
3.5kΩ
DRVDD
VIN+
VIN–
20kΩ
04530-0-005
20kΩ
V–
DX–
DX+
V–
V+
04530-0-008
Figure 5. Analog Inputs
V+
VDD
Figure 8. Data Outputs
30kΩ
04530-0-006
S1,S5
Figure 6. S1 to S5 Inputs
Rev. A | Page 12 of 28
AD9411
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–10
–10
SNR = 60.1dB
SINAD = 59.9dB
H2 = –91.3dBc
H3 = –75.2dBc
SFDR = 75.3dBc
–30
–50
–60
–60
dB
–50
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
0
10
20
30
40
50
60
70
80
MHz
–120
0
0
0
–10
–10
SNR = 59.8dB
SINAD = 59.8dB
H2 = –91.9dBc
H3 = –80.6dBc
SFDR = 73.2dBc
–30
–60
dB
–50
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
20
30
40
50
60
70
80
MHz
0
–10
SNR = 59.2dB
SINAD = 59.1dB
H2 = –70.1dBc
H3 = –87.0dBc
SFDR = 69.8dBc
dB
–70
–70
–80
–80
–90
–90
–100
–100
–110
–110
–120
40
50
60
70
80
MHz
04530-0-011
dB
–60
30
90
100
30
40
50
MHz
60
70
80
90
100
SNR = 50.6dB
SINAD = 43.8dB
H2 = –44.8dBc
H3 = –67.4dBc
SFDR = 43.6dBc
–40
–60
20
20
–30
–50
10
10
–20
–50
0
80
Figure 13. FFT: fS = 200 MSPS, AIN = 65 MHz @ −0.5 dBFS
0
–40
70
SNR = 59.5dB
SINAD = 59.4dB
H2 = –82.5dBc
H3 = –72.8dBc
SFDR = 72.7dBc
0
–10
–30
60
–120
Figure 10. FFT: fS = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS
–20
50
MHz
–40
–60
10
40
–30
–50
0
30
–20
04530-0-010
dB
–40
20
Figure 12. FFT: fS = 200 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
Figure 9. FFT: fS = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS
–20
10
04530-A-001
–40
04530-0-009
dB
–40
–20
04530-A-002
–30
–120
0
10
20
30
40
50
MHz
60
70
80
90
100
Figure 14. FFT: fS = 200 MSPS, AIN = 70 MHz @ −0.5 dBFS,
Single-Ended Drive, 1.5 V Input Range
Figure 11. FFT: fS = 170 MSPS, AIN = 10.3, MHz @ –0.5 dBFS,
Single-Ended Input, 0.76 V Input Range
Rev. A | Page 13 of 28
04530-A-003
–20
SNR = 59.7dB
SINAD = 59.5dB
H2 = –83.6dBc
H3 = –72.6dBc
SFDR = 72.5dBc
AD9411
100
0
–10
SFDR = 71.5dBc
90
–20
–30
80
–40
THIRD
–50
SECOND
dB
dB
SFDR
70
–60
–70
60
–80
50
–100
–90
–110
50
100
150
200
250
300
350
400
AIN (MHz)
–120
0
10
30
40
50
60
70
80
MHz
Figure 15. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency @ 170 MSPS
Figure 18. Two-Tone Intermodulation Distortion
(30.5 MHz and 31.0 MHz; fS = 170 MSPS)
100
0
90
–20
SECOND
–40
70
(dB)
80
(dB)
20
04530-0-019
0
04530-0-015
40
THIRD
–60
SFDR = 78.8dBc
50
–100
40
0
50
100
150
200
(MHz)
250
300
350
400
250
–120
0
Figure 16. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency @ 200 MSPS
61
100
04530-A-004
–80
04530-A-006
60
04530-A-008
SFDR
10
20
30
40
50
(MHz)
60
70
80
90
Figure 19. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; fS = 200 MSPS)
80
SNR_170
SFDR_170
59
75
57
70
SNR_200
SINAD_170
(dB)
53
51
60
49
50
47
45
45
50
100
150
200
250
(MHz)
300
SINAD_200
55
SINAD_200
0
SFDR_200
65
SINAD_170
350
400
450
04530-A-007
(dB)
55
40
0
50
100
150
200
(MSPS)
Figure 20. SINAD and SFDR vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS) 170/200 grade
Figure 17. SNR and SINAD vs. AIN Frequency; fS = 170/200 MSPS,
AIN @ –0.5 dBFS Full Scale = 1.536 V
Rev. A | Page 14 of 28
AD9411
90
300
60
250
50
200
40
OUTPUT SUPPLY
CURRENT
150
30
100
20
50
0
100
10
120
140
160
180
200
220
0
240
ENCODE (MSPS)
75
SFDR
70
65
SNR
60
SINAD
55
50
20
350
70
300
60
ANALOG SUPPLY CURRENT
250
50
40
200
OUTPUT SUPPLY CURRENT
150
30
100
20
50
10
0
100
120
140
160
180
200
SAMPLE RATE (MSPS)
220
0
240
1.2
RO = 13Ω TYP
1.0
VREF (V)
80
IDRVDD OUTPUT SUPPLY CURRENT (mA)
400
1.4
0.8
0.6
0.4
0.2
04530-A-009
IAVDD ANALOG SUPPLY CURRENT (mA)
90
80
Figure 24. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)
Figure 21. IAVDD and IDRVDD vs. Clock Rate, 170 MSPS Grade, CLOAD = 5 pF
(AIN = 10.3 MHz @ –0.5 dBFS)
450
30
40
50
60
70
SAMPLE CLOCK POSITIVE DUTY CYCLE
04530-A-010
70
0
0
1
2
3
4
5
6
7
8
04530-A-016
350
(dB)
80
ANALOG SUPPLY
CURRENT
IDRVDD OUTPUT SUPPLY CURRENT (mA)
400
80
04530-2-023
IAVDD ANALOG SUPPLY CURRENT (mA)
450
ILOAD (mA)
Figure 22. IAVDD and IDRVDD vs. Clock Rate, 200 MSPS Grade, CLOAD = 5 pF
(AIN = 10.3 MHz @ –0.5 dBFS)
Figure 25. VREFOUT vs. ILOAD (Both Speed Grades)
75
80
73
SFDR
SFDR
75
71
69
70
(dB)
65
63
61
65
SNR
60
SINAD
55
SINAD
59
55
20
30
40
50
60
70
80
ENCODE POSITIVE DUTY CYCLE (%)
90
Figure 23. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
50
0.5
0.7
0.9
1.1
1.3
1.5
VREF (V)
Figure 26. Sinad, SFDR vs. VREF in External Reference Mode
(AIN = 70 MHz @ –0.5 dBFS, 200 MSPS)
Rev. A | Page 15 of 28
04530-A-011
57
04530-0-025
dB
67
2.0
90
1.5
85
1.0
80
0.5
75
% GAIN ERROR
USING EXT REF
0
SFDR
dB
GAIN ERROR (%)
AD9411
70
–0.5
65
–1.0
60
–1.5
55
SNR
–30
–10
10
30
50
70
90
TEMPERATURE (°C)
50
–50
04530-0-028
–2.0
–50
–10
10
30
50
70
90
TEMPERATURE (°C)
Figure 27. Full-Scale Gain Error vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)
60
–30
04530-0-030
SINAD
Figure 30. SNR, SINAD, and SFDR vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
1.00
AVDD = 3.6V
0.75
59
0.50
AVDD = 3.3V
0.25
(dB)
LSB
AVDD = 3.15V
58
0
57
–0.25
AVDD = 3.0V
–0.50
56
–20
0
20
40
TEMPERATURE (°C)
60
80
–1.00
0
100
200
300
400
500
600
700
800
900
1000
CODE
04530-0-032
55
–40
04530-A-012
–0.75
Figure 31. Typical INL Plot
(AIN = 10.3 MHz @ –0.5 dBFS, 170/200 MSPS)
Figure 28. SINAD vs. Temperature and AVDD
(AIN = 10.3 MHz @ –0.5 dBFS, 200 MSPS)
1.0
1.250
0.8
0.6
1.245
0.2
LSB
1.240
0
–0.2
1.235
–0.4
–0.6
1.230
2.7
2.9
3.1
3.3
3.5
3.7
3.9
–1.0
0
200
300
400
500
CODE
AVDD (V)
Figure 29. VREF Output Voltage vs. AVDD (Both Speed Grades)
100
600
700
800
900
1000
04530-0-033
1.225
2.5
–0.8
04530-0-029
VREFOUT (V)
0.4
Figure 32. Typical DNL Plot (AIN = 10.3 MHz @ –0.5 dBFS) 170/200 MSPS
Rev. A | Page 16 of 28
AD9411
0
110
NPR = 51 dB
CLK = 200MSPS
NOTCH AT 18.5MHz
100
–20
90
SFDR –dBFS
80
–40
60
dB
dB
70
50
40
80dB
REFERENCE LINE
30
–60
–80
SFDR –dBc
20
–100
–80
–70
–60
–50
–40
–30
–20
–10
–120
04530-0-034
0
–90
0
ANALOG INPUT LEVEL (dBFS)
0
Figure 33. SFDR vs. AIN Input Level 10.3 MHz, AIN @ 170 MSPS
5
10
15
20
MHz
25
30
35
40
04530-A-005
10
Figure 36. Noise Power Ratio Plot (200 MSPS Grade)
90
4.5
80
70
4.0
60
SFDR –dBFS
SFDR –dBc
dB
ns
50
3.5
40
TPD
30
70dB REFERENCE LINE
3.0
20
TCPD
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (dBFS)
–10
0
2.5
–40
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 37. Propagation Delay vs. Temperature (Both Speed Grades)
Figure 34. SFDR vs. AIN Input Level 70 MHz, AIN @ 200 MSPS
1.4
900
0
NPR = 51.2dB
ENCODE = 170MSPS
NOTCH @ 18.15MHz
–20
1.3
800
VOS
–40
700
1.2
600
1.1
500
1.0
–100
–120
–140
0
10
20
30
40
MHz
0.9
400
VOD
300
0.8
200
0.7
100
0.6
0.5
0
0
2
4
6
8
10
12
14
RSET (kΩ)
Figure 35. Noise Power Ratio Plot (170 MSPS Grade)
Figure 38. LVDS Output Swing, Common-Mode Voltage vs. RSET,
Placed at LVDSBIAS (Both Speed Grades)
Rev. A | Page 17 of 28
VOS (V)
–80
04530-0-037
VDIF (mV)
–60
04530-0-035
NOISE LEVEL (dB)
–20
04530-0-036
0
–70
04530-A-013
10
AD9411
APPLICATION NOTES
The AD9411 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to quantization by the 10-bit core. For ease of use, the part includes an onboard reference and input logic that accepts TTL, CMOS, or
LVPECL levels. The digital output’s logic levels are LVDS
(ANSI-644) compatible.
CLOCK INPUT
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A track-andhold circuit is essentially a mixer, and any noise, distortion, or
timing jitter on the clock is combined with the desired signal at
the A/D output. For this reason, considerable care has been
taken in the design of the clock inputs of the AD9411, and the
user is advised to give careful thought to the clock source.
The AD9411 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLK+ and optimizes
timing internally. This allows a wide range of input duty cycles
at the input without degrading performance. Jitter in the rising
edge of the input is still of paramount concern and is not
reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 30 MHz
nominally. The time constant associated with the loop should
be considered in applications where the clock rate changes
dynamically, requiring a wait time of 1.5 µs to 5 µs after a
dynamic clock frequency increase before valid data is available.
This circuit is always on and cannot be disabled by the user.
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs, as illustrated in Figure 39. Note that for this low voltage
PECL device, the ac coupling is optional.
0.1µF
Table 7. Output Select Coding1
S1 (Data Format
Select)
1
0
X
X
S5 (Full-Scale
Select)2
X
X
1
0
Mode
Twos Complement
Offset Binary
Full Scale = 0.768 V
Full Scale = 1.536 V
1
X = Don’t Care.
2
S5 full-scale adjust (refer to the Analog Input section).
ANALOG INPUT
The analog input to the AD9411 is a differential buffer. For best
dynamic performance, impedances at VIN+ and VIN– should
match. The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven
differentially. SNR and SINAD performance degrades significantly if the analog input is driven with a single-ended signal.
A wideband transformer, such as Mini-Circuits’ ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 2.8 V (refer to the Equivalent Circuits section). Note
that the input common-mode can be overdriven by
approximately +/−150 mV around the self-bias point, as shown
in Figure 42.
Special care was taken in the design of the analog input section
of the AD9411 to prevent damage and corruption of data when
the input is overdriven. The nominal differential input range is
approximately 1.5 V p-p ~ (768 mV × 2). Note that the best
performance is achieved with S5 = 0 (full-scale = 1.5). See
Figure 40 and Figure 41.
AD9411
CLK+
S5 = GND
PECL
GATE
CLK–
0.1µF
Figure 39. Driving Clock Inputs with LVEL16
VIN+
768mV 2.8V
2.8V
VIN–
DIGITALOUT = ALL 1s
DIGITALOUT = ALL 0s
04530-0-041
510Ω
04530-A-017
510Ω
Figure 40. Differential Analog Input Range
Rev. A | Page 18 of 28
AD9411
providing a low skew clocking solution (see Figure 2). The onchip clock buffers should not drive more than 5 pF of capacitance
to limit switching transient effects on performance. The output
clocks are LVDS signals requiring 100 Ω differential termination
at receiver.
S5 = AVDD
VIN+
768mV 2.8V
2.8V
04530-0-042
VIN– = 2.8V
Figure 41. Single-Ended Analog Input Range
61
VOLTAGE REFERENCE
A stable and accurate 1.23 V voltage reference is built into the
AD9411 (VREF). The analog input full-scale range is linearly
proportional to the voltage at VREF. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. No appreciable degradation in
performance occurs when VREF is adjusted ±5%. A 0.1 µF
capacitor to ground is recommended at the VREF pin in
internal and external reference applications. Float the SENSE
pin for internal reference operation.
SINAD
60
59
dB
K
FULL
SCALE
S5 = 0
S5 = 1
58
K = 1.24
K = 0.62
0.1µF
VREF
A1
1V
EXTERNAL 1.23V
REFERENCE
56
2.0
2.2
2.4
2.6
2.8
3.0
ANALOG INPUT COMMON MODE (V)
04530-A-014
200Ω
3.2
1kΩ
Figure 42. SINAD Sensitivity to Analog Input Common-Mode Voltage,
(Ain = −.5 dBfs Differential Drive, S5 = 0)
DISABLE
A1
SENSE
VDD
3.3V
04530-0-043
57
LVDS OUTPUTS
The off-chip drivers provide LVDS compatible output levels. A
3.74 kΩ RSET resistor placed at Pin 7 (LVDSBIAS) to ground
sets the LVDS output current. The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a
nominal 350 mV swing at the receiver. LVDS mode facilitates
interfacing with LVDS receivers in custom ASICs and FPGAs
that have LVDS capability for superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a 100 Ω termination resistor as close to
the receiver as possible. It is recommended to keep the trace
lengths < 4 inches and to keep differential output trace lengths
as equal as possible.
Figure 43. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return
path of cable systems where the signals are typically QAM signals with a “noise-like” frequency spectrum. NPR performance
of the AD9411 was characterized in the lab yielding an effective
NPR = 51.2 dB at an analog input of 18 MHz. This agrees with a
theoretical maximum NPR of 51.6 dB for a 10-bit ADC at 13 dB
backoff. The rms noise power of the signal inside the notch is
compared with the rms noise level outside the notch using an
FFT. This test requires sufficiently long record lengths to
guarantee a large number of samples inside the notch. A highorder band-stop filter that provides the required notch depth
for testing is also needed.
CLOCK OUTPUTS (DCO+, DCO–)
The input clock is buffered on-chip and available off-chip at
DCO+ and DCO–. These clocks can facilitate latching off-chip,
Rev. A | Page 19 of 28
AD9411
SIGNAL
GENERATOR
REFIN
3.3V
+
AVDD GND DRVDD GND
BAND-PASS
FILTER
3.3V
+
VDL GND
ANALOG
J4
AD9411 EVALUATION BOARD
10MHz
REFOUT
SIGNAL
GENERATOR
CLOCK
J5
Figure 44. Evaluation Board Connections
Rev. A | Page 20 of 28
DATA
CAPTURE
AND
PROCESSING
04530-0-044
3.3V
+
AD9411
EVALUATION BOARD
The AD9411 evaluation board offers an easy way to test the
AD9411 in LVDS mode. It requires a clock source, an analog
input signal, and a 3.3 V power supply. The clock source is
buffered on the board to provide the clocks for the ADC,
latches, and a data-ready signal. The digital outputs and output
clocks are available at a 40-pin connector, P23. The board has
several different modes of operation and is shipped in the
following configurations:
•
Offset binary
•
Internal voltage reference
•
Full-scale adjust = low
GAIN
Full scale is set at E17–E19, E17–E18 sets S5 low, full scale =
1.5 V differential; E17–E19 sets S5 high, full scale = 0.75 V
differential. Best performance is obtained at 1.5 V full scale.
CLOCK
The clock input is terminated to ground through 50 Ω resistor
at SMB connector J5. The input is ac-coupled to a high speed
differential receiver (LVEL16) that provides the required low
jitter, fast edge rates needed for optimum performance. J5 input
should be > 0.5 V p-p. Power to the LVEL16 is set at Jumper
E47. E47–E45 powers the buffer from AVDD; E47–E46 powers
the buffer from VCLK/V_XTAL.
POWER CONNECTOR
VOLTAGE REFERENCE
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).
The AD9411 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when Jumpers E24–E27
and E25–E26 are left open. The full scale can be increased by
placing an optional resistor (R3). The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place Jumper E26–E25).
Jumper E27–E24 connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
Table 8. Power Connector, LVDS Mode
AVDD1 3.3 V
DRVDD1 3.3 V
VDL1 3.3 V
VCLK/V_XTAL
EXT_VREF2
1
2
Analog Supply for ADC (350 mA)
Output Supply for ADC (50 mA)
Supply for Support Logic
Supply for Clock Buffer/Optional XTAL
Optional External Reference Input
AVDD, DRVDD, and VDL are the minimum required power connections.
LVEL16 clock buffer can be powered from AVDD or VCLK at E47 jumper.
ANALOG INPUTS
DATA FORMAT SELECT
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is
terminated to ground through 50 Ω by R16. The input can be
alternatively terminated at the T1 transformer secondary by
R13 and R14. T1 is a wideband RF transformer that provides a
single-ended-to-differential conversion, allowing the ADC to be
driven differentially, which minimizes even-order harmonics.
An optional second transformer, T2, can be placed following T1
if desired. This provides some performance advantage (~1 dB to
2 dB) for high analog input frequencies (>100 MHz). If T2 is
placed, cut the two shorting traces at the pads. The analog
signal can be low-pass filtered by R41, C12 and R42, C13 at the
ADC input. The footprint for transformer T2 can be modified
to accept a wideband differential amplifier (AD8351) for low
frequency applications where gain is required. See the PCB
schematic for more information.
Data format select (DFS) sets the output data format of the
ADC. Setting DFS (E1–E2) low sets the output format to be
offset binary; setting DFS high (E1–E3) sets the output to twos
complement.
DATA OUTPUTS
The ADC LVDS digital outputs are routed directly to the
connector at the card edge. Resistor pads placed at the output
connector allow for termination if the connector receiving logic
lack the differential termination for the data bits and DCO.
Each output trace pair should be terminated differentially at
the far end of the line with a single 100 ohm resistor.
CLOCK XTAL
An optional XTAL oscillator can be placed on the board to
serve as a clock source for the PCB. Power to the XTAL is
through the VCLK/VXTAL pin at the power connector. If an
oscillator is used, ensure proper termination for best results.
The board was tested with a Valpey Fisher VF561 and a Vectron
JN00158-163.84.
Rev. A | Page 21 of 28
AD9411
Table 9. Evaluation Board Bill of Material—AD9411 PCB
No.
1
Quantity
33
Reference Designator
C1, C3*, C4–C11, C15–C17, C18*,
C19–C32, C35, C36, C39*, C40*, C58-C62
Device
Capacitor
Package
0603
Value
0.1 µF
2
4
C33*, C34*, C37*, C38*
Capacitor
0402
0.1 µF
3
4
C63–C66
Capacitor
TAJD
4
1
C2*
Capacitor
0603
10 pF
5
2
C12*, C13*
Capacitor
0603
20 pF
6
7
2
2
J4, J5
P21, P22
Jacks
Power Connectors—Top
8
2
P21, P22
Power Connectors—Posts
9
1
P23
40-Pin Right Angle Connector
SMB
25.602.5453.0
Wieland
Z5.531.3425.0
Wieland
Digi-Key
S2131-20-ND
10
16
R1, R6–R12*, R15*, R31–R37*
Resistor
0402
100
11
1
R2
Resistor
0603
3.7 kΩ
12
3
R5, R16, R27
Resistor
0603
50
13
2
R17, R18
Resistor
0603
510
14
2
R19, R20
Resistor
0603
150
15
2
R29, R30
Resistor
0603
1 kΩ
16
2
R41, R42
Resistor
0603
25
17
2
R3, R4
Resistor
0603
3.8 kΩ
18
2
R13, R14
Resistor
0603
25
19
6
R22*, R23*, R24*, R25*, R26*, R28*
Resistor
0603
100
20
5
R38*, R39*, R40*, R45*, R47*
Resistor
0402
25
21
2
R43*, R44*
Resistor
0402
10 kΩ
22
1
R46*
Resistor
0402
1.2 kΩ
23
2
R48*, R49*
Resistor
0402
0
24
2
R50*, R51*
Resistor
0402
1 kΩ
25
CAPL
10 µF
Mini Circuits
1
T1, T2*
RF Transformer
ADT1-1WT
26
1
U2
RF Amp
AD8351
27
1
U9
Optional XTAL
JN00158 or VF561
28
1
U1
AD9411
TQFP-100
29
1
U3
MC100LVEL16
SO8NB
* C2, C3, C12, C13, C18, C33, C34, C37, C38, C39, C40, R1, R6–R12, R15, R22–R26, R28, R31–R40, R43–R51 and T2 not placed.
Rev. A | Page 22 of 28
04530-A-015
GND
R27
50Ω
R17
510Ω
C5
0.1µF
C30
0.1µF
AMPIN
AIN
15
16
17
18
19
20
21
VCC
GND
GND
VCC
VCC
GND
R18
510Ω
VDL
25
24
2
3
4
U3
GND
C8
0.1µF
GND
GND
R5
50Ω
R19
510Ω
ELOUTB
ELOUT
R20
510Ω
6
7
GND
C36
0.1µF
AGND
AVDD
AGND
AINB
AVDD
AGND
AGND
AVDD
AVDD
VCC
D
Q
DN
QN
VBB
VEE
5
8
E45
E46
GND
10EL16
E47
C13
20pF
GND
VCC
23
22
GND
14
VCC
GND
AVDD
13
GND
AGND
12
GND
AGND
VREF
U1
AD9411
C9
0.1µF
C10
0.1µF
C4
0.1µF
GND
R34
100Ω
D2FB
D2F
R35
100Ω
D1FB
D1F
R36
100Ω
DNC 51
DNC 52
DRGND 53
DRVDD 54
D0– 55
D0+ 56
D1+ 58
D1– 57
D2– 59
D2+ 60
DRVDD 62
DRGND 61
DC0– 63
DC0+ 64
D3– 65
D3+ 66
SENSE
11
DRGND 67
AGND
D4– 68
9
AVDD
D4+ 69
D5– 70
LVDSBIAS
D5+ 71
S1
D6– 72
D6+ 73
S2
AGND
DRVDD 75
DRGND 74
10
7
6
5
4
3
DNC
S4
S5
D9B
D9
GND
R30
1kΩ
2
1
R8
100Ω
D10B
D10
8
VCC
R42 GND
25Ω
C2
10pF
C3
0.1µF
GND
C1
0.1µF
E24
E26
E19
E18
R7
100Ω
D11
R6
100Ω
D11B
VCC
VCC
E17
GND
MTHOLE6
H1
R29 GND
1kΩ
AMPINB
R41
C15
25Ω
0.1µF
R14
25Ω
GND
GND
J5
R13
25Ω
6 C11
0.1µF
4
2
PRI SEC
1
5
NC
3
ENCODE
4
GND
2
6 C7
0.1µF
PRI SEC
1
5
NC
3
E27
VREF
VCC
E25
C12
20pF
GND
GND
ADT1-1WT
T2 OPTIONAL
R4
3.8kΩ
GND
VCC
E3
E2
GND
E1
R3
GND 3.8kΩ
GND
VCC
VCC
GND
DRVDD
GND
ADT1-1WT
P21
P22
T2
PTM1CRO4
PTM1CRO4
T1
C6
0.1µF
AMP
GND
ANALOG R16
J4 50Ω
4
P4
R2
3.8kΩ
2
3
P2
P3
1
26 AGND
GND
P1
MTHOLE6
GND
AGND 100
27 AVDD
H2
VCC
AVDD 99
28 AVDD
VCC
VCC
VDL
VCC
AVDD 98
29 AVDD
VCC
4
GND
AGND 97
30 AGND
GND
P4
32 AGND
MTHOLE6
GND
AGND 96
31 AGND
GND
H3
VCC
VCC
AVDD 95
AVDD 94
34 AVDD
VCC
VREF
GND
AGND 93
35 AGND
GND
GND
GND
~ENC
2
VCC
AVDD 89
37 CLK–
3
VCC
AVDD 88
38 AGND
GND
P2
GND
AGND 87
39 AVDD
VCC
P3
VCC
AVDD 90
AGND 91
36 CLK+
MTHOLE6
GND
AGND 92
33 AVDD
GND
AGND 86
40 AVDD
VCC
H4
OR– 84
42 DNC
GND
OR+ 85
41 AGND
GND
1
D9+ 81
45 DNC
P1
D9– 80
46 DNC
GND
D8– 78
47 DRVDD
P16
DRVDD
DVRDD 83
43 DNC
DORB
D8+ 79
48 DRGND
GND
Rev. A | Page 23 of 28
DRVDD
Figure 45. Evaluation Board Schematic
50 DNC
GROUND PAD UNDER PART
GND
DRGND 82
44 DNC
D7– 76
DOR
D7+ 77
49 DNC
R1
100Ω
CONNECTOR
D0B
D0
DR
R37
100Ω
DRB
D6
R10
100Ω
D6B
P37 37
P3 3
P1 1
P5 5
P7 7
P9 9
GND 2 P2
6 P6
8 P8
10 P10
P11 11
P13 13
12 P12
P15 15
16 P16
14 P14
18 P18
20 P20
22 P22
24 P24
26 P26
28 P28
30 P30
32 P32
34 P34
36 P36
P39 39
40 P40
4 P4
D2B
D1B
D0B
D1FB
D2FB
DORB
D8B
D7B
D6B
D5B
D4B
D3B
D4B
D4
D8B
D8
GND
D2
D1
D0
D1F
D2F
DOR
GND
DR
P35 35 GND
P33 33 D11
P31 31 D10
P29 29 D9
P27 27 D8
P25 25 D7
P23 23 D6
P21 21 D5
P19 19 D4
P17 17 D3
R33
100Ω
R12
100Ω
38 P38
D3
R32
100Ω
D3B
D5
R9
100Ω
D5B
D7
R11
100Ω
D7B
D2
R31
100Ω GND
DRVDD
DRB
GND
D2B
GND
D1
D11B
R15
100Ω
D10B
D1B
D9B
GND
DRVDD
GND
DRVDD
GND
AD9411
AD9411
VCC
+
C64
10µF
C16
0.1µF
C17
0.1µF
C19
0.1µF
C21
0.1µF
C23
0.1µF
C20
0.1µF
C22
0.1µF
C25
0.1µF
C24
0.1µF
C27
0.1µF
C26
0.1µF
C29
0.1µF
C28
0.1µF
C31
0.1µF
C32
0.1µF
C35
0.1µF
GND
DRVDD
VDL
+
C65
10µF
C61
0.1µF
C62
0.1µF
C60
0.1µF
C59
0.1µF
C58
0.1µF
+
C66
10µF
VREF
C18
0.1µF
GND
GND
+
C63
10µF
GND
TO USE VF561 CRYSTAL
GND
VDL
R28
100Ω
GND
1
E/D
VCC
6
2
NC
OUTPUTB
5
3
GND
OUTPUT
4
R23
100Ω
VDL
P4
R25
100Ω
U9
GND
VDL
R24
100Ω
P5
04530-0-046
R26
100Ω
GND
Figure 46. Evaluation Board Schematic (continued)
R51
1kΩ
R50
1kΩ
VDL
GND
VDL
POWER DOWN
USE R43 OR R44
VDL
GND
R38
25kΩ
R43
10kΩ
C38
0.1µF
GND
R44
10kΩ
R39
25kΩ
AMP
C34
0.1µF
R40
25kΩ
R45
25kΩ
R47
25kΩ
PWUP
VOCM 10
RGP1
INHI
3
INLO
VPOS 9
OPHI 8
2
OPLO
4
AMP IN
GND
U2
AD8351
1
C33
0.1µF
C37
0.1µF
GND
5
RPG2
R49
0Ω
C39
0.1µF
AMPINB
7
COMM 6
GND
R48
0Ω
C40
0.1µF
AMPIN
R46
1.2kΩ
Figure 47. Evaluation Board Schematic (continued)
Rev. A | Page 24 of 28
04530-0-053
R22
100Ω
JN00158
04530-0-049
AD9411
04530-0-048
04530-0-050
Figure 50. PCB Ground Layer
Figure 48. PCB Top Side Silkscreen
Figure 51. PCB Split Power Plane
Figure 49. PCB Top Side Copper Routing
Rev. A | Page 25 of 28
04530-0-051
04530-0-052
AD9411
Figure 52. PCB Bottom Side Copper Routing
Figure 53. PCB Bottom Side Silkscreen
Rev. A | Page 26 of 28
AD9411
OUTLINE DIMENSIONS
0.75
0.60
0.45
16.00 SQ
1.20
MAX
14.00 SQ
100
1
76
76
75
100
1
75
SEATING
PLANE
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
25
26
0.20
0.09
51
50
25
50
1.05
1.00
0.95
7°
3.5°
0°
0.50 BSC
0.27
0.22
0.17
0.15
0.05
26
6.50
NOM
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MS-026AED-HD
NOTES
1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.
2. THE AD9411 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 54. 100-Lead Thin Plastic Quad Flat Package, Exposed Pad [TQFP/EP]
(SV-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9411BSV-170
AD9411BSV-200
AD9411/PCB
Temperature
Range
–40°C to +85°C
–40°C to +85°C
Package Description
TQFP/EP
TQFP/EP
EVALUATION BOARD
Rev. A | Page 27 of 28
Package Option
SV-100
SV-100
AD9411
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04530-0-7/04(A)
Rev. A | Page 28 of 28