DS64MB201
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SNLS307E – JANUARY 2011 – REVISED JULY 2013
DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and
De-Emphasis
Check for Samples: DS64MB201
FEATURES
DESCRIPTION
•
The DS64MB201 is a dual lane 2:1 multiplexer and
1:2 switch or fan-out buffer with signal conditioning
suitable for SATA/SAS and other high-speed bus
applications up to 6.4 Gbps. The device performs
both receive equalization and transmit de-emphasis,
allowing maximum flexibility of physical placement
within a system. The receiver's continuous time linear
equalizer (CTLE) provides a boost of up to +33 dB at
3 GHz and is capable of opening an input eye that is
completely closed due to inter-symbol interference
(ISI) induced by the interconnect medium. The
transmitter features a programmable output deemphasis driver and allows amplitude voltage levels
to be selected from 600 mVp-p to 1200 mVp-p to suit
multiple application scenarios. The signal conditioning
settings are programmable via control pin settings or
SMBus interface.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
Up to 6.4 Gbps dual lane 2:1 mux, 1:2 switch
or fan-out
Adjustable receive equalization up to +33 dB
gain
Adjustable transmit de-emphasis up to −12 dB
Adjustable transmit VOD
<0.25 UI of residual DJ at 6.4 Gbps with 40”
FR4 trace
SATA/SAS: OOB signal pass-through
Adjustable electrical IDLE detect threshold
Low power
Signal conditioning programmable via pin
selection or SMBus interface
Single 2.5V supply operation
>6 kV HBM ESD Rating
3.3V tolerant SMBus interface
High speed signal flow–thru pinout package:
54-pin WQFN (10 mm x 5.5 mm)
APPLICATIONS
•
•
•
•
•
•
SAS and SATA (1.5, 3.0 and 6 Gbps)
XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
sRIO – Serial Rapid I/O
Fibre Channel (4.25 Gbps)
10GBase-CX4, InfiniBand (SDR & DDR)
FR-4 backplane traces
To enable seamless upgrade from SAS/SATA 3.0
Gbps to 6.0 Gbps data rates without compromising
physical reach, DS64MB201 automatically detects
the incoming data rate and selects the optimal deemphasis pulse width. The device detects the out-ofband (OOB) idle and active signals of the SAS/SATA
specification and passes through with minimum signal
distortion.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
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Typical Application
DS64MB201
SEL0
HDD0
RX
Cs > 10 nF
2
Cs > 10 nF
2
SIB0+-
2
SIA1+-
2
SIB1+-
2
TXA
DOUT0+-
2
TX
SIA0+-
TXB
TXA
DOUT1+-
TXB
HDD1
RX
SATA/SAS
Controller
2
SOA0+-
2
DIN0+-
TX
2
SOB0+-
RXA
2
SOA1+-
2
SOB1+-
2
DIN1+-
RXB
RXA
RXB
SEL1
Figure 1.
2
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SNLS307E – JANUARY 2011 – REVISED JULY 2013
GND
VDD
DEMB/SCL
EQB/SDA
ENSMB
DEMA/AD2
EQA/AD3
51
50
49
48
47
46
EQD/AD1
53
52
DEMD/AD0
54
Pin Diagram
SMBUS AND CONTROL
NC
1
45
SIA0+
NC
2
44
SIA0-
DOUT0+
3
43
SIB0+
DOUT0-
4
42
SIB0-
NC
5
41
VDD
NC
6
40
SIA1+
DOUT1+
7
39
SIA1-
DOUT1-
8
38
SIB1+
37
SIB1-
TOP VIEW
DAP = GND
VDD
14
32
SOB0-
DIN1+
15
31
SOA1+
DIN1-
16
30
SOA1-
NC
17
29
SOB1+
NC
18
28
SOB1-
27
SOB0+
SD_TH
33
26
13
FANOUT
NC
25
SOA0-
TXIDLESO
34
24
12
TXIDLEDO
NC
23
SOA0+
VOD1
35
22
11
VOD0
DIN0-
21
VDD
RATE
36
20
10
SEL1
DIN0+
19
9
SEL0
VDD
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Figure 2. DS64MB201 Pin Diagram 54L WQFN
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Table 1. Pin Descriptions
Pin Name
Pin Number
I/O, Type
(1)
Pin Description
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip
50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD when
enabled.
SOA0+, SOA0-,
SOA1+, SOA1-
35, 34,
31, 30
O
Inverting and non-inverting low power differential signaling 50Ω outputs with deemphasis. Fully compatible with AC coupled CML inputs.
SIB0+, SIB0-,
SIB1+, SIB1-
43, 42,
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip
50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD when
enabled.
SOB0+, SOB0-,
SOB1+, SOB1-
33, 32,
29, 28
O
Inverting and non-inverting low power differential signaling 50Ω outputs with deemphasis. Fully compatible with AC coupled CML inputs.
DIN0+, DIN0-,
DIN1+, DIN1-
10, 11,
15, 16
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip
50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD when
enabled.
DOUT0+, DOUT0-,
DOUT1+, DOUT1-
3, 4,
7, 8
O
Inverting and non-inverting low power differential signaling 50Ω outputs with deemphasis. Fully compatible with AC coupled CML inputs.
I, LVCMOS w/
internal pulldown
System Management Bus (SMBus) enable pin.
HIGH = Register Access: Provides access to internal digital registers to control
such functions as equalization, de-emphasis, VOD, rate, channel powerdown, and
idle detection threshold.
LOW = Pin Mode: Access to the SMBus registers are disabled and control pins are
used to program VOD, rate, idle detection, equalization and de-emphasis settings.
Please refer to System Management Bus (SMBus) and Configuration Registers
section and Electrical Characteristics — Serial Management Bus Interface for
detailed information.
Control Pins — Shared (LVCMOS)
ENSMB
48
ENSMB = 1 (SMBUS MODE)
SDA, SCL
49, 50
I, LVCMOS
ENSMB = 1
The SMBus SDA (data input/output bi-directional) and SCL (clock input) pins are
enabled.
AD[3:0]
54, 53, 47, 46
I, LVCMOS w/
internal pulldown
ENSMB = 1
SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus
slave address inputs.
ENSMB = 0 (NORMAL PIN MODE)
EQA,
EQB,
EQD
46,
49,
53
I, Float,
LVCMOS
EQA/B/D, 3–level input controls the level of equalization.
EQA controls the level of equalization of the SIA0 and SIA1 inputs.
EQB controls the level of equalization of the SIB0 and SIB1 inputs.
EQD controls the level of equalization of the DIN0 and DIN1 inputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes high the SMBus control registers provide independent control
of each lane. See Table 2
DEMA,
DEMB,
DEMD
47,
50,
54
I, Float,
LVCMOS
DEMA/B/D, 3–level input controls the level of de-emphasis.
DEMA controls the level of de-emphasis of the SOA0 and SOA1 outputs.
DEMB controls the level of de-emphasis of the SOB0 and SOB1 outputs.
DEMD controls the level of de-emphasis of the DOUT0 and DOUT1 outputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes High the SMBus control registers provide independent control
of each lane. See Table 3
Control Pins — Both Modes (LVCMOS)
RATE
(1)
4
21
I, Float,
LVCMOS
RATE, 3–level input controls the pulse width of de-emphasis of the output.
RATE = 0 forces ~3 Gbps,
RATE = 1 forces ~6 Gbps,
RATE = Float enables auto rate detection. See Table 3
1 = HIGH, 0 = LOW, FLOAT = 3rd input state. FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pullup/pull-down. Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input. Input edge rate for
LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
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Table 1. Pin Descriptions (continued)
Pin Name
Pin Number
I/O, Type (1)
Pin Description
TXIDLEDO
24
I, Float,
LVCMOS
TXIDLEDO, 3–level input controls the driver output.
TXIDLEDO = 0 disables the signal detect/squelch function for DOUT.
TXIDLEDO = 1 forces the DOUT to be muted (electrical idle).
TXIDLEDO = Float enables the signal auto detect/squelch function for DOUT and
the signal detect voltage threshold level can be adjusted using the SD_TH pin. See
Table 4
TXIDLESO
25
I, Float,
LVCMOS
TXIDLESO, 3–level input controls the driver output.
TXIDLESO = 0 disables the signal detect/squelch function for SOUT.
TXIDLESO = 1 forces the SOUT to be muted (electrical idle).
TXIDLESO = Float enables the signal auto detect/squelch function for SOUT and
the signal detect voltage threshold level can be adjusted using the SD_TH pin. See
Table 4
FANOUT
26
I, LVCMOS w/
internal pulldown
FANOUT = 1 enables both A/B outputs for broadcast mode.
FANOUT = 0 disables one of the outputs depending on the SEL0, SEL1 pin. See
Table 6
SEL0, SEL1
19, 20
I, LVCMOS w/
internal pulldown
SEL0 is for lane 0, SEL1 is for lane 1
SEL0, SEL1 = 0 selects B input and B output.
SEL0, SEL1 = 1 selects A input and A output. See Table 6
VOD0, VOD1
22, 23
I, LVCMOS w/
internal pulldown
VOD[1:0] adjusts the output differential amplitude voltage level on all outputs.
00 set output VOD = 600 mVp-p (Default)
01 sets output VOD = 800 mVp-p
10 sets output VOD = 1000 mVp-p
11 sets output VOD = 1200 mVp-p
Note: VOD should be set to a minimum of 1000 mV to achieve stated DE levels.
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for default 130
mVp-p (differential).
See Table 5
VDD
9, 14, 36, 41,
51
Power
2.5V Power supply pins.
GND
DAP, 52
Power
DAP is the large metal contact at the bottom side, located at the center of the 54
pin WQFN package. It should be connected to the GND plane with at least 4 via to
lower the ground impedance and improve the thermal performance of the package.
NOTE: DAP is the primary GND
NC
1, 2, 5, 6, 12,
13, 17, 18
Analog
SD_TH
Power
No Connect — Leave pin open
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings
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(1) (2)
Supply Voltage (VDD)
-0.5V to +3.0V
LVCMOS Input/Output Voltage
-0.5V to +4.0V
Differential Input Voltage
-0.5V to (VDD+0.5V)
Differential Output Voltage
-0.5V to (VDD+0.5V)
Analog (SD_TH)
-0.5V to (VDD+0.5V)
Junction Temperature
+125°C
Storage Temperature
-40°C to +125°C
Maximum Package Power Dissipation at
25°C
NJY Package
4.21 W
Derate NJY Package
52.6mW/°C above +25°C
ESD Rating
HBM, STD - JESD22-A114C
≥6 kV
MM, STD - JESD22-A115-A
≥250 V
≥1250 V
CDM, STD - JESD22-C101-C
Thermal Resistance
θJC
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
19.1°C/W
For soldering specifications:
See product folder at http://www.ti.com/lit/SNOA549
(1)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are ensured for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office / Distributors for
availability and specifications.
(2)
Recommended Operating Conditions
Min
Typ
Max
Units
2.375
2.5
2.625
V
-40
25
+85
°C
3.6
V
Supply Voltage
VDD to GND
Ambient Temperature (1)
SMBus (SDA, SCL)
0
CML Differential Input Voltage
0
Supply Noise Tolerance up to 50 MHz (2)
(1)
(2)
2.0
Vp-p
100
mVP-P
OOB signal pass-through limited to a minimum ambient temperature of -10C
Allowed supply noise (mVP-P sine wave) under typical conditions.
Electrical Characteristics
Over recommended operating supply and temperature ranges with default register settings unless other specified. (1)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
850
950
mW
11
mW
POWER
PD
Power Dissipation
2.5V Operation
EQx = 0, DEMx = 0 dB,
K28.5 pattern,
VOD = 1.0 V p-p
Channel powerdown (2)
LVCMOS / LVTTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
3.6
V
VIL
Low Level Input Voltage
0
0.8
V
IIH
Input High Current
-15
+15
μA
(1)
(2)
6
VIN = 3.3V
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Measured with ENSMB = 1, all channels disabled using SMBus registers 0x01 and 0x02, and EQ in bypass (Default)
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.(1)
Symbol
IIL
Parameter
Input Low Current
Conditions
VIN = 0V
Min
Typ
-15
Max
Units
+15
μA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-DIFF
Rx Differential Return Loss
(SDD11) (3)
150 MHz – 1.5 GHz
-20
150 MHz – 3.0 GHz
-13.5
dB
150 MHz – 6.0 GHz
-8
RLRX-CM
Rx Common Mode Input Return
Loss (SCC11)
150 MHz – 3.0 GHz
See (3)
-10
dB
RRX-IB
Rx Impedance Balance (SDC11)
150 MHz – 3.0 GHz
See (3)
-27
dB
IIN
Maximum current allowed at IN+ or
IN- input pin.
RIN
Input Resistance
RITD
−30
Single ended to VDD
See (3)
+30
mA
Ω
50
(3)
Input Differential Impedance
between
IN+ and IN-
See
RITIB
Input Differential Impedance
Imbalance
See
(3)
RICM
Input Common Mode Impedance
See
(4)
VRX-DIFF
Differential Rx peak to peak
voltage
DC voltage,
SD_TH = 20 kΩ to GND
VRX-SD_TH
Electrical Idle detect threshold
(differential)
115
Ω
5
Ω
40
Ω
0.1
1.2
V
SD_TH = Float
See (5) and Figure 7
40
175
mVp-p
RL = 50 Ω ±1% to GND (AC coupled with 10
nF), 6.4 Gbps
DEMA = DEMB = 0 dB,
VOD1–0 = 00
See (6)
500
600
700
mVP-P
VOD1–0 = 11
1100
1265
1450
mVP-P
85
20
100
25
DIFFERENTIAL OUTPUTS (OUT_n+, OUT_n-)
VOD
Output Differential Voltage Swing
with de-emphasis disabled
VOCM
TTX-RF
Output Common-Mode Voltage
Transmitter Rise/ Fall Time
Single-ended measurement DC-Coupled with
50Ω termination
See (4)
20% to 80% of differential output voltage,
measured within 1” from output pins
See (4), (6), and Figure 3
VDD –
1.4
65
TRF-DELTA
Tx rise/fall mismatch
20% to 80% of differential output voltage
See (4) and (6)
RLTX-DIFF
Tx Differential Return Loss
(SDD22)
See (4)
Repeating 1100b (D24.3) pattern,
VOD = 1.0 Vp-p,
150 MHz – 1.5 GHz
-11
1.5 GHz – 3.0 GHz
-10
3 GHz – 6.0 GHz
-5
Repeating 1100b (D24.3) pattern,
VOD = 1.0 Vp-p,
50 MHz – 3.0 GHz
See (4)
-10
RLTX-CM
(3)
(4)
(5)
(6)
Tx Common Mode Return Loss
(SCC22)
V
85
ps
0.1
UI
dB
dB
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
Measured at package pins of receiver. Less than 65 mVp-p is IDLE, greater than 175 mVp-p is ACTIVE. SD_TH pin connected with
resistor to GND overrides this default setting.
Measured with clock-like {11111 00000} pattern.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.(1)
Symbol
RTX-IB
Parameter
Tx Impedance Balance
(SDC22)
ITX-SHORT
Conditions
Min
Repeating 1100b (D24.3) pattern,
VOD = 1.0 Vp-p,
50 MHz – 3.0 GHz
See (4)
Typ
-30
Tx Output Short Circuit Current
Limit
ROTD
Output Differential Impedance
between OUT+ and OUT-
See
(4)
ROTIB
Output Differential Impedance
Imbalance
See
(4)
(4)
Max
85
90
mA
125
Ω
5
Ω
35
Ω
±40
mV
Output Common Mode Impedance
See
VTX-CM-DELTA
Common Mode Voltage Delta
between active burst and electrical
Idle of an OOB signal
Minimum Temperature for OOB signal passthrough is -10C.
VIN = 800 mVp-p, at 3 Gbps,
See (7)
Max time to transition to valid
electrical idle after leaving active
burst in OOB signaling
Minimum Temperature for OOB signal passthrough is -10C.
VIN = 800 mVp-p, at 3 Gbps,
See Figure 5
6.5
9.5
ns
Max time to transition to valid
active burst after leaving idle in
OOB signaling
Minimum Temperature for OOB signal passthrough is -10C.
VIN = 800 mVp-p, at 3 Gbps,
See Figure 5
5.5
8.0
ns
150
200
250
ps
120
170
TID
TPD
Differential Propagation Delay (Low Propagation delay measure at midpoint
to High and High to Low Edge
crossing between input to outputEQx[1:0] =
11, DEMx[1:0] = —6 dB
See Figure 4
EQz[1:0] = OFF, DEMx[1:0] = 0 dB
25
dB
ROCM
TDI
20
100
Units
220
ps
TLSK
Lane to Lane Skew in a Single Part VDD = 2.5V, TA = 25C
27
ps
TPPSK
Part to Part Propagation Delay
Skew
VDD = 2.5V, TA = 25C
35
ps
TSM
Switch/Mux Time
Time to switch/mux between A and B
input/output signals
150
ns
EQUALIZATION
DJ1
Residual Deterministic Jitter at 6.4
Gbps
DJ2
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, 40” 4–mil FR4 trace,
ENSMB = 1, EQ setting = 0x3B, DEMx[1:0] =
0dB, VOD = 1.0 Vp-p, K28.5, SD_TH = float
See (8)
0.12
0.25
UIP-P
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, 40” 4–mil FR4 trace,
EQ setting = 0x3C, DEMx[1:0] = 0dB, VOD =
1.0 Vp-p, K28.5, SD_TH = float
See (8)
0.05
0.125
UIP-P
Random Jitter
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, Repeating 1100b (D24.3) pattern
0.5
Residual Deterministic Jitter at 6.4
Gbps
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, 10” 4–mil FR4 trace,
EQx = off, DEMx = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 1
See (8)
0.09
Residual Deterministic Jitter at 3.2
Gbps
RJ
psrms
DE-EMPHASIS
DJ3
(7)
(8)
8
0.20
UIP-P
Common-mode voltage (VCM) is expressed mathematically as the average of the two signal voltages with respect to local ground.VCM
= (A + B) / 2, A = OUT+, B = OUT-.
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not ensured.
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.(1)
Symbol
DJ4
Parameter
Residual Deterministic Jitter at 3.2
Gbps
Conditions
Min
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, 20” 4–mil FR4 trace,
EQx = off, DEMx = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 0
See (8)
Typ
Max
Units
0.07
0.18
UIP-P
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
2.1
High Power Specification
See
(1)
(1)
4
mA
2.375
3.6
V
-200
+200
µA
-15
CI
Capacitance for SDA and SDC
See
RTERM
External Termination Resistance
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
VDD3.3,
See (1),
and
(2)
(2)
, and
VDD2.5,
(1) (2)
, , and
µA
10
(3)
(3)
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 6
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
See
(4)
10
100
kHz
4.7
µs
4.0
µs
4.7
µs
At IPULLUP, Max
TSU:STA
Repeated Start Condition Setup
Time
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
ns
TTIMEOUT
Detect Clock Low Timeout
TLOW
Clock Low Period
THIGH
Clock High Period
See
(4)
TLOW:SEXT
Cumulative Clock Low Extend Time See
(Slave Device)
(4)
tF
Clock/Data Fall Time
See
(4)
tR
Clock/Data Rise Time
See
(4)
See
(4)
500
ms
tPOR
(1)
(2)
(3)
(4)
Time in which a device must be
operational after power-on reset
See
(4)
25
35
4.7
4.0
ms
µs
50
µs
2
ms
300
ns
1000
ns
Recommended value. Parameter not tested in production.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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Timing Diagrams
Figure 3. LPDS Output Transition Times
Figure 4. Propagation Delay Timing Diagram
Figure 5. Idle Timing Diagram
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 6. SMBus Timing Parameters
10
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Functional Description
The DS64MB201 is a 2–lane signal conditioning 2:1 multiplexer and 1:2 switch or fan-out buffer optimized for
PCB FR4 trace and cable interconnects up to 6 Gbps data rate. The DS64MB201 operates in two modes: Pin
Control Mode (ENSMB = 0) and SMBus Mode (ENSMB = 1).
Pin Control Mode:
When in pin mode (ENSMB = 0) , the transceiver is configurable with external pins. Equalization and deemphasis can be selected via pin for each side independently. When de-emphasis is asserted VOD is
automatically increased per the De-Emphasis table below for improved performance over lossy media. Rate
optimization is also pin controllable, with pin selections for 3 Gbps, 6 Gbps, and auto detect. The receiver
electrical idle detect threshold is also programmable via an optional external resistor on the SD_TH pin.
SMBUS Mode:
When in SMBus mode the VOD amplitude level, equalization and de-emphasis are all programmable on a
individual lane basis, instead of grouped by sides as in the pin mode case. Upon assertion of ENSMB pins EQx
and DEMx functions revert to register control immediately. The EQx and DEMx pins are converted to AD0-AD3
SMBus address pins. The other external control pins remain active unless their respective registers are written
to, in which case they are ignored until ENSMB is driven low. On power-up and when ENSMB is driven low all
registers are reset to their default state.
Table 2. Equalization Input Select Pins for SIA, SIB and DIN (3–Level Input)
(1)
EQA, EQB, EQD (1)
Equalization Level
0
9 dB at 3 GHz
Float (No Connect)
13.5 dB at 3 GHz
1
18.4 dB at 3 GHz
F = Float (No Connect), 1 = High and 0 = Low.
Table 3. De-Emphasis Input Select Pins for SOA, SOB and DOUT (3–Level Input)
RATE (1)
DEMA,
DEMB,
DEMD
De-Emphasis
Level (typ)
DE Pulse Width
(typ)
VOD (typ)
0/F
0
-3.5 dB
330 ps
VOD = 1000 mVp-p
-2 dB
330 ps
VOD = 1200 mVp-p
-6 dB
330 ps
VOD = 1000 mVp-p
-3 dB
330 ps
VOD = 1200 mVp-p
-3.5 dB
200 ps
VOD = 1000 mVp-p
-2 dB
200 ps
VOD = 1200 mVp-p
-6 dB
200 ps
VOD = 1000 mVp-p
-3 dB
200 ps
VOD = 1200 mVp-p
0/F
(1)
1
1/F
0
1/F
1
0/F
F
-9 dB
250 ps enhanced
VOD = 1200 mVp-p
1/F
F
-12 dB
160 ps enhanced
VOD = 1200 mVp-p
F = Float (No Connect), 1 = High and 0 = Low. Enhanced DE pulse width provides de-empahsis on second bit. When RATE = F (auto
rate detection active), the DE level and pulse width settings follow detected rate. RATE = 0 is 3 Gbps and RATE = 1 is 6 Gbps. Deemphasis should only be used with VOD = 1000 mVp-p or 1200 mVp-p. VOD less then 1000 mVp-p is not recommended with deemphasis. Please refer to VOD1 and VOD0 pin description to set the output differential voltage level.
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Table 4. Idle Control (3–Level Input)
TXIDLEDO/SO
Function
0
This state is for lossy media, dedicated Idle threshold detect circuit disabled, output follows input based
on EQ settings. Idle state not ensured.
Float
Float enables automatic idle detection. Idle on the input is passed to the output. Internal 50KΩ resistors
hold TXIDLEDO/SO pin at a mid level - don't connect this pin if the automatic idle detect function is
desired. This is the default state. Output in Idle if differential input signal less than value set by SD_TH
pin.
1
Manual override, output in electrical Idle. Differential inputs are ignored.
Table 5. Receiver Electrical Idle Detect Threshold Adjust
Receiver Electrical Idle Detect Threshold (DIFF p-p)
Float (no resistor required)
130 mV (default condition)
0
225 mV
80k
20 mV
SD_TH resistor value can be set from 0 through 80k ohms to achieve desired idle detect threshold, see Figure 7
ELECTRICAL IDLE DETECT THRESHOLD
(DIFF mVp-p)
(1)
SD_TH resistor value (Ω) (1)
250
VDD = 2.5V
TA = 25°C
200
150
100
50
0
0
10k 20k 30k 40k 50k 60k 70k 80k
SD_TH RESISTOR VALUE (:)
Figure 7. Typical Idle Threshold vs. SD_TH resistor value
12
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Device Connection Paths
The lanes of the DS64MB201 can be configured either as a 2:1 multiplexer, 1:2 switch or fan-out buffer. The
controller side is muxed to the disk drive side. The below table shows the logic for the multiplexer and switch
functions.
Table 6. Logic Table of Switch and Mux Control
FANOUT
SEL0
SEL1
Function — connection path
0
0
0
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
0
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
0
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
0
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
1
0
0
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOB1 and SOA1.
1
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOA1 and SOB1.
1
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOB1 and SOA1.
1
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOA1 and SOB1.
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System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be
pulled high to enable SMBus mode and allow access to the configuration registers.
The DS64MB201 has the AD[3:0] inputs in SMBus mode. These pins set the SMBus slave address inputs. The
AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device default
address byte is A0'h. Based on the SMBus 2.0 specification, the DS64MB201 has a 7-bit slave address of
1010000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The bold bits
indicate the AD[3:0] pin map to the slave address bits [4:1]. The device address byte can be set with the use of
the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDC and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not
5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus Transactions
The device supports WRITE and READ transactions. See Table 8 for register address, type (Read/Write, Read
Only), default value and function information.
When SMBus is enabled, all outputs of the DS64MB201 must use one of the following De-emphasis settings
(Table 7). The driver de-emphasis value is set on a per lane basis using 6 different registers. Each register
(0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode.
The VOD for each output should be set via register write or pin control to be a minimum of 1000 mV.
Table 7. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value
Register Setting
3 Gbps Operation
6 Gbps Operation
0.0 dB
0x01
10” trace or 1 meter 28 awg cable
5” trace or 0.5 meter 28 awg cable
-3.5 dB
0xE8
20” trace or 2 meters 28 awg cable
10” trace or 1meters 28 awg cable
-6 dB
0x88
25” trace or 3 meters cable
20” trace or 2 meters cable
-9 dB
0x90
5 meters 28 awg cable
3 meters 28 awg cable
-12 dB
0xA0
8 meters 28 awg cable
5 meters 28 awg cable
Writing a Register
To
1.
2.
3.
4.
5.
14
write a register, the following protocol is used (see SMBus 2.0 specification).
The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
The Host drive the 8-bit data byte.
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6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Recommended SMBus Register Settings
When SMBus mode is enabled (ENSMB = 1), the default register settings are not configured to an appropriate
level. Below is the recommended settings to configure the EQ, VOD and DE to a medium level that supports
interconnect length of 20 inches FR4 trace or 3 to 5 meters of cable length. Please refer to Table 2, Table 3,
Table 7, Table 8 for additional information and recommended settings.
1. Reset the SMBus registers to default values:
– Write 01'h to 0x00.
2. Set de-emphasis to -6 dB for all lanes:
– Write 88'h to 0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization to external pin level EQ[1:0] = 00 (~9 dB at 3 GHz) for all lanes:
– Write 30'h to 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x3A.
4. Set VOD = 1.0 Vp-p for all lanes:
– Write 0F'h to 0x17, 0x25, 0x2D, 0x34, 0x3B, 0x42.
Table 8. SMBus Register Map
Address
Register Name
Bit (s) Field
Type
Default
Description
0x00
Reset
7:1
Reserved
R/W
0x00
Set bits to 0.
0
Reset
7:0
PWDN CHx
0x01
PWDN lanes
SMBus Reset
1: Reset registers to default value
R/W
0x00
Power Down per lane
[7]: NC — SOB1
[6]: DIN1 — SOA1
[5]: NC — SOB0
[4]: DIN0 — SOA0
[3]: SIB1 — DOUT1
[2]: SIA1 — NC
[1]: SIB0 — DOUT0
[0]: SIA0 — NC
00'h = all lanes enabled
FF'h = all lanes disabled
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Table 8. SMBus Register Map (continued)
0x02
0x03
0x08
0x0F
0x12
0x15
16
PWDN Control
7:1
Reserved
0
PWDN Control
7:3
Reserved
2
SEL1
0: Selects SIB1 input and SOB1 output
1: Selects SIA1 input and SOA1 output
1
SEL0
0: Selects SIB0 input and SOB0 output
1: Selects SIA0 input and SOA0 output
0
FANOUT
0: Enable only A or B output depends on SEL1 and
SEL0 (SeeTable 6)
1: Enable both SOAn and SOBn output
7:5
Reserved
4
Override IDLE
0: Allow IDLE pin control
1: Block IDLE pin control
3
Reserved
Set bit to 0.
2
Override RATE
0: Allow RATE pin control
1: Block RATE pin control
1
Override SEL
0: Allow SEL pin control
1: Block SEL pin control
0
Override
FANOUT
0: Allow FANOUT pin control
1: Block FANOUT pin control
SIA0
EQ Control
7:6
Reserved
5:0
SIA0 EQ
SIA0
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
DOUT0
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
SEL / FANOUT
Control
Pin Control Override
R/W
0x00
Set bits to 0.
0: Normal operation
1: Enable PWDN control in Register 0x01
R/W
R/W
R/W
0x00
0x00
0x20
Set bits to 0.
Set bits to 0.
Set bits to 0.
SIA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
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Table 8. SMBus Register Map (continued)
0x16
SIB0
EQ Control
7:6
Reserved
5:0
SIB0 EQ
DOUT0
VOD Control
7
Reserved
6:0
DOUT0 VOD
0x18
DOUT0
DE Control
7:0
DOUT0 DEM
R/W
0x03
DOUT0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x19
SIB0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SIA1
EQ Control
7:6
Reserved
5:0
SIA1 EQ
SIA1
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
0x17
0x1D
0x20
R/W
0x20
Set bits to 0.
SIB0 Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x20
Set bits to 0.
SIA1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
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Table 8. SMBus Register Map (continued)
0x23
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
SIB1
EQ Control
7:6
Reserved
5:0
SIB1 EQ
DOUT1
VOD Control
7
Reserved
6:0
DOUT1 VOD
0x26
DOUT1
DE Control
7:0
DOUT1 DEM
R/W
0x03
DOUT1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x27
SIB1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOA0
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
0x24
0x25
0x2B
18
DOUT1
IDLE RATE Select
R/W
R/W
0x00
0x20
Set bits to 0.
Set bits to 0.
SIB1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
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Table 8. SMBus Register Map (continued)
0x2C
DIN0
EQ Control
7:6
Reserved
5:0
DIN0 EQ
SOA0
VOD Control
7
Reserved
6:0
SOA0 VOD
0x2E
SOA0
DE Control
7:0
SOA0 DEM
R/W
0x03
SOA0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x2F
DIN0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOB0
IDLE RATE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
7
Reserved
6:0
SOB0 VOD
0x2D
0x32
0x34
SOB0
VOD Control
R/W
0x20
Set bits to 0.
DIN0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
R/W
0x00
0x03
Set bits to 0.
Set bit to 0.
SOB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
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DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
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Table 8. SMBus Register Map (continued)
0x35
SOB0
DE Control
7:0
SOB0 DEM
R/W
0x03
SOB0 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x39
SOA1
IDLE RATE Select
7:6
Reserve
R/W
0x00
Set bits to 0.
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
DIN1
EQ Control
7:6
Reserved
5:0
DIN1 EQ
SOA1
VOD Control
7
Reserved
6:0
SOA1 VOD
0x3C
SOA1
DE Control
7:0
SOA1 DEM
R/W
0x03
SOA1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x3D
DIN1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
0x3A
0x3B
20
R/W
0x20
Set bits to 0.
DIN1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
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SNLS307E – JANUARY 2011 – REVISED JULY 2013
Table 8. SMBus Register Map (continued)
0x40
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:2
Reserved
Set bits to 0.
1
RATE auto
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0
RATE select
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
SOB1
VOD Control
7
Reserved
6:0
SOB1 VOD
0x43
SOB1
DE Control
7:0
SOB1 DEM
R/W
0x03
SOB1 DEM Control
[7]: DEM TYPE (Compatibility = 0 / Enhanced = 1)
[6:0]: DEM Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h = 0.0 dB
00111000 = E8'h = −3.5 dB
10001000 = 88'h = −6.0 dB
10010000 = 90'h = −9.0 dB
10100000 = A0'h = −12.0 dB
0x47
Global VOD Adjust
7:2
Reserved
R/W
0x02
Set bits to 0.
1:0
VOD Adjust
0x42
SOB1
IDLE RATE Select
R/W
R/W
0x00
0x03
Set bits to 0.
Set bit to 0.
SOB1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = 1200 mV
3F'h = Reserved
00
01
10
11
= -25.0%
= -12.5%
= +0.0% (Default)
= +12.5%
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DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
www.ti.com
Typical Performance
Unless otherwise noted, Typical Performance is measured at room temperature and nominal supply voltage.
Datarate: 6.4 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 3B'h
Figure 8. Electrical Specification DJ1: 40" 4-mil microstrip trace on Input
Datarate: 3.2 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 3C'h
Figure 9. Electrical Specification DJ2: 40" 4-mil microstrip trace on Input
22
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SNLS307E – JANUARY 2011 – REVISED JULY 2013
Typical Performance (continued)
Unless otherwise noted, Typical Performance is measured at room temperature and nominal supply voltage.
Datarate: 6.4 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 20'h (Bypass) and DE Setting = 88'h
Figure 10. Electrical Specification DJ3: 10" 4-mil microstrip trace on Output
Datarate: 3.2 Gbps
Input Pattern: K28.5
Signal Conditioning: EQ Setting = 20'h (Bypass) and DE Setting = 88'h
Figure 11. Electrical Specification DJ4: 20" 4-mil microstrip trace on Output
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DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
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APPLICATIONS INFORMATION
General Recommendations
The DS64MB201 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity
design issues.
PCB Layout Considerations for Differential Pairs
The CML inputs and LPDS outputs must have a controlled differential impedance of 100Ω. It is preferable to
route differential lines exclusively on one layer of the board, particularly for the input traces. The use of vias
should be avoided if possible. If vias must be used, they should be used sparingly and must be placed
symmetrically for each side of a given differential pair. Route the differential signals away from other signals and
noise sources on the printed circuit board. See AN-1187 (SNOA401) for additional information on WQFN
packages.
Power Supply Bypassing
Two approaches are recommended to ensure that the DS64MB201 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01 μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS64MB201. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
24
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SNLS307E – JANUARY 2011 – REVISED JULY 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 24
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
DS64MB201SQ/NOPB
ACTIVE
WQFN
NJY
54
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS64MB201
SQ
DS64MB201SQE/NOPB
ACTIVE
WQFN
NJY
54
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS64MB201
SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS64MB201SQ/NOPB
WQFN
NJY
54
2000
330.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
DS64MB201SQE/NOPB
WQFN
NJY
54
250
178.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS64MB201SQ/NOPB
WQFN
NJY
54
2000
367.0
367.0
38.0
DS64MB201SQE/NOPB
WQFN
NJY
54
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
SEE TERMINAL
DETAIL
3.51±0.1
19
(0.1)
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
PIN 1 ID
(OPTIONAL)
46
54X
54X
0.5
0.3
0.3
0.2
0.1
0.05
C A
C
B
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54
54X (0.25)
SEE DETAILS
46
1
45
50X (0.5)
(7.5)
SYMM
(9.8)
(1.17)
TYP
2X
(1.16)
28
18
( 0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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