CS3310
Stereo Digital Volume Control
Features
z Complete
Description
Digital Volume Control
The CS3310 is a complete stereo digital volume control
designed specifically for audio systems. It features a 16bit serial interface that controls two independent, lowdistortion audio channels.
— 2 Independent Channels
— Serial Control
— 0.5 dB Step Size
z Wide
The CS3310 includes an array of well-matched resistors
and a low noise active output stage that is capable of
driving a 600 Ω load. A total adjustable range of 127 dB,
in 0.5 dB steps, is achieved through 95.5 dB of attenuation and 31.5 dB of gain.
Adjustable Range
— -95.5 dB Attenuation
— +31.5 dB Gain
z Low
Distortion & Noise
— 0.001% THD+N
— 116 dB Dynamic Range
The simple 3-wire interface provides daisy-chaining of
multiple CS3310's for multi-channel audio systems.
z Noise
Free Level Transitions
Crosstalk Better Than
110 dB
The device operates from ±5 V supplies and has an input/output voltage range of ±3.75 V.
z Channel-to-Channel
ORDERING INFORMATION
CS3310-KS
CS3310-KSZ, Lead Free
AINL
16
+
-
14
8
MUX
8
1
8
AGNDL
AGNDR
0° to 70° C
0° to 70° C
Control
Register
15
10
2
3
16
Serial to
Parallel
Register
8
8
7
6
16-pin Plastic SOIC
16-pin Plastic SOIC
AOUTL
MUTE
ZCEN
CS
SDATAI
SDATAO
SCLK
MUX
AINR
12
13
VA+
Cirrus Logic, Inc.
www.cirrus.com
11
+
9
VA-
4
5
VD+
DGND
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
AOUTR
SEPTEMBER '05
DS82F1
1
CS3310
ANALOG CHARACTERISTICS (TA = 25 °C, VA+, VD+ = 5 V ± 5%; VA- = -5V ± 5%; Rs = 0; RL =
2 kΩ; CL = 20 pF; 10 Hz to 20 kHz Measurement Bandwidth; unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
Unit
Step Size
-
0.5
-
dB
Gain Error (31.5 dB Gain)
-
±0.05
-
dB
Gain Matching Between Channels
-
±0.05
-
dB
DC Characteristics
Input Resistance
RIN
8
10
-
kΩ
Input Capacitance
CIN
-
10
-
pF
THD+N
-
0.001
.0025
%
110
116
-
dB
(VA-)+1.25
-
(VA+)-1.25
V
AC Characteristics
Total Harmonic Distortion plus Noise (V in = 2V rms, 1 kHz)
Dynamic Range
Input/Output Voltage Range
Output Noise
(Note 1)
-
4.2
8.4
µVrms
Digital Feedthrough (Peak Component)
(Note 2)
-80
-
-
dB
Interchannel Isolation (1 kHz)
(Note 2)
-100
-110
-
dB
-
0.25
0.75
mV
Load Capacitance
-
-
100
pF
Short Circuit Current
-
20
-
mA
2
-
-
MHz
Output Buffer
Offset Voltage
Unity Gain Bandwidth, Small Signal
(Note 1)
VOS
(Note 2)
Power Supplies
Supply Current (No Load, AIN = 0 V)
IA+
IAID+
-
7.0
7.0
450
9.0
9.0
800
mA
mA
µA
Power Consumption
PD
-
72
94
mW
PSRR
-
80
-
dB
Power Supply Rejection Ratio (250 Hz)
Notes: 1. Measured with input grounded and Gain = 1. Will increase as a function of Gain settings >1.
2. This parameter is guaranteed by design and/or characterization.
2
DS82F1
CS3310
DIGITAL CHARACTERISTICS
(TA = 25 °C, VA+ , VD+ = 5V ± 5%, VA- = -5V ± 5% )
Parameter
Symbol
Min
Typ
Max
Unit
High-Level Input Voltage
VIH
2.0
-
VD+0.3
V
Low-Level Input Voltage
VIL
-0.3
-
+0.8
V
High-Level Output Voltage
(I O = 200µA)
VOH
VD-1.0
-
-
V
Low-Level Output Voltage
(I O = 3.2mA)
VOL
-
-
0.4
V
Iin
-
1.0
10
µA
Input Leakage Current
SWITCHING CHARACTERISTICS
(TA = 25 °C; VA+, VD+ = +5V ± 5%; VA- = -5V ± 5%; CL = 20 pF)
Parameter
Serial Clock
Symbol
Min
Typ
Max
Unit
SCLK
0
-
-
MHz
Serial Clock
Pulse Width High
Pulse Width Low
tph
tpl
80
80
-
-
ns
ns
MUTE
Pulse Width Low
-
2.0
-
-
ms
SDATAI Set Up Time
tSDVS
20
-
-
ns
SDATAI Hold Time
tSDH
20
-
-
ns
CS Valid to SCLK Rising
tCSVS
30
-
-
ns
SCLK Falling to CS High
tLTH
35
-
-
ns
CS Low to Output Active
tCSH
-
-
35
ns
SCLK Falling to Data Valid
tSSD
-
-
60
ns
tCSDH
-
-
100
ns
Input Timing
Output Timing
CS High to SDATAO Inactive
CS
t CSVS
t SDVS
t LTH
SCLK
t SDH
SDATAI
t CSDH
SDATAO
MSB
t CSH
t SSD
Figure 1. Serial Port Timing Diagram
DS82F1
3
CS3310
RECOMMENDED OPERATING CONDITIONS (DGND = 0V; all voltages with respect to ground)
Parameter
Symbol
Min
Typ
Max
Unit
VD+
VA+
VA
-
4.75
4.75
-4.75
-0.3
5.0
5.0
-5.0
-
VA+
5.25
-5.25
0.0
V
V
V
V
TA
0
25
70
°C
DC Power Supplies:
Positive Digital
Positive Analog
Negative Analog
(VD+) - (VA+) (Note 3)
Ambient Operating Temperature
Notes: 3. Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the
recommended power connections.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground.)
Parameter
Symbol
Min
Max
Unit
VD+
VA+
VA-
-0.3
-0.3
0.3
(VA+)+ 0.3
6.0
-6.0
V
V
V
Iin
-
±10
mA
VIND
-0.3
(VA+) + 0.3
V
TA
-55
+125
°C
TSTG
-65
+150
°C
DC Power Supplies:
Positive Digital
Positive Analog
Negative Analog
Input Current, Any Pin Except Supply
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
4
DS82F1
CS3310
**
10
10 µ F
+
0.1 µ F
1
ZCEN
4
12
VD+
+
0.1 µ F
+5V ANALOG
10 µ F
VA+
0.1 µ F
13
2
VA-
CS
3
CONTROLLER
0.1 µ F
SCLK
16
AUDIO
SOURCE
-5V ANALOG
CS3310
7
SDATAO
MUTE
*
AINL
AOUTL
9
+
SDATAI
6
8
10 µ F
14
11
AOUTR
AINR
DGND
AGNDL
AGNDR
5
15
10
47 kΩ
TO ANOTHER
CS3310 OR
CONTROLLER
AUDIO
OUTPUTS
*Required to terminate SDATAI due to high impedance
state of SDATAO when CS is high.
**Refer to Note 3.
Figure 2. Recommended Connection Diagram
DS82F1
5
CS3310
GENERAL DESCRIPTION
The CS3310 is a stereo, digital volume control designed for audio systems. The levels of the left
and right analog input channels are set by a 16-bit serial data word; the first 8 bits address the
right channel and the remaining 8 bits address the left channel, as detailed in Table 1. Resistor
values are decoded to 0.5 dB resolution by an internal multiplexer for a total attenuation range of
-95.5 dB. An output amplifier stage provides a programmable gain of up to 31.5 dB in 0.5 dB
steps. This results in an overall 8-bit adjustable range of 127 dB.
The CS3310 operates from ±5 V supplies and accepts inputs up to ±3.75 V. Once in operation,
the CS3310 can be brought to a muted state with the mute pin, MUTE, or by writing all zeros to
the volume control registers. The device contains a simple three wire serial interface which accepts 16-bit data. This interface also supports daisy-chaining capability.
SYSTEM DESIGN
Very few external components are required to support the CS3310. Normal power supply decoupling components are all that is required, as shown in Figure 2.
Serial Data Interface
The CS3310 has a simple, three wire interface that consists of three input pins: SDATAI, serial
data input; SCLK, serial data clock and CS, the chip select input. SDATAO, serial data output,
enables the user to read the current volume setting or provide daisy-chaining of multiple
CS3310’s.
The 16-bit serial data is formatted MSB first and clocked into SDATAI by the rising edge of SCLK
with CS low as shown in Figure 3. The data is latched by the rising edge of CS and the analog
output levels of both left and right channels are set. The existing data in the volume control data
register is clocked out SDATAO on the falling edge of SCLK. This data can be used to read current gain/attenuation levels or to daisy chain multiple CS3310’s. See Figure 1 for proper setup
and hold times for CS, SDATAI, SCLK, and SDATAO. SCLK and SDATAI should be active only
during volume setting operations to achieve optimum dynamic range.
Daisy Chaining
Digitally controlled, multi-channel audio systems often result in complex address decoding which
complicates PCB layout. This is greatly simplified with the daisy-chaining capability of the
CS3310.
6
DS82F1
CS3310
CS
SCLK
SDATAI
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
SDATAO
R7 R6 R5 R4 R3 R2 R1 R0 L7 L6 L5 L4 L3 L2 L1 L0
L0 = Left Channel Least Significant Bit
R0 = Right Channel Least Significant Bit
L7 = Left Channel Most Significant Bit
R7 = Right Channel Most Significant Bit
SDATAI is latched internally on the rising edge of SCLK
SDATAO transitions after the falling edge of SCLK
SDATAO bits reflect the data previously loaded into the CS3310
Figure 3. Serial Port Timing
In single device operation, volume control data is loaded into the 16-bit shift register by holding
the CS pin low for sixteen SCLK pulses and then latched on the rising edge of CS. The previous
contents of the shift-register are shifted through the register and out SDATAO during the process.
Multi-channel operation can be implemented as shown in Figure 4 by connecting the SDATAO
of device #1 to the SDATAI pin of device #2. In this manner multiple CS3310s can be loaded from
a single serial data line without complex addressing schemes. Volume control data is loaded by
holding CS low for 16 x N SCLK pulses, where N is the number of devices in the chain. The 16
bits clocked into device #1 on SCLK pulses 1-16 are clocked into device #2 on SCLK pulses 1732. The CS3310s are simultaneously updated on the rising edge of CS following 16 x N SCLK
pulses Notice that a 47 kohm resistor is required to terminate SDATAI, as shown in Figure 4, due
to the high impedance state of SDATAO when CS is high..
3
SDATAI
16
AUDIO
SIGNAL
9
SCLK
CS
AINL
6
CONTROLLER
2
CS3310
#1
AINR
AOUTL
AOUTR
SDATAO
14
11
7
47 k
3
SDATAI
16
AUDIO
SIGNAL
9
SCLK
CS
AINL
6
2
CS3310
#2
AINR
AOUTL
SDATAO
AOUTR
14
11
7
Figure 4. Daisy Chaining Diagram
DS82F1
7
CS3310
Changing the Analog Output Level
Care has been taken to ensure that there are no audible artifacts in the analog output signal during volume control changes. The gain/attenuation changes of the CS3310 occur at zero crossings to eliminate glitches during level transitions. The zero crossing for the left channel is the
voltage potential at the AGNDL pin; the voltage potential at the AGNDR pin defines the right
channel zero crossing.
A volume control change occurs after chip select latches the data in the volume control data register and two zero crossings are detected. If two zero crossings are not detected within 18 ms of
the change in CS, the new volume setting is implemented. The zero crossing enable pin, ZCEN,
enables or disables the zero crossing detection function as well as the 18 ms time-out circuit.
Input Code
(Left or Right Channel) Gain or Attenuation (dB)
11111111
11111110
•
•
11000000
•
00000010
00000001
00000000
+31.5
+31.0
•
•
0
•
-95.0
-95.5
Software Mute
Table 1. Input Code Definition
Analog Inputs and Outputs
The maximum input level is limited by the common-mode voltage capabilities of the internal opamp. Signals approaching the analog supply voltages may be applied to the AIN pins if the internal attenuator limits the output signal to within 1.25 volts of the analog supply rails.
The outputs are capable of driving 600 Ω loads to within 1.25 volts of the analog supply rails and
are short circuit protected to 20 mA.
As with any adjustable gain stage the affects of a DC offset at the input must be considered. Capacitively coupling the analog inputs may be required to prevent “clicks and pops” which occur
with gain changes if an appreciable offset is present.
Source Impedance Requirements
The CS3310 requires a low source impedance to achieve maximum performance. The ESD protection diodes on the analog input pins are reversed biased during normal operation. A characteristic of a reversed biased diode is a non-linear voltage dependent capacitance which can be
8
DS82F1
CS3310
a source of distortion if the source impedance becomes appreciable relative to the reversed biased diode capacitance. Source impedances equal to or less than 600 ohms will avoid this distortion mechanism for the CS3310.
Mute
Muting can be achieved by either hardware or software control. Hardware muting is accomplished via the MUTE input and software muting by loading all zeroes into the volume control register.
MUTE disconnects the internal buffer amplifiers from the output pins and terminates AOUTL and
AOUTR with 10 kΩ resistors to ground. The mute is activated with a zero crossing detection (independent of the zero cross enable status) or an 18 ms timeout to eliminate any audible “clicks”
or “pops”. MUTE also initiates an internal offset calibration.
A software mute is implemented by loading all zeroes into the volume control register. The internal amplifier is set to unity gain with the amplifier input connected to the maximum attenuation
point of the resistive divider, AGND.
A “soft mute” can be accomplished by sequentially ramping down from the current volume control
setting to the maximum attenuation code of all zeroes.
Power-Up Considerations
Upon initial application of power, the MUTE pin of the CS3310 should be set low to initiate a power-up sequence. This sequence sets the serial shift register and the volume control register to
zero and performs an offset calibration. The device should remain muted until the supply voltages have settled to ensure an accurate calibration. The device also includes an internal power-on
reset circuit that requires approximately 100 µs to settle and will ignore any attempts to address
the internal registers during this period.
The offset calibration minimizes internally generated offsets and ignores offsets applied to the
AIN pins. External clocks are not required for calibration.
Although the device is tolerant to power supply variation, the device will enter a hardware mute
state if the power supply voltage drops below approximately ±3.5 volts. A power-up sequence
will be initiated if the power supply voltage returns to greater than ±3.5 volts.
Applying power to VD+ prior to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the
recommended power connections.
DS82F1
9
CS3310
PCB Layout, Grounding and Power Supply Decoupling
As with any high performance device which contains both analog and digital circuitry, careful attention to power supply and grounding arrangements must be observed to optimize performance.
Figure 2 shows the recommended power arrangements with VA+ connected to a clean +5 volt
supply and VA- connected to a clean -5 volt supply. VD+ powers the digital interface circuitry and
should be powered from VA+, as shown in Figure 2, to avoid potentially destructive SCR latchup. Decoupling capacitors should be located as near to the CS3310 as possible, see Figure 5.
Figure 5. Recommended 2-Layer PCB Layout
Analog Ground Plane
10 Ω
10 µ F
+
10 µ F
+
VA+
VA10 µ F
+
0.1 µ F
0.1 µ F
0.1 µ F
The printed circuit board layout should have separate analog and digital regions with individual
ground planes. The CS3310 should reside in the analog region as shown in Figure 5. Care
should be taken to ensure that there is minimal resistance in the analog ground leads to the device to prevent any change in the defined attenuation settings. Extensive use of ground plane fill
on both the analog and digital sections of the circuit board will yield large reductions in radiated
noise effects.
Performance Plots
Figure 8 displays the CS3310 frequency response with a 3.75 Vp output.
Figure 9 shows the frequency response with a 0.375 Vp output.
Figure 6 is the Total Harmonic Distortion + Noise vs. amplitude at 1 kHz. The upper trace is the
THD+N vs. amplitude of the CS3310 The lower trace is the THD+N of the Audio Precision System One generator output connected directly to the analyzer input. The System One panel settings are identical to the previous test. This indicates that the THD+N contribution of the Audio
Precision actually degrades the measured performance of the CS3310 below 2.7 Vrms signal
levels.
10
DS82F1
CS3310
Figure 7 is a 16k FFT plot demonstrating the crosstalk performance of the CS3310 at 20 kHz.
Both channels were set to unity gain. The right channel input is grounded with the left channel
driven to 2.65 Vrms output at 20 kHz. The FFT plot is of the right channel output. This indicates
channel to channel crosstalk of -130 dB at 20 kHz.
Figure 10 is a series of plots which display the unity-gain THD+N vs. Frequency for 600 Ω, 2 kΩ
and infinite load conditions. The output was set to 2 Vrms. The Audio Precision System One was
bandlimited to 22 kHz
Figure 11 is a series of plots which display the unity-gain THD+N vs. Frequency for 1, 2 and 2.8
Vrms output levels. The output load was open circuit. The Audio Precision System One was
bandlimited to 22 kHz.
DS82F1
11
CS3310
.
THD+N% vs AMPL (Vrms)
AMPL (dBr) vs FREQ (Hz)
1
0
-20
-40
.1
-60
-80
.01
-100
-120
.001
-140
-160
.0001
0.1
1
3
-180
20.00 2.06k 4.11k 6.15k 8.19k 10.2k 12.3k 14.3k 16.4k 18.4k 20.5k 22.5k
Figure 6. THD+N vs. AMP
Figure 7. 20 kHz Crosstalk
AMPL (dBr) vs FREQ (Hz)
AMPL (dBr) vs FREQ (Hz)
1.0
1.0
0.5
0.5
0.0
0.0
-0.5
-0.5
-1.0
-1.0
-1.5
-1.5
-2.0
-2.0
10
100
10k
1k
100k 200k
Figure 8. Frequency Response Full Scale Input
0.1000
10
100
10k
1k
100k 200k
Figure 9. Frequency Response -20 dB Input
0.1000
600Ω
0.0100
0.0100
2kΩ
2.8 VRMS
0.0010
0.0010
OPEN
2 VRMS
1 VRMS
0.0001
20
100
1k
10k
20k
Figure 10. THD+N vs. Frequency LOAD = 600 Ω,
2 kΩ, open ckt
12
0.0001
20
100
1k
10k
20k
Figure 11. THD+N vs. Frequency Output levels of
1, 2, and 2.8 Vrms
DS82F1
CS3310
PIN DESCRIPTION
Zero Crossing Enable
ZCEN
1
16
AINL
Left Channel Input
Chip Select
CS
2
15
AGNDL
Left Analog Ground
Serial Data Input
SDATAI
3
14
AOUTL
Left Channel Output
Positive Digital Power
VD+
4
13
VA-
Negative Analog Power
Digital Ground
DGND
5
12
VA+
Positive Analog Power
Serial Clock Input
SCLK
6
11
AOUTR
Right Channel Output
Serial Data Output
SDATAO
7
10
AGNDR
Right Analog Ground
Mute
MUTE
8
9
AINR
Right Channel Input
Power Supply Connections
VA+ - Positive Analog Power, Pin 12.
Positive analog supply. Nominally +5 volts.
VA- - Negative Analog Power, Pin 13.
Negative analog supply. Nominally -5 volts.
AGNDL - Left Channel Analog Ground, Pin 15.
Analog ground reference for the left channel.
AGNDR - Right Channel Analog Ground, Pin 10.
Analog ground reference for the right channel.
VD+ - Positive Digital Power, Pin 4.
Positive supply for the digital section. Nominally +5 volts. Applying power to VD+ prior
to VA+ creates a SCR latch-up condition. Refer to Figure 2 for the recommended
power connections.
DGND - Digital Ground, Pin 5.
Digital ground for the digital section.
DS82F1
13
CS3310
Analog Inputs and Outputs
AINL, AINR - Left and Right Channel Analog Inputs, Pins 16, 9.
Analog input connections for the left and right channels. Nominally ±3.75 volts for a full
scale input.
AOUTL, AOUTR - Left and Right Channel Analog Outputs, Pins 14, 11.
Analog outputs for the left and right channels. Nominally ±3.75 volts for a full scale
output.
Digital Pins
SDATAI - Serial Data Input, Pin 3.
Serial input data that sets the analog output level of the left and right channels. The
data is formatted in a 16-bit word. The first eight bits clocked into this pin control the
analog output level for the right channel, and the second eight bits clocked into the
device control the analog output level for the left channel. The data is clocked into the
CS3310 by the rising edge of SCLK.
SDATAO - Serial Data Output, Pin 7.
Serial output data that provides daisy-chaining of multiple CS3310’s. This serial output
will output the previous sixteen bits of volume control data that were clocked into the
SDATAI pin. SDATAO will enter a High Impedance State when CS is High.
SCLK - Serial Input Clock, Pin 6.
Serial clock that clocks in the individual bits of serial data from the SDATAI pin. This
clock is also used to clock out the individual bits from the SDATAO pin. The SDATAI
data is latched on the rising edge, and SDATAO data is clocked out on the falling
edge.
CS - Chip Select, Pin 2.
When high, the SDATAO output is held in a high impedance state. A falling transition
defines the start of the 16-bit volume control word into the device. The 16-bit input
data is latched into the control register on the rising edge of CS.
MUTE - Mute, Pin 8.
Forces both the left and right analog output channels to ground. An offset calibration is
initiated following the low transition of MUTE. Calibration requires a minimum mute
period of 2 ms.
14
DS82F1
CS3310
ZCEN - Zero Crossing Enable, Pin 1.
This pin enables or disables the zero crossing detection and time-out function used
during analog output level transitions. A high level on this pin enables the zero
crossing detection function. A low level on this pin disables the zero crossing
detection.
PARAMETER DEFINITIONS
Dynamic Range
Full scale (RMS) signal to broadband noise ratio. The broadband noise is measured
over the specified bandwidth with the input grounded. Units in decibels.
Total Harmonic Distortion plus Noise
The ratio of the rms value of the signal to the rms sum of all other spectral
components over the specified bandwidth (typically 10 Hz to 20 kHz), including
distortion components. Expressed in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each
channel at the converter’s output with the input under test grounded and a full-scale
signal applied to the other channel. Units in decibels.
DS82F1
15
CS3310
PACKAGE DIMENSIONS
16L SOIC (300 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
A1
INCHES
DIM
A
A1
B
C
D
E
e
H
L
∝
MIN
0.093
0.004
0.013
0.009
0.398
0.291
0.040
0.394
0.016
0°
MAX
0.104
0.012
0.020
0.013
0.413
0.299
0.060
0.419
0.050
8°
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.30
0.33
0.51
0.23
0.32
10.10
10.50
7.40
7.60
1.02
1.52
10.00
10.65
0.40
1.27
0°
8°
JEDEC #: MS-013
16
DS82F1
CS3310
Revision
Date
PP1
April 1991
PP2
December 1992
Update specifications
PP3
February 1999
Update specifications
PP4
F1
July 2004
September 2005
Changes
Initial release
Update specifications and bring into new template.
Add lead free part.
Added “Lead Free” to Ordering Information on front page.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to www.cirrus.com
IIMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,
INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT
THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL
APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND
OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION
WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
DS82F1
17