KIT ATION EVALU E L B AVAILA 19-0795; Rev 0; 4/07 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs The MAX109, 2.2Gsps, 8-bit, analog-to-digital converter (ADC) enables the accurate digitizing of analog signals with frequencies up to 2.5GHz. Fabricated on an advanced SiGe process, the MAX109 integrates a highperformance track/hold (T/H) amplifier, a quantizer, and a 1:4 demultiplexer on a single monolithic die. The MAX109 also features adjustable offset, full-scale voltage (via REFIN), and sampling instance allowing multiple ADCs to be interleaved in time. The innovative design of the internal T/H amplifier, which has a wide 2.8GHz full-power bandwidth, enables a flat-frequency response through the second Nyquist region. This results in excellent ENOB performance of 6.9 bits. A fully differential comparator design and decoding circuitry reduce out-of-sequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastability performance (1014 clock cycles). This design guarantees no missing codes. The analog input is designed for both differential and single-ended use with a 500mVP-P input-voltage range. The output data is in standard LVDS format, and is demultiplexed by an internal 1:4 demultiplexer. The LVDS outputs operate from a supply-voltage range of 3V to 3.6V for compatibility with single 3V-reference systems. Control inputs are provided for interleaving additional MAX109 devices to increase the effective system-sampling rate. The MAX109 is offered in a 256-pin Super Ball-Grid Array (SBGA) package and is specified over the extended industrial temperature range (-40°C to +85°C). Features ♦ Ultra-High-Speed, 8-Bit, 2.2Gsps ADC ♦ 2.8GHz Full-Power Analog Input Bandwidth ♦ Excellent Signal-to-Noise Performance 44.6dB SNR at fIN = 300MHz 44dB SNR at fIN = 1600MHz ♦ Superior Dynamic Range at High-IF 61.7dBc SFDR at fIN = 300MHz 50.3dBc SFDR at fIN = 1600MHz -60dBc IM3 at fIN1 = 1590MHz and fIN2 = 1610MHz ♦ 500mVP-P Differential Analog Inputs ♦ 6.8W Typical Power Including the Demultiplexer ♦ Adjustable Range for Offset, Full-Scale, and Sampling Instance ♦ 50Ω Differential Analog Inputs ♦ 1:4 Demultiplexed LVDS Outputs ♦ Interfaces Directly to Common FPGAs with DDR and QDR Modes Ordering Information PART TEMP RANGE PINPACKAGE PKG CODE MAX109EHF-D -40°C to +85°C 256 SBGA H256-1 D = Dry pack. Pin Configuration Applications Radar Warning Receivers (RWR) Light Detection and Ranging (LIDAR) Digital RF/IF Signal Processing TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C Electronic Warfare (EW) Systems High-Speed Data-Acquisition Systems D E F Digital Oscilloscopes G High-Energy Physics Instrumentation J ATE Systems L H K MAX109 256-PIN SBGA PACKAGE M N P R T U V W Y 256-PIN SUPER BALL-GRID ARRAY ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX109 General Description PORTB DOR DCO RSTOUT DCO D[0:7] DOR C[0:7] PORTD B[0:7] PORTA A[0:7] PORTC MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs DEMUX RESET OUTPUT DEMUX CLOCK DRIVER QDR DEMUX CLOCK GENERATOR DDR DELAYED RESET LOGIC CLOCK DRIVER REFERENCE AMPLIFIER RESET PIPELINE 8-BIT ADC CORE QUANTIZER CLOCK DRIVER REFIN RESET INPUT DUAL LATCH REFOUT BANDGAP REFERENCE RSTINN RSTINP T/H AMPLIFIER INPUT CLOCK BUFFER GNDI 50Ω VOSADJ 50Ω INP INN 50Ω SAMPADJ CLKP 50Ω CLKCOM TEMPERATURE MONITOR TEMPMON CLKN Figure 1. Functional Diagram of the MAX109 2 _______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs RSTINP, RSTINN to GNDA .....................-0.3V to (VCCO + 0.3V) RSTOUTP, RSTOUTN to GNDO .............-0.3V to (VCCO + 0.3V) VOSADJ, SAMPADJ, TEMPMON to GNDI...............................-0.3V to (VCCI + 0.3V) PRN, DDR, QDR to GNDD.......................-0.3V to (VCCD + 0.3V) DELGATE0, DELGATE1 to GNDA ...........-0.3V to (VCCA + 0.3V) Continuous Power Dissipation (TA = +70°C) 256-Ball SBGA (derate 74.1mW/°C above +70°C for a multilayer board) ................................................. 5925.9mW Operating Temperature Range MAX109EHF ...................................................-40°C to +85°C Thermal Resistance θJA (Note 1) .......................................3°C/W Operating Junction Temperature.....................................+150°C Storage Temperature Range .............................-65°C to +150°C Note 1: Thermal resistance is based on a 5in x 5in multilayer board. The data sheet assumes a thermal environment of 3°C/W. Thermal resistance may be different depending on airflow and heatsink cooling capabilities. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY Resolution RES 8 Bits Integral Nonlinearity (Note 2) INL (Note 8) -0.8 ±0.25 +0.8 LSB Differential Nonlinearity (Note 2) DNL Guaranteed no missing codes, TA = +25°C (Note 8) -0.8 ±0.25 +0.8 LSB Transfer Curve Offset (Note 2) VOS VOSADJ control input open (Note 8) -5.5 0 +5.5 LSB VCM Signal and offset with respect to GNDI ANALOG INPUTS (INN, INP) Common-Mode Input-Voltage Range Common-Mode Rejection Ratio (Note 3) CMRR Full-Scale Input Range (Note 2) VFS Input Resistance RIN Input Resistance Temperature Coefficient TCR VREFIN = 2.5V ±1 V 50 dB 470 500 535 mVP-P 45 50 55 Ω 150 ppm/°C VOS ADJUST CONTROL INPUT (VOSADJ) Input Resistance (Note 4) Input Offset Voltage RVOSADJ VOS 25 50 75 kΩ VOSADJ = 0V -20 mV VOSADJ = 2.5V 20 mV SAMPLE ADJUST CONTROL INPUT (SAMPADJ) Input Resistance RSAMPADJ Aperture Time Adjust Range tAD 25 SAMPADJ = 0 to 2.5V 50 30 75 kΩ ps _______________________________________________________________________________________ 3 MAX109 ABSOLUTE MAXIMUM RATINGS VCCA to GNDA ....................................................... -0.3V to +6V VCCD to GNDD ....................................................... -0.3V to +6V VCCI to GNDI ........................................................... -0.3V to +6V VCCO to GNDO ................................................... -0.3V to +3.9V VEE to GNDI ............................................................ -6V to +0.3V Between Grounds (GNDA, GNDI, GNDO, GNDD, GNDR) ................................................ -0.3V to +0.3V VCCA to VCCD ..................................................... -0.3V to +0.3V VCCA to VCCI ....................................................... -0.3V to +0.3V Differential Voltage between INP and INN ........................... ±1V INP, INN to GNDI ................................................................. ±1V Differential Voltage between CLKP and CLKN..................... ±3V CLKP, CLKN, CLKCOM to GNDI ............................... -3V to +1V Digital LVDS Outputs to GNDO .............. -0.3V to (VCCO - 0.3V) REFIN, REFOUT to GNDR ........................-0.3V to (VCCI + 0.3V) REFOUT Current ...............................................-100µA to +5mA MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs DC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS REFERENCE INPUT AND OUTPUT (REFIN, REFOUT) Reference Output Voltage REFOUT Reference Output Load Regulation ∆REFOUT Reference Input Voltage REFIN Reference Input Resistance RREFIN MIN TYP MAX UNITS 2.460 2.500 2.525 V 0 < ISOURCE < 2.5mA 4 < 7.5 mV 2.500 ±0.25 V 5 kΩ 200 to 2000 mV -2 to +2 V CLOCK INPUTS (CLKP, CLKN) Clock Input Amplitude Peak-to-peak differential (Figure 13b) Clock Input Common-Mode Range Signal and offset referenced to CLKCOM Clock Input Resistance RCLK Input Resistance Temperature Coefficient TCR CLKP and CLKN to CLKCOM 45 50 55 150 Ω ppm/°C CMOS CONTROL INPUTS (DDR, QDR, PRN, DELGATE0, DELGATE1) High-Level Input Voltage VIH Threshold voltage = 1.2V 1.4 3.3 Low-Level Input Voltage VIL Threshold voltage = 1.2V 0.8 V High-Level Input Current IIH VIH = 3.3V 50 µA Low-Level Input Current IIL VIL = 0V -50 V µA LVDS INPUTS (RSTINP, RSTINN) Differential Input High Voltage 0.2 V Differential Input Low Voltage -0.2 V Minimum Common-Mode Input Voltage 1 V Maximum Common-Mode Input Voltage VCCO 0.15 V TEMPERATURE MEASUREMENT OUTPUT (TEMPMON) Temperature Measurement Accuracy T (°C) = [(VTEMPMON - VGNDI) x 1303.5] 371 ±7 °C Output Resistance Measured between TEMPMON and GNDI 0.725 kΩ LVDS OUTPUTS (PortA, PortB, PortC, PortD, DORP, DORN, DCOP, DCON, RSTOUTP, RSTOUTN) (Note 9) Differential Output Voltage VOD RLOAD = 100Ω 250 400 mV Output Offset Voltage VOS RLOAD = 100Ω 1.10 1.28 V 4 _______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDO = GNDD = GNDR = 0V, VOSADJ = SAMPADJ = open, digital output pins differential RL = 100Ω. Specifications ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS mA POWER REQUIREMENTS Analog Supply Current IVCCA 556 744 Positive Input Supply Current IVCCI 125 168 mA Negative Input Supply Current IIVEEI 181 240 mA Digital Supply Current IVCCD 291 408 mA Output Supply Current IVCCO 222 300 mA Power Dissipation PDISS 6.50 8.79 W Positive Power-Supply Rejection Ratio PSRRP (Note 5) 50 dB Negative Power-Supply Rejection Ratio PSRRN VEE = -5.25V to -4.75V 50 dB AC ELECTRICAL CHARACTERISTICS (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100Ω. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT Analog Input Full-Power Bandwidth (Note 6) Gain Flatness BW-3dB GF 1100MHz to 2200MHz 2.8 GHz ±0.3 dB DYNAMIC SPECIFICATIONS Signal-to-Noise Ratio Total Harmonic Distortion (Note 7) SNR300 fIN = 300MHz, fCLK = 2.2Gsps SNR1000 fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) 43.6 44.6 44.5 SNR1600 fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) 42.2 44.0 SNR2500 fIN = 2500MHz, fCLK = 2.2Gsps 42.9 SNR500 fIN = 500MHz, fCLK = 2.5Gsps 44.4 SNR1600 fIN = 1600MHz, fCLK = 2.5Gsps 44.0 dB THD300 fIN = 300MHz, fCLK = 2.2Gsps -55.6 THD1000 fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) -48.5 -42.5 THD1600 fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) -46.6 -39.6 THD2500 fIN = 2500MHz, fCLK = 2.2Gsps -43.7 THD500 fIN = 500MHz, fCLK = 2.5Gsps -49.0 THD1600 fIN = 1600MHz, fCLK = 2.5Gsps -43.1 dBc _______________________________________________________________________________________ 5 MAX109 DC ELECTRICAL CHARACTERISTICS (continued) MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs AC ELECTRICAL CHARACTERISTICS (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100Ω. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER Spurious Free Dynamic Range Signal-to-Noise-Plus-Distortion Ratio SYMBOL CONDITIONS MIN SFDR300 fIN = 300MHz, fCLK = 2.2Gsps SFDR1000 fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) 44.4 51.1 SFDR1600 fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) 43.7 50.3 SFDR2500 fIN = 2500MHz, fCLK = 2.2Gsps 45.0 SFDR500 fIN = 500MHz, fCLK = 2.5Gsps 53.7 SFDR1600 fIN = 1600MHz, fCLK = 2.5Gsps 44.6 SINAD300 fIN = 300MHz, fCLK = 2.2Gsps UNITS dBc 44.1 SINAD1000 fIN = 1000MHz, fCLK = 2.2Gsps (Note 8) 40.4 43.1 SINAD1600 fIN = 1600MHz, fCLK = 2.2Gsps (Note 8) 37.9 42.1 SINAD2500 fIN = 2500MHz, fCLK = 2.2Gsps 40.1 SINAD500 43.1 IM3 MAX 61.7 fIN = 500MHz, fCLK = 2.5Gsps SINAD1600 fIN = 1600MHz, fCLK = 2.5Gsps Third-Order Intermodulation TYP dB 40.5 fIN1 = 1590MHz, fIN2 = 1610MHz at -7dBFS -60 dBc 10-14 Metastability Probability TIMING CHARACTERISTICS Maximum Sample Rate fCLK(MAX) 2.2 Gsps Clock Pulse-Width Low tPWL tCLK = tPWL + tPWH (Note 8) 180 ps Clock Pulse-Width High tPWH tCLK = tPWL + tPWH (Note 8) 180 ps Aperture Delay tAD 200 ps Aperture Jitter tAJ 0.2 ps Reset Input Data Setup Time tSU (Note 8) 300 tHD (Note 8) 250 tPD1 DCO = fCLK / 4, CLK fall to DCO rise time 1.6 tPD1DDR DCO = fCLK / 8, DDR mode, CLK fall to DCO rise time 1.6 tPD1QDR DCO = fCLK / 16, QDR mode, CLK fall to DCO rise time 1.6 Reset Input Data Hold Time CLK-to-DCO Propagation Delay tPD2 DCO-to-Data Propagation Delay DCO Duty Cycle 6 DCO = fCLK / 4, DCO rise to data transition (Note 8) ps ps -520 ns +520 tPD2DDR DCO = fCLK / 8, DDR mode, DCO rise to data transition (Note 8) -520 + 2tCLK 2tCLK 520 + 2tCLK tPD2QDR DCO = fCLK / 16, QDR mode, DCO rise to data transition (Note 8) -520 + 2tCLK 2tCLK 520 + 2tCLK Clock mode independent 45 to 55 _______________________________________________________________________________________ ps % 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.2Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 400mVP-P differential, digital output pins differential RL = 100Ω. Typical values are at TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS Output Rise Time tRDATA 20% to 80%, CL < 2pF 500 LVDS Output Fall Time tFDATA 20% to 80%, CL < 2pF 500 ps ps LVDS Differential Skew tSKEW1 Any two LVDS output signals, except DCO <100 ps PortD Data Pipeline Delay tPDD 7.5 Clock Cycles PortC Data Pipeline Delay tPDC 8.5 Clock Cycles PortB Data Pipeline Delay tPDB 9.5 Clock Cycles PortA Data Pipeline Delay tPDA 10.5 Clock Cycles Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The fullscale range (FSR) is defined as 255 x slope of the line where the slope of the line is determined by the end-point code transitions. When the analog input voltage exceeds positive FSR, the output code is 11111111; when the analog input voltage is beyond the negative FSR, the output code is 00000000. Note 3: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the common-mode voltage, expressed in dB. Note 4: The offset-adjust control input is tied to an internal 1.25V reference level through a resistor. Note 5: Measured with the positive supplies tied to the same potential, VCCA = VCCD = VCCI. VCC varies from 4.75V to 5.25V. Note 6: To achieve 2.8GHz full-power bandwidth, careful board layout techniques are required. Note 7: The total harmonic distortion (THD) is computed from the second through the 15th harmonics. Note 8: Guaranteed by design and characterization. Note 9: RSTOUTP/RSTOUTN are tested for functionality. Typical Operating Characteristics (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100Ω. Typical values are at TJ = +105°C, unless otherwise noted.) -30 -40 -50 -60 -20 -30 -40 -50 -60 -20 -30 -40 -50 -60 -70 -70 -70 -80 -80 -80 -90 0 276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz) -90 0 276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz) fCLK = 2.21184GHz fIN = 999.135MHz AIN = -1.059dBFS SNR = 44.5dB SINAD = 43.3dB THD = -49.5dBc SFDR = 52.1dBc HD2 = -57.3dBc HD3 = -52.1dBc -10 MAX109 toc03 0 AMPLITUDE (dB) AMPLITUDE (dB) -20 fCLK = 2.21184GHz fIN = 300.105MHz AIN = -1.034dBFS SNR = 45.1dB SINAD = 44.8dB THD = -56.2dBc SFDR = 62.4dBc HD2 = -64.4dBc HD3 = -62.7dBc -10 AMPLITUDE (dB) -10 FFT PLOT (16,384-POINT DATA RECORD) FFT PLOT (16,384-POINT DATA RECORD) 0 MAX109 toc01 fCLK = 2.21184GHz fIN = 98.145MHz AIN = -0.975dBFS SNR = 45.2dB SINAD = 44.8dB THD = -55.7dBc SFDR = 57.2dBc HD2 = -69.6dBc HD3 = -57.2dBc MAX109 toc02 FFT PLOT (16,384-POINT DATA RECORD) 0 -90 0 276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz) _______________________________________________________________________________________ 7 MAX109 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100Ω. Typical values are at TJ = +105°C, unless otherwise noted.) -50 -60 -30 -40 -50 -30 -40 -50 -70 -80 -80 -80 -90 -90 0 7.5 ENOB (Bits) SINAD 38 60 -THD, SFDR (dBc) 7.0 42 276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz) 65 MAX109 toc08 SNR 46 8.0 0 2fIN1 - fIN2 -THD, SFDR vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS) ENOB vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS) MAX109 toc07 50 -90 312.32 624.64 936.96 1249.28 156.16 468.48 780.8 1098.12 ANALOG INPUT FREQUENCY (MHz) 2fIN2 - fIN1 -60 -70 276.48 552.96 829.44 1105.92 138.24 414.72 691.20 967.68 ANALOG INPUT FREQUENCY (MHz) MAX109 toc06 MAX109 toc05 -60 SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS) SNR, SINAD (dB) -20 -70 0 fCLK = 2.21184GHz fIN1 = 1590.165MHz fIN2 = 1610.415MHz AIN1 = AIN2 = -7.13dBFS IM3 = -60.8dBc -10 6.5 6.0 MAX109 toc09 -40 -20 0 AMPLITUDE (dB) -30 fCLK = 2.49856GHz fIN = 1599.268MHz AIN = -1.059dBFS SNR = 44.1dB SINAD = 41.2dB THD = -44.4dBc SFDR = 46.1dBc HD2 = -50.1dBc HD3 = -46.1dBc -10 AMPLITUDE (dB) AMPLITUDE (dB) -20 0 MAX109 toc04 fCLK = 2.21184GHz fIN = 1600.155MHz AIN = -0.992dBFS SNR = 44.2dB SINAD = 42.6dB THD = -47.5dBc SFDR = 51.1dBc HD2 = -51.1dBc HD3 = -52.1dBc -10 TTIMD PLOT (16,384-POINT DATA RECORD) FFT PLOT (16,384-POINT DATA RECORD) FFT PLOT (16,384-POINT DATA RECORD) 0 55 SFDR 50 45 -THD 34 40 5.5 35 5.0 30 2000 0 2500 -40 HD3 -50 -55 -60 HD2 -65 SNR 46 SNR, SINAD (dB) -45 2000 50 MAX109 toc10 -35 1000 1500 fIN (MHz) 500 1000 1500 fIN (MHz) 2000 2500 ENOB vs. ANALOG INPUT FREQUENCY (fCLK = 2.49856Gsps, AIN = -1dBFS) 8.0 7.5 7.0 42 38 SINAD 6.5 6.0 34 -70 0 2500 SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 2.49856Gsps, AIN = -1dBFS) HD2, HD3 vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, AIN = -1dBFS) -30 500 MAX109 toc12 1000 1500 fIN (MHz) ENOB (Bits) 500 MAX109 toc11 0 HD2, HD3 (dBc) MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs 5.5 -75 30 -80 0 8 500 1000 1500 fIN (MHz) 2000 2500 5.0 0 500 1000 1500 fIN (MHz) 2000 2500 0 500 1000 1500 fIN (MHz) _______________________________________________________________________________________ 2000 2500 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs SINAD 45 -50 -55 -60 HD2 -65 40 -75 5 1000 1500 fIN (MHz) 2000 0 0 2500 ENOB vs. ANALOG INPUT AMPLITUDE (fCLK = 2.21184Gsps, fIN = 1600.1550MHz) 7.5 6.0 -45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS) 2500 55 -THD, SFDR (dBc) 6.5 2000 60 50 7.0 1000 1500 fIN (MHz) -THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 2.21184Gsps, fIN = 1600.1550MHz) MAX109 to16 8.0 500 35 -25 -30 -THD 0 SNR, SINAD vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS) SNR 8.0 7.5 0 -45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS) SINAD 6.5 6.0 34 SFDR 55 50 45 -THD 35 5.0 500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz) 0 40 5.5 30 60 -THD, SFDR (dBc) 38 -5 -THD, SFDR vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS) 7.0 42 ENOB (Bits) SNR, SINAD (dB) 46 -5 ENOB vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS) MAX109 toc19 50 HD2 -70 -45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS) MAX109 toc20 -5 -50 -65 20 -45 -40 -35 -30 -25 -20 -15 -10 AIN (dBFS) -45 -60 25 5.0 -40 -55 30 5.5 HD3 -35 40 0 -20 SFDR 45 -5 HD2, HD3 vs. ANALOG INPUT AMPLITUDE (fCLK = 2.21184Gsps, fIN = 1600.1550MHz) HD2, HD3 (dBc) 500 15 10 MAX109 toc17 0 20 -70 -80 35 25 MAX109 toc18 50 30 MAX109 toc21 HD2, HD3 (dBc) SFDR MAX109 toc15 35 -45 -THD ENOB (Bits) HD3 SNR 40 SNR, SINAD (dB) 55 -35 -40 45 MAX109 toc14 60 -THD, SFDR (dBc) -30 MAX109 toc13 65 500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz) 500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz) _______________________________________________________________________________________ 9 MAX109 Typical Operating Characteristics (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100Ω. Typical values are at TJ = +105°C, unless otherwise noted.) SNR, SINAD vs. ANALOG INPUT AMPLITUDE -THD, SFDR vs. ANALOG INPUT FREQUENCY HD2, HD3 vs. ANALOG INPUT FREQUENCY (fCLK = 2.21184Gsps, fIN = 1600.1550MHz) (fCLK = 2.49856Gsps, AIN = -1dBFS) (fCLK = 2.49865Gsps, AIN = -1dBFS) Typical Operating Characteristics (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100Ω. Typical values are at TJ = +105°C, unless otherwise noted.) -THD, SFDR (dBc) 44 42 40 HD2 SINAD 36 -75 4.75 500 750 1000 1250 1500 1750 2000 2250 2500 fCLK (MHz) SINAD MAX109 toc26 SFDR 49 4.95 5.05 VCCD (V) 5.15 -THD 48 47 4.95 5.05 VCCD (V) 0.8 0.6 5.15 5.25 -5.25 48 47 46 0.8 0.6 0.4 0.4 0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -1.0 -1.0 -4.85 -4.75 0 32 64 96 128 160 192 224 256 DIGITAL OUTPUT CODE -4.75 0 -0.8 -5.05 -4.95 VEE (V) -4.85 -0.2 44 -5.15 -5.05 -4.95 VEE (V) 1.0 45 -5.25 -5.15 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE (262,144-POINT DATA RECORD) DNL (LSB) INL (LSB) -THD MAX109 toc24 SINAD 36 4.85 1.0 50 SFDR 42 38 MAX109 toc29 VCCA = VCCI = 5V VCCD = 5V VCCO = 3.3V 44 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE (262,144-POINT DATA RECORD) MAX109 toc28 53 5.25 SNR 40 -THD, SFDR vs. VEE (fIN = 1600.1550MHz, AIN = -1dBFS) 49 VCCA = VCCI = 5V VCCD = 5V VCCO = 3.3V 48 VCCA = VCCI = 5V VCCO = 3.3V VEE = -5V 4.75 5.25 5.15 MAX109 toc30 4.85 4.95 5.05 VCCA/VCCI (V) 50 44 4.75 4.85 46 45 36 10 4.75 SNR, SINAD vs. VEE (fIN = 1600.1550MHz, AIN = -1dBFS) 50 46 38 51 5.25 SNR, SINAD (dB) -THD, SFDR (dBc) SNR, SINAD (dB) 42 52 5.15 51 44 40 VCCD = 5V VCCO = 3.3V VEE = -5V 44 4.95 5.05 VCCA/VCCI (V) 52 SNR 46 -THD 47 45 53 MAX109 toc25 VCCA = VCCI = 5V VCCO = 3.3V VEE = -5V SFDR 48 -THD, SFDR vs. VCCD (fIN = 1600.1550MHz, AIN = -1dBFS) SNR, SINAD vs. VCCD (fIN = 1600.1550MHz, AIN = -1dBFS) 50 4.85 49 46 VCCD = 5V VCCO = 3.3V VEE = -5V 38 -70 50 MAX109 toc27 SNR, SINAD (dB) -60 48 51 46 -55 VCCA AND VCCI CONNECTED TOGETHER 52 SNR HD3 -65 VCCA AND VCCI CONNECTED TOGETHER 48 53 MAX109 toc23 -45 HD2, HD3 (dBc) 50 MAX109 toc22 -40 -50 -THD, SFDR vs. VCCA/VCCI (fIN = 1600.1550MHz, AIN = -1dBFS) SNR, SINAD vs. VCCA/VCCI (fIN = 1600.1550MHz, AIN = -1dBFS) HD2, HD3 vs. CLOCK SPEED (fIN = 1600MHz, AIN = -1dBFS) -THD, SFDR (dBc) MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs 0 32 64 96 128 160 192 224 256 DIGITAL OUTPUT CODE ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs -3 -2 -3 2.4945 -5 -5 2.4935 -6 10,000 2.4925 6200 5900 VCCO = 3V to 3.6V VCCA = VCCI = VCCD = 5V VEE = -5V 850 800 750 ENOB vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS) 7.25 3.0 5.25 54 -THD, SFDR (dBc) 6.50 6.25 40 38 85 [125.9] SNR 39 35 3.6 -40 [-22.1] -40 [-22.1] -44 -15 [7.5] 10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (°C) [DIE TEMPERATURE (°C)] 85 [125.9] HD2, HD3 vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS) -46 SFDR HD2 44 5.75 10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (°C) [DIE TEMPERATURE (°C)] 3.5 46 42 -15 [7.5] 3.3 3.4 VCCO (V) 48 6.00 -40 [-22.1] 5.25 41 -THD, SFDR vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS) 50 6.75 3.2 52 7.00 5.50 3.1 HD2, HD3 (dBc) 4.95 5.05 5.15 VCCA/VCCI/VCCD/-VEE (V) MAX109 toc37 7.50 4.85 5.15 SINAD 43 MAX109 toc38 4.75 4.95 5.05 VCCA/VCCI (V) 37 650 5300 4.85 45 700 5600 4.75 SNR, SINAD vs. TEMPERATURE (fIN = 1600.1550MHz, AIN = -1dBFS) SNR, SINAD (dB) 6500 10,000 900 POWER DISSIPATION (mW) VCCO = 3.3V VCCA = VCCI = VCCD = 4.75V to 5V VEE = -4.75V to -5.25V 100 1000 ANALOG INPUT FREQUENCY (MHz) OUTPUT DRIVER POWER DISSIPATION vs. VCCO (fIN = 1600.1550MHz, AIN = -1dBFS) MAX109 toc34 6800 10 MAX109 toc35 100 1000 ANALOG INPUT FREQUENCY (MHz) MAX109 toc33 2.4955 -4 10 VCCA AND VCCI CONNECTED TOGETHER VCCO = 3.3V VCCD = 5V VEE = -5V 2.4965 -4 ANALOG/DIGITAL POWER DISSIPATION vs. VCCA/VCCI/VCCD/-VEE (fIN = 1600.1550MHz, AIN = -1dBFS) POWER DISSIPATION (mW) VREFOUT (V) -2 -6 ENOB (Bits) 2.4975 -1 GAIN (dB) GAIN (dB) -1 2.4985 MAX109 toc36 0 MAX109 toc39 0 2.4995 MAX109 toc32 1 MAX109 toc31 1 -48 -50 HD3 -52 -THD -54 -15 [7.5] 10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (°C) [DIE TEMPERATURE (°C)] 85 [125.9] -56 -40 [-22.1] -15 [7.5] 10 35 60 [37.1] [66.7] [96.3] TEMPERATURE (°C) [DIE TEMPERATURE (°C)] ______________________________________________________________________________________ 85 [125.9] 11 MAX109 Typical Operating Characteristics (continued) (VCCA = VCCI = VCCD = 5V, VCCO = 3.3V, VEE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, fCLK = 2.21184Gsps, analog input amplitude at -1dBFS differential, clock input amplitude 10dBm differential, digital output pins differential RL = 100Ω. Typical values are at TJ = +105°C, unless otherwise noted.) SMALL-SIGNAL INPUT BANDWIDTH FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY REFERENCE VOLTAGE vs. VCCA/VCCI vs. ANALOG INPUT FREQUENCY (AIN = -1dBFS) (AIN = -20dBFS) MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs Pin Description PIN NAME A1, A2, B1, B2, C1–C5, D5, L1–L4, U5, V1–V4, W1, W2, Y1, Y2 VCCO LVDS Output Power Supply. Accepts an input-voltage range of 3.3V ±10%. A3, A4, B3, B4, D1–D4, K1–K4, U1–U4, W3, W4, Y3, Y4 GNDO LVDS Output Ground. Ground connection for LVDS output drivers. A9, B9, C10, D10, U10, V10, W10, Y10 VCCD Digital Logic Power Supply. Accepts an input-voltage range of 5V ±5%. A10, B10, C11, D11, U11, V11, W11, Y11 GNDD Digital Ground. Ground connection for digital logic circuitry. A11, A19, B11, B18, C12, C18, D12, D18, E17, U17, V17, W17, Y17, U12, V12, W12, Y12 VCCA Analog Supply Voltage for Comparator Array. Accepts an input-voltage range of 5V ±5%. A12, A18, B12, B13, B17, C13, C17, D13, D17, U13, U16, V13, V16, W13, W16, Y13, Y16 GNDA Analog Ground. Ground connection for comparator array. H17–H20, P17–P20, U15, V15, W15, Y15 VCCI Analog Supply Voltage. Analog power supply (positive rail) for T/H amplifier. Accepts an inputvoltage range of 5V ±5%. E18, F17–F20, J17, J18, J19, N17, N18, N19, T17–T20, U18 VEE Negative Power Supply. Analog power supply (negative rail) for the T/H amplifier. Accepts an input-voltage range of -5V ±5%. D19, D20, E19, E20, G17–G20, J20, K17, K18, K19, L17–L20, M17, M18, M19, N20, R17–R20, U14, U19, U20, V14, V19, V20, W14, Y14 GNDI 12 FUNCTION Analog Ground. Ground connection for the T/H amplifier. ______________________________________________________________________________________ PIN NAME 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs PIN NAME A14 CLKP True/Positive Sampling Clock Input. Positive terminal for differential input configuration. FUNCTION A16 CLKN Complementary/Negative Sampling Clock Input. Negative terminal for differential input configuration. A13, A15, A17, B14, B15, B16, C14, C15, C16, D14, D15, D16 CLKCOM 50Ω Clock Termination Return B20 SAMPADJ Sampling Point Adjustment Input. Allows the user to adjust the sampling event by applying a voltage between 0 to 2.5V to this input. B19 DELGATE1 Timing Delay Adjustment. Coarse (MSB) adjustment for the timing between T/H amplifier and quantizer. C19 DELGATE0 Timing Delay Adjustment. Coarse (LSB) adjustment for the timing between T/H amplifier and quantizer. Y20 REFIN Y19 REFOUT Internal Reference Output. Connect to REFIN, if using the internal 2.5V bandgap reference. V18, W18, Y18 GNDR Bandgap Reference Ground. Ground connection for the internal bandgap reference and its related circuitry. M20 INP True/Positive Analog Input Terminal. For single-ended signals, apply signal to INP and reverseterminate INN to GNDI with a 50Ω resistor. K20 INN Complementary/Negative Analog Input Terminal. For singled-ended signals, reverse-terminate INN to GNDI with a 50Ω resistor and apply the signal directly to INP. W20 VOSADJ M4 DORP True/Positive LVDS Data-Overrange Output Bit. This output flags over- and under-range conditions of the data converter. M3 DORN Complementary/Negative LVDS Data-Overrange Output Bit. This output flags over- and underrange conditions on the data converter. M2 DCOP True/Positive LVDS Data Clock Output. Synchronize user-supplied data-capture board or dataacquisition system to this clock. M1 DCON Complementary/Negative LVDS Data Clock Output. Synchronize user-supplied data-capture board or data-acquisition system to this clock. Reference Voltage Input. For applications requiring improved gain performance and referencevoltage adjustability, allows the user to utilize the REFIN input by applying a more accurate and adjustable reference source. This input accepts an input-voltage range of 2.5V ±10%. Analog Voltage Input to Adjust the Converter Offset. This input accepts an input-voltage range of 0 to 2.5V allowing the offset to be adjusted at roughly ±10 LSB. ______________________________________________________________________________________ PIN NAME 13 MAX109 Pin Description (continued) 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs MAX109 Pin Description (continued) PIN 14 NAME FUNCTION Y5 QDR Quad Data Rate Input (CMOS). Connect to GNDD for the default data rate to be applied. Connect to VCCD to achieve four times the specified data rate. W5 DDR Double Data Rate Input (CMOS). Connect to GNDD for the standard data rate to be applied. Connect to VCCD to achieve two times the specified data rate. V5 PRN Pseudorandom Number Generator Enable Input (CMOS). When enabled, pseudorandom patterns appear on all four LVDS output ports (PortA, PortB, PortC, and PortD). D9 RSTINP True/Positive Reset Input C9 RSTINN Complementary/Negative Reset Input B5 RSTOUTP True/Positive LVDS Reset Output A5 RSTOUTN Complementary LVDS Reset Output B8 D7P True/Positive Output Bit D7P, PortD, Bit 7 A8 D7N Complementary/Negative Output Bit D7N, PortD, Bit 7 B6 D6P True/Positive Output Bit D6P, PortD, Bit 6 A6 D6N Complementary/Negative Output Bit D6N, PortD, Bit 6 F2 D5P True/Positive Output Bit D5P, PortD, Bit 5 F1 D5N Complementary/Negative Output Bit D5N, PortD, Bit 5 H2 D4P True/Positive Output Bit D4P, PortD, Bit 4 H1 D4N Complementary/Negative Output Bit D4N, PortD, Bit 4 N2 D3P True/Positive Output Bit D3P, PortD, Bit 3 N1 D3N Complementary/Negative Output Bit D3N, PortD, Bit 3 R2 D2P True/Positive Output Bit D2P, PortD, Bit 2 R1 D2N Complementary/Negative Output Bit D2N, PortD, Bit 2 W6 D1P True/Positive Output Bit D1P, PortD, Bit 1 Y6 D1N Complementary/Negative Output Bit D1N, PortD, Bit 1 W8 D0P True/Positive Output Bit D0P, PortD, Bit 0 Complementary/Negative Output Bit, D0N, PortD, Bit 0 Y8 D0N D8 C7P True/Positive Output Bit C7P, PortC, Bit 7 C8 C7N Complementary/Negative Output Bit C7N, PortC, Bit 7 D6 C6P True/Positive Output Bit C6P, PortC, Bit 6 C6 C6N Complementary/Negative Output Bit C6N, PortC, Bit 6 F4 C5P True/Positive Output Bit C5P, PortC, Bit 5 F3 C5N Complementary/Negative Output Bit C5N, PortC, Bit 5 H4 C4P True/Positive Output Bit C4P, PortC, Bit 4 H3 C4N Complementary/Negative Output Bit C4N, PortC, Bit 4 N4 C3P True/Positive Output Bit C3P, PortC, Bit 3 N3 C3N Complementary/Negative Output Bit C3N, PortC, Bit 3 R4 C2P True/Positive Output Bit C2P, PortC, Bit 2 ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs PIN NAME R3 C2N FUNCTION Complementary/Negative Output Bit C2N, PortC, Bit 2 U6 C1P True/Positive Output Bit C1P, PortC, Bit 1 V6 C1N Complementary/Negative Output Bit C1N, PortC, Bit 1 U8 C0P True/Positive Output Bit C0P, PortC, Bit 0 V8 C0N Complementary/Negative Output Bit C0N, PortC, Bit 0 B7 B7P True/Positive Output Bit B7P, PortB, Bit 7 A7 B7N Complementary/Negative Output Bit B7N, PortB, Bit 7 E2 B6P True/Positive Output Bit B6P, PortB, Bit, 6 E1 B6N Complementary/Negative Output Bit B6N, PortB, Bit 6 G2 B5P True/Positive Output Bit B5P, PortB, Bit 5 G1 B5N Complementary/Negative Output Bit B5N, PortB, Bit 5 J2 B4P True/Positive Output Bit B4P, PortB, Bit 4 J1 B4N Complementary/Negative Output Bit B4N, PortB, Bit 4 P2 B3P True/Positive Output Bit B3P, PortB, Bit 3 P1 B3N Complementary/Negative Output Bit B3N, PortB, Bit 3 T2 B2P True/Positive Output Bit B2P, PortB, Bit 2 Complementary/Negative Output Bit B2N, PortB, Bit 2 T1 B2N W7 B1P True/Positive Output Bit B1P, PortB, Bit 1 Y7 B1N Complementary/Negative Output Bit B1N, PortB, Bit 1 W9 B0P True/Positive Output Bit B0P, PortB, Bit 0 Y9 B0N Complementary/Negative Output Bit B0N, PortB, Bit 0 D7 A7P True/Positive Output Bit A7P, PortA, Bit 7 C7 A7N Complementary/Negative Output Bit A7N, PortA, Bit 7 E4 A6P True/Positive Output Bit A6P, PortA, Bit 6 E3 A6N Complementary/Negative Output Bit A6N, PortA, Bit 6 G4 A5P True/Positive Output Bit A5P, PortA, Bit 5 G3 A5N Complementary/Negative Output Bit A5N, PortA, Bit 5 J4 A4P True/Positive Output Bit A4P, PortA, Bit 4 Complementary/Negative Output Bit A4N, PortA, Bit 4 J3 A4N P4 A3P True/Positive Output Bit A3P, PortA, Bit 3 P3 A3N Complementary/Negative Output Bit A3N, PortA, Bit 3 T4 A2P True/Positive Output Bit A2P, PortA, Bit 2 T3 A2N Complementary/Negative Output Bit A2N, PortA, Bit 2 ______________________________________________________________________________________ 15 MAX109 Pin Description (continued) 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs MAX109 Pin Description (continued) PIN NAME U7 A1P True/Positive Output Bit A1P, PortA, Bit 1 FUNCTION V7 A1N Complementary/Negative Output Bit A1N, PortA, Bit 1 U9 A0P True/Positive Output Bit A0P, PortA, Bit 0 V9 A0N Complementary/Negative Output Bit A0N, PortA, Bit 0 W19 A20, C20 TEMPMON Temperature Monitor Output. Resulting output voltage corresponds to die temperature. T.P. Test Point. Do not connect. Detailed Description Principle of Operation The architecture of the MAX109 provides the fastest multibit conversion of all common integrated ADC designs. The key to its architecture is an innovative, high-performance comparator design. The MAX109 quantizer and its encoding logic translate the comparator outputs into a parallel 8-bit output code and pass the binary code on to the 1:4 demultiplexer. Four separate ports (PortA, PortB, PortC, and PortD) output true LVDS data at speeds of up to 550Msps per port (depending on how the demultiplexer section is set on the MAX109). The ideal transfer function appears in Figure 2. 16 OVERRANGE 3 2 1 0 (-FS + 1 LSB) 129 128 127 126 0 ANALOG INPUT (+FS - 1 LSB) +FS OVERRANGE + 255 255 254 DIGITAL OUTPUT The MAX109 is an 8-bit, 2.2Gsps flash analog-to-digital converter (ADC) with an on-chip T/H amplifier and 1:4 demultiplexed high-speed LVDS outputs. The ADC (Figure 1) employs a fully differential 8-bit quantizer and a unique encoding scheme to limit metastable states and ensures no error exceeds a maximum of 1 LSB. An integrated 1:4 output demultiplexer simplifies interfacing to the part by reducing the output data rate to one-quarter the sampling clock rate. This demultiplexer circuit has integrated reset capabilities that allow multiple MAX109 converters to be time-interleaved to achieve higher effective sampling rates. When clocked at 2.2Gsps, the MAX109 provides a typical effective number of bits (ENOB) of 6.9 bits at an analog input frequency of 1600MHz. The MAX109 analog input is designed for both differential and single-ended use with a 500mVP-P full-scale input range. In addition, this fast ADC features an on-chip 2.5V precision bandgap reference. In order to improve the MAX109 gain error further, an external reference may be used (see the Internal Reference section). Figure 2. Ideal Transfer Function On-Chip Track/Hold Amplifier As with all ADCs, if the input waveform is changing rapidly during conversion, ENOB and signal-to-noise ratio (SNR) specifications will degrade. The MAX109’s on-chip, wide-bandwidth (2.8GHz) T/H amplifier reduces this effect and increases the ENOB performance significantly, allowing precise capture of fastchanging analog data at high conversion rates. The T/H amplifier accepts and buffers both DC- and AC-coupled analog input signals and allows a full-scale signal input range of 500mVP-P. The T/H amplifier’s differential 50Ω input termination simplifies interfacing to the MAX109 with controlled impedance lines. Figure 3 shows a simplified diagram of the T/H amplifier stage internal to the MAX109. ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs INPUT AMPLIFIER INP INN BUFFER AMPLIFIER T/H TO COMPARATORS 50Ω 50Ω CHOLD CLKP CLKN CLOCK SPLITTER 50Ω Clock System GNDI GNDI TO COMPARATORS 50Ω CLKCOM Figure 3. Internal Structure of the 3.2GHz T/H Amplifier CLKN CLKP tAW ANALOG INPUT tAD tAJ SAMPLED DATA (T/H) T/H TRACK HOLD TRACK APERTURE DELAY (tAD) APERTURE WIDTH (tAW) APERTURE JITTER (tAJ) Figure 4. T/H Aperture Timing Aperture width, delay, and jitter are parameters that affect the dynamic performance of high-speed converters. Aperture jitter, in particular, directly influences SNR and limits the maximum slew rate (dV/dt) that can be digitized without contributing significant errors. The MAX109’s innovative T/H amplifier design limits aperture jitter typically to 0.2ps. The MAX109 clock signals are terminated with 50Ω to the CLKCOM pin. The clock system provides clock signals, T/H amplifier, quantizer, and all back-end digital blocks. The MAX109 also produces a digitized output clock for synchronization with external FPGA or datacapture devices. Note that there is a 1.6ns delay between the clock input (CLKP/CLKN) and its digitized output representation (DCOP/DCON). Sampling Point Adjustment (SAMPADJ) The proper sampling point can be adjusted by utilizing SAMPADJ as the control line. SAMPADJ accepts an input-voltage range of 0 to 2.5V, correlating with up to 32ps timing adjustment. The nominal open-circuit voltage corresponds to the minimum sampling delay. With an input resistance RSAMPADJ of typically 50kΩ, this pin can be adjusted externally with a 10kΩ potentiometer connected between REFOUT and GNDI to adjust for the proper sampling point. T/H Amplifier to Quantizer Capture Point Adjustment (DELGATE0, DELGATE1) Another important feature of the MAX109, is the selection of the proper quantizer capture point between the T/H amplifier and the ADC core. Depending on the selected sampling speed for the application, two control lines can be utilized to set the proper capture point between these two circuits. DELGATE0 (LSB) and DELGATE1 (MSB) set the coarse timing of the proper capture point. Using these control lines allow the user to adjust the time after which the quantizer latches held data from the T/H amplifier between 25ps and 50ps (Table 1). This timing feature enables the MAX109 T/H amplifier to settle its output properly before the quantizer captures and digitizes the data, thereby achieving the best dynamic performance for any application. ______________________________________________________________________________________ 17 MAX109 SIMPLIFIED DIAGRAM (INPUT ESD PROTECTION NOT SHOWN). Aperture Width, Aperture Jitter, and Aperture Delay Aperture width (tAW) is the time the T/H circuit requires to disconnect the hold capacitor from the input circuit (e.g., to turn off the sampling bridge and put the T/H unit in hold mode). Aperture jitter (tAJ) is the sample-tosample variation in the time between the samples. Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample event is occurring (Figure 4). MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs Table 1. Timing Adjustments for T/H Amplifier and Quantizer DELGATE1 DELGATE0 TIME DELAY BETWEEN T/H AND QUANTIZER RECOMMENDED FOR CLOCK SPEEDS OF 0 1 25ps fCLK = 2.2Gsps to 2.5Gsps 1 0 50ps fCLK = 1.75Gsps to 2.2Gsps VCCO CMFB AOP–A7P BOP–B7P COP–C7P DOP–D7P DCOP RSTOUTP VCCO GNDO Internal Reference The MAX109 features an on-chip 2.5V precision bandgap reference used to generate the full-scale range for the data converter. Connecting REFIN with REFOUT applies the reference output to the positive input of the reference buffer. The buffer’s negative input is internally connected to GNDR. It is recommended that GNDR be connected to GNDI on the user’s application board. If required, REFOUT can source up to 2.5mA to supply other external devices. Additionally, an adjustable external reference can be used to adjust the ADC’s fullscale range. To use an external reference supply, connect a high-precision bandgap reference to the REFIN pin and leave the REFOUT pin floating. REFIN has a typical input resistance RREFIN of 5kΩ and accepts input voltages of 2.5V ±10%. Digital LVDS Outputs The MAX109 provides data in offset binary format to differential LVDS outputs on four output ports (PortA, PortB, PortC, and PortD). A simplified circuit schematic of the LVDS output cells is shown in Figure 5. All LVDS outputs are powered from the output driver supply V CC O, which can be operated at 3.3V ±10%. The MAX109 LVDS outputs provide a differential outputvoltage swing of 600mVP-P with a common-mode voltage of approximately 1.2V, and must be differentially terminated at the far end of each transmission line pair (true and complementary) with 100Ω. Data Out-of-Range Operation (DORP, DORN) A single differential output pair (DORP, DORN) is provided to flag an out-of-range condition, if the applied signal is outside the allowable input range, where outof-range is above positive full scale (+FS) or below 18 AON–A7N BON–B7N CON–C7N DON–D7N DCON RSTOUTN GNDO CMFB: COMMON-MODE FEEDBACK Figure 5. Simplified LVDS Output Circuitry Table 2. Data Rate Selection for Demultiplexer Operation DDR QDR DEMULTIPLEXER OPERATION DCO SPEED 0 X SDR mode, PortA, PortB, PortC, and PortD enabled, 550Msps per port fCLK / 4 1 0 DDR mode, PortA, PortB, PortC, and PortD enabled, 550Msps per port fCLK / 8 1 1 QDR mode, PortA, PortB, PortC, and PortD enabled, 550Msps per port fCLK / 16 X = Do not care. negative full scale (-FS). The DORP/DORN transitions high/low whenever any of the four output ports (PortA, PortB, PortC, and PortD) display out-of-range data. DORP/DORN features the same latency as the ADC output data and is demultiplexed in a similar fashion, so that this out-of-range signal and the data samples are time-aligned. Demultiplexer Operation The MAX109’s internal 1:4 demultiplexer spreads the ADC core’s 8-bit data across 32 true LVDS outputs and allows for easy data capture in three different modes. Two TTL/CMOS-compatible inputs are utilized to create the different modes: SDR (standard data rate), DDR ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs MAX109 ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN N N+1 N+2 N+3 N+4 N+5 CLKP tPD1 N+6 N+7 N+8 tPWH N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 tCLK tPWL DCON DCOP SAMPLE HERE tPD2 PORTA DATA N+1 N+5 PORTB DATA N+2 N+6 PORTC DATA N+3 N+7 N+4 N+8 PORTD DATA N NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK. Figure 6. Timing Diagram for SDR Mode, fCLK / 4 Mode (double data rate), and QDR (quadruple data rate). Setting these two bits for different modes allows the user to update and process the outputs at one-quarter (SDR mode), one-eighth (DDR mode), or one-sixteenth (QDR mode) the sampling clock (Table 2), relaxing the need for an ultra-fast FPGA or data-capture interface. Data is presented on all four ports of the converterdemultiplexer circuit outputs. Note that there is a data latency between the sampled data and each of the output ports. The data latency is 10.5 clock cycles for PortA, 9.5 clock cycles for PortB, 8.5 clock cycles for PortC, and 7.5 clock cycles for PortD. This holds true for all demultiplexer modes. Figures 6, 7, and 8 display the demultiplexer timing for fCLK / 4, fCLK / 8, and fCLK / 16 modes. Pseudorandom Number (PRN) Generator The MAX109 features a PRN generator that enables the user to test the demultiplexed digital outputs at full clock speed and with a known test pattern. The PRN generator is a combination of shift register and feedback logic with 255 states. When PRN is high, the inter- Table 3. Pseudorandom Number Generator Patterns CODE OUTPUT PRN PATTERN 1 00000001 2 00000010 3 00000100 4 00001000 5 00010001 6 00100011 7 01000111 8 10001110 9 00011100 10 00111000 — — — — 250 00110100 251 01101000 252 11010000 253 10100000 254 01000000 255 10000000 ______________________________________________________________________________________ 19 MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 CLKP tPD1DDR DCON DCOP tPD2DDR SAMPLE HERE PORTA DATA N+1 N+5 PORTB DATA N+2 N+6 PORTC DATA N+3 N+7 N+4 N+8 PORTD DATA N NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK. Figure 7. Timing Diagram for DDR Mode, fCLK / 8 Mode ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 CLKP tPD1QDR DCON DCOP FROM DLL IN FPGA tPD2QDR SAMPLE HERE PORTA DATA N+1 N+5 PORTB DATA N+2 N+6 PORTC DATA N+3 N+7 N+4 N+8 PORTD DATA N NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK. Figure 8. Timing Diagram for QDR Mode, fCLK / 16 Mode 20 ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs +250mV 500mVP-P FS ANALOG INPUT RANGE 500mV 0V INN -250mV t VIN = ±250mV Single-Ended Analog Inputs Figure 9. Single-Ended Analog Input Signal Swing INP INN +125mV ±250mV FS ANALOG INPUT RANGE 250mV Applications Information -250mV 0V -125mV t Figure 10. Differential Analog Input Signal Swing REFOUT The MAX109 is designed to work at full speed for both single-ended and differential analog inputs; however, for optimum dynamic performance it is recommended that the inputs are driven differentially. Inputs INP and INN feature on-chip, laser-trimmed 50Ω termination resistors. In a typical single-ended configuration, the analog input signal (Figure 9) enters the T/H amplifier stage at the in-phase input (INP), while the inverted phase input (INN) is reverse-terminated to GNDI with an external 50Ω resistor. Single-ended operation allows for an input amplitude of 500mVP-P. Table 4 shows a selection of input voltages and their corresponding output codes for single-ended operation. Differential Analog Inputs POTENTIOMETER 10kΩ To obtain a full-scale digital output with differential input drive (Figure 10), 250mVP-P must be applied between INP and INN (INP = 125mV and INN = -125mV). Midscale digital output codes (01111111 or 10000000) occur when there is no voltage difference between INP and INN. For a zero-scale digital output code, the inphase INP input must see -125mV and the inverted input INN must see 125mV. A differential input drive is recommended for best performance. Table 5 represents a selection of differential input voltages and their corresponding output codes. VOSADJ GNDI Figure 11. Offset Adjustment Circuit CLKP 1V 50Ω Offset Adjust CLKCOM 50Ω The MAX109 provides a control input (VOSADJ) to compensate for system offsets. The offset adjust input is a self-biased voltage-divider from the internal 2.5V precision reference. The nominal open-circuit voltage is one-half the reference voltage. With an input resistance (RVOSADJ) of typically 50kΩ, VOSADJ can be driven with an external 10kΩ potentiometer (Figure 11) connected between REFOUT and GNDI to correct for offset errors. For stabilizing purposes, decouple this output with a 0.01µF capacitor to GNDI. VOSADJ allows for a typical offset adjustment of ±10 LSB. GNDI CLKN SIMPLIFIED DIAGRAM (INPUT ESD PROTECTION NOT SHOWN). Clock Operation VEE Figure 12. Clock Input Structure The MAX109 clock inputs are designed for either single-ended or differential operation (Figure 12) with flexi- ______________________________________________________________________________________ 21 MAX109 nal shift register is enabled and multiplexed with the input of the 1:4 demultiplexer, replacing the quantizer 8-bit output. The test pattern consists of 8 bits. Table 3 depicts the composition of the first and last steps of the PRN pattern. The entire look-up table can be downloaded from the Maxim website at www.maxim-ic.com. INP MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs Table 4. Digital Output Codes Corresponding to a DC-Coupled Single-Ended Analog Input IN-PHASE/TRUE INPUT (INP) INVERTED/COMPLEMENTARY INPUT (INN) OUT-OF-RANGE BIT (DORP/DORN) OUTPUT CODE 250mV 0 1 11111111 (full scale) 250mV - 1 LSB 0 0 11111111 0 0 0 10000000 toggles 01111111 -250mV + 1 LSB 0 0 00000001 -250mV 0 0 00000000 (zero scale) <-250mV 0 1 00000000 (out of range) Table 5. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input IN-PHASE/TRUE INPUT (INP) INVERTED/COMPLEMENTARY INPUT (INN) OUT-OF-RANGE BIT (DORP/DORN) OUTPUT CODE 125mV -125mV 1 11111111 (full scale) 125mV - 0.5 LSB -125mV + 0.5 LSB 0 11111111 0 0 0 10000000 toggles 01111111 -125mV + 0.5 LSB 125mV - 0.5 LSB 0 00000001 -125mV 125mV 0 00000000 (zero scale) <-125mV >+125mV 1 00000000 (out of range) Table 6. Driving Options for DC-Coupled Clock CLKP CLKN CLKCOM REFERENCE Single-ended sine wave CLOCK DRIVE -10dBm to +15dBm Externally terminated to GNDI with 50Ω GNDI Figure 13a Differential sine wave Figure 13b -10dBm to +10dBm -10dBm to +10dBm GNDI Single-ended ECL ECL drive -1.3V -2V Figure 13c Differential ECL ECL drive ECL drive -2V Figure 13d Table 7. Demultiplexer and Reset Operations SIGNAL/PIN NAME TYPE FUNCTIONAL DESCRIPTION CLKP/CLKN Sampling clock inputs Master ADC timing signal. The ADC samples on the rising edge of CLKP. DCOP/DCON LVDS outputs Data clock output (LVDS). Output data changes on the rising edge of DCOP. RSTINP/RSTINN LVDS inputs Demultiplexer reset input signals. Resets the internal demultiplexer when asserted. RSTOUTP/RSTOUTN LVDS outputs Reset outputs for synchronizing the resets of multiple external devices. ble input drive requirements. Each clock input is terminated with an on-chip, laser-trimmed 50Ω resistor to CLKCOM (clock-termination return). The CLKCOM termination voltage can be connected anywhere between ground and -2V for compatibility with standard-ECL drive levels. The clock inputs are internally buffered with a preamplifier to ensure proper operation of the data converter, even with small-amplitude sine-wave sources. The MAX109 was designed for single-ended, low-phase 22 noise sine-wave clock signals with as little as 100mV amplitude (-10dBm), thereby eliminating the need for an external ECL clock buffer and its added jitter. Single-Ended Clock Inputs (Sine-Wave Drive) Excellent performance is obtained by AC- or DC-coupling a low-phase-noise sine-wave source into a single clock input (Figure 13a, Table 6). For proper DC balance, the undriven clock input should be externally ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs CLKN = 0V -0.5V t NOTE: CLKCOM = 0V Figure 13a. Single-Ended Clock Input—Sine-Wave Drive CLKP CLKN +0.5V -0.5V NOTE: CLKCOM = 0V t Figure 13b. Differential Clock Input—Sine-Wave Drive CLKP -0.8V CLKN = -1.3V Differential Clock Inputs (Sine-Wave Drive) The advantages of differential clock drive (Figure 13b, Table 6) can be obtained by using an appropriate balun transformer to convert single-ended sine-wave sources into differential drives. The precision on-chip, laser-trimmed 50Ω clock-termination resistors ensure excellent amplitude matching. See the Single-Ended Clock Inputs (Sine-Wave Drive) section for proper input amplitude requirements. Single-Ended Clock Inputs (ECL Drive) Configure the MAX109 for single-ended ECL clock drive by connecting the clock inputs as shown in Figure 13c and Table 6. A well-bypassed VBB supply (-1.3V) is essential to avoid coupling noise into the undriven clock input, which would degrade dynamic performance. Differential Clock Inputs (ECL Drive) Drive the MAX109 from a standard differential ECL clock source (Figure 13d, Table 6) by setting the clock termination voltage at CLKCOM to -2V. Bypass the clock termination return (CLKCOM) as close to the ADC as possible with a 0.01µF capacitor connected to GNDI. Demultiplexer Reset Operation -1.8V NOTE: CLKCOM = -2V t Figure 13c. Single-Ended Clock Input—ECL Drive CLKP CLKN -0.8V -1.8V NOTE: CLKCOM = -2V t Figure 13d. Differential Clock Input—ECL Drive 50Ω reverse-terminated to GNDI. The dynamic performance of the data converter is essentially unaffected by clock-drive power levels from -10dBm to +10dBm. The MAX109 dynamic performance specifications are determined by a single-ended clock drive of 10dBm. To avoid saturation of the input amplifier stage, limit the clock power level to a maximum of 15dBm. The MAX109 features an internal 1:4 demultiplexer that reduces the data rate of the output digital data to onequarter the sample clock rate. A reset for the demultiplexer is necessary when interleaving multiple MAX109 converters and/or synchronizing external demultiplexers. The simplified block diagram of Figure 1 shows that the demultiplexer reset signal path consists of four main circuit blocks. From input to output, they are the reset input dual latch, the reset pipeline, the demultiplexer clock generator, and the reset output. The signals associated with the demultiplexer-reset operation and the control of this section are listed in Table 7. Reset Input Dual Latch The reset input dual-latch circuit block accepts LVDS reset inputs. For applications that do not require a synchronizing reset, the reset inputs may be left open. Figure 14 shows a simplified schematic of the reset input structure. To latch the reset input data properly, the setup time (tSU) and the data-hold time (tHD) must be met with respect to the rising edge of the sample clock. The timing diagram of Figure 15 shows the timing relationship of the reset input and sampling clock. Reset Pipeline The next section in the reset signal path is the reset pipeline. This block adds clock cycles of latency to the ______________________________________________________________________________________ 23 MAX109 CLKP +0.5V MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs VCCO 500Ω RSTINP 500Ω RSTINN 100kΩ SIMPLIFIED DIAGRAM (INPUT ESD PROTECTION NOT SHOWN) GNDD VCCO Figure 14. Reset Circuitry—Input Structure RSTINP 50% 50% RSTINN tSU tHD CLKP 50% CLKN Figure 15. Timing Relationship between Sampling Clock and Reset Input reset signal to match the latency of the converted analog data through the ADC. In this way, when reset data arrives at the RSTOUTP/RSTOUTN LVDS output it will be time-aligned with the analog data present in data ports PortA, PortB, PortC, and PortD at the time the reset input was deasserted. Demultiplexer Clock Generator The demultiplexer clock generator creates the clocks required for the different modes of demultiplexer operation. DDR and QDR control the demultiplexed mode selection, as described in Table 2. The timing diagrams in Figures 6, 7, and 8 show the output timing and data alignment for SDR, DDR, and QDR modes, respectively. The phase relationship between the sampling clock at the CLKP/CLKN inputs and the DCO clock at the DCOP/DCON outputs is random at device power-up. Reset all MAX109 devices to a known DCO phase after initial power-up for applications such as interleaving, where two or more MAX109 devices are used to achieve higher effective sampling rates. This synchro- 24 nization is necessary to set the order of output samples between the devices. Resetting the converters accomplishes this synchronization. The reset signal is used to force the internal counter in the demultiplexer clockgenerator block to a known phase state. Reset Output Finally, the reset signal is presented in true LVDS format to the last block of the reset signal path. RSTOUT outputs the time-aligned reset signal, used for resetting additional external demultiplexers in applications that need further output data-rate reduction. Many demultiplexer devices require their reset signal to be asserted for several clock cycles while they are clocked. To accomplish this, the MAX109 DCO clock will continue to toggle while RSTOUT is asserted. When a single MAX109 device is used, no synchronizing reset is required because the order of the samples in the output ports remains unchanged, regardless of the phase of the DCO clock. In all modes, RSTOUT is delayed by 7.5 clock cycles, starting with the first rising edge of CLKP following the falling edge of the RSTINP signal. With the next reset cycle PortD data shows the expected and proper data on the output, while the remaining three ports (PortA, PortB, and PortC) keep their previous data, which may or may not be swallowed , depending on the power-up state of the demultiplexer clock generator. With the next cycle, the right data is presented for all four ports in the proper order. The aforementioned reset output and data-reset operation is valid for SDR, DDR, and QDR modes. Die Temperature Measurement The die temperature of the MAX109 can be determined by monitoring the voltage V TEMPMON between the TEMPMON output and GNDI. The corresponding voltage is proportional to the actual die temperature of the converter and can be calculated as follows: TDIE (°C) = [(VTEMPMON - VGNDI) × 1303.5] - 371 The MAX109 exhibits a typical TEMPMON voltage of 0.35V, resulting in an overall die temperature of +90°C. The converter’s die temperature can be lowered considerably by cooling the MAX109 with a properly sized heatsink. Adding airflow across the part with a small fan can further lower the die temperature, making the system more thermally manageable and stable. Thermal Management Depending on the application environment for the SBGA-packaged MAX109, the user can apply an external heatsink with integrated fan to the package after board assembly. Existing open-tooled heatsinks with ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs MAX109 ADC SAMPLE NUMBER ADC SAMPLES ON THE RISING EDGE OF CLKP CLKN CLKP RESET INPUT N N+1 N+2 RSTINN tSU N+3 N+4 N+5 N+6 N+7 N+8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 tHD RSTINP DCON DCOP SAMPLE HERE PORTA DATA N+5 PORTB DATA N+6 PORTC DATA N+7 PORTD DATA N+4 N+8 RSTOUTN RESETOUT DATA PORT RSTOUTP THE GRAY AREAS INDICATE A POWER-UP DEPENDENT STATE, WHICH IS UNKNOWN AT THE TIME THE RESET IS BEING ASSERTED. Figure 16. Reset Output Timing in Demultiplexed SDR Mode integrated fans are available from Co-Fan USA (e.g., the 30-1101-02 model, which is used on the evaluation kit of the MAX109). This particular heatsink with integrated fan is available with pre-applied adhesive for easy package mounting. puts, should be routed on 50Ω microstrip lines, such as those employed on the MAX109 evaluation kit. The MAX109 has separate analog and digital powersupply inputs: • VEE (-5V) is the analog and substrate supply Bypassing/Layout/Power Supply • VCCI (5V) to power the T/H amplifier, clock distribution, bandgap reference, and reference amplifier • VCCA (5V) to supply the ADC’s comparator array • VCCO (3.3V) to establish power for all LVDS-based circuit sections • VCCD (5V) to supply all logic circuits of the data converter The MAX109 VEE supply contacts must not be left open while the part is being powered up. To avoid this condition, add a high-speed Schottky diode (such as a Motorola 1N5817) between VEE and GNDI. This diode prevents the device substrate from forward biasing, which could cause latchup. All supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the PCB. For best performance, bypass all power supplies to the appropriate grounds with a 330µF and 33µF tantalum capacitor to filter powersupply noise, in parallel with 0.1µF capacitors and highquality 0.01µF ceramic chip capacitors. Each power Grounding and power-supply decoupling strongly influence the MAX109’s performance. At a 2.2GHz clock frequency and 8-bit resolution, unwanted digital crosstalk may couple through the input, reference, power supply, and ground connections and adversely influence the dynamic performance of the ADC. Therefore, closely follow the grounding and power-supply decoupling guidelines (Figure 17). Maxim strongly recommends using a multilayer printed circuit board (PCB) with separate ground and power-supply planes. Since the MAX109 has separate analog and digital ground connections (GNDA, GNDI, GNDR, and GNDD, respectively), the PCB should feature separate analog and digital ground sections connected at only one point (star ground at the power supply). Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. High-speed signals, including clocks, analog inputs, and digital out- ______________________________________________________________________________________ 25 MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX109, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. VCCO 330µF GNDD 33µF 0.1µF 0.01µF 0.01µF 0.01µF 0.01µF VCCI Offset Error GNDI 330µF 33µF 0.1µF 0.01µF 0.01µF 330µF 33µF 0.1µF 0.01µF 0.01µF 0.01µF Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally, the mid-scale MAX109 transition occurs at 0.5 LSB above mid scale. The offset error is the amount of deviation between the measured mid-scale transition point and the ideal midscale transition point. 0.01µF VCCA GNDA Bit Error Rates Errors resulting from metastable states may occur when the analog input voltage (at the time the sample is taken) falls close to the decision point of any one of the input comparators. Here, the magnitude of the error depends on the location of the comparator in the comparator network. If it is the comparator for the MSB, the error will reach full scale. The MAX109’s unique encoding scheme solves this problem by limiting the magnitude of these errors to 1 LSB. VCCD 330µF GNDD 33µF 0.1µF 0.01µF 0.01µF 0.01µF 0.01µF 330µF 33µF 0.1µF 0.01µF 0.01µF 0.01µF VEE 1N5817 GNDI 0.01µF VCCA = +4.75V TO +5.25V VCCD = +4.75V TO +5.25V VCCI = +4.75V TO +5.25V VCCO = +3.0V TO VCCD VEE = -4.75V TO -5.25V NOTE: LOCATE ALL 0.01µF CAPACITORS AS CLOSE AS POSSIBLE TO THE MAX109 DEVICE. Figure 17. MAX109 Decoupling and Bypassing Recommendations supply for the chip should have its own 0.01µF capacitor, which should be placed as close as possible to the MAX109 for optimum high-frequency noise filtering. Static/DC Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the MAX109, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. 26 Dynamic/AC Parameter Definitions Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first 15 harmonics (HD2 through HD16), and the DC offset: SNR = 20 x log (SIGNALRMS / NOISERMS) Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus ______________________________________________________________________________________ 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs Effective Number of Bits (ENOB) ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB is calculated from a curve fit referenced to the theoretical full-scale range. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 15 harmonics of the input signal to the fundamental itself. This is expressed as: ⎛ V22 + V32 + ... + V162 THD = 20 × log ⎜ ⎜ V1 ⎝ ⎞ ⎟ ⎟ ⎠ Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Third-Order Intermodulation (IM3) IM3 is the total power of the third-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones, fIN1 and fIN2. The individual input tone levels are at -7dBFS. The third-order intermodulation products are located at 2 x fIN1-fIN2, 2 x fIN2-fIN1, 2 x fIN1+fIN2, and 2 x fIN2+fIN1. Full-Power Bandwidth A large -1dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency. where V1 is the fundamental amplitude, and V2 through V16 are the amplitudes of the 2nd- through 16th-order harmonics (HD2 through HD16). ______________________________________________________________________________________ 27 MAX109 distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) SUPER BGA.EPS MAX109 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs PACKAGE OUTLINE, 25x25 / 27x27 MM SBGA 192 / 256 BALLS, 1.27 MM PITCH 21-0073 28 ______________________________________________________________________________________ E 1 2 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs PACKAGE OUTLINE, 25x25 / 27x27 MM SBGA 192 / 256 BALLS, 1.27 MM PITCH 21-0073 E 2 2 Note: The MAX109 is packaged in a 27mm x 27mm, 256 SBGA package. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 © 2007 Maxim Integrated Products CARDENAS is a registered trademark of Maxim Integrated Products, Inc. MAX109 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)