TI JM38510/11905BPA Low-noise jfet-input operational amplifier Datasheet

TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
D Low Power Consumption
D Wide Common-Mode and Differential
Voltage Ranges
D Low Input Bias and Offset Currents
D Output Short-Circuit Protection
D Low Total Harmonic Distortion
. . . 0.003% Typ
D Low Noise
D
D
D
D
D
Vn = 18 nV/√Hz Typ at f = 1 kHz
High Input Impedance . . . JFET Input Stage
Internal Frequency Compensation
Latch-Up-Free Operation
High Slew Rate . . . 13 V/μs Typ
Common-Mode Input Voltage Range
Includes VCC+
description/ordering information
The JFET-input operational amplifiers in the TL07x series are similar to the TL08x series, with low input bias
and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07x series ideally
suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input
impedance) coupled with bipolar output stages integrated on a single monolithic chip.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military
temperature range of −55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
description/ordering information (continued)
ORDERING INFORMATION
TA
VIOmax
AT 25°C
TL071CP
TL071CP
Tube of 50
TL072CP
TL072CP
Tube of 25
TL074CN
TL074CN
Tube of 75
TL071CD
Reel of 2500
TL071CDR
Tube of 75
TL072CD
Reel of 2500
TL072CDR
Tube of 50
TL074CD
Reel of 2500
TL074CDR
Reel of 2000
TL074CNSR
TL074
Reel of 2000
TL071CPSR
TL071
Reel of 2000
TL072CPSR
T072
Reel of 2000
TL072CPWR
T072
Tube of 90
TL074CPW
Reel of 2000
TL074CPWR
Tube of 50
TL071ACP
TL071ACP
Tube of 50
TL072ACP
TL072ACP
Tube of 25
TL074ACN
TL074ACN
Tube of 75
TL071ACD
Reel of 2500
TL071ACDR
Tube of 75
TL072ACD
Reel of 2500
TL072ACDR
Tube of 50
TL074ACD
Reel of 2500
TL074ACDR
SOP (PS)
Reel of 2000
TL072ACPSR
T072A
SOP (NS)
Reel of 2000
TL074ACNSR
TL074A
Tube of 50
TL071BCP
TL071BCP
Tube of 50
TL072BCP
TL072BCP
Tube of 25
TL074BCN
TL074BCN
Tube of 75
TL071BCD
Reel of 2500
TL071BCDR
Tube of 75
TL072BCD
Reel of 2500
TL072BCDR
Tube of 50
TL074BCD
Reel of 2500
TL074BCDR
Reel of 2000
TL074BCNSR
PDIP (N)
SOIC (D)
10 mV
SOP (NS)
SOP (PS)
TSSOP (PW)
PDIP (P)
PDIP (N)
0°C to 70°C
SOIC (D)
PDIP (P)
PDIP (N)
3 mV
SOIC (D)
SOP (NS)
†
2
TOP-SIDE
MARKING
Tube of 50
PDIP (P)
6 mV
ORDERABLE
PART NUMBER
PACKAGE†
TL071C
TL072C
TL074C
T074
071AC
072AC
TL074AC
071BC
072BC
TL074BC
TL074B
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
description/ordering information (continued)
ORDERING INFORMATION
TA
VIOmax
AT 25°C
TL071IP
TL071IP
Tube of 50
TL072IP
TL072IP
Tube of 25
TL074IN
TL074IN
Tube of 75
TL071ID
Reel of 2500
TL071IDR
Tube of 75
TL072ID
Reel of 2500
TL072IDR
Tube of 50
TL074ID
Reel of 2500
TL074IDR
CDIP (JG)
Tube of 50
TL072MJGB
TL072MJGB
CFP (U)
Tube of 150
TL072MUB
TL072MUB
LCCC (FK)
Tube of 55
TL072MFKB
TL072MFKB
CDIP (J)
Tube of 25
TL074MJB
TL074MJB
CFP (W)
Tube of 25
TL074MWB
TL074MWB
LCCC (FK)
Tube of 55
TL074MFKB
TL074MFKB
PDIP (N)
6 mV
SOIC (D)
6 mV
−55°C
55°C to 125°C
9 mV
†
TOP-SIDE
MARKING
Tube of 50
PDIP (P)
−40°C
40 C to 85°C
85 C
ORDERABLE
PART NUMBER
PACKAGE†
TL071I
TL072I
TL074I
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TL071, TL071A, TL071B
D, P, OR PS PACKAGE
(TOP VIEW)
OFFSET N1
IN−
IN+
VCC−
1
8
2
7
3
6
4
5
TL072, TL072A, TL072B
D, JG, P, PS, OR PW PACKAGE
(TOP VIEW)
NC
VCC+
OUT
OFFSET N2
1OUT
1IN−
1IN+
VCC−
1
8
2
7
3
6
4
5
TL074A, TL074B
D, J, N, NS, OR PW PACKAGE
TL074 . . . D, J, N, NS, PW,
OR W PACKAGE
(TOP VIEW)
VCC+
2OUT
2IN−
2IN+
1OUT
1IN−
1IN+
VCC+
2IN+
2IN−
2OUT
TL072
U PACKAGE
(TOP VIEW)
NC
1OUT
1IN−
1IN+
VCC−
5
17
6
16
7
15
8
14
9 10 11 12 13
8
4
7
5
6
3
12
4
11
5
10
6
9
7
8
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1IN−
1OUT
NC
4OUT
4IN−
NC
2OUT
NC
2IN−
NC
1IN+
NC
VCC+
NC
2IN+
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC − No internal connection
symbols
TL071
TL072 (each amplifier)
TL074 (each amplifier)
OFFSET N1
IN+
+
IN+
+
IN−
−
OUT
IN−
−
OUT
OFFSET N2
4
POST OFFICE BOX 655303
4OUT
4IN−
4IN+
VCC−
3IN+
3IN−
3OUT
TL074
FK PACKAGE
(TOP VIEW)
NC
1OUT
NC
V CC+
NC
NC
VCC+
NC
OUT
NC
13
2IN−
2OUT
NC
3OUT
3IN−
3 2 1 20 19
18
9
3
NC
V CC−
NC
2IN+
NC
4
NC
1IN−
NC
1IN+
NC
NC
V CC−
NC
OFFSET N2
NC
NC
IN−
NC
IN+
NC
10
2
14
2
NC
VCC+
2OUT
2IN−
2IN+
TL072
FK PACKAGE
(TOP VIEW)
NC
OFFSET N1
NC
NC
NC
TL071
FK PACKAGE
(TOP VIEW)
1
1
• DALLAS, TEXAS 75265
4IN+
NC
VCC−
NC
3IN+
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
schematic (each amplifier)
VCC+
IN+
64 Ω
IN−
128 Ω
OUT
64 Ω
C1
18 pF
ÎÎÎ
ÁÁÁ
ÁÁÁ
1080 Ω
1080 Ω
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC−
OFFSET
N1
OFFSET
N2
TL071 Only
All component values shown are nominal.
COMPONENT COUNT†
COMPONENT
TYPE
Resistors
Transistors
JFET
Diodes
Capacitors
epi-FET
†
TL071
TL072
TL074
11
14
2
1
1
1
22
28
4
2
2
2
44
56
6
4
4
4
Includes bias and trim circuitry
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (see Note 1): VCC+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
VCC− . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 V
Input voltage, VI (see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15 V
Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited
Package thermal impedance, θJA (see Notes 5 and 6): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97°C/W
D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W
PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W
PW package (8 pin) . . . . . . . . . . . . . . . . . . . 149°C/W
PW package (14 pin) . . . . . . . . . . . . . . . . . . 113°C/W
U package . . . . . . . . . . . . . . . . . . . . . . . . . . . 185°C/W
Package thermal impedance, θJC (see Notes 7 and 8): FK package . . . . . . . . . . . . . . . . . . . . . . . . . 5.61°C/W
J package . . . . . . . . . . . . . . . . . . . . . . . . . 15.05°C/W
JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W
W package . . . . . . . . . . . . . . . . . . . . . . . . 14.65°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J, JG, or W package . . . . . . . . . . . . 300°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC−.
2. Differential voltages are at IN+, with respect to IN−.
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the
dissipation rating is not exceeded.
5. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
6. The package thermal impedance is calculated in accordance with JESD 51-7.
7. Maximum power dissipation is a function of TJ(max), θJC, and TC. The maximum allowable power dissipation at any allowable case
temperature is PD = (TJ(max) − TC)/θJC. Operating at the absolute maximum TJ of 150°C can affect reliability.
8. The package thermal impedance is calculated in accordance with MIL-STD-883.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
electrical characteristics, VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS†
TL071C
TL072C
TL074C
TA‡
MIN
VIO
α
V
IO
IIO
VO = 0
0,
RS = 50 Ω
Temperature
coefficient of input
offset voltage
VO = 0,
RS = 50 Ω
Input offset current
VO = 0
Input bias current§
VICR
Common-mode
Common
mode
input voltage range
VOM
Maximum peak
output voltage
swing
TYP
MAX
3
10
Full range
Full range
18
25°C
5
100
65
200
Full range
RL ≥ 10 kΩ
6
MIN
TYP
MAX
2
3
7.5
MIN
100
65
200
MAX
3
6
8
18
5
100
65
200
5
100
pA
2
nA
65
200
pA
20
nA
2
7
7
±11
−12
to
15
±11
−12
to
15
±11
−12
to
15
±11
−12
to
15
25°C
±12
±13.5
±12
±13.5
±12
±13.5
±12
±13.5
±12
±12
±12
±12
±10
±10
±10
±10
mV
μV/°C
18
5
2
UNIT
TYP
5
18
7
TL071I
TL072I
TL074I
25°C
25
C
Full range
RL ≥ 2 kΩ
MAX
3
10
25°C
RL = 10 kΩ
TYP
13
Full range
VO = 0
MIN
TL071BC
TL072BC
TL074BC
V
V
Large-signal
differential voltage
amplification
B1
Unity-gain
bandwidth
25°C
3
3
3
3
ri
Input resistance
25°C
1012
1012
1012
1012
Ω
kSVR
Common mode
Common-mode
rejection ratio
Supply-voltage
rejection ratio
(ΔVCC ± /ΔVIO)
VO = ±10 V
V,
RL ≥ 2 kΩ
25°C
25
Full range
15
200
50
200
50
200
50
200
V/mV
25
25
25
MHz
VIC = VICRmin,
RS = 50 Ω
VO = 0,
25°C
70
100
75
100
75
100
75
100
dB
VCC = ± 9 V to ±15 V,
RS = 50 Ω
VO = 0,
25°C
70
100
80
100
80
100
80
100
dB
25°C
14
1.4
25°C
120
ICC
Supply current
(each amplifier)
VO = 0
0,
VO1/ VO2
Crosstalk
attenuation
AVD = 100
No load
2
5
2.5
14
1.4
120
2
5
2.5
14
1.4
120
2
5
2.5
14
1.4
120
2
5
2.5
mA
dB
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified.
Full range is TA = 0°C to 70°C for TL07_C,TL07_AC, TL07_BC and is TA = −40°C to 85°C for TL07_I.
§ Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in Figure 4. Pulse techniques must be used
that maintain the junction temperature as close to the ambient temperature as possible.
‡
7
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
AVD
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IIB
CMRR
†
Input offset voltage
25°C
TL071AC
TL072AC
TL074AC
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
electrical characteristics, VCC± = ±15 V (unless otherwise noted)
PARAMETER
TEST
CONDITIONS†
TA
TL071M
TL072M
‡
MIN
VIO
Input offset voltage
VO = 0
0,
RS = 50 Ω
αV
Temperature coefficient of
input offset voltage
VO = 0,
RS = 50 Ω
IIO
Input offset current
VO = 0
IO
IIB
Input bias current‡
VICR
Common-mode input
voltage range
VOM
Maximum
M
i
peakk output
t t
voltage swing
25°C
TL074M
TYP
MAX
3
6
Full range
MIN
TYP
3
9
Full range
18
25°C
5
Full range
100
5
25°C
65
200
65
25°C
±11
−12
to
15
±11
−12
to
15
RL ≥ 10 kΩ
25°C
±12
±13.5
±12
±13.5
Full range
RL ≥ 2 kΩ
25°C
±12
±12
±10
±10
35
200
35
mV
μV/°C
18
50
RL = 10 kΩ
9
15
20
VO = 0
UNIT
MAX
100
pA
20
nA
200
pA
50
nA
V
V
200
AVD
Large signal differential
Large-signal
voltage amplification
VO = ±10 V
V,
B1
Unity-gain bandwidth
TA = 25°C
3
3
1012
1012
Ω
RL ≥ 2 kΩ
15
V/mV
15
MHz
ri
Input resistance
TA = 25°C
CMRR
Common mode rejection
Common-mode
ratio
VIC = VICRmin,
RS = 50 Ω
VO = 0,
25°C
80
86
80
86
dB
kSVR
Supply voltage rejection
Supply-voltage
ratio (ΔVCC±/ΔVIO)
VCC = ±9 V to ±15 V,
RS = 50 Ω
VO = 0,
25°C
80
86
80
86
dB
ICC
Supply current (each
amplifier)
VO = 0,
25°C
1.4
VO1/VO2
Crosstalk attenuation
AVD = 100
25°C
120
No load
†
2.5
1.4
120
2.5
mA
dB
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in
Figure 4. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible.
‡ All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is
TA = −55°C to 125°C.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
operating characteristics, VCC± = ±15 V, TA = 25°C
TL07xM
PARAMETER
TEST CONDITIONS
SR
Slew rate at unity gain
VI = 10 V,
CL = 100 pF,
RL = 2 kΩ,
See Figure 1
tr
Rise time overshoot
Rise-time
factor
VI = 20 mV,
CL = 100 pF,
RL = 2 kΩ,
See Figure 1
Vn
Equivalent input noise
voltage
RS = 20 Ω
In
Equivalent input noise
current
RS = 20 Ω,
f = 1 kHz
THD
Total harmonic distortion
VIrms = 6 V,
RL ≥ 2 kΩ,
f = 1 kHz
AVD = 1,
RS ≤ 1 kΩ,
MIN
TYP
5
13
ALL OTHERS
MAX
MAX
UNIT
MIN
TYP
8
13
V/μs
μs
0.1
0.1
20%
20%
18
18
nV/√Hz
4
4
μV
0.01
0.01
0.003
%
0.003%
f = 1 kHz
f = 10 Hz to 10 kHz
pA/√Hz
PARAMETER MEASUREMENT INFORMATION
10 kΩ
−
VI
+
CL = 100 pF
1 kΩ
VO
RL = 2 kΩ
+
RL
IN−
CL = 100 pF
Figure 2. Gain-of-10 Inverting Amplifier
Figure 1. Unity-Gain Amplifier
−
TL071
OUT
IN+
N2
+
VI
−
VO
N1
100 kΩ
1.5 kΩ
VCC−
Figure 3. Input Offset-Voltage Null Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IIB
Input bias current
vs Free-air temperature
4
VOM
Maximum output voltage
vs Frequency
vs Free-air
Free air temperature
vs Load resistance
vs Supply voltage
5, 6, 7
8
9
10
AVD
Large signal differential voltage amplification
Large-signal
vs Free-air
Free air temperature
vs Frequency
11
12
Phase shift
vs Frequency
12
Normalized unity-gain bandwidth
vs Free-air temperature
13
Normalized phase shift
vs Free-air temperature
13
CMRR
Common-mode rejection ratio
vs Free-air temperature
14
ICC
Supply current
vs Supply voltage
vs Free-air temperature
15
16
PD
Total power dissipation
vs Free-air temperature
17
Normalized slew rate
vs Free-air temperature
18
Vn
Equivalent input noise voltage
vs Frequency
19
THD
Total harmonic distortion
vs Frequency
20
Large-signal pulse response
vs Time
21
Output voltage
vs Elapsed time
22
VO
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS†
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREQUENCY
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
100
±15
VOM
VOM − Maximum Peak Output Voltage − V
IIIB−
IB Input Bias Current − nA
VCC± = ±15 V
10
1
−50
−25
0
25
50
75
100
VCC± = ±15 V
VCC± = ±10 V
±7.5
ÎÎÎÎ
VCC± = ±5 V
±5
±2.5
125
0
100
1k
TA − Free-Air Temperature − °C
Figure 4
VCC± = ±15 V
±10
±15
RL = 2 kΩ
TA = 25°C
See Figure 2
VCC± = ±10 V
±7.5
ÁÁ
ÁÁ
ÁÁ
±5
VCC± = ±5 V
±2.5
0
100
1k
10 k
100 k
f − Frequency − Hz
1M
10 M
±12.5
±10
ÎÎÎÎ
ÎÎÎÎ
10 M
VCC± = ±15 V
RL = 2 kΩ
See Figure 2
TA = 25°C
ÎÎÎÎÎ
ÎÎÎÎÎ
TA = −55°C
±7.5
±5
ÁÁÁ
ÁÁÁ
ÁÁÁ
TA = 125°C
±2.5
0
10 k
Figure 6
†
1M
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREQUENCY
VOM
VOM − Maximum Peak Output Voltage − V
VOM
VOM − Maximum Peak Output Voltage − V
ÎÎÎÎÎ
ÎÎÎÎÎ
±12.5
10 k
100 k
f − Frequency − Hz
Figure 5
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREQUENCY
±15
RL = 10 kΩ
TA = 25°C
See Figure 2
ÎÎÎÎÎ
±10
ÁÁÁ
ÁÁÁ
0.1
0.01
−75
±12.5
ÎÎÎÎÎ
ÎÎÎÎÎ
40 k 100 k
400 k 1 M
f − Frequency − Hz
4M
10 M
Figure 7
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS†
MAXIMUM PEAK OUTPUT VOLTAGE
vs
LOAD RESISTANCE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
±15
RL = 10 kΩ
ÎÎÎÎ
ÎÎÎÎ
±12.5
VOM
VOM − Maximum Peak Output Voltage − V
VOM − Maximum Peak Output Voltage − V
VOM
±15
RL = 2 kΩ
±10
±7.5
±5
ÁÁ
ÁÁ
±2.5
VCC± = ±15 V
See Figure 2
0
−75
−50
−25
0
25
50
75
100
125
VCC± = ±15 V
TA = 25°C
See Figure 2
±12.5
ÁÁ
ÁÁ
±10
±7.5
±5
±2.5
0
0.1
0.2
TA − Free-Air Temperature − °C
0.4
1000
RL = 10 kΩ
TA = 25°C
±12.5
400
AVD
A
VD − Large-Signal Differential
Voltage Amplification − V/mV
VOM
VOM − Maximum Peak Output Voltage − V
7 10
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
±15
±10
±7.5
±5
±2.5
200
100
40
20
10
4
2
0
0
2
4
6
8
10
12
14
16
1
−75
VCC± = ±15 V
VO = ±10 V
RL = 2 kΩ
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
|VCC±| − Supply Voltage − V
Figure 11
Figure 10
12
4
Figure 9
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
†
2
RL − Load Resistance − kΩ
Figure 8
ÁÁ
ÁÁ
ÁÁ
0.7 1
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS†
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE SHIFT
vs
FREQUENCY
VCC± = ±5 V to ±15 V
RL = 2 kΩ
TA = 25°C
105
104
0°
Differential
Voltage
Amplification
103
45°
102
Phase Shift
AVD
A
VD − Large-Signal Differential
Voltage Amplification
106
90°
Phase Shift
101
135°
1
10
1
100
1k
10 k 100 k
f − Frequency − Hz
1M
180°
10 M
Figure 12
NORMALIZED UNITY-GAIN BANDWIDTH
AND PHASE SHIFT
vs
FREE-AIR TEMPERATURE
1.03
Unity-Gain Bandwidth
1.2
1.01
1.1
1
Phase Shift
1
0.99
0.9
0.8
0.7
−75
1.02
VCC± = ±15 V
RL = 2 kΩ
f = B1 for Phase Shift
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Normalized Phase Shift
Normalized Unity-Gain Bandwidth
1.3
0.98
0.97
125
Figure 13
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS†
SUPPLY CURRENT PER AMPLIFIER
vs
SUPPLY VOLTAGE
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
2
VCC± = ±15 V
ICC − Supply Current Per Amplifier − mA
I CC±
CMRR − Common-Mode Rejection Ratio − dB
89
RL = 10 kΩ
88
87
86
85
83
−75
1.6
1.4
1.2
1
0.8
ÁÁ
ÁÁ
84
−50
−25
0
25
50
75
100
TA = 25°C
No Signal
No Load
1.8
0.6
0.4
0.2
0
125
0
2
TA − Free-Air Temperature − °C
4
Figure 14
VCC± = ±15 V
No Signal
No Load
1.8
14
16
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
VCC± = ±15 V
No Signal
No Load
225
200
175
TL074
150
125
ÎÎÎÎ
ÎÎÎÎ
100
TL072
75
TL071
50
25
−50
−25
0
25
50
75
100
125
0
−75
−50
−25
0
25
50
75
100
TA − Free-Air Temperature − °C
Figure 16
14
12
250
TA − Free-Air Temperature − °C
†
10
TOTAL POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
PD
PD − Total Power Dissipation − mW
ICC − Supply Current Per Amplifier − mA
I CC±
2
0
−75
8
Figure 15
SUPPLY CURRENT PER AMPLIFIER
vs
FREE-AIR TEMPERATURE
ÁÁÁ
ÁÁÁ
ÁÁÁ
6
|VCC±| − Supply Voltage − V
Figure 17
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
NORMALIZED SLEW RATE
vs
FREE-AIR TEMPERATURE
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
Vn
V
nV/ Hz
n − Equivalent Input Noise Voltage − nV/Hz
Normalized Slew Rate − V/μ s
1.15
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
1.10
1.05
1
0.95
0.90
0.85
−75
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
50
VCC± = ±15 V
AVD = 10
RS = 20 Ω
TA = 25°C
40
30
20
10
0
−50
−25
0
25
50
75
100
10
125
40 100
TA − Free-Air Temperature − °C
Figure 18
6
VCC± = ±15 V
AVD = 1
VI(RMS) = 6 V
TA = 25°C
0.1
0.04
0.01
0.004
0.001
100
400
1k
4 k 10 k
f − Frequency − Hz
VOLTAGE-FOLLOWER
LARGE-SIGNAL PULSE RESPONSE
VI and VO − Input and Output Voltages − V
THD − Total Harmonic Distortion − %
0.4
40 k 100 k
Figure 19
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
1
400 1 k
4 k 10 k
f − Frequency − Hz
40 k 100 k
VCC± = ±15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
4
Output
2
0
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÎÎÎ
ÎÎÎ
−2
Input
−4
−6
0
0.5
1
1.5
t − Time − μs
2
2.5
3
3.5
Figure 21
Figure 20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
ELAPSED TIME
28
24
VO
V
O − Output Voltage − mV
Overshoot
20
90%
16
12
ÁÁÁ
ÁÁÁ
8
4
VCC± = ±15 V
RL = 2 kΩ
TA = 25°C
10%
0
tr
−4
0
0.1
0.2 0.3 0.4 0.5
t − Elapsed Time − μs
0.6
Figure 22
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
0.7
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
APPLICATION INFORMATION
Table of Application Diagrams
PART
NUMBER
FIGURE
0.5-Hz square-wave oscillator
TL071
23
High-Q notch filter
TL071
24
Audio-distribution amplifier
TL074
25
100-kHz quadrature oscillator
TL072
26
AC amplifier
TL071
27
APPLICATION DIAGRAM
RF = 100 kΩ
VCC+
−
Output
−
TL071
CF = 3.3 μF
Input
R1
R2
C3
+
−15 V
R1 + R2 + 2R3 + 1.5 MW
R3
C1
C2
9.1 kΩ
1
2p R
F
C
F
Figure 23. 0.5-Hz Square-Wave Oscillator
C1 + C2 + C3 + 110 pF
2
1
+ 1 kHz
fO +
2p R1 C1
Figure 24. High-Q Notch Filter
VCC+
−
1 MΩ
TL074
VCC+
+
VCC−
−
1 μF
TL074
VCC+
+
100 kΩ
Output B
VCC−
VCC+
VCC+
100 kΩ
TL074
Output C
+
100 μF
TL074
VCC−
100 kΩ
+
100 kΩ
−
Input
Output A
−
f+
Output
VCC−
1 kΩ
3.3 kΩ
TL071
+
15 V
3.3 kΩ
VCC−
Figure 25. Audio-Distribution Amplifier
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TL071, TL071A, TL071B, TL072
TL072A, TL072B, TL074, TL074A, TL074B
LOW-NOISE JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS080J − SEPTEMBER 1978 − REVISED MARCH 2005
APPLICATION INFORMATION
1N4148
6 sin ωt
18 kΩ (see Note A)
−15 V
18 pF
18 pF
1 kΩ
VCC+
VCC+
−
88.4 kΩ
TL072
−
+
6 cos ωt
TL072
+
88.4 kΩ
VCC−
1 kΩ
18 pF
VCC−
15 V
1N4148
18 kΩ (see Note A)
88.4 kΩ
NOTE A: These resistor values may be adjusted for a symmetrical output.
Figure 26. 100-kHz Quadrature Oscillator
VCC+
0.1 μF
10 kΩ
10 kΩ
IN−
1 MΩ
−
TL071
50 Ω
+
IN+
0.1 μF
10 kΩ
N2
N1
100 kΩ
Figure 27. AC Amplifier
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
OUT
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
8102304HA
OBSOLETE
81023052A
ACTIVE
8102305HA
ACTIVE
8102305PA
ACTIVE
81023062A
ACTIVE
LCCC
8102306CA
ACTIVE
8102306DA
ACTIVE
JM38510/11905BPA
ACTIVE
JM38510/11906BCA
OBSOLETE
TL071ACD
ACTIVE
TL071ACDE4
ACTIVE
TL071ACDG4
Pins Package Eco Plan (2)
Qty
Package
Drawing
LCCC
FK
20
1
TBD
CFP
U
10
1
TBD
A42
N / A for Pkg Type
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
FK
20
1
TBD
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
CFP
W
14
1
TBD
A42
N / A for Pkg Type
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
CDIP
J
14
TBD
Call TI
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071ACDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071ACDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071ACDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071ACP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071ACPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071BCD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071BCDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071BCDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071BCDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071BCDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071BCDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071BCP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071BCPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
10
TBD
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
Package
Type
Call TI
Call TI
POST-PLATE N / A for Pkg Type
POST-PLATE N / A for Pkg Type
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL071CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071CPSR
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CPSRE4
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CPSRG4
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071CPWLE
OBSOLETE
TSSOP
PW
8
TL071ID
ACTIVE
SOIC
D
8
TL071IDE4
ACTIVE
SOIC
D
TL071IDG4
ACTIVE
SOIC
TL071IDR
ACTIVE
TL071IDRE4
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
TBD
Call TI
Call TI
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071IDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL071IJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
TL071IP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL071MFKB
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
Call TI
TL071MJG
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
TL071MJGB
OBSOLETE
CDIP
JG
8
TBD
Call TI
Call TI
TL072ACD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072ACDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072ACDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072ACDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072ACDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072ACDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072ACJG
OBSOLETE
CDIP
JG
8
TL072ACP
ACTIVE
PDIP
P
8
50
Addendum-Page 2
TBD
Call TI
Pb-Free
CU NIPDAU
Call TI
N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL072ACPE4
ACTIVE
PDIP
P
8
TL072ACPSR
ACTIVE
SO
PS
8
TL072ACPSRE4
ACTIVE
SO
PS
TL072ACPSRG4
ACTIVE
SO
TL072BCD
ACTIVE
TL072BCDE4
Lead/Ball Finish
MSL Peak Temp (3)
(RoHS)
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072BCDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072BCDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072BCDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072BCDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072BCP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL072BCPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL072CD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CDE4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CDRE4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL072CPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL072CPSLE
OBSOLETE
SO
PS
8
TL072CPSR
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CPSRE4
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CPSRG4
ACTIVE
SO
PS
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CPWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL072CPWRE4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
CU NIPDAU
Level-1-260C-UNLIM
TBD
Addendum-Page 3
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL072CPWRG4
ACTIVE
TSSOP
PW
8
TL072ID
ACTIVE
SOIC
D
8
75
TL072IDE4
ACTIVE
SOIC
D
8
TL072IDG4
ACTIVE
SOIC
D
8
TL072IDR
ACTIVE
SOIC
D
TL072IDRE4
ACTIVE
SOIC
TL072IDRG4
ACTIVE
TL072IP
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL072IPE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL072MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
TL072MJG
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
TL072MJGB
ACTIVE
CDIP
JG
8
1
TBD
A42
N / A for Pkg Type
TL072MUB
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
TL074ACD
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACDE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACDR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACDRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACJ
OBSOLETE
CDIP
J
14
TBD
Call TI
TL074ACN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL074ACNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL074ACNSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACNSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ACNSRG4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074BCD
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074BCDE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 4
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL074BCDG4
ACTIVE
SOIC
D
14
TL074BCDR
ACTIVE
SOIC
D
TL074BCDRE4
ACTIVE
SOIC
TL074BCDRG4
ACTIVE
TL074BCN
50
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL074BCNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL074CD
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CDE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CDG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CDR
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CDRE4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CDRG4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CN
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL074CNE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL074CNSR
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CNSRE4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CNSRG4
ACTIVE
SO
NS
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CPWE4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CPWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CPWLE
OBSOLETE
TSSOP
PW
14
TBD
Call TI
TL074CPWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CPWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074CPWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074ID
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TL074IDE4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 5
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
11-Nov-2009
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TL074IDG4
ACTIVE
SOIC
D
14
TL074IDR
ACTIVE
SOIC
D
TL074IDRE4
ACTIVE
SOIC
TL074IDRG4
ACTIVE
TL074IJ
50
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
OBSOLETE
CDIP
J
14
TL074IN
ACTIVE
PDIP
N
14
TL074INE4
ACTIVE
PDIP
N
TBD
Call TI
Call TI
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TL074MFK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
TL074MFKB
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE N / A for Pkg Type
TL074MJ
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
TL074MJB
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
TL074MWB
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TL071ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071BCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL071CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL071IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072ACDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072ACPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL072BCDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL072CPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
TL072IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL072IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL074ACDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TL074ACNSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
TL074BCDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TL074CDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TL074CNSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
TL074CPWR
TSSOP
PW
14
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
TL074IDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL071ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TL071BCDR
SOIC
D
8
2500
340.5
338.1
20.6
TL071CDR
SOIC
D
8
2500
346.0
346.0
29.0
TL071CDR
SOIC
D
8
2500
340.5
338.1
20.6
TL071CPSR
SO
PS
8
2000
346.0
346.0
33.0
TL071IDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072ACDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072ACPSR
SO
PS
8
2000
346.0
346.0
33.0
TL072BCDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072CDR
SOIC
D
8
2500
346.0
346.0
29.0
TL072CDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072CPSR
SO
PS
8
2000
346.0
346.0
33.0
TL072CPWR
TSSOP
PW
8
2000
346.0
346.0
29.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Aug-2009
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL072IDR
SOIC
D
8
2500
340.5
338.1
20.6
TL072IDR
SOIC
D
8
2500
346.0
346.0
29.0
TL074ACDR
SOIC
D
14
2500
333.2
345.9
28.6
TL074ACNSR
SO
NS
14
2000
346.0
346.0
33.0
TL074BCDR
SOIC
D
14
2500
333.2
345.9
28.6
TL074CDR
SOIC
D
14
2500
333.2
345.9
28.6
TL074CNSR
SO
NS
14
2000
346.0
346.0
33.0
TL074CPWR
TSSOP
PW
14
2000
346.0
346.0
29.0
TL074IDR
SOIC
D
14
2500
333.2
345.9
28.6
Pack Materials-Page 3
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
0.063 (1,60)
0.015 (0,38)
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification.
Falls within MIL STD 1835 GDIP1-T8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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