TI1 MSP432P411YIPZ Simplelink mixed-signal microcontroller Datasheet

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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
MSP432P411x, MSP432P401x SimpleLink™ Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Core
– Arm® 32-Bit Cortex®-M4F CPU With Floating
Point Unit and Memory Protection Unit
– Frequency up to 48 MHz
– ULP Benchmark
– 150.6 ULPBench™-CP
Performance Benchmark
– 3.41 CoreMark/MHz
– 1.22 DMIPS/MHz (Dhrystone 2.1)
• Advanced Low-Power Analog Features
– SAR Analog-To-Digital Converter (ADC) With
16-Bit Precision and up to 1 Msps
– Differential and Single-Ended Inputs
– Two Window Comparators
– Up to 24 Input Channels
– Internal Voltage Reference With 25-ppm/°C
Typical Stability
– Two Analog Comparators
– Integrated LCD Driver With Contrast Control for
up to 320 Segments
• Memories
– Up to 2048KB of Flash Main Memory
(Organized Into Two Banks Enabling
Simultaneous Read or Execute During Erase)
– 32KB of Flash Information Memory (Including
area used for BSL, TLV, and Flash Mailbox)
– Up to 256KB of SRAM (Including 8KB of
Backup Memory)
– 2KB of Utility SRAM
– 32KB of ROM with MSP432™ Peripheral Driver
Libraries
• Ultra-Low-Power Operating Modes
– Active: 100 µA/MHz
– Low-Frequency Active: 95 µA (at 128 kHz)
– LPM3 (With RTC): 820 nA
– LPM3.5 (With RTC): 820 nA
– LPM4: 690 nA
– LPM4.5: 22 nA
• SimpleLink™ Platform
– Support for Bluetooth® Low Energy, Wi-Fi®, and
Sub-1 GHz
– Single Development Environment
– 100% Code Reuse Across SimpleLink SDK
• Operating Characteristics
– Wide Supply Voltage Range: 1.62 V to 3.7 V
– Temperature Range (Ambient): –40°C to 85°C
• Flexible Clocking Features
– Programmable Internal DCO (up to 48 MHz)
– 32.768-kHz Low-Frequency Crystal (LFXT)
– High-Frequency Crystal (HFXT) up to 48 MHz
– Low-Frequency Trimmed Internal Reference
Oscillator (REFO)
– Very-Low-Power Low-Frequency Internal
Oscillator (VLO)
– Module Oscillator (MODOSC)
– System Oscillator (SYSOSC)
• Code Security Features
– JTAG and SWD Lock
– IP Protection (up to Four Secure Flash Zones,
Each With Configurable Start Address and Size)
• Enhanced System Options
– Programmable Supervision and Monitoring of
Supply Voltage
– Multiple-Class Resets for Better Control of
Application and Debug
– 8-Channel DMA
– RTC With Calendar and Alarm Functions
• Timing and Control
– Up to Four 16-Bit Timers, Each With up to Five
Capture, Compare, PWM Capability
– Two 32-Bit Timers with Interrupt Generation
Capability
• Serial Communication
– Up to Four eUSCI_A Modules
– UART With Automatic Baud-Rate Detection
– IrDA Encode and Decode
– SPI (up to 16 Mbps)
– Up to Four eUSCI_B Modules
– I2C (With Multiple-Slave Addressing)
– SPI (up to 16 Mbps)
• Flexible I/O Features
– Ultra-Low-Leakage I/Os (±20 nA Maximum)
– All I/Os With Capacitive Touch Capability
– Up to 48 I/Os With Interrupt and Wake-up
Capability
– Up to 24 I/Os With Port Mapping Capability
– Eight I/Os With Glitch Filtering Capability
• Encryption and Data Integrity Accelerators
– 128-, 192-, or 256-Bit AES Encryption and
Decryption Accelerator
– 32-Bit Hardware CRC Engine
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
• JTAG and Debug Support
– 4-Pin JTAG and 2-Pin SWD Debug Interfaces
1.2
•
•
Applications
Metering
– Flow Meter
– Electric Meters
– Fault Detectors
– Field Transmitters
Building Automation
– Thermostat
– Security Systems
– Smoke Detectors
– Access Panels
1.3
– Serial Wire Trace
– Power Debug and Profiling of Applications
•
•
Factory Automation
– Wireless Power Monitor
– Predictive Failure Sensors
– Field Transmitter
– Foundational Field Bus
Health and Fitness
– Health Monitors
– Fitness Accessories
– Blood Glucose Meters
Description
The SimpleLink MSP432P411x and MSP432P401x microcontrollers (MCUs) are optimized wireless host
MCUs with an integrated 16-bit precision ADC, delivering ultra-low-power performance including 100
µA/MHz in active power and 820 nA in standby power with FPU and DSP extensions. As an optimized
wireless host MCU, the MSP432P411x and MSP432P401x let developers add high-precision analog and
memory extension to applications based on SimpleLink wireless connectivity solutions.
The MSP432P411x and MSP432P401x devices are part of the SimpleLink MCU platform, which consists
of Wi-Fi, Bluetooth low energy, Sub-1 GHz, and host MCUs. All share a common, easy-to-use
development environment with one core software development kit (SDK) and a rich tool set. A one-time
integration of the SimpleLink platform lets you add any combination of devices from the portfolio into your
design. The ultimate goal of the SimpleLink platform is to achieve 100 percent code reuse when your
design requirements change. For more information, visit www.ti.com/simplelink.
MSP432P411x and MSP432P401x MCUs are supported by a comprehensive ecosystem of tools,
software, documentation, training, and support to get your development started quickly. The LaunchPad™
development kit or MSP-TS432PZ100 target socket board (with additional MCU sample) along with the
free SimpleLink MSP432 SDK are all you need to get started.
Device Information
PART NUMBER
BODY SIZE
(2)
MSP432P4111PZ
MSP432P411YPZ
MSP432P411VPZ
LQFP (100)
14 mm × 14 mm
MSP432P4011RGC
MSP432P401YRGC
MSP432P401VRGC
VQFN (64)
9 mm × 9 mm
(1)
(2)
2
PACKAGE
(1)
For the most current part, package, and ordering information for all available devices, see the Package
Option Addendum in Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
Device Overview
Copyright © 2017–2018, Texas Instruments Incorporated
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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
1.4
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Functional Block Diagram
Figure 1-1 and Figure 1-2 show the functional block diagrams of the MSP432P411x and MSP432P401x
devices, respectively.
LFXIN, LFXOUT,
HFXIN HFXOUT
DCOR
PJ.x
P1.x to P10.x
LPM3.5 Domain
Capacitive Touch I/O 0,
Capacitive Touch I/O 1
DMA
PCM
PSS
Power
Control
Manager
Power
Supply
System
Backup
Memory
CS
RTC_C
WDT_A
Clock
System
Real-Time
Clock
Watchdog
Timer
Utility
SRAM
ROM
(Driver
Library)
RSTCTL
SYSCTL_A
Reset
Controller
System
Controller
SRAM
8KB
I/O Ports
I/O Ports
P1 to P10
78 I/Os
PJ
6 I/Os
8 Channels
Address
CPU
Bus
Control
Logic
Data
Flash
Arm
Cortex-M4F
2048KB
1024KB
512KB
SRAM
(includes
Backup
Memory)
256KB
128KB
2KB
32KB
AES256
Security
Encryption,
Decryption
CRC32
MPU
NVIC, SysTick
FPB, DWT
LCD_F
ITM, TPIU
JTAG, SWD
8-mux
up to
320
Segments
Precision
ADC
Comp_E0
Comp_E1
REF_A
1 Msps,
SAR A/D
Analog
Comparator
Voltage
Reference
TA0, TA1
TA2,TA3
Timer_A
16 Bit
5 CCR
Timer32
Two 32-bit
Timers
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA, SPI)
eUSCI_B0
eUSCI_B1
eUSCI_B2
eUSCI_B3
2
(I C, SPI)
Copyright © 2017, Texas Instruments Incorporated
Figure 1-1. MSP432P411x Functional Block Diagram
Device Overview
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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Copyright © 2017–2018, Texas Instruments Incorporated
3
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
LFXIN, LFXOUT,
HFXIN HFXOUT
DCOR
P1.x to P10.x
PJ.x
LPM3.5 Domain
Capacitive Touch I/O 0,
Capacitive Touch I/O 1
DMA
PCM
PSS
Power
Control
Manager
Power
Supply
System
Backup
Memory
CS
RTC_C
WDT_A
Clock
System
Real-Time
Clock
Watchdog
Timer
Utility
SRAM
ROM
(Driver
Library)
RSTCTL
SYSCTL_A
Reset
Controller
System
Controller
SRAM
8KB
I/O Ports
I/O Ports
P1 to P10
78 I/Os
PJ
6 I/Os
8 Channels
Address
CPU
Arm
Cortex-M4F
Bus
Control
Logic
Data
Flash
2048KB
1024KB
512KB
SRAM
(includes
Backup
Memory)
256KB
128KB
2KB
32KB
AES256
Security
Encryption,
Decryption
CRC32
MPU
NVIC, SysTick
FPB, DWT
ITM, TPIU
Precision
ADC
Comp_E0
Comp_E1
REF_A
JTAG, SWD
1 Msps,
SAR A/D
Analog
Comparator
Voltage
Reference
TA0, TA1
TA2,TA3
Timer_A
16 Bit
5 CCR
Timer32
Two 32-bit
Timers
eUSCI_A0
eUSCI_A1
eUSCI_A2
eUSCI_A3
(UART,
IrDA, SPI)
eUSCI_B0
eUSCI_B1
eUSCI_B2
eUSCI_B3
(I2C, SPI)
Copyright © 2017, Texas Instruments Incorporated
Figure 1-2. MSP432P401x Functional Block Diagram
The CPU and all of the peripherals in the device interact with each other through a common AHB matrix.
In some cases, there are bridges between the AHB ports and the peripherals. These bridges are
transparent to the application from a memory map perspective and, therefore, are not shown in the block
diagram.
4
Device Overview
Copyright © 2017–2018, Texas Instruments Incorporated
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Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table of Contents
1
2
3
Device Overview ......................................... 1
1.1
Features .............................................. 1
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
5
5.20
Revision History ......................................... 5
Device Comparison ..................................... 6
Related Products ..................................... 6
3.1
4
5.19
Terminal Configuration and Functions .............. 7
4.1
Pin Diagram for MSP432P411xI Devices ............ 7
4.2
Pin Diagram for MSP432P401xI Devices ............ 8
4.3
Pin Attributes ......................................... 9
4.4
Signal Descriptions .................................. 20
4.5
Pin Multiplexing
4.6
Buffer Types......................................... 29
4.7
Connections for Unused Pins ....................... 30
.....................................
6
29
Specifications ........................................... 31
........................
........................................
Recommended Operating Conditions ...............
Recommended External Components .............
Operating Mode VCC Ranges .......................
Operating Mode CPU Frequency Ranges .........
Operating Mode Peripheral Frequency Ranges ....
5.1
Absolute Maximum Ratings
31
5.2
ESD Ratings
31
5.3
5.4
5.5
5.6
5.7
5.8
31
32
32
33
33
Operating Mode Execution Frequency vs Flash
Wait-State Requirements ........................... 34
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
Current Consumption During Device Reset.........
Current Consumption in LDO-Based Active
Modes – Dhrystone 2.1 Program ...................
Current Consumption in DC/DC-Based Active
Modes – Dhrystone 2.1 Program ...................
Current Consumption in Low-Frequency Active
Modes – Dhrystone 2.1 Program ...................
Typical Characteristics of Active Mode Currents for
CoreMark Program ..................................
Typical Characteristics of Active Mode Currents for
Prime Number Program .............................
Typical Characteristics of Active Mode Currents for
Fibonacci Program ..................................
Typical Characteristics of Active Mode Currents for
While(1) Program ...................................
Typical Characteristics of Low-Frequency Active
Mode Currents for CoreMark Program ..............
7
35
35
8
35
36
37
38
39
40
41
Current Consumption in LDO-Based LPM0 Modes . 42
9
Current Consumption in DC/DC-Based LPM0
Modes ............................................... 42
Current Consumption in Low-Frequency LPM0
Modes ............................................... 42
5.21
Current Consumption in LPM3, LPM4 Modes ...... 43
5.22
Current Consumption in LPM3 Modes With LCD ... 44
5.23
Current Consumption in LPM3.5, LPM4.5 Modes .. 44
........ 45
................ 45
5.26 Timing and Switching Characteristics ............... 46
Detailed Description ................................... 97
6.1
Overview ............................................ 97
6.2
Processor and Execution Features ................. 97
6.3
Memory Map ........................................ 98
6.4
Memories on MSP432P4x1x....................... 121
6.5
DMA ................................................ 126
6.6
Memory Map Access Details ...................... 127
6.7
Interrupts ........................................... 128
6.8
System Control..................................... 131
6.9
Peripherals ......................................... 137
6.10 Code Development and Debug .................... 147
6.11 Performance Benchmarks ......................... 149
6.12 Input/Output Diagrams ............................. 151
6.13 Device Descriptors (TLV) .......................... 192
6.14 Identification........................................ 195
Applications, Implementation, and Layout ...... 197
7.1
Device Connection and Layout Fundamentals .... 197
5.24
Current Consumption of Digital Peripherals
5.25
Thermal Resistance Characteristics
7.2
Peripheral and Interface-Specific Design
Information ......................................... 198
Device and Documentation Support .............. 200
...................
8.1
Getting Started and Next Steps
8.2
Device and Development Tool Nomenclature ..... 200
8.3
Tools and Software ................................ 201
8.4
Documentation Support ............................ 203
8.5
Related Links
8.6
Community Resources............................. 205
8.7
Trademarks ........................................ 205
8.8
Electrostatic Discharge Caution
8.9
Export Control Notice .............................. 205
8.10
Glossary............................................ 206
......................................
...................
200
205
205
Mechanical, Packaging, and Orderable
Information ............................................. 206
2 Revision History
Changes from December 16, 2017 to February 2, 2018
•
Page
Removed mention of an internal charge pump on the LCD_F module in Section 6.9.11, LCD Controller (LCD_F) . 146
Revision History
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
Copyright © 2017–2018, Texas Instruments Incorporated
5
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
3 Device Comparison
Table 3-1 summarizes the features of MSP432P4x1x devices.
Table 3-1. Device Comparison
(1)
eUSCI
(1)
(2)
3.1
DEVICE
FLASH
(KB)
SRAM
(KB)
Precision ADC
(Channels)
LCD
(Segments)
COMP_E0
(Channels)
COMP_E1
(Channels)
Timer_A (2)
CHANNEL
A:
UART, IrDA,
SPI
CHANNEL
B:
SPI, I2C
20-mA
DRIVE
I/Os
TOTAL
I/Os
PACKAGE
MSP432P4111IPZ
2048
256
24 ext, 2 int
320
8
8
5, 5, 5, 5
4
4
4
84
100 PZ
MSP432P411YIPZ
1024
256
24 ext, 2 int
320
8
8
5, 5, 5, 5
4
4
4
84
100 PZ
MSP432P411VIPZ
512
128
24 ext, 2 int
320
8
8
5, 5, 5, 5
4
4
4
84
100 PZ
MSP432P4011IRGC
2048
256
12 ext, 2 int
N/A
2
4
5, 5, 5
3
3
4
48
64 RGC
MSP432P401YIRGC
1024
256
12 ext, 2 int
N/A
2
4
5, 5, 5
3
3
4
48
64 RGC
MSP432P401VIRGC
512
128
12 ext, 2 int
N/A
2
4
5, 5, 5
3
3
4
48
64 RGC
For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output
generators, respectively.
Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI Microcontrollers Low-power and high-performance MCUs, with wired and wireless connectivity options.
Products for SimpleLink MSP432 MCUs The SimpleLink MSP432 MCUs with an ultra-low-power Arm Cortex-M4 core are optimized for Internetof-Things sensor node applications. With an integrated Precision ADC, the family enables acquisition and processing of highprecision signals without sacrificing power and is an optimal host MCU for TI's SimpleLink wireless connectivity solutions.
Companion Products for MSP432P4111 Review products that are frequently purchased or used in conjunction with this product.
Reference Designs for MSP432P4111 The TI Designs Reference Design Library is a robust reference design library that spans analog,
embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include
schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.
6
Device Comparison
Copyright © 2017–2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
4 Terminal Configuration and Functions
4.1
Pin Diagram for MSP432P411xI Devices
P6.2/UCB1STE/C1.5/L27
P6.3/UCB1CLK/C1.4/L26
P6.4/UCB1SIMO/UCB1SDA/C1.3/L25
P6.5/UCB1SOMI/UCB1SCL/C1.2/L24
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
DVSS3
RSTn/NMI
AVSS2
PJ.2/HFXOUT
PJ.3/HFXIN
AVCC2
P7.0/PM_SMCLK/PM_DMAE0/R03
P7.1/PM_C0OUT/PM_TA0CLK/R13
P7.2/PM_C1OUT/PM_TA1CLK/R23
P7.3/PM_TA0.0
PJ.4/TDI
PJ.5/TDO/SWO
SWDIOTMS
SWCLKTCK
P9.4/UCA3STE/L43
P9.5/UCA3CLK/L42
P9.6/UCA3RXD/UCA3SOMI/L41
P9.7/UCA3TXD/UCA3SIMO/L40
P10.0/UCB3STE/L39
Figure 4-1 shows the pinout of the 100-pin PZ package.
67
P5.3/A2
P1.6/UCB0SIMO/UCB0SDA/L13
10
66
P5.2/A3
P1.7/UCB0SOMI/UCB0SCL/L12
11
65
P5.1/A4
VCORE
12
64
P5.0/A5
DVCC1
13
63
P4.7/A6
VSW
14
62
P4.6/A7
DVSS1
15
61
P4.5/A8
P2.0/PM_UCA1STE/L11
16
60
P4.4/HSMCLK/SVMHOUT/A9
P2.1/PM_UCA1CLK/L10
17
59
P4.3/MCLK/RTCCLK/A10
P2.2/PM_UCA1RXD/PM_UCA1SOMI/L9
18
58
P4.2/ACLK/TA2CLK/A11
P2.3/PM_UCA1TXD/PM_UCA1SIMO/L8
19
57
P4.1/A12/L12
P2.4/PM_TA0.1/L23
20
56
P4.0/A13/L13
P2.5/PM_TA0.2/L22
21
55
P6.1/A14/L14
P2.6/PM_TA0.3/L21
22
54
P6.0/A15/L15
P2.7/PM_TA0.4/L20
23
53
P9.1/A16/L16
P10.4/TA3.0/C0.7/L35
24
52
P9.0/A17/L17
P10.5/TA3.1/C0.6/L34
25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P8.7/A18/L18
P7.4/PM_TA1.4/C0.5/L31
A.
B.
C.
D.
E.
P8.6/A19/L19
9
P8.5/A20/L44
P5.4/A1
P1.5/UCB0CLK/L14
P8.4/A21/L45
68
P8.3/TA3CLK/A22/L46
8
P8.2/TA3.2/A23/L47
P5.5/A0
P1.4/UCB0STE/L15
AVCC1
69
DCOR
7
AVSS1
P5.6/TA2.1/VREF+/VeREF+/C1.7
P1.3/UCA0TXD/UCA0SIMO/L16
PJ.1/LFXOUT
70
PJ.0/LFXIN
6
AVSS3
P5.7/TA2.2/VREF-/VeREF-/C1.6
P1.2/UCA0RXD/UCA0SOMI/L17
P3.7/PM_UCB2SOMI/PM_UCB2SCL/L0
71
P3.6/PM_UCB2SIMO/PM_UCB2SDA/L1
5
P3.5/PM_UCB2CLK/L2
DVSS2
P1.1/UCA0CLK/L18
P3.4/PM_UCB2STE/L3
72
P3.3/PM_UCA2TXD/PM_UCA2SIMO/L4
4
P3.2/PM_UCA2RXD/PM_UCA2SOMI/L5
DVCC2
P1.0/UCA0STE/L19
P3.1/PM_UCA2CLK/L6
73
P3.0/PM_UCA2STE/L7
3
P8.1/UCB3CLK/TA2.0/C0.0
P9.2/TA3.3/L33
P10.3/UCB3SOMI/UCB3SCL/L36
P8.0/UCB3STE/TA1.0/C0.1
74
P7.7/PM_TA1.1/C0.2/L28
2
P7.6/PM_TA1.2/C0.3/L29
P9.3/TA3.4/L32
P10.2/UCB3SIMO/UCB3SDA/L37
P7.5/PM_TA1.3/C0.4/L30
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
P10.1/UCB3CLK/L38
The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default
mapping. See Section 6.9.2 for details.
A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-1. 100-Pin PZ Package (Top View)
Terminal Configuration and Functions
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Copyright © 2017–2018, Texas Instruments Incorporated
7
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
4.2
www.ti.com
Pin Diagram for MSP432P401xI Devices
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
DVSS3
RSTn/NMI
AVSS2
PJ.2/HFXOUT
PJ.3/HFXIN
AVCC2
P7.0/PM_SMCLK/PM_DMAE0
P7.1/PM_C0OUT/PM_TA0CLK
P7.2/PM_C1OUT/PM_TA1CLK
P7.3/PM_TA0.0
PJ.4/TDI
PJ.5/TDO/SWO
SWDIOTMS
SWCLKTCK
Figure 4-2 shows the pinout of the 64-pin RGC package.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
6
43
P5.4/A1
P1.6/UCB0SIMO/UCB0SDA
7
42
P5.3/A2
P1.7/UCB0SOMI/UCB0SCL
8
41
P5.2/A3
VCORE
9
40
P5.1/A4
DVCC1
10
39
P5.0/A5
VSW
11
38
P4.7/A6
DVSS1
12
37
P4.6/A7
P2.0/PM_UCA1STE
13
36
P4.5/A8
P2.1/PM_UCA1CLK
14
35
P4.4/HSMCLK/SVMHOUT/A9
P2.2/PM_UCA1RXD/PM_UCA1SOMI
15
34
P4.3/MCLK/RTCCLK/A10
P2.3/PM_UCA1TXD/PM_UCA1SIMO
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
A.
B.
C.
D.
E.
F.
P4.2/ACLK/TA2CLK/A11
AVCC1
DCOR
P5.5/A0
P1.5/UCB0CLK
AVSS1
44
PJ.1/LFXOUT
5
PJ.0/LFXIN
P5.6/TA2.1/VREF+/VeREF+/C1.7
P1.4/UCB0STE
AVSS3
45
P3.7/PM_UCB2SOMI/PM_UCB2SCL
4
P3.6/PM_UCB2SIMO/PM_UCB2SDA
P5.7/TA2.2/VREF-/VeREF-/C1.6
P1.3/UCA0TXD/UCA0SIMO
P3.5/PM_UCB2CLK
46
P3.4/PM_UCB2STE
3
P3.3/PM_UCA2TXD/PM_UCA2SIMO
DVSS2
P1.2/UCA0RXD/UCA0SOMI
P3.2/PM_UCA2RXD/PM_UCA2SOMI
47
P3.1/PM_UCA2CLK
DVCC2
2
P3.0/PM_UCA2STE
48
P1.1/UCA0CLK
P8.1/UCB3CLK/TA2.0/C0.0
1
P8.0/UCB3STE/TA1.0/C0.1
P1.0/UCA0STE
The secondary digital functions on Ports P2, P3, and P7 are fully mappable. This pinout shows only the default
mapping. See Section 6.9.2 for details.
A glitch filter is implemented on these digital I/Os: P1.0, P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, P6.7.
TI recommends connecting the thermal pad on the QFN package to DVSS.
UART BSL pins: P1.2 - BSLRXD, P1.3 - BSLTXD
SPI BSL pins: P1.4 - BSLSTE, P1.5 - BSLCLK, P1.6 - BSLSIMO, P1.7 - BSLSOMI
I2C BSL pins: P3.6 - BSLSDA, P3.7 - BSLSCL
Figure 4-2. 64-Pin RGC Package (Top View)
8
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
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MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
4.3
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Pin Attributes
Table 4-1 describes the attributes of the pins for the MSP432P411xI devices.
Table 4-1. Pin Attributes for MSP432P411xI
PIN NO.
(PZ
PACKAGE)
1
2
3
4
SIGNAL NAME
RESET STATE
AFTER POR (6)
DVCC
OFF
DVCC
N/A
L38
O
Analog
DVCC
N/A
P10.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3SIMO
I/O
LVCMOS
DVCC
N/A
UCB3SDA
I/O
LVCMOS
DVCC
N/A
L37
O
Analog
DVCC
N/A
P10.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3SOMI
I/O
LVCMOS
DVCC
N/A
UCB3SCL
I/O
LVCMOS
DVCC
N/A
L36
O
Analog
DVCC
N/A
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
N/A
UCA0SOMI
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
N/A
UCA0SIMO
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
L14
(7)
(5)
LVCMOS
L15
(1)
(2)
(3)
(4)
(5)
(6)
POWER SOURCE
LVCMOS
L16
9
(4)
I/O
P1.3 (RD)
8
BUFFER TYPE
I/O
L17
7
(3)
UCB3CLK
L18
6
SIGNAL TYPE
P10.1 (RD)
L19
5
(1) (2)
(RD) indicates the reset default signal name for that pin.
To determine the pin mux encodings for each pin, see Section 6.12.
Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
Buffer Types: See Section 4.6 for details
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
N/A = Not applicable
This LCD drive pin is also mirrored at a different location in the 100-pin PZ package. Assign the LCD drive output to only one pin at a
time.
Terminal Configuration and Functions
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9
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table 4-1. Pin Attributes for MSP432P411xI (continued)
PIN NO.
(PZ
PACKAGE)
10
SIGNAL NAME
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
N/A
UCB0SDA
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
N/A
UCB0SCL
I/O
LVCMOS
DVCC
N/A
(7)
O
Analog
DVCC
N/A
L12
12
VCORE
–
Power
DVCC
N/A
13
DVCC1
–
Power
N/A
N/A
14
VSW
–
Power
N/A
N/A
15
DVSS1
–
Power
N/A
N/A
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1STE
I/O
LVCMOS
DVCC
N/A
L11
O
Analog
DVCC
N/A
P2.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1CLK
I/O
LVCMOS
DVCC
N/A
L10
O
Analog
DVCC
N/A
P2.2 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1RXD
I
LVCMOS
DVCC
N/A
PM_UCA1SOMI
I/O
LVCMOS
DVCC
N/A
L9
O
Analog
DVCC
N/A
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1TXD
O
LVCMOS
DVCC
N/A
PM_UCA1SIMO
I/O
LVCMOS
DVCC
N/A
L8
O
Analog
DVCC
N/A
P2.4 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.1
I/O
LVCMOS
DVCC
N/A
L23
O
Analog
DVCC
N/A
P2.5 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.2
I/O
LVCMOS
DVCC
N/A
L22
O
Analog
DVCC
N/A
P2.6 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.3
I/O
LVCMOS
DVCC
N/A
L21
O
Analog
DVCC
N/A
P2.7 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.4
I/O
LVCMOS
DVCC
N/A
L20
O
Analog
DVCC
N/A
P10.4 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.0
I/O
LVCMOS
DVCC
N/A
C0.7
I
Analog
DVCC
N/A
L35
O
Analog
DVCC
N/A
P10.5 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.1
I/O
LVCMOS
DVCC
N/A
C0.6
I
Analog
DVCC
N/A
L34
O
Analog
DVCC
N/A
16
17
18
19
20
21
22
23
24
25
10
SIGNAL TYPE
P1.6 (RD)
L13
11
(1) (2)
Terminal Configuration and Functions
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-1. Pin Attributes for MSP432P411xI (continued)
PIN NO.
(PZ
PACKAGE)
26
27
28
29
30
SIGNAL NAME
(1) (2)
32
33
34
35
36
37
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
P7.4 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.4
I/O
LVCMOS
DVCC
N/A
C0.5
I
Analog
DVCC
N/A
L31
O
Analog
DVCC
N/A
P7.5 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.3
I/O
LVCMOS
DVCC
N/A
C0.4
I
Analog
DVCC
N/A
L30
O
Analog
DVCC
N/A
P7.6 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.2
I/O
LVCMOS
DVCC
N/A
C0.3
I
Analog
DVCC
N/A
L29
O
Analog
DVCC
N/A
P7.7 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA1.1
I/O
LVCMOS
DVCC
N/A
C0.2
I
Analog
DVCC
N/A
L28
O
Analog
DVCC
N/A
P8.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3STE
I/O
LVCMOS
DVCC
N/A
TA1.0
I/O
LVCMOS
DVCC
N/A
C0.1
31
SIGNAL TYPE
I
Analog
DVCC
N/A
P8.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3CLK
I/O
LVCMOS
DVCC
N/A
TA2.0
I/O
LVCMOS
DVCC
N/A
C0.0
I
Analog
DVCC
N/A
P3.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2STE
I/O
LVCMOS
DVCC
N/A
L7
O
Analog
DVCC
N/A
P3.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2CLK
I/O
LVCMOS
DVCC
N/A
L6
O
Analog
DVCC
N/A
P3.2 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2RXD
I
LVCMOS
DVCC
N/A
PM_UCA2SOMI
I/O
LVCMOS
DVCC
N/A
L5
O
Analog
DVCC
N/A
P3.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2TXD
O
LVCMOS
DVCC
N/A
PM_UCA2SIMO
I/O
LVCMOS
DVCC
N/A
L4
O
Analog
DVCC
N/A
P3.4 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2STE
I/O
LVCMOS
DVCC
N/A
L3
O
Analog
DVCC
N/A
P3.5 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2CLK
I/O
LVCMOS
DVCC
N/A
L2
O
Analog
DVCC
N/A
Terminal Configuration and Functions
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11
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table 4-1. Pin Attributes for MSP432P411xI (continued)
PIN NO.
(PZ
PACKAGE)
38
39
40
41
42
SIGNAL NAME
(1) (2)
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
P3.6 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2SIMO
I/O
LVCMOS
DVCC
N/A
PM_UCB2SDA
I/O
LVCMOS
DVCC
N/A
L1
O
Analog
DVCC
N/A
P3.7 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2SOMI
I/O
LVCMOS
DVCC
N/A
PM_UCB2SCL
I
LVCMOS
DVCC
N/A
L0
O
Analog
DVCC
N/A
AVSS3
–
Power
N/A
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
PJ.1 (RD)
I/O
LVCMOS
DVCC
OFF
PJ.0 (RD)
LFXIN
LFXOUT
O
Analog
DVCC
N/A
43
AVSS1
–
Power
N/A
N/A
44
DCOR
–
Analog
N/A
N/A
45
AVCC1
–
Power
N/A
N/A
P8.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.2
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
46
47
48
49
50
A23
L47
O
Analog
DVCC
N/A
P8.3 (RD)
I/O
LVCMOS
DVCC
OFF
I
LVCMOS
DVCC
N/A
A22
I
Analog
DVCC
N/A
L46
O
Analog
DVCC
N/A
P8.4 (RD)
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
TA3CLK
A21
L45
O
Analog
DVCC
N/A
P8.5 (RD)
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
A20
L44
O
Analog
DVCC
N/A
P8.6 (RD)
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
A19
L19
(7)
P8.7 (RD)
51
A18
L18
(7)
P9.0 (RD)
52
A17
L17
(7)
P9.1 (RD)
53
A16
L16
(7)
P6.0 (RD)
54
A15
L15
12
SIGNAL TYPE
(7)
Terminal Configuration and Functions
O
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
O
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
O
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
O
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
O
Analog
DVCC
N/A
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MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-1. Pin Attributes for MSP432P411xI (continued)
PIN NO.
(PZ
PACKAGE)
SIGNAL NAME
(1) (2)
P6.1 (RD)
55
A14
L14
(7)
P4.0 (RD)
56
A13
62
63
64
65
66
67
68
69
70
(5)
RESET STATE
AFTER POR (6)
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
O
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
DVCC
N/A
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
O
Analog
DVCC
N/A
P4.2 (RD)
I/O
LVCMOS
DVCC
OFF
ACLK
O
LVCMOS
DVCC
N/A
TA2CLK
I
LVCMOS
DVCC
N/A
A12
(7)
I
Analog
DVCC
N/A
P4.3 (RD)
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
N/A
RTCCLK
O
LVCMOS
DVCC
N/A
A10
61
POWER SOURCE
Analog
A11
60
(4)
Analog
L12
59
BUFFER TYPE
I
(7)
P4.1 (RD)
58
(3)
O
L13
57
SIGNAL TYPE
I
Analog
DVCC
N/A
P4.4 (RD)
I/O
LVCMOS
DVCC
OFF
HSMCLK
O
LVCMOS
DVCC
N/A
SVMHOUT
O
LVCMOS
DVCC
N/A
A9
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
P4.5 (RD)
A8
P4.6 (RD)
A7
P4.7 (RD)
A6
P5.0 (RD)
A5
P5.1 (RD)
A4
P5.2 (RD)
A3
P5.3 (RD)
A2
P5.4 (RD)
A1
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
P5.6 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.1
I/O
LVCMOS
DVCC
N/A
VREF+
O
Analog
DVCC
N/A
VeREF+
I
Analog
DVCC
N/A
C1.7
I
Analog
DVCC
N/A
P5.5 (RD)
A0
Terminal Configuration and Functions
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table 4-1. Pin Attributes for MSP432P411xI (continued)
PIN NO.
(PZ
PACKAGE)
SIGNAL NAME
(1) (2)
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
P5.7 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.2
I/O
LVCMOS
DVCC
N/A
VREF-
O
Analog
DVCC
N/A
VeREF-
I
Analog
DVCC
N/A
C1.6
I
Analog
DVCC
N/A
72
DVSS2
–
Power
N/A
N/A
73
DVCC2
71
74
75
76
77
78
79
80
–
Power
N/A
N/A
P9.2 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.3
I/O
LVCMOS
DVCC
N/A
L33
O
Analog
DVCC
N/A
P9.3 (RD)
I/O
LVCMOS
DVCC
OFF
TA3.4
I/O
LVCMOS
DVCC
N/A
L32
O
Analog
DVCC
N/A
P6.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1STE
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
C1.5
L27
O
Analog
DVCC
N/A
P6.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1CLK
I/O
LVCMOS
DVCC
N/A
C1.4
I
Analog
DVCC
N/A
L26
O
Analog
DVCC
N/A
P6.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SIMO
I/O
LVCMOS
DVCC
N/A
UCB1SDA
I/O
LVCMOS
DVCC
N/A
C1.3
I
Analog
DVCC
N/A
L25
O
Analog
DVCC
N/A
P6.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB1SOMI
I/O
LVCMOS
DVCC
N/A
UCB1SCL
I/O
LVCMOS
DVCC
N/A
C1.2
I
Analog
DVCC
N/A
L24
O
Analog
DVCC
N/A
P6.6 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.3
I/O
LVCMOS
DVCC
N/A
UCB3SIMO
I/O
LVCMOS
DVCC
N/A
UCB3SDA
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P6.7 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.4
I/O
LVCMOS
DVCC
N/A
UCB3SOMI
I/O
LVCMOS
DVCC
N/A
UCB3SCL
C1.1
81
82
83
84
14
SIGNAL TYPE
I/O
LVCMOS
DVCC
N/A
C1.0
I
Analog
DVCC
N/A
DVSS3
–
Power
N/A
N/A
RSTn (RD)
I
LVCMOS
DVCC
PU
NMI
I
LVCMOS
DVCC
N/A
AVSS2
–
Power
N/A
N/A
Terminal Configuration and Functions
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-1. Pin Attributes for MSP432P411xI (continued)
PIN NO.
(PZ
PACKAGE)
85
86
87
88
89
SIGNAL NAME
(1) (2)
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
PJ.2 (RD)
I/O
LVCMOS
DVCC
OFF
HFXOUT
O
Analog
DVCC
N/A
PJ.3 (RD)
I/O
LVCMOS
DVCC
OFF
HFXIN
I
Analog
DVCC
N/A
AVCC2
–
Power
N/A
N/A
P7.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_SMCLK
O
LVCMOS
DVCC
N/A
PM_DMAE0
I
LVCMOS
DVCC
N/A
R03
I
Analog
DVCC
N/A
P7.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_C0OUT
O
LVCMOS
DVCC
N/A
PM_TA0CLK
I
LVCMOS
DVCC
N/A
R13
90
SIGNAL TYPE
I
Analog
DVCC
N/A
P7.2 (RD)
I/O
LVCMOS
DVCC
OFF
PM_C1OUT
O
LVCMOS
DVCC
N/A
PM_TA1CLK
I
LVCMOS
DVCC
N/A
R23
I
Analog
DVCC
N/A
P7.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.0
I/O
LVCMOS
DVCC
N/A
PJ.4
I/O
LVCMOS
DVCC
N/A
I
LVCMOS
DVCC
PU
PJ.5
I/O
LVCMOS
DVCC
N/A
TDO (RD)
O
LVCMOS
DVCC
N/A
SWO
O
LVCMOS
DVCC
N/A
94
SWDIOTMS
I/O
LVCMOS
DVCC
PU
95
SWCLKTCK
I
LVCMOS
DVCC
PD
P9.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3STE
I/O
LVCMOS
DVCC
N/A
L43
O
Analog
DVCC
N/A
P9.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3CLK
I/O
LVCMOS
DVCC
N/A
L42
O
Analog
DVCC
N/A
P9.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3RXD
I
LVCMOS
DVCC
N/A
UCA3SOMI
I/O
LVCMOS
DVCC
N/A
L41
O
Analog
DVCC
N/A
P9.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA3TXD
O
LVCMOS
DVCC
N/A
UCA3SIMO
I/O
LVCMOS
DVCC
N/A
91
92
93
96
97
98
99
100
TDI (RD)
L40
O
Analog
DVCC
N/A
P10.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3STE
I/O
LVCMOS
DVCC
N/A
L39
O
Analog
DVCC
N/A
Terminal Configuration and Functions
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
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Table 4-2 describes the attributes of the pins for the MSP432P401xI devices.
Table 4-2. Pin Attributes for MSP432P401xI
PIN NO.
(RGC
PACKAGE)
1
2
3
4
5
6
7
8
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
OFF
P1.0 (RD)
I/O
LVCMOS
DVCC
UCA0STE
I/O
LVCMOS
DVCC
N/A
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
N/A
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
N/A
UCA0SOMI
I/O
LVCMOS
DVCC
N/A
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
N/A
UCA0SIMO
I/O
LVCMOS
DVCC
N/A
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
N/A
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
N/A
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
N/A
UCB0SDA
I/O
LVCMOS
DVCC
N/A
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
N/A
UCB0SCL
I/O
LVCMOS
DVCC
N/A
VCORE
–
Power
DVCC
N/A
10
DVCC1
–
Power
N/A
N/A
11
VSW
–
Power
N/A
N/A
12
DVSS1
–
Power
N/A
N/A
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1STE
I/O
LVCMOS
DVCC
N/A
P2.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1CLK
I/O
LVCMOS
DVCC
N/A
P2.2 (RD)
14
15
16
16
(1) (2)
9
13
(1)
(2)
(3)
(4)
(5)
(6)
SIGNAL NAME
I/O
LVCMOS
DVCC
OFF
PM_UCA1RXD
I
LVCMOS
DVCC
N/A
PM_UCA1SOMI
I/O
LVCMOS
DVCC
N/A
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA1TXD
O
LVCMOS
DVCC
N/A
PM_UCA1SIMO
I/O
LVCMOS
DVCC
N/A
(RD) indicates the reset default signal name for that pin.
To determine the pin mux encodings for each pin, see Section 6.12.
Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
Buffer Types: See Section 4.6 for details
The power source shown in this table is the I/O power source, which may differ from the module power source.
Reset States:
OFF = High-impedance with Schmitt trigger and pullup or pulldown (if available) disabled
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
N/A = Not applicable
Terminal Configuration and Functions
Copyright © 2017–2018, Texas Instruments Incorporated
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-2. Pin Attributes for MSP432P401xI (continued)
PIN NO.
(RGC
PACKAGE)
17
18
19
20
21
22
23
24
25
26
27
28
29
SIGNAL NAME
(1) (2)
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
P8.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3STE
I/O
LVCMOS
DVCC
N/A
TA1.0
I/O
LVCMOS
DVCC
N/A
C0.1
I
Analog
DVCC
N/A
P8.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB3CLK
I/O
LVCMOS
DVCC
N/A
TA2.0
I/O
LVCMOS
DVCC
N/A
C0.0
I
Analog
DVCC
N/A
P3.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2STE
I/O
LVCMOS
DVCC
N/A
P3.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2CLK
I/O
LVCMOS
DVCC
N/A
P3.2 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2RXD
I
LVCMOS
DVCC
N/A
PM_UCA2SOMI
I/O
LVCMOS
DVCC
N/A
P3.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCA2TXD
O
LVCMOS
DVCC
N/A
PM_UCA2SIMO
I/O
LVCMOS
DVCC
N/A
P3.4 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2STE
I/O
LVCMOS
DVCC
N/A
P3.5 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2CLK
I/O
LVCMOS
DVCC
N/A
P3.6 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2SIMO
I/O
LVCMOS
DVCC
N/A
PM_UCB2SDA
I/O
LVCMOS
DVCC
N/A
P3.7 (RD)
I/O
LVCMOS
DVCC
OFF
PM_UCB2SOMI
I/O
LVCMOS
DVCC
N/A
PM_UCB2SCL
I
LVCMOS
DVCC
N/A
AVSS3
–
Power
N/A
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
PJ.1 (RD)
I/O
LVCMOS
DVCC
OFF
PJ.0 (RD)
LFXIN
LFXOUT
O
Analog
DVCC
N/A
30
AVSS1
–
Power
N/A
N/A
31
DCOR
–
Analog
N/A
N/A
32
AVCC1
–
Power
N/A
N/A
P4.2 (RD)
I/O
LVCMOS
DVCC
OFF
ACLK
O
LVCMOS
DVCC
N/A
TA2CLK
I
LVCMOS
DVCC
N/A
33
A11
34
I
Analog
DVCC
N/A
P4.3 (RD)
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
N/A
RTCCLK
O
LVCMOS
DVCC
N/A
A10
I
Analog
DVCC
N/A
Terminal Configuration and Functions
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17
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table 4-2. Pin Attributes for MSP432P401xI (continued)
PIN NO.
(RGC
PACKAGE)
35
36
37
38
39
40
41
42
43
44
45
SIGNAL NAME
(1) (2)
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
P4.4 (RD)
I/O
LVCMOS
DVCC
OFF
HSMCLK
O
LVCMOS
DVCC
N/A
SVMHOUT
O
LVCMOS
DVCC
N/A
A9
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
P4.5 (RD)
A8
P4.6 (RD)
A7
P4.7 (RD)
A6
P5.0 (RD)
A5
P5.1 (RD)
A4
P5.2 (RD)
A3
P5.3 (RD)
A2
P5.4 (RD)
A1
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
I/O
LVCMOS
DVCC
OFF
I
Analog
DVCC
N/A
P5.6 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.1
I/O
LVCMOS
DVCC
N/A
VREF+
O
Analog
DVCC
N/A
VeREF+
I
Analog
DVCC
N/A
P5.5 (RD)
A0
C1.7
I
Analog
DVCC
N/A
P5.7 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.2
I/O
LVCMOS
DVCC
N/A
VREF-
O
Analog
DVCC
N/A
VeREF-
I
Analog
DVCC
N/A
C1.6
I
Analog
DVCC
N/A
47
DVSS2
–
Power
N/A
N/A
48
DVCC2
–
Power
N/A
N/A
P6.6 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.3
I/O
LVCMOS
DVCC
N/A
UCB3SIMO
I/O
LVCMOS
DVCC
N/A
UCB3SDA
I/O
LVCMOS
DVCC
N/A
I
Analog
DVCC
N/A
P6.7 (RD)
I/O
LVCMOS
DVCC
OFF
TA2.4
I/O
LVCMOS
DVCC
N/A
UCB3SOMI
I/O
LVCMOS
DVCC
N/A
UCB3SCL
46
49
C1.1
50
51
18
SIGNAL TYPE
I/O
LVCMOS
DVCC
N/A
C1.0
I
Analog
DVCC
N/A
DVSS3
–
Power
N/A
N/A
Terminal Configuration and Functions
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-2. Pin Attributes for MSP432P401xI (continued)
PIN NO.
(RGC
PACKAGE)
52
53
54
55
56
57
58
59
SIGNAL NAME
(1) (2)
SIGNAL TYPE
(3)
BUFFER TYPE
(4)
POWER SOURCE
(5)
RESET STATE
AFTER POR (6)
RSTn (RD)
I
LVCMOS
DVCC
PU
NMI
I
LVCMOS
DVCC
N/A
AVSS2
PJ.2 (RD)
–
Power
N/A
N/A
I/O
LVCMOS
DVCC
OFF
HFXOUT
O
Analog
DVCC
N/A
PJ.3 (RD)
I/O
LVCMOS
DVCC
OFF
HFXIN
I
Analog
DVCC
N/A
AVCC2
–
Power
N/A
N/A
P7.0 (RD)
I/O
LVCMOS
DVCC
OFF
PM_SMCLK
O
LVCMOS
DVCC
N/A
PM_DMAE0
I
LVCMOS
DVCC
N/A
P7.1 (RD)
I/O
LVCMOS
DVCC
OFF
PM_C0OUT
O
LVCMOS
DVCC
N/A
PM_TA0CLK
I
LVCMOS
DVCC
N/A
P7.2 (RD)
I/O
LVCMOS
DVCC
OFF
PM_C1OUT
O
LVCMOS
DVCC
N/A
PM_TA1CLK
I
LVCMOS
DVCC
N/A
P7.3 (RD)
I/O
LVCMOS
DVCC
OFF
PM_TA0.0
I/O
LVCMOS
DVCC
N/A
PJ.4
I/O
LVCMOS
DVCC
N/A
I
LVCMOS
DVCC
PU
PJ.5
I/O
LVCMOS
DVCC
N/A
TDO (RD)
O
LVCMOS
DVCC
N/A
SWO
O
LVCMOS
DVCC
N/A
63
SWDIOTMS
I/O
LVCMOS
DVCC
PU
64
SWCLKTCK
I
LVCMOS
DVCC
PD
QFN Pad
–
–
N/A
–
60
61
62
Pad
TDI (RD)
Terminal Configuration and Functions
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
4.4
www.ti.com
Signal Descriptions
Table 4-3 describes the signals for all device variants and package options.
Table 4-3. Signal Descriptions
ADC
Clock
(1)
(2)
20
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
A0
69
44
I
ADC analog input A0
A1
68
43
I
ADC analog input A1
A2
67
42
I
ADC analog input A2
A3
66
41
I
ADC analog input A3
A4
65
40
I
ADC analog input A4
A5
64
39
I
ADC analog input A5
A6
63
38
I
ADC analog input A6
A7
62
37
I
ADC analog input A7
A8
61
36
I
ADC analog input A8
A9
60
35
I
ADC analog input A9
A10
59
34
I
ADC analog input A10
A11
58
33
I
ADC analog input A11
A12
57
N/A
I
ADC analog input A12
A13
56
N/A
I
ADC analog input A13
A14
55
N/A
I
ADC analog input A14
A15
54
N/A
I
ADC analog input A15
A16
53
N/A
I
ADC analog input A16
A17
52
N/A
I
ADC analog input A17
A18
51
N/A
I
ADC analog input A18
A19
50
N/A
I
ADC analog input A19
A20
49
N/A
I
ADC analog input A20
A21
48
N/A
I
ADC analog input A21
A22
47
N/A
I
ADC analog input A22
A23
46
N/A
I
ADC analog input A23
ACLK
58
33
O
ACLK clock output
DCOR
44
31
–
DCO external resistor pin
HFXIN
86
55
I
Input for high-frequency crystal oscillator HFXT
HFXOUT
85
54
O
Output for high-frequency crystal oscillator HFXT
HSMCLK
60
35
O
HSMCLK clock output
LFXIN
41
28
I
Input for low-frequency crystal oscillator LFXT
LFXOUT
42
29
O
Output of low-frequency crystal oscillator LFXT
MCLK
59
34
O
MCLK clock output
FUNCTION
SIGNAL NAME
DESCRIPTION
N/A = not available
I = input, O = output
Terminal Configuration and Functions
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-3. Signal Descriptions (continued)
Comparator
LCD
(3)
(4)
(3)
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
C0.0
31
18
I
Comparator_E0 input 0
C0.1
30
17
I
Comparator_E0 input 1
C0.2
29
N/A
I
Comparator_E0 input 2
C0.3
28
N/A
I
Comparator_E0 input 3
C0.4
27
N/A
I
Comparator_E0 input 4
C0.5
26
N/A
I
Comparator_E0 input 5
C0.6
25
N/A
I
Comparator_E0 input 6
C0.7
24
N/A
I
Comparator_E0 input 7
C1.0
81
50
I
Comparator_E1 input 0
C1.1
80
49
I
Comparator_E1 input 1
C1.2
79
N/A
I
Comparator_E1 input 2
C1.3
78
N/A
I
Comparator_E1 input 3
C1.4
77
N/A
I
Comparator_E1 input 4
C1.5
76
N/A
I
Comparator_E1 input 5
C1.6
71
46
I
Comparator_E1 input 6
C1.7
70
45
I
Comparator_E1 input 7
L0
39
N/A
O
LCD drive pin 0 for either segment or common output
L1
38
N/A
O
LCD drive pin 1 for either segment or common output
L2
37
N/A
O
LCD drive pin 2 for either segment or common output
L3
36
N/A
O
LCD drive pin 3 for either segment or common output
L4
35
N/A
O
LCD drive pin 4 for either segment or common output
L5
34
N/A
O
LCD drive pin 5 for either segment or common output
L6
33
N/A
O
LCD drive pin 6 for either segment or common output
L7
32
N/A
O
LCD drive pin 7 for either segment or common output
L8
19
N/A
O
LCD drive pin 8 for either segment or common output
L9
18
N/A
O
LCD drive pin 9 for either segment or common output
L10
17
N/A
O
LCD drive pin 10 for either segment or common output
L11
16
N/A
O
LCD drive pin 11 for either segment or common output
L12
(4)
11
57
N/A
O
LCD drive pin 12 for either segment or common output
L13
(4)
10
56
N/A
O
LCD drive pin 13 for either segment or common output
L14
(4)
9
55
N/A
O
LCD drive pin 14 for either segment or common output
L15
(4)
8
54
N/A
O
LCD drive pin 15 for either segment or common output
L16
(4)
7
53
N/A
O
LCD drive pin 16 for either segment or common output
L17
(4)
6
52
N/A
O
LCD drive pin 17 for either segment or common output
L18
(4)
5
51
N/A
O
LCD drive pin 18 for either segment or common output
L19
(4)
4
50
N/A
O
LCD drive pin 19 for either segment or common output
FUNCTION
SIGNAL NAME
DESCRIPTION
Available only on MSP432P411x devices.
This LCD drive pin is also mirrored at a different location in the 100-pin PZ package. Assign the LCD drive output to only one pin at a
time.
Terminal Configuration and Functions
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table 4-3. Signal Descriptions (continued)
LCD (3)
(continued)
Debug
22
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
L20
23
N/A
O
LCD drive pin 20 for either segment or common output
L21
22
N/A
O
LCD drive pin 21 for either segment or common output
L22
21
N/A
O
LCD drive pin 22 for either segment or common output
L23
20
N/A
O
LCD drive pin 23 for either segment or common output
L24
79
N/A
O
LCD drive pin 24 for either segment or common output
L25
78
N/A
O
LCD drive pin 25 for either segment or common output
L26
77
N/A
O
LCD drive pin 26 for either segment or common output
L27
76
N/A
O
LCD drive pin 27 for either segment or common output
L28
29
N/A
O
LCD drive pin 28 for either segment or common output
L29
28
N/A
O
LCD drive pin 29 for either segment or common output
L30
27
N/A
O
LCD drive pin 30 for either segment or common output
L31
26
N/A
O
LCD drive pin 31 for either segment or common output
L32
75
N/A
O
LCD drive pin 32 for either segment or common output
L33
74
N/A
O
LCD drive pin 33 for either segment or common output
L34
25
N/A
O
LCD drive pin 34 for either segment or common output
L35
24
N/A
O
LCD drive pin 35 for either segment or common output
L36
3
N/A
O
LCD drive pin 36 for either segment or common output
L37
2
N/A
O
LCD drive pin 37 for either segment or common output
L38
1
N/A
O
LCD drive pin 38 for either segment or common output
L39
100
N/A
O
LCD drive pin 39 for either segment or common output
L40
99
N/A
O
LCD drive pin 40 for either segment or common output
L41
98
N/A
O
LCD drive pin 41 for either segment or common output
L42
97
N/A
O
LCD drive pin 42 for either segment or common output
L43
96
N/A
O
LCD drive pin 43 for either segment or common output
L44
49
N/A
O
LCD drive pin 44 for either segment or common output
L45
48
N/A
O
LCD drive pin 45 for either segment or common output
L46
47
N/A
O
LCD drive pin 46 for either segment or common output
L47
46
N/A
O
LCD drive pin 47 for either segment or common output
R03
88
N/A
I
Input port of fourth most positive analog LCD voltage V4 in
external bias mode
R13
89
N/A
I
Input port of fourth most positive analog LCD voltage V3 in
external bias mode
R23
90
N/A
I
Input port of fourth most positive analog LCD voltage V2 in
external bias mode
SWCLKTCK
95
64
I
Serial wire clock input (SWCLK)/JTAG clock input (TCK)
SWDIOTMS
94
63
I/O
Serial wire data input/output (SWDIO)/JTAG test mode
select (TMS)
SWO
93
62
O
Serial wire trace output
TDI
92
61
I
JTAG test data input
TDO
93
62
O
JTAG test data output
FUNCTION
SIGNAL NAME
Terminal Configuration and Functions
DESCRIPTION
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-3. Signal Descriptions (continued)
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
P1.0
4
1
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability
P1.1
5
2
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P1.2
6
3
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P1.3
7
4
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P1.4
8
5
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability
P1.5
9
6
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability
P1.6
10
7
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P1.7
11
8
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function. This I/O can be configured for high drive
operation with a drive capability of up to 20 mA.
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function. This I/O can be configured for high drive
operation with a drive capability of up to 20 mA.
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function. This I/O can be configured for high drive
operation with a drive capability of up to 20 mA.
FUNCTION
SIGNAL NAME
GPIO Port 1
P2.0
P2.1
P2.2
GPIO Port 2
16
17
18
13
14
15
DESCRIPTION
P2.3
19
16
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function. This I/O can be configured for high drive
operation with a drive capability of up to 20 mA.
P2.4
20
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P2.5
21
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P2.6
22
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P2.7
23
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
Terminal Configuration and Functions
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table 4-3. Signal Descriptions (continued)
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
P3.0
32
19
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability, and with reconfigurable port
mapping secondary function
P3.1
33
20
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P3.2
34
21
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P3.3
35
22
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P3.4
36
23
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability, and with reconfigurable port
mapping secondary function
P3.5
37
24
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability, and with reconfigurable port
mapping secondary function
P3.6
38
25
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P3.7
39
26
I/O
General-purpose digital I/O with port interrupt and wake-up
capability and with reconfigurable port mapping secondary
function
P4.0
56
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P4.1
57
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P4.2
58
33
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P4.3
59
34
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P4.4
60
35
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P4.5
61
36
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P4.6
62
37
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P4.7
63
38
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.0
64
39
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.1
65
40
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.2
66
41
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.3
67
42
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.4
68
43
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.5
69
44
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.6
70
45
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P5.7
71
46
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
FUNCTION
SIGNAL NAME
GPIO Port 3
GPIO Port 4
GPIO Port 5
24
Terminal Configuration and Functions
DESCRIPTION
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-3. Signal Descriptions (continued)
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
DESCRIPTION
P6.0
54
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P6.1
55
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P6.2
76
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P6.3
77
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P6.4
78
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P6.5
79
N/A
I/O
General-purpose digital I/O with port interrupt and wake-up
capability
P6.6
80
49
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability
P6.7
81
50
I/O
General-purpose digital I/O with port interrupt, wake-up,
and glitch filtering capability
P7.0
88
57
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.1
89
58
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.2
90
59
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.3
91
60
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.4
26
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.5
27
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.6
28
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P7.7
29
N/A
I/O
General-purpose digital I/O with reconfigurable port
mapping secondary function (RD)
P8.0
30
17
I/O
General-purpose digital I/O
P8.1
31
18
I/O
General-purpose digital I/O
P8.2
46
N/A
I/O
General-purpose digital I/O
P8.3
47
N/A
I/O
General-purpose digital I/O
P8.4
48
N/A
I/O
General-purpose digital I/O
P8.5
49
N/A
I/O
General-purpose digital I/O
P8.6
50
N/A
I/O
General-purpose digital I/O
P8.7
51
N/A
I/O
General-purpose digital I/O
P9.0
52
N/A
I/O
General-purpose digital I/O
P9.1
53
N/A
I/O
General-purpose digital I/O
P9.2
74
N/A
I/O
General-purpose digital I/O
P9.3
75
N/A
I/O
General-purpose digital I/O
P9.4
96
N/A
I/O
General-purpose digital I/O
P9.5
97
N/A
I/O
General-purpose digital I/O
P9.6
98
N/A
I/O
General-purpose digital I/O
P9.7
99
N/A
I/O
General-purpose digital I/O
FUNCTION
SIGNAL NAME
GPIO Port 6
GPIO Port 7
GPIO Port 8
GPIO Port 9
Terminal Configuration and Functions
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
Table 4-3. Signal Descriptions (continued)
GPIO Port 10
GPIO Port J
I2C
Port Mapper
26
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
P10.0
100
N/A
I/O
General-purpose digital I/O
P10.1
1
N/A
I/O
General-purpose digital I/O
P10.2
2
N/A
I/O
General-purpose digital I/O
P10.3
3
N/A
I/O
General-purpose digital I/O
P10.4
24
N/A
I/O
General-purpose digital I/O
P10.5
25
N/A
I/O
General-purpose digital I/O
PJ.0
41
28
I/O
General-purpose digital I/O
PJ.1
42
29
I/O
General-purpose digital I/O
PJ.2
85
54
I/O
General-purpose digital I/O
PJ.3
86
55
I/O
General-purpose digital I/O
PJ.4
92
61
I/O
General-purpose digital I/O
PJ.5
93
62
I/O
General-purpose digital I/O
UCB0SCL
11
8
I/O
I2C clock in eUSCI_B0 I2C mode
UCB0SDA
10
7
I/O
I2C data in eUSCI_B0 I2C mode
UCB1SCL
79
N/A
I/O
I2C clock in eUSCI_B1 I2C mode
UCB1SDA
78
N/A
I/O
I2C data in eUSCI_B1 I2C mode
UCB3SCL
3
N/A
I/O
I2C clock in eUSCI_B3 I2C mode
UCB3SCL
81
50
I/O
I2C clock in eUSCI_B3 I2C mode
UCB3SDA
2
N/A
I/O
I2C data in eUSCI_B3 I2C mode
UCB3SDA
80
49
I/O
I2C data in eUSCI_B3 I2C mode
PM_C0OUT
89
58
O
Default mapping: Comparator_E0 output
PM_C1OUT
90
59
O
Default mapping: Comparator_E1 output
PM_DMAE0
88
57
I
Default mapping: DMA external trigger input
PM_SMCLK
88
57
O
Default mapping: SMCLK clock output
PM_TA0.0
91
60
I/O
Default mapping: TA0 CCR0 capture: CCI0A input,
compare: Out0
PM_TA0.1
20
N/A
I/O
Default mapping: TA0 CCR1 capture: CCI1A input,
compare: Out1
PM_TA0.2
21
N/A
I/O
Default mapping: TA0 CCR2 capture: CCI2A input,
compare: Out2
PM_TA0.3
22
N/A
I/O
Default mapping: TA0 CCR3 capture: CCI3A input,
compare: Out3
PM_TA0.4
23
N/A
I/O
Default mapping: TA0 CCR4 capture: CCI4A input,
compare: Out4
PM_TA0CLK
89
58
I
PM_TA1.2
28
N/A
I/O
Default mapping: TA1 CCR2 capture: CCI2A input,
compare: Out2
PM_TA1.3
27
N/A
I/O
Default mapping: TA1 CCR3 capture: CCI3A input,
compare: Out3
PM_TA1.4
26
N/A
I/O
Default mapping: TA1 CCR4 capture: CCI4A input,
compare: Out4
PM_TA1CLK
90
59
I
FUNCTION
SIGNAL NAME
Terminal Configuration and Functions
DESCRIPTION
Default mapping: TA0 input clock
Default mapping: TA1 input clock
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 4-3. Signal Descriptions (continued)
FUNCTION
Port Mapper
(continued)
Power
SIGNAL
TYPE (2)
PM_UCA1CLK
17
14
I/O
PM_UCA1RXD
18
15
I
Default mapping: Receive data in eUSCI_A1 UART mode
PM_UCA1SIMO
19
16
I/O
Default mapping: Slave in, master out for eUSCI_A1 SPI
mode
PM_UCA1SOMI
18
15
I/O
Default mapping: Slave out, master in for eUSCI_A1 SPI
mode
PM_UCA1STE
16
13
I/O
Default mapping: Slave transmit enable for eUSCI_A1 SPI
mode
PM_UCA1TXD
19
16
O
Default mapping: Transmit data for eUSCI_A1 UART mode
PM_UCA2CLK
33
20
I/O
Default mapping: Clock signal input for eUSCI_A2 SPI
slave mode
Clock signal output for eUSCI_A2 SPI master mode
PM_UCA2RXD
34
21
I
PM_UCA2SIMO
35
22
I/O
Default mapping: Slave in, master out for eUSCI_A2 SPI
mode
PM_UCA2SOMI
34
21
I/O
Default mapping: Slave out, master in for eUSCI_A2 SPI
mode
PM_UCA2STE
32
19
I/O
Default mapping: Slave transmit enable for eUSCI_A2 SPI
mode
PM_UCA2TXD
35
22
O
Default mapping: Transmit data for eUSCI_A2 UART mode
PM_UCB2CLK
37
24
I/O
Default mapping: Clock signal input for eUSCI_B2 SPI
slave mode
Clock signal output for eUSCI_B2 SPI master mode
PM_UCB2SCL
39
26
I
Default mapping: I2C clock for eUSCI_B2 I2C mode
PM_UCB2SDA
38
25
I/O
Default mapping: I2C data for eUSCI_B2 I2C mode
PM_UCB2SIMO
38
25
I/O
Default mapping: Slave in, master out for eUSCI_B2 SPI
mode
PM_UCB2SOMI
39
26
I/O
Default mapping: Slave out, master in for eUSCI_B2 SPI
mode
PM_UCB2STE
36
23
I/O
Default mapping: Slave transmit enable for eUSCI_B2 SPI
mode
AVCC1
45
32
–
Analog power supply
AVCC2
87
56
–
Analog power supply
AVSS1
43
30
–
Analog ground supply
AVSS2
84
53
–
Analog ground supply
AVSS3
40
27
–
Analog ground supply
DVCC1
13
10
–
Digital power supply
DVCC2
73
48
–
Digital power supply
DVSS1
15
12
–
Digital ground supply
DVSS2
72
47
–
Digital ground supply
82
51
–
Must be connected to ground
12
9
–
Regulated core power supply (internal use only, no
external current loading)
VSW
14
11
–
DC/DC converter switching output
RTCCLK
59
34
O
RTC_C clock calibration output
VCORE
(5)
(1)
RGC
DVSS3
RTC
SIGNAL NO.
PZ
SIGNAL NAME
(5)
DESCRIPTION
Default mapping: Clock signal input in eUSCI_A1 SPI
slave mode
Clock signal output in eUSCI_A1 SPI master mode
Default mapping: Receive data for eUSCI_A2 UART mode
VCORE is for internal use only. Do not use for external current loading. Connect VCORE to only the recommended capacitor value,
CVCORE.
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Table 4-3. Signal Descriptions (continued)
Reference
SPI
System
Thermal
28
SIGNAL NO.
(1)
PZ
RGC
SIGNAL
TYPE (2)
VREF+
70
45
O
Internal shared reference voltage positive terminal
VREF-
71
46
O
Internal shared reference voltage negative terminal
VeREF+
70
45
I
Positive terminal of external reference voltage to ADC
VeREF-
71
46
I
Negative terminal of external reference voltage to ADC
(recommended to connect to onboard ground)
UCA0CLK
5
2
I/O
Clock signal input for eUSCI_A0 SPI slave mode
Clock signal output for eUSCI_A0 SPI master mode
UCA0SIMO
7
4
I/O
Slave in, master out for eUSCI_A0 SPI mode
UCA0SOMI
6
3
I/O
Slave out, master in for eUSCI_A0 SPI mode
UCA0STE
4
1
I/O
Slave transmit enable for eUSCI_A0 SPI mode
UCA3CLK
97
N/A
I/O
Clock signal input for eUSCI_A3 SPI slave mode
Clock signal output for eUSCI_A3 SPI master mode
UCA3SIMO
99
N/A
I/O
Slave in, master out for eUSCI_A3 SPI mode
UCA3SOMI
98
N/A
I/O
Slave out, master in for eUSCI_A3 SPI mode
UCA3STE
96
N/A
I/O
Slave transmit enable for eUSCI_A3 SPI mode
UCB0CLK
9
6
I/O
Clock signal input for eUSCI_B0 SPI slave mode
Clock signal output for eUSCI_B0 SPI master mode
UCB0SIMO
10
7
I/O
Slave in, master out for eUSCI_B0 SPI mode
UCB0SOMI
11
8
I/O
Slave out, master in for eUSCI_B0 SPI mode
UCB0STE
8
5
I/O
Slave transmit enable for eUSCI_B0 SPI mode
UCB1CLK
77
N/A
I/O
Clock signal input for eUSCI_B1 SPI slave mode
Clock signal output for eUSCI_B1 SPI master mode
UCB1SIMO
78
N/A
I/O
Slave in, master out for eUSCI_B1 SPI mode
UCB1SOMI
79
N/A
I/O
Slave out, master in for eUSCI_B1 SPI mode
UCB1STE
76
N/A
I/O
Slave transmit enable for eUSCI_B1 SPI mode
UCB3CLK
1
31
18
I/O
Clock signal input for eUSCI_B3 SPI slave mode
Clock signal output for eUSCI_B3 SPI master mode
UCB3SIMO
2
80
49
I/O
Slave in, master out for eUSCI_B3 SPI mode
UCB3SOMI
3
81
50
I/O
Slave out, master in for eUSCI_B3 SPI mode
UCB3STE
30
100
17
I/O
Slave transmit enable for eUSCI_B3 SPI mode
NMI
83
52
I
External nonmaskable interrupt
RSTn
83
52
I
External reset (active low)
SVMHOUT
60
35
O
SVMH output
QFN Pad
N/A
Pad
–
QFN package exposed thermal pad. TI recommends
connection to VSS.
FUNCTION
SIGNAL NAME
Terminal Configuration and Functions
DESCRIPTION
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Table 4-3. Signal Descriptions (continued)
UART
(1)
RGC
SIGNAL
TYPE (2)
PM_TA1.1
29
N/A
I/O
Default mapping: TA1 CCR1 capture: CCI1A input,
compare: Out1
TA1.0
30
17
I/O
TA1 CCR0 capture: CCI0A input, compare: Out0
TA2.0
31
18
I/O
TA2 CCR0 capture: CCI0A input, compare: Out0
TA2.1
70
45
I/O
TA2 CCR1 capture: CCI1A input, compare: Out1
TA2.2
71
46
I/O
TA2 CCR2 capture: CCI2A input, compare: Out2
TA2.3
80
49
I/O
TA2 CCR3 capture: CCI3A input, compare: Out3
TA2.4
81
50
I/O
TA2 CCR4 capture: CCI4A input, compare: Out4
TA2CLK
58
33
I
TA3.0
24
N/A
I/O
TA3 CCR0 capture: CCI0A input, compare: Out0
TA3.1
25
N/A
I/O
TA3 CCR1 capture: CCI1A input, compare: Out1
TA3.2
46
N/A
I/O
TA3 CCR2 capture: CCI2A input, compare: Out2
TA3.3
74
N/A
I/O
TA3 CCR3 capture: CCI3A input, compare: Out3
TA3.4
75
N/A
I/O
TA3 CCR4 capture: CCI4A input, compare: Out4
TA3CLK
47
N/A
I
TA3 input clock
UCA0RXD
6
3
I
Receive data for eUSCI_A0 UART mode
UCA0TXD
7
4
O
Transmit data for eUSCI_A0 UART mode
UCA3RXD
98
N/A
I
Receive data for eUSCI_A3 UART mode
UCA3TXD
99
N/A
O
Transmit data for eUSCI_A3 UART mode
SIGNAL NAME
Timer
4.5
SIGNAL NO.
PZ
FUNCTION
DESCRIPTION
TA2 input clock
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and diagrams of the
multiplexed ports, see Section 6.12.
4.6
Buffer Types
Table 4-4 describes the buffer types that are referenced in Table 4-1 and Table 4-2.
Table 4-4. Buffer Type
BUFFER TYPE
(STANDARD)
Analog
(1)
NOMINAL
VOLTAGE
HYSTERESIS
PU OR PD
NOMINAL PU OR
PD STRENGTH
(µA)
OUTPUT DRIVE
STRENGTH (mA)
OTHER
CHARACTERISTIC
S
3.0 V
N
N/A
N/A
N/A
See analog modules
in Section 5 for
details.
HVCMOS
13.0 V
LVCMOS
3.0 V
Y
Y
(2)
N/A
N/A
See Section 5.26.6.
Programmable
See Section 5.26.6.
See Section 5.26.6.
Power (DVCC)
(3)
3.0 V
N
N/A
N/A
N/A
Power (AVCC)
(3)
3.0 V
N
N/A
N/A
N/A
0V
N
N/A
N/A
N/A
Power (DVSS and
AVSS) (3)
(1)
(2)
(3)
SVSMH enables
hysteresis on
DVCC.
This is a switch, not a buffer.
Only for input pins.
This is supply input, not a buffer.
Terminal Configuration and Functions
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Connections for Unused Pins
Table 4-5 lists the correct termination of all unused pins.
Table 4-5. Connection for Unused Pins
(1)
PIN
POTENTIAL
AVCC
DVCC
AVSS
DVSS
VSW
Open
Leave VSW pin unconnected if DC/DC regulator operation is not required.
Px.0 to Px.7
Open
Set to port function, output direction, and leave unconnected on the PCB.
RSTn/NMI
DVCC or VCC
47-kΩ pullup with 1.1-nF pulldown
PJ.4/TDI
Open
The JTAG TDI pin is shared with general-purpose I/O function (PJ.4). If not being used,
set this pin to port function, output direction. When used as the JTAG TDI pin, leave this
pin open.
PJ.5/TDO/SWO
DVCC or VCC
The JTAG TDO/SWO pin is shared with general-purpose I/O function (PJ.5). If not being
used, set this pin to port function, output direction. When used as the JTAG TDO/SWO
pin, use an external pulldown on this pin.
SWDIOTMS
DVCC or VCC
Use an external pullup on this pin.
SWCLKTCK
DVCC or VCC
Use an external pulldown on this pin.
(1)
30
COMMENT
For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Voltage applied at DVCC and AVCC pins to VSS
Voltage difference between DVCC and AVCC pins
Voltage applied to any pin
MIN
MAX
UNIT
–0.3
4.17
V
±0.3
V
–0.3
VCC + 0.3 V
(4.17 V MAX)
V
(2)
(3)
Diode current at any device pin
Storage temperature, Tstg
(4)
–40
Maximum junction temperature, TJ
(1)
(2)
(3)
(4)
±2
mA
125
°C
95
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage differences between DVCC and AVCC exceeding the specified limits may cause malfunction of the device.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
(3)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
(2)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (3)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
All pins pass HBM up to ±1000 V except the DVSS3 pin. The DVSS3 pin is used for TI internal test purposes. Connect the DVSS3 pin
to supply ground on the customer application board.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3
Recommended Operating Conditions
Typical data are based on VCC = 3.0 V, TA = 25°C (unless otherwise noted)
MIN
Supply voltage range at all DVCC and
AVCC pins (1) (2) (3)
VCC
3.7
Normal operation with internal VCC
supervision
1.71
3.7
Normal operation without internal VCC
supervision
1.62
3.7
Supply voltage on all DVSS and AVSS pins
IINRUSH
Inrush current into the VCC pins (4)
fMCLK
Frequency of the CPU and AHB clock in the system (5)
TA
Operating free-air temperature
TJ
Operating junction temperature
–40
(2)
(3)
(4)
(5)
MAX
1.71
VSS
(1)
NOM
At power up (with internal VCC
supervision)
0
UNIT
V
V
100
mA
0
48
MHz
–40
85
°C
85
°C
TI recommends powering AVCC and DVCC from the same source. A maximum difference of ±0.1 V between AVCC and DVCC can be
tolerated during power up and operation. See Section 5.4 for decoupling capacitor recommendations.
Supply voltage must not change faster than 1 V/ms. Faster changes can cause the VCCDET to trigger a reset even within the
recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
Does not include I/O currents (driven by application requirements).
Operating frequency may require the flash to be accessed with wait states. See Section 5.8 for further details.
Specifications
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Recommended External Components (1)
5.4
CDVCC
Capacitor on DVCC pin
CVCORE
Capacitor on VCORE pin
(2) (3)
MIN
NOM
For DC/DC operation (4)
3.3
4.7
For LDO-only operation
3.3
4.7
1.54
4.7
9
µF
70
100
9000
nF
For DC/DC operation, including
capacitor tolerance
For LDO-only operation, including
capacitor tolerance
MAX
UNIT
µF
CAVCC
Capacitor on AVCC pin
3.3
4.7
LVSW
Inductor between VSW and VCORE pins for DC/DC
3.3
4.7
13
µH
RLVSW-DCR
Allowed DCR for LVSW
150
350
mΩ
ISAT-LVSW
LVSW saturation current
(1)
(2)
(3)
(4)
5.5
µF
700
mA
For optimum performance, select components that match the NOM values in this table.
See Section 7 for more details on component selection, placement, and related PCB design guidelines.
Consider the tolerances of the capacitance and inductance values when choosing components to ensure that the MIN and MAX limits
are never exceeded.
CDVCC should not be smaller than CVCORE.
Operating Mode VCC Ranges
over operating free-air temperature (unless otherwise noted)
PARAMETER
VCC_LDO
OPERATING MODE
AM_LDO_VCORE0
AM_LF_VCORE0
LPM0_LDO_VCORE0
LPM0_LF_VCORE0
LPM3_VCORE0
LPM4_VCORE0
LPM3.5
AM_LDO_VCORE1
AM_LF_VCORE1
LPM0_LDO_VCORE1
LPM0_LF_VCORE1
LPM3_VCORE1
LPM4_VCORE1
(1) (2)
TEST CONDITIONS
MIN
MAX
LDO active, SVSMH disabled
1.62
3.7
LDO active, SVSMH enabled
1.71
3.7
UNIT
V
VCC_DCDC_DF0
AM_DCDC_VCORE0
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1
LPM0_DCDC_VCORE1
DC/DC active, DC/DC operation not forced
(DCDC_FORCE = 0), SVSMH enabled or
disabled (3)
2.0
3.7
V
VCC_DCDC_DF1
AM_DCDC_VCORE0
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1
LPM0_DCDC_VCORE1
DC/DC active, DC/DC operation forced
(DCDC_FORCE = 1), SVSMH enabled or disabled
1.8
3.7
V
LDO disabled, SVSMH disabled
1.62
3.7
LDO disabled, SVSMH enabled
1.71
3.7
VCC_VCORE_OFF
(1)
(2)
(3)
(4)
32
(4)
LPM4.5
V
Flash remains active only in active modes and LPM0 modes.
Low-frequency active and low-frequency LPM0, LPM3, LPM4, and LPM3.5 modes are based on LDO only.
When VCC falls below the specified MIN value, the DC/DC operation automatically switches to LDO, as long as the VCC drop is slower
than the rate that is reliably detected. See Table 5-20 for more details.
Core voltage is off in LPM4.5 mode.
Specifications
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Operating Mode CPU Frequency Ranges (1)
5.6
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
OPERATING MODE
DESCRIPTION
fMCLK
MIN
MAX
UNIT
fAM_LDO_VCORE0
AM_LDO_VCORE0
Normal-performance mode with LDO as the active
regulator
0
24
MHz
fAM_LDO_VCORE1
AM_LDO_VCORE1
High-performance mode with LDO as the active
regulator
0
48
MHz
fAM_DCDC_VCORE0
AM_DCDC_VCORE0
Normal-performance mode with DC/DC as the active
regulator
0
24
MHz
fAM_DCDC_VCORE1
AM_DCDC_VCORE1
High-performance mode with DC/DC as the active
regulator
0
48
MHz
fAM_LF_VCORE0
AM_LF_VCORE0
Low-frequency mode with LDO as the active regulator
0
128
kHz
fAM_LF_VCORE1
AM_LF_VCORE1
Low-frequency mode with LDO as the active regulator
0
128
kHz
MIN
MAX
UNIT
Peripheral frequency range in LDO or DC/DCbased active or LPM0 modes for VCORE0
0
12
MHz
Peripheral frequency range in LDO or DC/DCbased active or LPM0 modes for VCORE1
0
24
MHz
Peripheral frequency range in low-frequency
active or low-frequency LPM0 modes for
VCORE0 and VCORE1
0
128
kHz
Peripheral frequency in LPM3 mode for VCORE0
and VCORE1
0
128
kHz
LPM4_VCORE1
Peripheral frequency in LPM4 mode for VCORE0
and VCORE1
0
128
kHz
LPM3.5
Peripheral frequency in LPM3.5 mode
0
32.768
kHz
(1)
The DMA can be operated at the same frequency as the CPU.
5.7
Operating Mode Peripheral Frequency Ranges
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
OPERATING MODE
DESCRIPTION
AM_LDO_VCORE0
fAM_LPM0_VCORE0
AM_DCDC_VCORE0
LPM0_LDO_VCORE0
LPM0_DCDC_VCORE0
AM_LDO_VCORE1
fAM_LPM0_VCORE1
AM_DCDC_VCORE1
LPM0_LDO_VCORE1
LPM0_DCDC_VCORE1
AM_LF_VCORE0
fAM_LPM0_LF
AM_LF_VCORE1
LPM0_LF_VCORE0
LPM0_LF_VCORE1
fLPM3 (1)
fLPM4 (2)
fLPM3.5 (1)
(1)
(2)
LPM3_VCORE0
LPM3_VCORE1
LPM4_VCORE0
Only RTC and WDT can be active.
Peripherals available in LPM4 can be operational on external clocks.
Specifications
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5.8
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Operating Mode Execution Frequency vs Flash Wait-State Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
NUMBER OF
FLASH WAIT
STATES
FLASH READ
MODE
fMAX_NRM_FLWAIT0
0
fMAX_NRM_FLWAIT1
PARAMETER
MAXIMUM SUPPORTED MCLK FREQUENCY (1) ,
(2)
AM_LDO_VCORE0,
AM_DCDC_VCORE0
AM_LDO_VCORE1,
AM_DCDC_VCORE1
UNIT
Normal read
mode
10
13
MHz
1
Normal read
mode
21
27
MHz
fMAX_NRM_FLWAIT2
2
Normal read
mode
24
40
MHz
fMAX_NRM_FLWAIT3
3
Normal read
mode
24
48
MHz
fMAX_ORM_FLWAIT0
0
Other read
modes (3)
6
7
MHz
fMAX_ORM_FLWAIT1
1
Other read
modes (3)
12
14
MHz
fMAX_ORM_FLWAIT2
2
Other read
modes (3)
18
21
MHz
fMAX_ORM_FLWAIT3
3
Other read
modes (3)
24
28
MHz
fMAX_ORM_FLWAIT4
4
Other read
modes (3)
24
35
MHz
fMAX_ORM_FLWAIT5
5
Other read
modes (3)
24
42
MHz
fMAX_ORM_FLWAIT6
6
Other read
modes (3)
24
48
MHz
(1)
(2)
(3)
34
Violation of the maximum frequency limitation for a given wait-state configuration results in nondeterministic data or instruction fetches
from the flash memory.
In low-frequency active modes, the flash can always be accessed with 0 wait states, because the maximum MCLK frequency is limited
to 128 kHz.
Other read modes refers to Read Margin 0, Read Margin 01, Program Verify, and Erase Verify.
Specifications
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5.9
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Current Consumption During Device Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IRESET
(1)
(2)
(3)
VCC
Current during device reset
MIN
(1) (2) (3)
TYP
2.2 V
690
3.0 V
760
MAX
1000
UNIT
µA
Device held in reset through RSTn/NMI pin.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
5.10 Current Consumption in LDO-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted) (1)
EXECUTION
MEMORY
PARAMETER
MCLK = 1 MHz MCLK = 8 MHz
VCC
TYP
(2) (3) (4) (5)
MCLK =
16 MHz
MCLK =
24 MHz
MCLK =
32 MHz
MCLK =
40 MHz
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
5700
6300
7000
7600
7300
8200
5000
5550
6100
6800
7200
7900
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM_LDO_VCORE0,Flash (6)
(7) (8)
Flash
3.0 V
700
950
2000
2400
3200
3600
4000
4500
IAM_LDO_VCORE1,Flash (6)
(7) (8)
Flash
3.0 V
720
1050
2150
2600
3520
4000
5000
5600
IAM_LDO_VCORE0,SRAM (9)
SRAM
3.0 V
640
900
1600
2000
2675
3100
3750
4250
IAM_LDO_VCORE1,SRAM (9)
SRAM
3.0 V
650
1000
1625
2100
2725
3200
3825
4350
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
UNIT
µA
µA
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
All SRAM banks are active.
All peripherals are inactive.
Device executing the Dhrystone 2.1 program. Code execution from flash, stack, and data in SRAM.
Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
Device executing the Dhrystone 2.1 program. Code execution from SRAM, stack and data in SRAM.
5.11 Current Consumption in DC/DC-Based Active Modes – Dhrystone 2.1 Program
over recommended operating free-air temperature (unless otherwise noted) (1)
EXECUTION
MEMORY
PARAMETER
MCLK = 1 MHz MCLK = 8 MHz
VCC
(2) (3) (4) (5)
MCLK =
16 MHz
MCLK =
24 MHz
MCLK =
32 MHz
MCLK =
40 MHz
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
3650
4250
4450
5100
4650
5300
3100
3650
3770
4400
4400
5100
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
IAM_DCDC_VCORE0,Flash (6)
(7) (8)
Flash
3.0 V
580
800
1280
1750
1970
2300
2390
2900
IAM_DCDC_VCORE1,Flash (6)
(7) (8)
Flash
3.0 V
620
900
1490
1850
2325
2750
3250
3800
IAM_DCDC_VCORE0,SRAM (9)
SRAM
3.0 V
550
750
1040
1400
1600
2000
2170
2650
IAM_DCDC_VCORE1,SRAM (9)
SRAM
3.0 V
580
850
1150
1550
1790
2200
2440
2900
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
UNIT
µA
µA
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
All SRAM banks are active.
All peripherals are inactive.
Device executing the Dhrystone 2.1 program. Code execution from flash. Stack and data in SRAM.
Flash configured to minimum wait states required to support operation at given frequency and core voltage level.
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data in SRAM.
Specifications
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35
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
5.12 Current Consumption in Low-Frequency Active Modes – Dhrystone 2.1 Program
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
(6) (7) (8)
IAM_LF_VCORE0,
flash
IAM_LF_VCORE1,
flash
IAM_LF_VCORE0,
SRAM
IAM_LF_VCORE1,
SRAM
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
36
(6) (7) (8)
(9)
(9)
EXECUTION
MEMORY
Flash
Flash
SRAM
SRAM
VCC
–40°C
TYP
MAX
25°C
TYP
2.2 V
90
95
3.0 V
90
95
2.2 V
92
100
3.0 V
95
110
2.2 V
88
95
3.0 V
88
95
2.2 V
92
98
3.0 V
93
100
60°C
MAX
120
150
115
130
TYP
(2) (3) (4) (5)
85°C
MAX
TYP
110
140
110
150
120
160
130
200
110
140
110
150
118
165
120
166
MAX
350
500
300
400
UNIT
μA
μA
μA
μA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
MCLK sourced by REFO at 128 kHz.
All peripherals are inactive.
SRAM banks 0 and 1 enabled for execution from flash, and SRAM banks 0 to 3 enabled for execution from SRAM.
Flash configured to 0 wait states.
Device executing the Dhrystone 2.1 program. Code execution from Flash. Stack and data in SRAM.
Flash instruction and data buffers are enabled (BUFI = BUFD = 1).
Device executing the Dhrystone 2.1 program. Code execution from SRAM. Stack and data also in SRAM.
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
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MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
AM_LDO_VCORE0
AM_LDO_VCORE1
Current (mA)
Current (mA)
5.13 Typical Characteristics of Active Mode Currents for CoreMark Program
0
5
10
15
Flash Execution
20
25
30
Frequency (MHz)
35
40
45
AM_LDO_VCORE0
AM_LDO_VCORE1
0
50
5
10
15
D001
VCC = 3 V
TA = 25°C
SRAM Execution
Figure 5-1. Frequency vs Current Consumption
20
25
30
Frequency (MHz)
35
40
45
50
D002
VCC = 3 V
TA = 25°C
Figure 5-2. Frequency vs Current Consumption
4.5
4.5
AM_DCDC_VCORE0
AM_DCDC_VCORE1
4
AM_DCDC_VCORE0
AM_DCDC_VCORE1
4
3.5
3.5
Current (mA)
Current (mA)
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
3
2.5
2
3
2.5
2
1.5
1.5
1
1
0.5
0.5
0
5
10
Flash Execution
15
20
25
30
Frequency (MHz)
35
VCC = 3 V
40
45
50
0
5
10
D003
TA = 25°C
Figure 5-3. Frequency vs Current Consumption
SRAM Execution
15
20
25
30
Frequency (MHz)
VCC = 3 V
35
40
45
D004
TA = 25°C
Figure 5-4. Frequency vs Current Consumption
Specifications
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Copyright © 2017–2018, Texas Instruments Incorporated
50
37
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
6.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
AM_LDO_VCORE0
AM_LDO_VCORE1
5.5
5
4
3.5
3
2.5
2
1
0.5
5
10
15
Flash Execution
20
25
30
Frequency (MHz)
35
40
45
50
0
5
10
15
D005
VCC = 3 V
TA = 25°C
SRAM Execution
Figure 5-5. Frequency vs Current Consumption
20
25
30
Frequency (MHz)
35
40
45
50
D006
VCC = 3 V
TA = 25°C
Figure 5-6. Frequency vs Current Consumption
3.9
4.5
AM_DCDC_VCORE0
AM_DCDC_VCORE1
4
AM_DCDC_VCORE0
AM_DCDC_VCORE1
3.6
3.3
3
Current (mA)
3.5
Current (mA)
4.5
1.5
0
3
2.5
2
2.7
2.4
2.1
1.8
1.5
1.2
1.5
0.9
1
0.6
0.3
0.5
0
5
10
Flash Execution
15
20
25
30
Frequency (MHz)
VCC = 3 V
35
40
45
Specifications
50
0
5
10
D007
TA = 25°C
Figure 5-7. Frequency vs Current Consumption
38
AM_LDO_VCORE0
AM_LDO_VCORE1
6
Current (mA)
Current (mA)
5.14 Typical Characteristics of Active Mode Currents for Prime Number Program
SRAM Execution
15
20
25
30
Frequency (MHz)
VCC = 3 V
35
40
45
50
D008
TA = 25°C
Figure 5-8. Frequency vs Current Consumption
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.15 Typical Characteristics of Active Mode Currents for Fibonacci Program
6.5
AM_LDO_VCORE0
AM_LDO_VCORE1
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
5
10
15
Flash Execution
20
25
30
Frequency (MHz)
35
40
45
50
0
5
10
15
D009
VCC = 3 V
TA = 25°C
SRAM Execution
Figure 5-9. Frequency vs Current Consumption
20
25
30
Frequency (MHz)
35
40
45
50
D010
VCC = 3 V
TA = 25°C
Figure 5-10. Frequency vs Current Consumption
3.9
5
AM_DCDC_VCORE0
AM_DCDC_VCORE1
4.5
AM_DCDC_VCORE0
AM_DCDC_VCORE1
3.6
3.3
4
3
3.5
Current (mA)
Current (mA)
AM_LDO_VCORE0
AM_LDO_VCORE1
6
Current (mA)
Current (mA)
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
3
2.5
2
2.7
2.4
2.1
1.8
1.5
1.2
1.5
0.9
1
0.6
0.3
0.5
0
5
10
Flash Execution
15
20
25
30
Frequency (MHz)
35
VCC = 3 V
40
45
50
0
5
10
D011
TA = 25°C
Figure 5-11. Frequency vs Current Consumption
SRAM Execution
15
20
25
30
Frequency (MHz)
VCC = 3 V
35
40
45
D012
TA = 25°C
Figure 5-12. Frequency vs Current Consumption
Specifications
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39
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
www.ti.com
5.16 Typical Characteristics of Active Mode Currents for While(1) Program
6.5
8.5
AM_LDO_VCORE0
AM_LDO_VCORE1
6
5.5
7.5
5
6.5
4.5
Current (mA)
Current (mA)
AM_LDO_VCORE0
AM_LDO_VCORE1
4
3.5
3
2.5
5.5
4.5
3.5
2.5
2
1.5
1.5
1
0.5
0.5
0
5
10
15
Flash Execution
20
25
30
Frequency (MHz)
35
40
45
0
50
5
10
15
D013
VCC = 3 V
TA = 25°C
SRAM Execution
20
25
30
Frequency (MHz)
35
40
45
50
D014
VCC = 3 V
TA = 25°C
Figure 5-14. Frequency vs Current Consumption
Figure 5-13. Frequency vs Current Consumption
5.5
4
AM_DCDC_VCORE0
AM_DCDC_VCORE1
3.5
AM_DCDC_VCORE0
AM_DCDC_VCORE1
5
4.5
4
Current (mA)
Current (mA)
3
2.5
2
3.5
3
2.5
2
1.5
1.5
1
1
0.5
0.5
0
5
10
Flash Execution
15
20
25
30
Frequency (MHz)
VCC = 3 V
35
40
45
Specifications
0
5
10
D015
TA = 25°C
Figure 5-15. Frequency vs Current Consumption
40
50
SRAM Execution
15
20
25
30
Frequency (MHz)
VCC = 3 V
35
40
45
50
D016
TA = 25°C
Figure 5-16. Frequency vs Current Consumption
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.17 Typical Characteristics of Low-Frequency Active Mode Currents for CoreMark Program
110
126
AM_LF_VCORE0
AM_LF_VCORE1
124
108
122
Current (PA)
Current (PA)
120
118
116
114
AM_LF_VCORE0
AM_LF_VCORE1
106
104
102
112
110
100
108
106
2.2
2.3
Flash Execution
2.4
2.5
2.6
2.7
Supply Voltage
2.8
TA = 25°C
2.9
3
98
2.2
2.3
D017
MCLK = 128 kHz
Figure 5-17. Supply Voltage vs Current Consumption
SRAM Execution
2.4
2.5
2.6
2.7
Supply Voltage
TA = 25°C
2.8
2.9
D018
MCLK = 128 kHz
Figure 5-18. Supply Voltage vs Current Consumption
Specifications
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3
41
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
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5.18 Current Consumption in LDO-Based LPM0 Modes
over recommended operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0_LDO_VCORE0
ILPM0_LDO_VCORE1
(1)
(2)
(3)
(4)
(5)
(6)
VCC
MCLK =
1 MHz
MCLK =
8 MHz
MCLK =
16 MHz
(2) (3) (4) (5) (6)
MCLK =
24 MHz
MCLK =
32 MHz
TYP
MAX
MCLK =
40 MHz
TYP
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
2.2 V
520
750
610
850
710
950
810
1050
3.0 V
520
750
610
850
710
950
810
1050
2.2 V
525
800
630
900
750
1050
860
1200
1025
1350
1160
1500
1240
1600
3.0 V
525
800
630
900
750
1050
860
1200
1025
1350
1160
1500
1240
1600
UNIT
MAX
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU is off, flash or SRAM not being accessed.
All SRAM banks are active.
All peripherals are inactive.
5.19 Current Consumption in DC/DC-Based LPM0 Modes
over recommended operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0_DCDC_VCORE0
ILPM0_DCDC_VCORE1
(1)
(2)
(3)
(4)
(5)
(6)
VCC
MCLK =
1 MHz
MCLK =
8 MHz
MCLK =
16 MHz
(2) (3) (4) (5) (6)
MCLK =
24 MHz
MCLK =
32 MHz
TYP
MAX
MCLK =
40 MHz
TYP
MCLK =
48 MHz
TYP
MAX
TYP
MAX
TYP
MAX
TYP
MAX
MAX
TYP
2.2 V
490
700
550
750
620
850
700
950
3.0 V
485
650
535
700
585
750
650
850
2.2 V
510
750
590
850
680
950
775
1050
900
1200
1010
1300
1080
1400
3.0 V
505
700
570
800
635
850
715
950
815
1050
900
1150
960
1200
UNIT
MAX
µA
µA
MCLK sourced by DCO.
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU is off, flash or SRAM not being accessed.
All SRAM banks are active.
All peripherals are inactive.
5.20 Current Consumption in Low-Frequency LPM0 Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM0_LF_VCORE0
ILPM0_LF_VCORE1
(1)
(2)
(3)
(4)
(5)
(6)
42
VCC
–40°C
TYP
25°C
MAX
TYP
2.2 V
73
77
3.0 V
73
77
2.2 V
75
80
3.0 V
75
80
60°C
MAX
100
100
TYP
(2) (3) (4) (5) (6)
85°C
MAX
TYP
87
113
87
113
92
122
92
122
MAX
200
250
UNIT
μA
μA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
MCLK sourced by REFO at 128 kHz.
All peripherals are inactive.
Bank 0 of SRAM are active. Rest of the banks are powered down.
CPU is off, flash or SRAM not being accessed.
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.21 Current Consumption in LPM3, LPM4 Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM3_VCORE0_RTCLF
(7) (8)
ILPM3_VCORE0_RTCREFO
ILPM3_VCORE1_RTCLF
(10)
ILPM4_VCORE1
(10)
IIDLE, PG1, VCORE0
IIDLE, PG1, VCORE1
IIDLE, PG2, VCORE0
IIDLE, PG2, VCORE1
IIDLE, PG3, VCORE0
IIDLE, PG3, VCORE1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(9) (8)
(7) (8)
ILPM3_VCORE1_RTCREFO
ILPM4_VCORE0
VCC
(9) (8)
–40°C
TYP
25°C
MAX
TYP
60°C
MAX
TYP
85°C
MAX
TYP
2.2 V
0.64
0.79
1.38
2.90
3.0 V
0.66
0.82
1.41
3.10
2.2 V
0.98
1.27
1.93
3.50
3.0 V
1.10
1.36
2.00
3.70
2.2 V
0.91
1.17
1.91
3.80
3.0 V
0.94
1.20
1.95
3.85
2.2 V
1.27
1.63
2.38
4.30
3.0 V
1.33
1.69
2.58
4.85
2.2 V
0.50
0.66
1.04
3.10
3.0 V
0.53
0.69
1.07
3.10
2.2 V
0.65
0.90
1.74
4.01
3.0 V
0.67
0.92
1.77
4.05
2.2 V
0.22
0.34
0.92
2.42
3.0 V
0.22
0.34
0.93
2.43
2.2 V
0.35
0.53
1.27
3.07
3.0 V
0.35
0.53
1.28
3.08
2.2 V
0.25
0.40
1.15
3.08
3.0 V
0.25
0.41
1.15
3.09
2.2 V
0.41
0.65
1.61
3.96
3.0 V
0.41
0.65
1.61
3.96
2.2 V
0.28
0.45
1.27
3.40
3.0 V
0.28
0.45
1.27
3.41
2.2 V
3.53
3.74
5.45
8.38
3.0 V
3.53
3.75
5.45
8.38
3.80
(2) (3) (4) (5) (6)
MAX
UNIT
μA
8.00
μA
μA
μA
μA
μA
uA
uA
uA
uA
uA
uA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU is off, flash powered down.
Bank 0 of SRAM retained, all other banks powered down.
See Table 5-51 for details on additional current consumed for each extra Bank that is enabled for retention.
SVSMH is disabled.
RTC sourced by LFXT. Effective load capacitance of LF crystal is 3.7 pF.
WDT module is disabled.
RTC sourced by REFO.
RTC and WDT modules disabled.
Specifications
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MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
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5.22 Current Consumption in LPM3 Modes With LCD
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ILPM3_VCORE0_LCDEXT
(7) (8) (9)
ILPM3_VCORE0_LCDINT
(7) (8) (10)
ILPM3_VCORE1_LCDEXT
(7) (8) (9)
ILPM3_VCORE1_LCDINT
(7) (8) (10)
VCC
–40°C
TYP
(1) (2) (3) (4) (5) (6)
25°C
MAX
TYP
60°C
MAX
TYP
85°C
MAX
TYP
2.4 V
1.24
1.60
3.16
7.29
3.0 V
1.27
1.63
3.18
7.32
2.4 V
1.61
1.98
3.53
7.68
3.0 V
1.64
2.00
3.56
7.70
2.4 V
4.60
5.44
7.97
13.15
3.0 V
4.64
5.47
7.99
13.19
2.4 V
5.00
5.86
8.35
13.55
3.0 V
5.04
5.89
8.38
13.59
MAX
UNIT
μA
μA
μA
μA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU is off, flash powered down.
Block 0 of SRAM retained, all other blocks and banks powered down.
See Table 5-51 for details on additional current consumed for each extra block that is enabled for retention.
SVSMH is disabled.
RTC sourced by LFXT. Effective load capacitance of LF crystal is 3.7 pF.
WDT module is disabled.
LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDSSEL = 0, LCDPREx =
101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz). Current through external resistors not included (voltage levels are supplied
by test equipment). Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(10) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDSSEL = 0, LCDPREx = 101,
LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz) Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
5.23 Current Consumption in LPM3.5, LPM4.5 Modes
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
ILPM3.5_RTCLF
(3) (4) (5) (6) (7)
ILPM3.5_RTCREFO
ILPM4.5
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
44
(3) (4) (8) (6) (7)
(9) (7)
VCC
–40°C
TYP
25°C
MAX
TYP
60°C
MAX
TYP
85°C
MAX
TYP
2.2 V
0.64
0.79
1.38
2.90
3.0 V
0.66
0.82
1.41
3.10
2.2 V
0.98
1.27
1.93
3.50
3.0 V
1.10
1.36
2.00
3.70
2.2 V
13
19
62
207
3.0 V
14
22
69
229
500
(2)
MAX
UNIT
μA
μA
1200
nA
Current measured into VCC.
All other input pins tied to 0 V or VCC. Outputs do not source or sync any current.
CPU and flash are powered down.
Bank 0 of SRAM retained, all other banks powered down.
RTC sourced by LFXT. Effective load capacitance of LF crystal is 3.7 pF.
WDT module is disabled.
SVSMH is disabled.
RTC sourced by REFO.
No core voltage. CPU, flash and all banks of SRAM powered down.
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.24 Current Consumption of Digital Peripherals
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
ITIMER_A
Timer_A configured as PWM timer with 50% duty cycle
5
µA/MHz
ITIMER32
Timer32 enabled
3.5
µA/MHz
IUART
eUSCI_A configured in UART mode
6.5
µA/MHz
ISPI
eUSCI_A configured in SPI master mode
5
µA/MHz
2
II2C
eUSCI_B configured in I C master mode
5
µA/MHz
IWDT_A
WDT_A configured in interval timer mode
6
µA/MHz
IRTC_C
RTC_C enabled and sourced from 32-kHz LFXT
IAES256
ICRC32
(1)
100
nA
AES256 active
19
µA/MHz
CRC32 active
2
µA/MHz
Measured with VCORE = 1.2 V.
5.25 Thermal Resistance Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
THERMAL METRIC (1)
PACKAGE
VALUE (2)
(3)
UNIT
RθJA
Junction-to-ambient thermal resistance, still air
44.5
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance
6.4
°C/W
RθJB
Junction-to-board thermal resistance
22.0
°C/W
ΨJB
Junction-to-board thermal characterization parameter
21.7
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.2
°C/W
RθJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
RθJA
Junction-to-ambient thermal resistance, still air
28.2
°C/W
RθJC(TOP)
Junction-to-case (top) thermal resistance
7.7
°C/W
RθJB
Junction-to-board thermal resistance
6.8
°C/W
ΨJB
Junction-to-board thermal characterization parameter
6.7
°C/W
ΨJT
Junction-to-top thermal characterization parameter
0.1
°C/W
RθJC(BOTTOM)
Junction-to-case (bottom) thermal resistance
0.7
°C/W
(1)
(2)
(3)
LQFP-100 (PZ)
QFN-64 (RGC)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
N/A = Not applicable
Specifications
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MSP432P4111, MSP432P4011, MSP432P411Y
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5.26 Timing and Switching Characteristics
5.26.1 Reset Timing
Table 5-1 lists the latencies to recover from different types of resets.
Table 5-1. Reset Recovery Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
(1)
TYP
MAX
UNIT
5
MCLK
cycles
25
MCLK
cycles
tSOFT
Latency from release of soft reset to first CPU instruction fetch
tHARD
Latency from release of hard reset to release of soft reset
tPOR
Latency from release of device POR to release of hard reset
15
25
µs
tCOLDPWR,
100nF
Latency from a cold power-up condition to release of device POR, CVCORE = 100 nF
300
400
µs
4.7µF
Latency from a cold power-up condition to release of device POR, CVCORE = 4.7 µF
400
500
µs
tCOLDPWR,
(1)
See Section 6.8.1 for details on the various classes of resets on the device
Table 5-2 lists the latencies to recover from an external reset applied on RSTn pin.
Table 5-2. External Reset Recovery Latencies (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
tAM_RSTn
External reset applied when device is in LDO-based or DC/DC-based active
modes,
MCLK = 1 to 48 MHz
tAMLF_RSTn, 128 kHz
MAX
UNIT
4.5
ms
External reset applied when device is in low-frequency active modes,
MCLK = 128 kHz
5
ms
tAMLF_RSTn, 32 kHz
External reset applied when device is in low-frequency active modes,
MCLK = 32.768 kHz
6
ms
tLPM0_RSTn
External reset applied when device is in LDO-based or DC/DC-based LPM0
modes,
MCLK = 1 to 48 MHz
4.5
ms
tLPM0LF_RSTn, 128 kHz
External reset applied when device is in low-frequency LPM0 modes,
MCLK = 128 kHz
5
ms
tLPM0LF_RSTn, 32 kHz
External reset applied when device is in low-frequency LPM0 modes,
MCLK = 32.768 kHz
6
ms
tLPM3_LPM4_RSTn
External reset applied when device is in LPM3 or LPM4 modes,
MCLK = 24 or 48 MHz while entering LPM3 or LPM4 modes
4.5
ms
tLPMx.5_RSTn
External reset applied when device is in LPM3.5 or LPM4.5 modes
4.5
ms
(1)
External reset is applied on RSTn pin, and the latency is measured from release of external reset to start of user application code.
5.26.2 Peripheral Register Access Timing
Table 5-3 lists the latency involved when CPU performs read or write access to peripheral registers.
Table 5-3. Peripheral Register Access Latency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
treg_access
(1)
(2)
46
Number of CPU clock cycles required for read or write access to peripheral registers
MIN
MAX
UNIT
2 (1)
5 (2)
MCLK
cycles
The bridge that connects CPU to peripherals runs at half of the speed of the CPU.
The maximum value depends on the previous opcode executing in the CPU pipeline and the status of the bus (idle or busy performing
data access).
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.26.3 Mode Transition Timing
Table 5-4 lists the latencies required to change between different active modes.
Table 5-4. Active Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ORIGINAL
OPERATING MODE
FINAL OPERATING
MODE
Power Off
AM_LDO_VCORE0
From VCC reaching 1.71 V to start of
user application code
tAMLDO0_AMLDO1
AM_LDO_VCORE0
AM_LDO_VCORE1
Transition from AM_LDO_VCORE0 to
AM_LDO_VCORE1,
MCLK frequency = 24 MHz
tAMLDO1_AMLDO0
AM_LDO_VCORE1
AM_LDO_VCORE0
tAMLDO0_AMDCDC0
AM_LDO_VCORE0
tAMDCDC0_AMLDO0
AM_DCDC_VCORE0
tAMLDO1_AMDCDC1
AM_LDO_VCORE1
tAMDCDC1_AMLDO1
AM_DCDC_VCORE1
AM_LDO_VCORE1
AM_LDO_VCORE0
AM_LF_VCORE0
PARAMETER
tOFF_AMLDO0
tAMLDO0_AMLF0
TEST CONDITIONS
TYP
MAX
UNIT
6
ms
300
350
µs
Transition from AM_LDO_VCORE1 to
AM_LDO_VCORE0,
MCLK frequency = 24 MHz
4
5
µs
Transition from AM_LDO_VCORE0 to
AM_DCDC_VCORE0 AM_DCDC_VCORE0,
MCLK frequency = 24 MHz
20
30
µs
10
15
µs
20
30
µs
Transition from AM_DCDC_VCORE1
to AM_LDO_VCORE1,
MCLK frequency = 48 MHz
10
15
µs
Transition from AM_LDO_VCORE0 to
AM_LF_VCORE0, SELM = 2,
REFO frequency = 128 kHz
90
100
µs
Transition from AM_LF_VCORE0 to
AM_LDO_VCORE0,
SELM = 2, REFO frequency =
128 kHz
50
60
µs
Transition from AM_LDO_VCORE1 to
AM_LF_VCORE1, SELM = 2,
REFO frequency = 128 kHz
90
100
µs
Transition from AM_LF_VCORE1 to
AM_LDO_VCORE1, SELM = 2,
REFO frequency = 128 kHz
50
60
µs
AM_LDO_VCORE0
Transition from AM_DCDC_VCORE0
to AM_LDO_VCORE0,
MCLK frequency = 24 MHz
Transition from AM_LDO_VCORE1 to
AM_DCDC_VCORE1 AM_DCDC_VCORE1,
MCLK frequency = 48 MHz
tAMLF0_AMLDO0
AM_LF_VCORE0
AM_LDO_VCORE0
tAMLDO1_AMLF1
AM_LDO_VCORE1
AM_LF_VCORE1
tAMLF1_AMLDO1
AM_LF_VCORE1
AM_LDO_VCORE1
Specifications
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Table 5-5 lists the latencies required to change between different active and LPM0 modes.
Table 5-5. LPM0 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tAMLDOx_LPM0LDOx
(1)
tLPM0LDOx_AMLDOx (2)
tAMDCDCx_LPM0DCDCx (1)
tLPM0DCDCx_AMDCDCx (2)
tAMLFx_LPM0LFx
(1)
tLPM0LFx_AMLFx (2)
(1)
(2)
48
ORIGINAL OPERATING
MODE
AM_LDO_VCOREx
LPM0_LDO_VCOREx
AM_DCDC_VCOREx
LPM0_DCDC_VCOREx
AM_LF_VCOREx
LPM0_LF_VCOREx
FINAL OPERATING
MODE
TEST CONDITIONS
TYP
LPM0_LDO_VCOREx
Transition from
AM_LDO_VCORE0 or
AM_LDO_VCORE1 to
LPM0_LDO_VCORE0 or
LPM0_LDO_VCORE1
1
AM_LDO_VCOREx
Transition from
LPM0_LDO_VCORE0 or
LPM0_LDO_VCORE1 to
AM_LDO_VCORE0 or
AM_LDO_VCORE1
through I/O interrupt
3
LPM0_DCDC_VCOREx
Transition from
AM_DCDC_VCORE0 or
AM_DCDC_VCORE1 to
LPM0_DCDC_VCORE0
or
LPM0_DCDC_VCORE1
1
AM_DCDC_VCOREx
Transition from
LPM0_DCDC_VCORE0
or
LPM0_DCDC_VCORE1
to AM_DCDC_VCORE0
or AM_DCDC_VCORE1
through I/O interrupt
3
Transition from
AM_LF_VCORE0 or
AM_LF_VCORE1 to
LPM0_LF_VCORE0 or
LPM0_LF_VCORE1
1
Transition from
LPM0_LF_VCORE0 or
LPM0_LF_VCORE1 to
AM_LF_VCORE0 or
AM_LF_VCORE1 through
I/O interrupt
3
LPM0_LF_VCOREx
AM_LF_VCOREx
MAX
UNIT
MCLK
cycles
4
MCLK
cycles
MCLK
cycles
4
MCLK
cycles
MCLK
cycles
4
MCLK
cycles
This is the latency between execution of WFI instruction by CPU to assertion of SLEEPING signal at CPU output.
This is the latency between I/O interrupt event to deassertion of SLEEPING signal at CPU output.
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 5-6 lists the latencies required to change between different active modes and LPM3 or LPM4
modes.
Table 5-6. LPM3, LPM4 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ORIGINAL
OPERATING MODE
PARAMETER
tAMLDO0_LPMx0
(1)
tLPMx0_AMLDO0_NORIO
AM_LDO_VCORE0
(2)
(2)
tLPMx0_AMLDO0_GFLTIO
tAMLDO1_LPMx1
(1)
tLPMx1_AMLDO1_NORIO
tLPMx1_AMLDO1_GFLTIO
tAMLFx_LPMx_128k
tAMLFx_LPMx_32k
(2)
(1)
(1)
tLPMx_AMLFx_NORIO_128k
tLPMx_AMLFx_NORIO_32k
(1)
(2)
(2)
(2)
MAX
UNIT
18
60
µs
AM_LDO_VCORE0
Transition from LPM3 or
LPM4 at VCORE0 to
AM_LDO_VCORE0 through
wake-up event from
nonglitch-filter type I/O
SELM = 3.
DCO frequency =
24 MHz
8
9
µs
AM_LDO_VCORE0
Transition from LPM3 or
LPM4 at VCORE0 to
AM_LDO_VCORE0 through
wake-up event from glitchfilter type I/O, GLTFLT_EN
= 1
SELM = 3.
DCO frequency =
24 MHz
9
10
µs
Transition from
LPM3_LPM4_VCORE1 AM_LDO_VCORE1 to
LPM3 or LPM4 at VCORE1
SELM = 3.
DCO frequency =
48 MHz
17
60
µs
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1 through
wake-up event from
nonglitch-filter type I/O
SELM = 3.
DCO frequency =
48 MHz
7.5
8
µs
AM_LDO_VCORE1
Transition from LPM3 or
LPM4 at VCORE1 to
AM_LDO_VCORE1 through
wake-up event from glitchfilter type I/O, GLTFLT_EN
= 1
SELM = 3.
DCO frequency =
48 MHz
8
9
µs
LPM3_LPM4_VCOREx
Transition from
AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM3
or LPM4 at VCORE0 or
VCORE1
SELM = 2. REFO
frequency =
128 kHz
255
290
µs
LPM3_LPM4_VCOREx
Transition from
AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM3
or LPM4 at VCORE0 or
VCORE1
SELM = 0. LFXT
frequency =
32.768 kHz
980
1025
µs
AM_LF_VCOREx
Transition from LPM3 or
LPM4 at VCORE0 or
VCORE1 to
AM_LF_VCORE0 or
AM_LF_VCORE1 through
wake-up event from
nonglitch-filter type I/O
SELM = 2. REFO
frequency =
128 kHz
45
50
µs
AM_LF_VCOREx
Transition from LPM3 or
LPM4 at VCORE0 or
VCORE1 to
AM_LF_VCORE0 or
AM_LF_VCORE1 through
wake-up event from
nonglitch-filter type I/O
SELM = 0. LFXT
frequency =
32.768 kHz
150
170
µs
LPM3_LPM4_VCORE1
LPM3_LPM4_VCORE1
AM_LF_VCOREx
TYP
SELM = 3.
DCO frequency =
24 MHz
LPM3_LPM4_VCORE0
AM_LF_VCOREx
TEST CONDITIONS
Transition from
LPM3_LPM4_VCORE0 AM_LDO_VCORE0 to
LPM3 or LPM4 at VCORE0
LPM3_LPM4_VCORE0
AM_LDO_VCORE1
(2)
FINAL OPERATING
MODE
LPM3_LPM4_VCOREx
LPM3_LPM4_VCOREx
This is the latency from WFI instruction execution by CPU to LPM3 or LPM4 entry.
This is the latency from I/O wake-up event to MCLK clock start at device pin.
Specifications
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Table 5-7 lists the latencies required to change to and from LPM3.5 and LPM4.5 modes.
Table 5-7. LPM3.5, LPM4.5 Mode Transition Latencies
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
ORIGINAL
OPERATING MODE
FINAL OPERATING
MODE
tAMLDOx_LPM3.5 (1)
AM_LDO_VCOREx
LPM3.5
tAMDCDCx_LPM3.5 (1)
AM_DCDC_VCOREx
PARAMETER
TYP
MAX
Transition from AM_LDO_VCORE0 or
AM_LDO_VCORE1 to LPM3.5
57
60
µs
LPM3.5
Transition from AM_DCDC_VCORE0 or
AM_DCDC_VCORE1 to LPM3.5
70
83
µs
AM_LF_VCOREx
LPM3.5
Transition from AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM3.5
224
275
µs
tAMLDOx_LPM4.5 (2)
AM_LDO_VCOREx
LPM4.5
Transition from AM_LDO_VCORE0 or
AM_LDO_VCORE1 to LPM4.5
57
60
µs
tAMDCDCx_LPM4.5 (2)
AM_DCDC_VCOREx
LPM4.5
Transition from AM_DCDC_VCORE0 or
AM_DCDC_VCORE1 to LPM4.5
68
81
µs
AM_LF_VCOREx
LPM4.5
Transition from AM_LF_VCORE0 or
AM_LF_VCORE1 to LPM4.5
230
248
µs
tLPM3.5_AMLDO0 (3)
LPM3.5
AM_LDO_VCORE0
Transition from LPM3.5 to
AM_LDO_VCORE0
0.7
0.8
ms
tLPM4.5_AMLDO0_SVSMON, 100 nF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH enabled while in LPM4.5,
CVCORE = 100 nF
0.8
0.9
ms
tLPM4.5_AMLDO0_SVSMON, 4.7 µF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH enabled while in LPM4.5,
CVCORE = 4.7 µF
0.9
1.0
ms
tLPM4.5_AMLDO0_SVSMOFF, 100 nF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH disabled while in LPM4.5,
CVCORE = 100 nF
1.0
1.1
ms
tLPM4.5_AMLDO0_SVSMOFF, 4.7 µF (3)
LPM4.5
AM_LDO_VCORE0
Transition from LPM4.5 to
AM_LDO_VCORE0,
SVSMH disabled while in LPM4.5,
CVCORE = 4.7 µF
1.1
1.2
ms
tAMLFx_LPM3.5 (1)
tAMLFx_LPM4.5 (2)
(1)
(2)
(3)
50
TEST CONDITIONS
UNIT
This is the latency from WFI instruction execution by CPU to LPM3.5 mode entry.
This is the latency from WFI instruction execution by CPU to LPM4.5 mode entry.
This is the latency from I/O wake-up event to start of user application code.
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.26.4 Clock Specifications
Table 5-8 lists the input requirement for the low-frequency crystal oscillator, LFXT.
Table 5-8. Low-Frequency Crystal Oscillator, LFXT, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
UNIT
ESR
Crystal equivalent series resistance
16
40
65
kΩ
CLFXT
Capacitance from LFXT input to ground and from
LFXT output to ground (1)
7.4
12
24
pF
CSHUNT
Crystal shunt capacitance
0.6
0.8
1.6
pF
Cm
Crystal motional capacitance
1
2
10
fF
(1)
fOSC = 32.768 kHz
MIN
Does not include board parasitics. Package and board add additional capacitance to CLFXT.
Table 5-9 lists the characteristics of the low-frequency crystal oscillator, LFXT.
Table 5-9. Low-Frequency Crystal Oscillator, LFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IVCC,LFXT
Current consumption
TEST CONDITIONS
(1)
VCC
MIN
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
CL,eff = 3.7 pF, Typical ESR, CSHUNT
100
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {1},
CL,eff = 6 pF, Typical ESR, CSHUNT
120
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {2},
CL,eff = 9 pF, Typical ESR, CSHUNT
fLFXT
LFXT oscillator crystal
frequency
LFXTBYPASS = 0 (2)
DCLFXT
LFXT oscillator duty cycle
fLFXT = 32.768 kHz (2)
fLFXT,SW
LFXT oscillator logic-level
square-wave input frequency
LFXTBYPASS = 1 (3)
DCLFXT,
LFXT oscillator logic-level
square-wave input duty cycle
LFXTBYPASS = 1
OALFXT
(1)
(2)
(3)
(4)
(5)
Oscillation allowance for
LF crystals (5)
MAX
3.0 V
nA
170
32.768
(4)
UNIT
150
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
CL,eff = 12 pF, Typical ESR, CSHUNT
SW
TYP
30%
10
kHz
70%
32.768
30%
50
kHz
70%
LFXTBYPASS = 0, LFXTDRIVE = {1},
fLFXT = 32.768 kHz, CL,eff = 6 pF
200
240
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32.768 kHz, CL,eff = 12 pF
300
340
kΩ
Total current measured on both AVCC and DVCC supplies.
Measured at ACLK pin.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF
Specifications
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Table 5-9. Low-Frequency Crystal Oscillator, LFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
CLFXIN
Integrated load capacitance at
LFXIN terminal (6) (7)
2
pF
CLFXOUT
Integrated load capacitance at
LFXOUT terminal (6) (7)
2
pF
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {0},
CL,eff = 3.7 pF, Typical ESR, CSHUNT,
FCNTLF_EN = 0 (2)
tSTART,LFXT Start-up time (8)
fFault,LFXT
Oscillator fault frequency (9)
fOSC = 32.768 kHz,
LFXTBYPASS = 0, LFXTDRIVE = {3},
CL,eff = 12 pF, Typical ESR, CSHUNT,
FCNTLF_EN = 0 (2)
1.1
3.0 V
s
1.3
(10)
1
3
kHz
(6)
This represents all the parasitic capacitance present at the LFXIN and LFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the LFXIN and LFXOUT terminals, respectively.
(7) Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 3.7 pF, 6 pF, 9 pF, and 12 pF. Maximum shunt capacitance of 1.6 pF. Because the
PCB adds additional capacitance, it must also be considered in the overall capacitance. Verify that the recommended effective load
capacitance of the selected crystal is met.
(8) Does not include programmable start-up counter.
(9) Frequencies greater than the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set
the flag. A static condition or stuck-at-fault condition sets the fault flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
Table 5-10 lists the input requirements for the high-frequency crystal oscillator, HFXT.
Table 5-10. High-Frequency Crystal Oscillator, HFXT, Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
ESR
Crystal equivalent series resistance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOSC = 1 MHz to ≤ 4 MHz
75
150
fOSC = > 4 MHz to ≤ 8 MHz
75
150
fOSC = > 8 MHz to ≤ 16 MHz
40
80
fOSC = > 16 MHz to ≤ 24 MHz
30
60
fOSC = > 24 MHz to ≤ 32 MHz
20
40
fOSC = > 32 MHz to ≤ 48 MHz
15
30
36
pF
Ω
CHFXT
Capacitance from HFXT input to ground
and from HFXT output to ground
fOSC = 1 MHz to 48 MHz
28
32
CSHUNT
Crystal shunt capacitance
fOSC = 1 MHz to 48 MHz
1
3
7
pF
Cm
Crystal motional capacitance
fOSC = 1 MHz to 48 MHz
3
7
30
fF
52
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 5-11 lists the characteristics of the high-frequency crystal oscillator, HFXT.
Table 5-11. High-Frequency Crystal Oscillator, HFXT
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IDVCC,HFXT
HFXT oscillator crystal current
HF mode at typical ESR
HFXT oscillator crystal
frequency, crystal mode
fHFXT
TEST CONDITIONS
60
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1, CL,eff = 16 pF,
Typical ESR and CSHUNT
100
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 2, CL,eff = 16 pF,
Typical ESR and CSHUNT
180
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 3, CL,eff = 16 pF,
Typical ESR and CSHUNT
260
fOSC = 40 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 5, CL,eff = 16 pF,
Typical ESR and CSHUNT
480
fOSC = 48 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 6, CL,eff = 16 pF,
Typical ESR and CSHUNT
550
HFXTBYPASS = 0, HFFREQ = 0
(1)
1
HFXTBYPASS = 0, HFFREQ = 1
(1)
4.01
8
HFXTBYPASS = 0, HFFREQ = 2
(1)
8.01
16
HFXTBYPASS = 0, HFFREQ = 3
(1)
16.01
24
HFXTBYPASS = 0, HFFREQ = 4
(1)
24.01
32
HFXTBYPASS = 0, HFFREQ = 5
(1)
32.01
40
HFXTBYPASS = 0, HFFREQ = 6
(1)
40.01
48
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
HFXTBYPASS = 1 (1) (2)
UNIT
μA
320
fHFXT,SW
(1)
(2)
MAX
3.0 V
fOSC = 32 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 4, CL,eff = 16 pF,
Typical ESR and CSHUNT
Measured at MCLK or HSMCLK,
fHFXT = 1 MHz to 48 MHz
HFXT oscillator logic-level
square-wave input duty cycle
TYP
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT
HFXT oscillator duty cycle
SW
MIN
40
DCHFXT
DCHFXT,
VCC
fOSC = 1 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT
40%
4
50%
MHz
60%
0.8
48
HFXTBYPASS = 1,
External clock used as a direct source to
MCLK or HSMCLK with no divider
(DIVM = 0 or DIVHS = 0).
45%
55%
HFXTBYPASS = 1,
External clock used as a direct source to
MCLK or HSMCLK with divider (DIVM > 0
or DIVHS > 0) or not used as a direct
source to MCLK or HSMCLK.
40%
60%
MHz
Maximum frequency of operation of the entire device cannot be exceeded.
When HFXTBYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger Inputs section of this data sheet. Duty cycle requirements are defined by DCHFXT, SW.
Specifications
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Table 5-11. High-Frequency Crystal Oscillator, HFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
OAHFXT
(3)
54
Oscillation allowance for
HFXT crystals (3)
MIN
TYP
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 0,
fHFXT,HF = 1 MHz, CL,eff = 16 pF
TEST CONDITIONS
VCC
1225
5000
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 0,
fHFXT,HF = 4 MHz, CL,eff = 16 pF
640
1250
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1,
fHFXT,HF = 8 MHz, CL,eff = 16 pF
360
750
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 2,
fHFXT,HF = 16 MHz, CL,eff = 16 pF
200
425
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 3,
fHFXT,HF = 24 MHz, CL,eff = 16 pF
135
275
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 4,
fHFXT,HF = 32 MHz, CL,eff = 16 pF
110
225
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 5
fHFXT,HF = 40 MHz, CL,eff = 16 pF
105
160
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 6,
fHFXT,HF = 48 MHz, CL,eff = 16 pF
80
140
MAX
UNIT
Ω
Oscillation allowance is based on a safety factor of 5 for recommended crystals.
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 5-11. High-Frequency Crystal Oscillator, HFXT (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tSTART,HFXT
TEST CONDITIONS
Start-up time (4)
VCC
MIN
TYP
fOSC = 1 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 0,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
4
fOSC = 4 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 0, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
1.8
fOSC = 8 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 1, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
0.7
fOSC = 16 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 2, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
0.6
fOSC = 24 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 3, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
MAX
UNIT
ms
3.0 V
450
fOSC = 32 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 4, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
300
fOSC = 40 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 5, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
250
fOSC = 48 MHz,
HFXTBYPASS = 0, HFXTDRIVE = 1,
HFFREQ = 6, CL,eff = 16 pF,
Typical ESR and CSHUNT,
FCNTHF_EN = 0
250
µs
CHFXIN
Integrated load capacitance at
HFXIN terminal (5) (6)
2
pF
CHFXOUT
Integrated load capacitance at
HFXOUT terminal (5) (6)
2
pF
fFault,HFXT
Oscillator fault frequency (7)
(4)
(5)
(6)
(7)
(8)
(8)
400
700
kHz
Does not include programable start-up counter.
This represents all the parasitic capacitance present at the HFXIN and HFXOUT terminals, respectively, including parasitic bond and
package capacitance. The effective load capacitance, CL,eff can be computed as CIN × COUT / (CIN + COUT), where CIN and COUT are the
total capacitance at the HFXIN and HFXOUT terminals, respectively.
Requires external capacitors at both terminals to meet the effective load capacitance specified by crystal manufacturers. Recommended
effective load capacitance values supported are 14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF. The PCB adds
additional capacitance, so it must also be considered in the overall capacitance. Verify that the recommended effective load capacitance
of the selected crystal is met.
Frequencies greater than the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set
the flag. A static condition or stuck-at-fault condition sets the fault flag.
Measured with logic-level input frequency but also applies to operation with crystals.
Specifications
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Table 5-12 lists the characteristics of the DCO.
Table 5-12. DCO
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fRSEL0_CTR
fRSEL1_CTR
fRSEL2_CTR
fRSEL3_CTR
fRSEL4_CTR
fRSEL5_CTR
MIN
TYP
MAX
DCO center frequency
accuracy for range 0
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 0, DCOTUNE = 0
1.443
1.5
1.557
External resistor mode,
DCORSEL = 0, DCOTUNE = 0
1.482
1.5
1.518
DCO center frequency
accuracy for range 1
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 1, DCOTUNE = 0
2.885
3
3.115
External resistor mode,
DCORSEL = 1, DCOTUNE = 0
2.964
3
3.036
DCO center frequency
accuracy for range 2
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 2, DCOTUNE = 0
5.77
6
6.23
External resistor mode,
DCORSEL = 2, DCOTUNE = 0
5.928
6
6.072
DCO center frequency
accuracy for range 3
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 3, DCOTUNE = 0
11.541
12
12.459
External resistor mode,
DCORSEL = 3, DCOTUNE = 0
11.856
12
12.144
DCO center frequency
accuracy for range 4
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 4, DCOTUNE = 0
23.082
24
24.918
External resistor mode,
DCORSEL = 4, DCOTUNE = 0
23.712
24
24.288
DCO center frequency
accuracy for range 5
with calibrated factory
settings
Internal resistor mode,
DCORSEL = 5, DCOTUNE = 0
46.164
48
49.836
External resistor mode,
DCORSEL = 5, DCOTUNE = 0
47.424
48
48.576
DCO frequency drift with
temperature (1)
dfDCO/dT
TEST CONDITIONS
VCC, TA
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
Internal resistor mode,
At fixed voltage
1.62 V to 3.7 V
250
External resistor mode (2)
At fixed voltage
1.62 V to 3.7 V
60
–40°C to 85 °C
0.1
%/V
ppm/°C
dfDCO/dVCC
DCO frequency voltage
drift with voltage (3)
At fixed temperature, applicable for
both DCO Internal and External
resistor modes
fRSEL0
DCO frequency range 0
DCORSEL = 0
DCO internal or external resistor
mode
3.0 V, 25℃
0.98
2.26
MHz
fRSEL1
DCO frequency range 1
DCORSEL = 1
DCO internal or external resistor
mode
3.0 V, 25℃
1.96
4.51
MHz
fRSEL2
DCO frequency range 2
DCORSEL = 2
DCO internal or external resistor
mode
3.0 V, 25℃
3.92
9.02
MHz
fRSEL3
DCO frequency range 3
DCORSEL = 3
DCO internal or external resistor
mode
3.0 V, 25℃
7.84
18.04
MHz
fRSEL4
DCO frequency range 4
DCORSEL = 4
DCO internal or external resistor
mode
3.0 V, 25℃
15.68
36.07
MHz
fRSEL5
DCO frequency range 5
DCORSEL = 5
DCO internal or external resistor
mode
3.0 V, 25℃
31.36
52
MHz
fDCO_DC
Duty cycle
(1)
(2)
(3)
56
47%
50%
53%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Does not include temperature coefficient of external resistor.
The recommended value of external resistor at DCOR pin: 91 kΩ, 0.1%, ±25 ppm/℃.
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 5-12. DCO (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tDCO_JITTER
TEST CONDITIONS
DCO period jitter
TYP
MAX
DCORSEL = 5, DCOTUNE = 0
VCC, TA
MIN
50
90
DCORSEL = 4, DCOTUNE = 0
80
120
DCORSEL = 3, DCOTUNE = 0
115
170
DCORSEL = 2, DCOTUNE = 0
160
240
DCORSEL = 1, DCOTUNE = 0
225
340
450
550
DCORSEL = 0, DCOTUNE = 0
UNIT
ps
TDCO_STEP
Step size
Step size of the DCO
tDCO_SETTLE_RANGE
DCO settling from worst
case DCORSELn to
DCORSELm
DCO settled to within 1.5% of
steady state frequency
10
μs
tDCO_SETTLE_TUNE
DCO settling worst case
DCOTUNEn to
DCOTUNEm within any
DCORSEL setting
DCO settled to within 1.5% of
steady state frequency
10
μs
tSTART
DCO start-up time (4)
DCO settled to within 0.5% of
steady state frequency
(4)
0.2%
5
μs
The maximum parasitic capacitance at the DCO external resistance pin (DCOR) should not exceed 5 pF to ensure the specified DCO
start-up time.
Table 5-13 lists the overall tolerance of the DCO.
Table 5-13. DCO Overall Tolerance
over operating free-air temperature range (unless otherwise noted)
RESISTOR OPTION
Internal resistor
External resistor
with 25-ppm TCR
TEMPERATURE
CHANGE
TEMPERATURE
DRIFT (%)
VOLTAGE
CHANGE
VOLTAGE DRIFT
(%)
OVERALL DRIFT
(%)
OVERALL
ACCURACY (%)
–40°C to 85 °C
±3.125
1.62 V to 3.7 V
±0.2
±3.325
±3.825
0°C
0
1.62 V to 3.7 V
±0.2
±0.2
±0.7
–40°C to 85 °C
±3.125
0V
0
±3.125
±3.625
–40°C to 85 °C
±0.5
1.62 V to 3.7 V
±0.2
±0.7
±1.2
0°C
0
1.62 V to 3.7 V
±0.2
±0.2
±0.7
–40°C to 85 °C
±0.5
0V
0
±0.5
±1
Specifications
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Table 5-14 lists the characteristics of the internal very-low-power low-frequency oscillator (VLO).
Table 5-14. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
IVLO
Current consumption (1)
fVLO
VLO frequency
dfVLO/dT
VLO frequency temperature drift (2)
dfVLO/dVCC
VLO frequency supply voltage drift (3)
DCVLO
Duty cycle
(1)
(2)
(3)
TEST CONDITIONS
MIN
TYP
MAX
50
6
nA
9.4
18
0.1
kHz
%/°C
0.2
40%
UNIT
%/V
50%
60%
Current measured on DVCC supply
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Table 5-15 lists the characteristics of the internal-reference low-frequency oscillator (REFO) in 32.768‑kHz
mode.
Table 5-15. Internal-Reference Low-Frequency Oscillator (REFO) – 32.768-kHz Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
REFO frequency calibrated
fREFO
REFO absolute tolerance calibrated
dfREFO/dT
REFO frequency temperature drift (3)
dfREFO/dVCC
REFO frequency supply voltage drift (4)
DCREFO
REFO duty cycle
(1)
(2)
(3)
(4)
TYP
REFO current consumption (2)
IREFO
MAX
µA
32.768
kHz
TA = –40°C to 85°C
TA = 25°C
UNIT
0.6
±4%
3V
±1.5%
0.012
%/°C
0.2
%/V
40%
50%
60%
REFO is configured to 32.768-kHz mode with REFOFSEL = 0.
Total current measured on both AVCC and DVCC supplies.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Table 5-16 lists the characteristics of the internal-reference low-frequency oscillator (REFO) in 128‑kHz
mode.
Table 5-16. Internal-Reference Low-Frequency Oscillator (REFO) – 128-kHz Mode (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
REFO current consumption (2)
REFO
REFO absolute tolerance calibrated
REFO frequency temperature drift
REFO frequency supply voltage drift (4)
DCREFO
REFO duty cycle
58
±6%
3V
±1.5%
(3)
dfREFO/dVCC
kHz
TA = –40°C to 85°C
TA = 25°C
UNIT
µA
128
dfREFO/dT
(1)
(2)
(3)
(4)
MAX
1
REFO frequency calibrated
fREFO
TYP
0.018
%/°C
0.4
40%
50%
%/V
60%
REFO is configured to 128-kHz mode with REFOFSEL = 1.
Total current measured on both AVCC and DVCC supplies.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 5-17 lists the characteristics of the module oscillator (MODOSC).
Table 5-17. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IMODOSC
Current consumption (1)
fMODOSC
MODOSC frequency
dfMODOSC/dT
MODOSC frequency temperature
drift (2)
dfMODOSC/dV
CC
MODOSC frequency supply voltage
drift (3)
DCMODOSC
Duty cycle
(1)
(2)
(3)
VCC
MIN
TYP
MAX
50
23
40%
25
UNIT
μA
27
MHz
0.02
%/℃
0.3
%/V
50%
60%
Total current measured on both AVCC and DVCC supplies.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Table 5-18 lists the characteristics of the system oscillator (SYSOSC).
Table 5-18. System Oscillator (SYSOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISYSOSC
Current consumption (1)
fSYSOSC
SYSOSC frequency
dfSYSOSC/ dT
SYSOSC frequency temperature
drift (2)
dfSYSOSC/
dVCC
SYSOSC frequency supply voltage
drift (3)
DCSYSOSC
Duty cycle
(1)
(2)
(3)
TEST CONDITIONS
VCC
MIN
TYP
MAX
30
4.25
40%
5.0
UNIT
μA
5.75
MHz
0.03
%/℃
0.5
%/V
50%
60%
Current measured on AVCC supply.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.62 V to 3.7 V) – MIN(1.62 V to 3.7 V)) / MIN(1.62 V to 3.7 V) / (3.7 V – 1.62 V)
Specifications
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5.26.5 Power Supply System
Table 5-19 lists the LDO VCORE regulator characteristics.
Table 5-19. VCORE Regulator (LDO) Characteristics
MIN
TYP
MAX
UNIT
VCORE0-HP
Static VCORE voltage level 0
in active and LPM0 modes
PARAMETER
Device power modes AM_LDO_VCORE0,
LPM0_LDO_VCORE0
TEST CONDITIONS
1.12
1.2
1.28
V
VCORE1-HP
Static VCORE voltage level 1
in active and LPM0 modes
Device power modes AM_LDO_VCORE1,
LPM0_LDO_VCORE1
1.31
1.4
1.49
V
VCORE0-LF
Static VCORE voltage level 0
in low-frequency active and
low-frequency LPM0 modes
Device power modes AM_LF_VCORE0
1.12
1.2
1.28
V
VCORE1-LF
Static VCORE voltage level 1
in low-frequency active and
low-frequency LPM0 modes
Device power modes AM_LF_VCORE1
1.31
1.4
1.49
V
VCORE0-LPM34
Static VCORE voltage level 0
in LPM3 and LPM4 modes
Device power modes LPM3, LPM4
1.08
1.2
1.32
V
VCORE1-LPM34
Static VCORE voltage level 1
in LPM3 and LPM4 modes
Device power modes LPM3, LPM4
1.27
1.4
1.53
V
VCORE0-LPM35
Static VCORE voltage level 0
in LPM3.5 mode
Device power mode LPM3.5
1.08
1.2
1.32
V
IINRUSH-ST
Inrush current at start-up
Device power up
200
mA
IPEAK-LDO
Peak current drawn by LDO
from DVCC
350
mA
ISC-coreLDO
Short-circuit current limit for
core LDO
300
mA
Measured when output is shorted to ground
Table 5-20 lists the DC/DC VCORE regulator characteristics.
Table 5-20. VCORE Regulator (DC/DC) Characteristics
PARAMETER
DVCC-DCDC
(1)
VDCDC_SO
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Allowed DVCC range for DC/DC
operation
DCDC_FORCE = 1
1.8
3.7
V
DC/DC to LDO switch over
voltage
dDVCC/dt = 1 V/ms, DCDC_FORCE = 0
1.8
2.0
V
VCORE0-DCDC
Device power modes
Static VCORE voltage level 0 in
AM_DCDC_VCORE0,
DC/DC high-performance modes
LPM0_DCDC_VCORE0
1.12
1.2
1.28
V
VCORE1-DCDC
Device power modes
Static VCORE voltage level 1 in
AM_DCDC_VCORE1,
DC/DC high-performance modes
LPM0_DCDC_VCORE1
1.31
1.4
1.49
V
IPEAK-DCDC
Peak current drawn by DC/DC
from DVCC
300
mA
ISC-DCDC
Short-circuit current limit for
DC/DC
500
mA
(1)
60
Measured when output is shorted to
ground
When DVCC falls below this voltage, the regulator automatically switches from DC/DC to LDO.
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 5-21 lists the VCCDET characteristics.
Table 5-21. PSS, VCCDET
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
VVCC_VCCDET-
VCCDET power-down level
dDVCC/dt < 3 V/s (1)
- trip point with falling VCC
0.64
1.12
1.55
V
VVCC_VCCDET+
VCCDET power-up level trip point with rising VCC
0.70
1.18
1.59
V
VVCC_VCC_hys
VCCDET hysteresis
30
65
100
mV
(1)
TEST CONDITIONS
dDVCC/dt < 3 V/s (1)
The VCCDET levels are measured with a slow-changing supply. Faster slopes can result in different levels.
Table 5-22 lists the SVSMH characteristics.
Table 5-22. PSS, SVSMH
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISVSMH
VSVSMH-,HP
VSVSMH+,HP
SVSMH current consumption,
low-power mode
SVSMH current consumption,
high-performance mode
SVSMH threshold level during
high-performance mode
(falling DVCC)
SVSMH threshold level, highperformance mode (rising
DVCC)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SVSMHOFF = 0, SVSMHLP = 1
200
400
nA
SVSMHOFF = 0, SVSMHLP = 0
7
10
μA
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 0,
DC (dDVCC/dt < 1 V/s)
1.59
1.64
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 1,
DC (dDVCC/dt < 1 V/s)
1.59
1.64
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 2,
DC (dDVCC/dt < 1 V/s)
1.59
1.64
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 3,
DC (dDVCC/dt < 1 V/s)
2.0
2.06
2.12
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 4,
DC (dDVCC/dt < 1 V/s)
2.2
2.26
2.32
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 5,
DC (dDVCC/dt < 1 V/s)
2.4
2.47
2.54
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 6,
DC (dDVCC/dt < 1 V/s)
2.7
2.79
2.88
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 7,
DC (dDVCC/dt < 1 V/s)
2.9
3.0
3.1
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 0,
DC (dDVCC/dt < 1 V/s)
1.6
1.66
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 1,
DC (dDVCC/dt < 1 V/s)
1.6
1.66
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 2,
DC (dDVCC/dt < 1 V/s)
1.6
1.66
1.71
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 3,
DC (dDVCC/dt < 1 V/s)
2.02
2.07
2.14
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 4,
DC (dDVCC/dt < 1 V/s)
2.22
2.27
2.34
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 5,
DC (dDVCC/dt < 1 V/s)
2.42
2.48
2.56
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 6,
DC (dDVCC/dt < 1 V/s)
2.72
2.8
2.9
SVSMHOFF = 0, SVSMHLP = 0, SVSMHTH = 7,
DC (dDVCC/dt < 1 V/s)
2.92
3.01
3.12
V
V
Specifications
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Table 5-22. PSS, SVSMH (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VSVSMH-,LP
VSVSMH_hys
tPD,SVSMH
t(SVSMH)
(1)
62
SVSMH threshold level, lowpower mode (falling DVCC)
MIN
TYP
MAX
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 0,
DC (dDVCC/dt < 1 V/s)
TEST CONDITIONS
1.55
1.62
1.71
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 1,
DC (dDVCC/dt < 1 V/s)
1.55
1.62
1.71
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 2,
DC (dDVCC/dt < 1 V/s)
1.55
1.62
1.71
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 3,
DC (dDVCC/dt < 1 V/s)
2.0
2.09
2.18
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 4,
DC (dDVCC/dt < 1 V/s)
2.2
2.3
2.4
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 5,
DC (dDVCC/dt < 1 V/s)
2.4
2.51
2.62
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 6,
DC (dDVCC/dt < 1 V/s)
2.7
2.83
2.94
SVSMHOFF = 0, SVSMHLP = 1, SVSMHTH = 7,
DC (dDVCC/dt < 1 V/s)
2.87
3.0
3.13
15
30
SVSMH hysteresis
UNIT
V
SVSH propagation delay,
high-performance mode
SVSMHOFF = 0, SVSMHLP = 0,
very fast dVDVCC/dt
3
10
SVSH propagation delay, lowpower mode
SVSMHOFF = 0, SVSMHLP = 1,
very fast dVDVCC/dt
25
100
SVSMH on or off delay time
SVSMHOFF = 1 → 0, SVSMHLP = 0
17
40
mV
μs
(1)
μs
If the SVSMH is disabled in active mode and is enabled before entering a low-power mode of the device (LPM3, LPM4, LPM3.5, or
LPM4.5) ensure that sufficient time has elapsed since enabling of the module before entry into the device low-power mode to allow for
successful wake up of the SVSMH module according to the the SVSMH on or off delay time specification. Otherwise, SVSMH may trip,
causing the device to reset and wake up from the low-power mode.
Specifications
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5.26.6 Digital I/Os
Table 5-23 lists the characteristics of the digital inputs.
Table 5-23. Digital Inputs (Applies to Both Normal and High-Drive I/Os)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
2.2 V
0.99
TYP
MAX
1.65
3V
1.35
2.25
2.2 V
0.55
1.21
3V
0.75
1.65
2.2 V
0.32
0.84
3V
0.4
1.0
UNIT
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS,
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
11
pF
CI,ana
Input capacitance, port pins shared with
analog functions
VIN = VSS or VCC
11
pF
Ilkg,ndio
Normal I/O high-impedance input leakage
current
See
(1) (2)
2.2 V, 3 V
±20
nA
Ilkg,hdio
High-drive I/O high-impedance input leakage
current
See
(1) (2)
2.2 V, 3 V
±20
nA
tint
tRST
(1)
(2)
(3)
(4)
(5)
External interrupt timing (external trigger
pulse duration to set interrupt flag)
External reset pulse duration on RSTn pin (5)
20
Ports with interrupt capability and
without glitch filter (3)
2.2 V, 3 V
20
Ports with interrupt capability and
with glitch filter, glitch filter disabled
(GLTFLT_EN = 0) (3)
2.2 V, 3 V
20
Ports with interrupt capability and
with glitch filter, glitch filter enabled
(GLTFTL_EN = 1) (4)
2.2 V, 3 V
0.25
2.2 V, 3 V
1
30
40
V
V
V
kΩ
ns
1
µs
µs
The input leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The input leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration tint is met. It may be set by trigger signals
shorter than tint.
A trigger pulse duration less than the MIN value is always filtered, and a trigger pulse duration more than the MAX value is always
passed. The trigger pulse may or may not be filtered if the duration is between the MIN and MAX values.
Not applicable if RSTn/NMI pin configured as NMI.
Specifications
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Table 5-24 lists the characteristics of the normal-drive digital outputs. See Figure 5-19, Figure 5-20,
Figure 5-21, and Figure 5-22 for the typical characteristics graphs.
Table 5-24. Digital Outputs, Normal I/Os
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
I(OHmax) = –1 mA (1)
VOH
High-level output voltage
2.2 V
I(OHmax) = –3 mA (2)
I(OHmax) = –2 mA (1)
3.0 V
I(OHmax) = –6 mA (2)
I(OLmax) = 1 mA (1)
VOL
Low-level output voltage
2.2 V
I(OLmax) = 3 mA (2)
I(OLmax) = 2 mA (1)
3.0 V
I(OLmax) = 6 mA (2)
Port output frequency (with RC
load) (3)
fPx.y
Port output duty cycle (with RC
Load)
dPx.y
fPort_CLK
dPort_CLK
trise,dig
tfall,dig
trise,ana
tfall,ana
(1)
(2)
(3)
(4)
(5)
(6)
(7)
64
Clock output frequency (3)
Clock output duty cycle
Port output rise time, digital only
port pins
Port output fall time, digital only
port pins
Port output rise time, port pins
with shared analog functions
Port output fall time, port pins
with shared analog functions
VCORE = 1.4 V, CL = 20 pF, RL
VCORE = 1.4 V, CL = 20 pF, RL
VCORE = 1.4 V, CL = 20 pF (5)
VCORE = 1.4 V, CL = 20 pF
CL = 20 pF
CL = 20 pF
CL = 20 pF
CL = 20 pF
(6)
(7)
(6)
(7)
(5)
(4) (5)
(4) (5)
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.60
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.60
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
40%
60%
2.2 V
40%
60%
3.0 V
45%
55%
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
40%
60%
2.2 V
40%
60%
3.0 V
45%
55%
UNIT
V
V
MHz
MHz
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
ns
ns
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit - it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 3.2 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 20 pF is connected to the output to VSS.
The output voltage reaches at least 20% and 80% VCC at the specified toggle frequency.
Measured from 20% of VCC to 80% of VCC.
Measured from 80% of VCC to 20% of VCC.
Specifications
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Table 5-25 lists the characteristics of the high-drive digital outputs. See Figure 5-23, Figure 5-24, Figure 525, and Figure 5-26 for the typical characteristics graphs.
Table 5-25. Digital Outputs, High-Drive I/Os
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
I(OHmax) = –5 mA (1)
VOH
2.2 V
I(OHmax) = –15 mA (2)
High-level output voltage
I(OHmax) = –10 mA (1)
3.0 V
I(OHmax) = –20 mA (2)
I(OLmax) = 5 mA (1)
VOL
2.2 V
I(OLmax) = 15 mA (2)
Low-level output voltage
I(OLmax) = 10 mA (1)
3.0 V
I(OLmax) = 20 mA (2)
Port output frequency (with RC
load) (3)
fPx.y
Port output duty cycle (with RC
Load)
dPx.y
fPort_CLK
dPort_CLK
trise
(2)
(3)
(4)
(5)
(6)
(7)
Clock output duty cycle
Port output rise time
tfall
(1)
Clock output frequency (3)
Port output fall time
VCORE = 1.4 V, CL = 80 pF, RL
VCORE = 1.4 V, CL = 80 pF, RL
(4) (5)
(4) (5)
VCORE = 1.4 V, CL = 80 pF (5)
VCORE = 1.4 V, CL = 80 pF
CL = 80 pF
CL = 80 pF
(5)
(6)
(7)
MIN
MAX
VCC – 0.25
VCC
VCC – 0.60
VCC
VCC – 0.25
VCC
VCC – 0.50
VCC
VSS
VSS + 0.25
VSS
VSS + 0.60
VSS
VSS + 0.25
VSS
VSS + 0.50
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
45%
55%
2.2 V
45%
55%
3.0 V
45%
55%
1.62 V
24
2.2 V
24
3.0 V
24
1.62 V
45%
55%
2.2 V
45%
55%
3.0 V
45%
55%
UNIT
V
V
MHz
MHz
1.62 V
8
2.2 V
5
3.0 V
3
1.62 V
8
2.2 V
5
3.0 V
3
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
The port can output frequencies at least up to the specified limit, and it might support higher frequencies.
A resistive divider with 2 × R1 and R1 = 3.2 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the
divider. CL = 80 pF is connected to the output to VSS.
The output voltage reaches at least 20% and 80% VCC at the specified toggle frequency.
Measured from 20% of VCC to 80% of VCC.
Measured from 80% of VCC to 20% of VCC.
Table 5-26 lists the frequencies of the pin-oscillator ports. See Figure 5-27 and Figure 5-28 for the typical
characteristics graphs.
Table 5-26. Pin-Oscillator Frequency, Ports Px
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
foPx.y
(1)
Pin-oscillator frequency
TEST CONDITIONS
VCC
MIN
TYP
Px.y, CL = 10 pF (1)
3.0 V
1900
Px.y, CL = 20 pF (1)
3.0 V
1150
MAX
UNIT
kHz
CL is the external load capacitance connected from the output to VSS and includes all parasitic effects such as PCB traces.
Specifications
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18
30
16
27
Low-Level Output Current (mA)
Low-Level Output Current (mA)
5.26.6.1 Typical Characteristics, Normal-Drive I/O Outputs at 3.0 V and 2.2 V
14
12
10
8
6
4
2
TA = 25°C
TA = 85°C
0
24
21
18
15
12
9
6
3
TA = 25°C
TA = 85°C
0
-2
-3
0
0.25
0.5
0.75
1
1.25 1.5 1.75
Low-Level Output Voltage (V)
VCC = 2.2 V
2
2.25
0
P7.0
0.9 1.2 1.5 1.8 2.1 2.4
Low-Level Output Voltage (V)
2.7
3
D010
P7.0
Figure 5-20. Low-Level Output Voltage vs
Low-Level Output Current
0
0
TA = 25°C
TA = 85°C
-2
-4
-6
-8
-10
-12
-14
-6
-9
-12
-15
-18
-21
-24
-27
-16
-30
-18
-33
0
0.25
0.5
VCC = 2.2 V
0.75
1
1.25 1.5 1.75
High-Level Output Voltage (V)
2
P7.0
Figure 5-21. High-Level Output Voltage vs
High-Level Output Current
Specifications
TA = 25°C
TA = 85°C
-3
High-Level Output Current (mA)
High-Level Output Current (mA)
0.6
VCC = 3.0 V
Figure 5-19. Low-Level Output Voltage vs
Low-Level Output Current
66
0.3
D006
2.25
0
0.3
0.6
D004
VCC = 3.0 V
0.9 1.2 1.5 1.8 2.1 2.4
High-Level Output Voltage (V)
2.7
3
D008
P7.0
Figure 5-22. High-Level Output Voltage vs
High-Level Output Current
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5.26.6.2 Typical Characteristics, High-Drive I/O Outputs at 3.0 V and 2.2 V
160
100
Low-Level Output Current (mA)
Low-Level Output Current (mA)
90
80
70
60
50
40
30
20
10
TA = 25°C
TA = 85°C
0
-10
140
120
100
80
60
40
20
TA = 25°C
TA = 85°C
0
0
0.25
0.5
0.75
1
1.25 1.5 1.75
Low-Level Output Voltage (V)
VCC = 2.2 V
2
2.25
0
P2.1
0.6
0.9 1.2 1.5 1.8 2.1 2.4
Low-Level Output Voltage (V)
VCC = 3.0 V
Figure 5-23. Low-Level Output Voltage vs
Low-Level Output Current
2.7
3
D009
P2.1
Figure 5-24. Low-Level Output Voltage vs
Low-Level Output Current
0
-5
TA = 25°C
TA = 85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
0.3
D005
-15
-25
-35
-45
-55
-65
-75
-85
0
0.25
0.5
VCC = 2.2 V
0.75
1
1.25 1.5 1.75
High-Level Output Voltage (V)
2
P2.1
Figure 5-25. High-Level Output Voltage vs
High-Level Output Current
2.25
TA = 25°C
TA = 85°C
-20
-40
-60
-80
-100
-120
-140
-160
0
0.3
0.6
D003
VCC = 3.0 V
0.9 1.2 1.5 1.8 2.1 2.4
High-Level Output Voltage (V)
2.7
D007
P2.1
Figure 5-26. High-Level Output Voltage vs
High-Level Output Current
Specifications
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5.26.6.3 Typical Characteristics, Pin-Oscillator Frequency
1750
TA = 25°C
TA = 85°C
1800
Pin Oscillator Frequency (kHz)
Pin Oscillator Frequency (kHz)
2100
1500
1200
900
600
300
10
20
30
40
50
Load Capacitance (pF)
One output active at a time
60 70 80
100
D002
VCC = 3.0 V
Figure 5-27. Load Capacitance vs Pin Oscillator Frequency
68
Specifications
TA = 25°C
TA = 85°C
1500
1250
1000
750
500
250
10
20
30
40
50
Load Capacitance (pF)
One output active at a time
60 70 80
100
D001
VCC = 2.2 V
Figure 5-28. Load Capacitance vs Pin Oscillator Frequency
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.26.7 Precision ADC
Table 5-27 lists the power supply and input range conditions for the ADC.
Table 5-27. Precision ADC Power Supply and Input Range Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
NOM
MAX
UNIT
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V,
ADC14PWRMD = 2
1.62
3.7
V
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V,
ADC14PWRMD = 0
1.8
3.7
V
V(Ax)
Analog input voltage
range (1)
All ADC analog input pins Ax
0
AVCC
V
VCM
Input common-mode range
All ADC analog input pins Ax (ADC14DIF = 1)
0
VREF /
2
VREF
V
I(ADC14)
single-ended
mode
I(ADC14)
differential
mode
CI
RI
(1)
(2)
(3)
Operating supply current
into AVCC plus DVCC
terminal (2)
Operating supply current
into AVCC plus DVCC
terminal (2)
fADC14CLK = 25 MHz,
1 Msps (ADC14PWRMD = 0),
ADC14ON = 1, ADC14DIF = 0,
ADC14VRSEL = 0xE, REFON = 0,
ADC14SHT0x = 0x0, ADC14SHT1x = 0x0
3.0 V
490
640
2.2 V
450
580
fADC14CLK = 5 MHz,
200 ksps (ADC14PWRMD = 2),
ADC14ON = 1, ADC14DIF = 0,
ADC14VRSEL = 0xE, REFON = 0,
ADC14SHT0x = 0x0, ADC14SHT1x = 0x0
3.0 V
215
270
2.2 V
210
260
fADC14CLK = 25 MHz,
1 Msps (ADC14PWRMD = 0),
ADC14ON = 1, ADC14DIF = 1,
ADC14VRSEL = 0xE, REFON = 0,
ADC14SHT0x = 0x0, ADC14SHT1x = 0x0
3.0 V
690
875
2.2 V
620
785
fADC14CLK = 5 MHz,
200 ksps (ADC14PWRMD = 2),
ADC14ON = 1, ADC14DIF = 1,
ADC14VRSEL = 0xE, REFON = 0,
ADC14SHT0x = 0x0, ADC14SHT1x = 0x0
3.0 V
275
335
2.2 V
260
320
12
15
1.8 V to
3.7 V
0.135
1
1.62 V to
<1.8 V
0.15
1.5
Input capacitance into a
single terminal (3)
Input MUX ON-resistance
0 V ≤ V(Ax)≤ AVCC
µA
µA
pF
kΩ
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter I(ADC14).
Represents only the ADC switching capacitance. See the digital inputs electrical specification for internal parasitic pin capacitance.
Specifications
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Table 5-28 lists the timing parameters of the ADC.
Table 5-28. Precision ADC Timing Parameters
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ADC clock frequency (1)
fADC14CLK
ADC14PWRMD = 2
1.62 V to 3.7 V
0.128
5.75
ADC14RES = 11
16
ADC14RES = 10
14
ADC14RES = 01
11
ADC14RES = 00
9
Turnon settling time of ADC
See
Sampling time (3)
RS = 200 Ω, Cpext = 10 pF,
RI = 1 kΩ, CI = 15 pF, Cpint = 5 pF
(3)
(4)
MAX
25
tADC14ON
(1)
(2)
TYP
0.128
Clock cycles for conversion
(4)
MIN
1.8 V to 3.7 V
NCONVERT
tSample
VCC
ADC14PWRMD = 0
(2)
UNIT
MHz
cycles
1.5
µs
0.215
µs
MODOSC can be used for 1 Msps and SYSOSC can be used for 200 ksps sampling rate operations of ADC.
The condition is that the error in a conversion started after tADC14ON is less than ±1 LSB. The reference and input signal are already
settled.
Sampling time should be at least 4 × (1 / fADC14CLK).
tsample ≥ (n + 1) × ln(2) × [(RS + RI) × CI + RS × (Cpext + Cpint)], where n = ADC resolution =14, RS = external source resistance, Cpext =
external parasitic capacitance.
Table 5-29 lists the linearity parameters of the ADC.
Table 5-29. Precision ADC Linearity Parameters (1) (2)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
Integral linearity error (INL)
ED
Differential linearity error
(DNL)
EO
Offset error
EG
Gain error
(1)
(2)
70
MAX
UNIT
±2.3
LSB
1
LSB
14
EI
ET
TYP
Total unadjusted error
–0.99
bits
ADC14VRSEL = 0xE, 0xF
±0.2
±1
ADC14VRSEL = 0x1
±1.2
±2
ADC14VRSEL = 0xE
±2
±4
ADC14VRSEL = 0xF
±20
±60
ADC14VRSEL = 0x1
±50
±180
ADC14VRSEL = 0xE
±4
±15
ADC14VRSEL = 0xF
±22
±62
ADC14VRSEL = 0x1
±55
±185
mV
LSB
LSB
Minimum reference voltage of 1.45 V is necessary to meet the specified accuracy. Lower reference voltage down to 1.2 V can be
applied for 1-Msps sampling rate with reduced accuracy requirements.
Connect the VeREF- pin to onboard ground for ADC14VRSEL = 0xE.
Specifications
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Table 5-30 lists the dynamic parameters of the ADC.
Table 5-30. Precision ADC Dynamic Parameters (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
SINAD (2)
Signal-to-noise and distortion
ENOB (2)
Effective number of bits
MIN
TYP
1 Msps, ADC14DIF = 0, ADC14VRSEL = 0xE,
2.5-V reference, 20-kHz input sine,
LDO based operation
TEST CONDITIONS
71
73
1 Msps, ADC14DIF = 0, ADC14VRSEL = 0xE,
2.5-V reference, 20-kHz input sine,
DC/DC based operation
62
70
1 Msps, ADC14DIF = 1, ADC14VRSEL = 0xE,
2.5-V reference, 20-kHz input sine
79
81
1 Msps, ADC14DIF = 0, ADC14VRSEL = 0xE,
2.5-V reference, 20-kHz input sine,
LDO based operation
11.5
11.8
1 Msps, ADC14DIF = 0, ADC14VRSEL = 0xE,
2.5-V reference, 20-kHz input sine,
DC/DC based operation
10
11.3
1 Msps, ADC14DIF = 1, ADC14VRSEL = 0xE,
2.5-V reference, 20-kHz input sine
12.8
13.2
MAX
UNIT
dB
bit
CMRR_DC
Common-mode rejection ratio, Common-mode input signal = 0 to VREF pp at DC,
DC
ADC14DIF = 1
70
85
dB
CMRR_AC
Common-mode rejection ratio, Common-mode input signal = 0 to VREF pp at
AC
1 MHz, ADC14DIF = 1
55
65
dB
PSRR_DC
Power supply rejection ratio,
DC
PSRR_AC
(1)
(2)
Power supply rejection ratio,
AC
AVCC = AVCC (min) to AVCC(max),
ADC14DIF = 0, ADC14VRSEL = 0xE
1
2.5
mV/V
AVCC = AVCC (min) to AVCC(max),
ADC14DIF = 1, ADC14VRSEL = 0xE
50
150
µV/V
dAVCC = 0.1 V at 1 kHz,
ADC14DIF = 0, ADC14VRSEL = 0xE
1
mV/V
dAVCC = 0.1 V at 1 kHz,
ADC14DIF = 1, ADC14VRSEL = 0xE
50
µV/V
VeREF- pin should be connected to onboard ground for ADC14VRSEL = 0xE.
ADC clock derived from HFXT oscillator.
Specifications
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Table 5-31 lists the characteristics of the temperature sensor and built-in V1/2.
Table 5-31. Precision ADC Temperature Sensor and Built-In V1/2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VSENSOR
Temperature sensor voltage (1)
(see Figure 5-29)
TCSENSOR
Change in voltage with
temperature (2)
ADC14ON = 1, ADC14TCMAP = 1
tSENSOR
Sample time required if ADCTCMAP
= 1 and channel (MAX – 1) is
selected (3)
ADC14ON = 1, ADC14TCMAP = 1,
Error of conversion result ≤ 1 LSB
V1/2
AVCC voltage divider for
ADC14BATMAP = 1 on MAX input
channel
ADC14ON = 1, ADC14BATMAP = 1
tV 1/2
Sample time required if
ADC14BATMAP = 1 and channel
MAX is selected (4)
ADC14ON = 1, ADC14BMAP = 1
(sample)
(sample)
(1)
(2)
(3)
(4)
(2)
VCC
MIN
TYP
MAX
UNIT
ADC14ON = 1, ADC14TCMAP = 1,
TA = 0°C
685
mV
1.9
mV/°C
5
48%
µs
50%
52%
1
µs
The temperature sensor offset can be as much as ±35°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
The TLV structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage levels. The
sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature,°C) + VSENSOR, where TCSENSOR and VSENSOR can be
computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 250 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
The on-time tV1/2 (on) is included in the sampling time tV1/2 (sample). No additional on time is needed.
875
Typical Temperature Sensor Voltage (mV)
850
825
800
775
750
725
700
675
650
625
600
-40
-20
0
20
40
60
Ambient Temperature (°C)
80
100
D020
Figure 5-29. Typical Temperature Sensor Voltage
72
Specifications
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Table 5-32 lists the characteristics of the internal reference buffers of the ADC.
Table 5-32. Precision ADC Internal Reference Buffers
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
ADC ON, REFOUT = 0, ADC14PWRMD = 0,
REFVSEL = {0, 1, 3}
Operating supply current into
AVCC terminal (1)
IREF+
ADC ON, REFOUT = 0, ADC14PWRMD = 2,
REFVSEL = {0, 1, 3}
3V
ADC ON, REFOUT = 1, ADC14PWRMD = 2,
REFVSEL = {0, 1, 3}
ton
(1)
Turnon time
TYP
MAX
600
800
200
300
650
850
3V
UNIT
µA
5
µs
MAX
UNIT
AVCC
V
0
V
AVCC
V
The internal reference current is supplied through terminal AVCC.
Table 5-33 lists the characteristics of the ADC external reference.
Table 5-33. Precision ADC External Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VeREF+
Positive external reference voltage
input (1)
VeREF–
Negative external reference voltage
input
(VeREF+ VeREF–)
Differential external reference voltage
input (1)
IVeREF+
IVeREF–
IVeREF+
IVeREF–
CVeREF+
(1)
(2)
Static input current in single ended
input mode
TEST CONDITIONS
MIN
1.45
1.45
1.45 V ≤ VeREF+≤ VAVCC, VeREF– = 0 V,
fADC14CLK = 25 MHz, ADC14SHT0x = 0x1,
ADC14SHT1x = 0x1, ADC14DIF = 0
±75
1.45 V ≤ VeREF+≤ VAVCC, VeREF– = 0 V,
fADC14CLK = 5 MHz, ADC14SHT0x = 0x1,
ADC14SHT1x = 0x1, ADC14DIF = 0
±15
µA
1.45 V ≤ VeREF+≤ VAVCC, VeREF– = 0 V,
fADC14CLK = 25 MHz, ADC14SHT0x = 0x1,
Static input current in differential input ADC14SHT1x = 0x1, ADC14DIF = 1
mode
1.45 V ≤ VeREF+≤ VAVCC, VeREF– = 0 V
fADC14CLK = 5 MHz, ADC14SHT0x = 0x1,
ADC14SHT1x = 0x1, ADC14DIF = 1
Capacitance at VeREF+ terminal
TYP
See
(2)
±150
µA
±30
5
µF
Lower reference voltage down to 1.2 V can be applied for 1-Msps sampling rate with reduced accuracy requirements of linearity
parameters.
Connect two decoupling capacitors, 5 µF and 50 nF, to the VeREF+ terminal to decouple the dynamic current required for an external
reference source if it is used for the Precision ADC.
Specifications
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5.26.7.1 Typical Characteristics of ADC
typical characteristics at 3 V, 25°C, and 1-Msps sampling rate of ADC (unless otherwise specified)
Table 5-34 lists the ADC typical characteristics graphs.
Table 5-34. ADC Typical Characteristics Graphs
TITLE
TEST CONDITIONS
FIGURE
VRSEL = 14, VREF = 2.5 V, Resolution = 14 Bit, ADC14PWRMD = 0
Figure 5-30
VRSEL = 14, VREF = 2.5 V, Resolution = 12 Bit, ADC14PWRMD = 2
Figure 5-31
VRSEL = 1, VREF = 2.5 V, REFOUT = 0, ADC14PWRMD = 0, Resolution = 14 Bit
Figure 5-32
VRSEL = 1, VREF = 2.5 V, REFOUT = 0, ADC14PWRMD = 2, Resolution = 12 Bit
Figure 5-33
VRSEL = 1, VREF = 2.5 V, REFOUT = 1, ADC14PWRMD = 2, Resolution = 12 Bit
Figure 5-34
VRSEL = 1, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-35
VRSEL = 1, VREF = 2.5 V, Input Mode = Differential
Figure 5-36
VRSEL = 14, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-37
VRSEL = 14, VREF = 2.5 V, Input Mode = Differential
Figure 5-38
VRSEL = 15, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-39
VRSEL = 15, VREF = 2.5 V, Input Mode = Differential
Figure 5-40
VRSEL = 1, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-41
VRSEL = 1, VREF = 2.5 V, Input Mode = Differential
Figure 5-42
VRSEL = 14, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-43
VRSEL = 14, VREF = 2.5 V, Input Mode = Differential
Figure 5-44
VRSEL = 15, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-45
VRSEL = 15, VREF = 2.5 V, Input Mode = Differential
Figure 5-46
fin = 20 kHz, VRSEL = 1, VREF = 2.5 V, SINAD = 69 dB,
THD = –86 dB, Input Mode = Single Ended
Figure 5-47
fin = 20 kHz, VRSEL = 1, VREF = 2.5 V, SINAD = 74 dB,
THD = –91 dB, Input Mode = Differential
Figure 5-48
fin = 20 kHz, VRSEL = 14, VREF = 2.5 V, SINAD = 73 dB,
THD = –92 dB, Input Mode = Single Ended
Figure 5-49
fin = 20 kHz, VRSEL = 14, VREF = 2.5 V, SINAD = 82 dB,
THD = –100 dB, Input Mode = Differential
Figure 5-50
fin = 20 kHz, VRSEL = 15, VREF = 2.5 V, SINAD = 72 dB,
THD = –90 dB, Input Mode = Single Ended
Figure 5-51
fin = 20 kHz, VRSEL = 15, VREF = 2.5 V, SINAD = 80 dB,
THD = –100 dB, Input Mode = Differential
Figure 5-52
SINAD vs Reference Voltage
fin = 20 kHz, VRSEL = 14
Figure 5-53
ENOB vs Reference Voltage
fin = 20 kHz, VRSEL = 14
Figure 5-54
THD vs Reference Voltage
fin = 20 kHz, VRSEL = 14
Figure 5-55
SFDR vs Reference Voltage
fin = 20 kHz, VRSEL = 14
Figure 5-56
SINAD vs Temperature
fin = 20 kHz, VRSEL = 14
Figure 5-57
ENOB vs Temperature
fin = 20 kHz, VRSEL = 14
Figure 5-58
THD vs Temperature
fin = 20 kHz, VRSEL = 14
Figure 5-59
SFDR vs Temperature
fin = 20 kHz, VRSEL = 14
Figure 5-60
VRSEL = 14, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-61
VRSEL = 14, VREF = 2.5 V, Input Mode = Differential
Figure 5-62
VRSEL = 14, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-63
VRSEL = 14, VREF = 2.5 V, Input Mode = Differential
Figure 5-64
VRSEL = 14, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-65
VRSEL = 14, VREF = 2.5 V, Input Mode = Differential
Figure 5-66
VRSEL = 14, VREF = 2.5 V, Input Mode = Single Ended
Figure 5-67
VRSEL = 14, VREF = 2.5 V, Input Mode = Differential
Figure 5-68
Current vs Sampling Rate
INL vs ADC Output Code
DNL vs ADC Output Code
Power vs Input Frequency
INL vs Temperature
DNL vs Temperature
Offset Voltage vs Temperature
Gain Error vs Temperature
74
Specifications
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800
300
Single Ended
Differential Ended
700
250
Current (µA)
600
Current (µA)
Single Ended
Differential Ended
500
400
200
150
100
300
50
200
100
0
0
200
400
600
800
Sampling Rate (ksps)
VRSEL = 14
Resolution = 14 Bit
1000
1200
0
20
40
60
D050
VREF = 2.5 V
ADC14PWRMD = 0
80 100 120 140 160 180 200 220
Sampling Rate (ksps)
D051
VRSEL = 14
Resolution = 12 Bit
Figure 5-30. Current vs Sampling Rate
VREF = 2.5 V
ADC14PWRMD = 2
Figure 5-31. Current vs Sampling Rate
1400
600
Single Ended
Differential Ended
1300
Single Ended
Differential Ended
550
1100
Current (µA)
Current (µA)
1200
1000
900
500
450
400
800
350
700
600
300
0
200
400
600
800
Sampling Rate (ksps)
VRSEL = 1
REFOUT = 0
Resolution = 14 Bit
1000
1200
0
20
D052
VREF = 2.5 V
ADC14PWRMD = 0
Figure 5-32. Current vs Sampling Rate
40
60
80 100 120 140 160 180 200 220
Sampling Rate (ksps)
D053
VRSEL = 1
REFOUT = 0
Resolution = 12 Bit
VREF = 2.5 V
ADC14PWRMD = 2
Figure 5-33. Current vs Sampling Rate
1050
Single Ended
Differential Ended
Current (µA)
1000
950
900
850
800
750
0
20
40
60
80 100 120 140 160 180 200 220
Sampling Rate (ksps)
D054
VRSEL = 1
REFOUT = 1
Resolution = 12 Bit
VREF = 2.5 V
ADC14PWRMD = 2
Figure 5-34. Current vs Sampling Rate
Specifications
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2
2
1.5
1.5
Typical Integral Nonlinearilty (LSB)
Typical Integral Nonlinearilty (LSB)
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
1
0.5
0
-0.5
-1
-1.5
-2
1
0.5
0
-0.5
-1
-1.5
-2
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D055
VRSEL = 1
Input Mode = Single Ended
0
VREF = 2.5 V
1.5
1.5
Typical Integral Nonlinearilty (LSB)
Typical Integral Nonlinearilty (LSB)
2
0
-0.5
-1
-1.5
-2
2048
4096
1
0.5
0
-0.5
-1
-1.5
6144 8192 10240 12288 14336 16384
ADC Output Code
D057
VRSEL = 14
Input Mode = Single Ended
0
VREF = 2.5 V
1.5
1.5
Typical Integral Nonlinearilty (LSB)
2
0.5
0
-0.5
-1
-1.5
-2
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D058
VREF = 2.5 V
Figure 5-38. INL vs ADC Output Code
2
1
2048
VRSEL = 14
Input Mode = Differential
Figure 5-37. INL vs ADC Output Code
Typical Integral Nonlinearilty (LSB)
VREF = 2.5 V
-2
0
1
0.5
0
-0.5
-1
-1.5
-2
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D059
VRSEL = 15
Input Mode = Single Ended
VREF = 2.5 V
Figure 5-39. INL vs ADC Output Code
76
6144 8192 10240 12288 14336 16384
ADC Output Code
D056
Figure 5-36. INL vs ADC Output Code
2
0.5
4096
VRSEL = 1
Input Mode = Differential
Figure 5-35. INL vs ADC Output Code
1
2048
Specifications
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D060
VRSEL = 15
Input Mode = Differential
VREF = 2.5 V
Figure 5-40. INL vs ADC Output Code
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
1
Typical Differential Nonlinearilty (LSB)
Typical Differential Nonlinearilty (LSB)
1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D061
VRSEL = 1
Input Mode = Single Ended
0
VREF = 2.5 V
6144 8192 10240 12288 14336 16384
ADC Output Code
D062
VREF = 2.5 V
Figure 5-42. DNL vs ADC Output Code
1
1
Typical Differential Nonlinearilty (LSB)
Typical Differential Nonlinearilty (LSB)
4096
VRSEL = 1
Input Mode = Differential
Figure 5-41. DNL vs ADC Output Code
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D063
VRSEL = 14
Input Mode = Single Ended
0
VREF = 2.5 V
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D064
VRSEL = 14
Input Mode = Differential
Figure 5-43. DNL vs ADC Output Code
VREF = 2.5 V
Figure 5-44. DNL vs ADC Output Code
1
Typical Differential Nonlinearilty (LSB)
1
Typical Differential Nonlinearilty (LSB)
2048
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D065
VRSEL = 15
Input Mode = Single Ended
VREF = 2.5 V
Figure 5-45. DNL vs ADC Output Code
0
2048
4096
6144 8192 10240 12288 14336 16384
ADC Output Code
D066
VRSEL = 15
Input Mode = Differential
VREF = 2.5 V
Figure 5-46. DNL vs ADC Output Code
Specifications
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20
20
0
0
-20
-20
-40
-40
Power (dB)
Power (dB)
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
-60
-80
-60
-80
-100
-100
-120
-120
-140
-140
-160
-160
0
50
0
100 150 200 250 300 350 400 450 500 550
Input Frequency (kHz)
D067
fin = 20 kHz
VREF = 2.5 V
THD = –86 dB
VRSEL = 1
SINAD = 69 dB
Input Mode = Single Ended
20
0
0
-20
-20
-40
-40
Power (dB)
Power (dB)
VRSEL = 1
SINAD = 74 dB
Input Mode = Differential
Figure 5-48. Power vs Input Frequency
20
-60
-80
-100
-60
-80
-100
-120
-140
-120
-160
-140
-180
-160
0
50
100 150 200 250 300 350 400 450 500 550
Input Frequency (kHz)
D069
fin = 20 kHz
VREF = 2.5 V
THD = –92 dB
0
50
VRSEL = 14
SINAD = 73 dB
Input Mode = Single Ended
0
0
-20
-20
-40
-40
Power (dB)
20
-80
VRSEL = 14
SINAD = 82 dB
Input Mode = Differential
Figure 5-50. Power vs Input Frequency
20
-60
100 150 200 250 300 350 400 450 500 550
Input Frequency (kHz)
D070
fin = 20 kHz
VREF = 2.5 V
THD = –100 dB
Figure 5-49. Power vs Input Frequency
Power (dB)
100 150 200 250 300 350 400 450 500 550
Input Frequency (kHz)
D068
fin = 20 kHz
VREF = 2.5 V
THD = –91 dB
Figure 5-47. Power vs Input Frequency
-60
-80
-100
-100
-120
-120
-140
-140
-160
-160
0
50
100 150 200 250 300 350 400 450 500 550
Input Frequency (kHz)
D071
fin = 20 kHz
VREF = 2.5 V
THD = –90 dB
VRSEL = 15
SINAD = 72 dB
Input Mode = Single Ended
Figure 5-51. Power vs Input Frequency
78
50
Specifications
0
50
100 150 200 250 300 350 400 450 500 550
Input Frequency (kHz)
D072
fin = 20 kHz
VREF = 2.5 V
THD = –100 dB
VRSEL = 15
SINAD = 80 dB
Input Mode = Differential
Figure 5-52. Power vs Input Frequency
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
15
Single Ended
Differential Ended
85
Single Ended
Differential Ended
14
Effective Number of Bits
Signal-to-Noise and Distortion (dBFS)
90
80
75
70
13
12
11
10
65
9
60
1
1.25
1.5
1.75
2
2.25
Reference Voltage (V)
fin = 20 kHz
2.5
1
2.75
VRSEL = 14
1.5
1.75
2
2.25
Reference Voltage (V)
fin = 20 kHz
Figure 5-53. SINAD vs Reference Voltage
2.5
2.75
D074
VRSEL = 14
Figure 5-54. ENOB vs Reference Voltage
-80
120
Single Ended
Differential Ended
-85
Spurious-Free Dynamic Range (dBFS)
Total Harmonic Distortion (dBFS)
1.25
D073
-90
-95
-100
-105
-110
Single Ended
Differential Ended
115
110
105
100
95
90
85
80
1
1.25
1.5
1.75
2
2.25
Reference Voltage (V)
fin = 20 kHz
2.5
2.75
D075
VRSEL = 14
Figure 5-55. THD vs Reference Voltage
1
1.25
1.5
1.75
2
2.25
Reference Voltage (V)
fin = 20 kHz
2.5
2.75
D076
VRSEL = 14
Figure 5-56. SFDR vs Reference Voltage
Specifications
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16
Single Ended
Differential Ended
87
Single Ended
Differential Ended
15
Effective Number of Bits
Signal-to-Noise and Distortion (dBFS)
90
84
81
78
75
72
14
13
12
11
69
66
-60
-40
-20
0
20
40
Temperature (°C)
fin = 20 kHz
60
80
10
-60
100
VRSEL = 14
VREF = 2.5 V
0
20
40
Temperature (°C)
60
80
100
D078
VRSEL = 14
VREF = 2.5 V
Figure 5-58. ENOB vs Temperature
-80
120
Single Ended
Differential Ended
-83
Spurious-Free Dynamic Range (dBFS)
Total Harmonic Distortion (dBFS)
-20
fin = 20 kHz
Figure 5-57. SINAD vs Temperature
-86
-89
-92
-95
-98
-101
-104
-107
-110
-60
-40
fin = 20 kHz
-20
0
20
40
Temperature (°C)
60
VRSEL = 14
Figure 5-59. THD vs Temperature
80
-40
D077
Specifications
80
100
Single Ended
Differential Ended
115
110
105
100
95
90
85
80
-60
-40
-20
D079
VREF = 2.5 V
fin = 20 kHz
0
20
40
Temperature (°C)
60
VRSEL = 14
80
100
D080
VREF = 2.5 V
Figure 5-60. SFDR vs Temperature
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
2
2
Maximum INL
Minimum INL
1.5
Integral Nonlinearity (LSB)
Integral Nonlinearity (LSB)
1.5
1
0.5
0
-0.5
-1
-1.5
1
0.5
0
-0.5
-1
-1.5
-2
-60
-40
-20
0
20
40
Temperature (°C)
60
80
-2
-60
100
-40
-20
D081
VRSEL = 14
Input Mode = Single Ended
VREF = 2.5 V
0
20
40
Temperature (°C)
60
80
100
D082
VRSEL = 14
Input Mode = Differential
Figure 5-61. INL vs Temperature
VREF = 2.5 V
Figure 5-62. INL vs Temperature
1
1
Maximum DNL
Minimum DNL
0.8
Differential Nonlinearity (LSB)
0.8
Differential Nonlinearity (LSB)
Maximum INL
Minimum INL
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
Maximum DNL
Minimum DNL
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1
-60
-40
-20
0
20
40
Temperature (°C)
60
VRSEL = 14
Input Mode = Single Ended
Figure 5-63. DNL vs Temperature
80
100
D083
VREF = 2.5 V
-1
-60
-40
-20
0
20
40
Temperature (°C)
60
VRSEL = 14
Input Mode = Differential
80
100
D084
VREF = 2.5 V
Figure 5-64. DNL vs Temperature
Specifications
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0.5
0.5
0.4
0.4
0.3
0.3
Offset Voltage (mV)
Offset Voltage (mV)
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
0.2
0.1
0
-0.1
-0.2
0.2
0.1
0
-0.1
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
-60
-40
-20
0
20
40
Temperature (°C)
60
80
-0.5
-60
100
VRSEL = 14
Input Mode = Single Ended
VREF = 2.5 V
3
3
2
2
Gain Error (LSB)
Gain Error (LSB)
4
1
0
-1
-3
VRSEL = 14
Input Mode = Single Ended
80
82
Specifications
100
D087
VREF = 2.5 V
Figure 5-67. Gain Error vs Temperature
100
D086
VREF = 2.5 V
-1
-3
60
80
0
-2
0
20
40
Temperature (°C)
60
1
-2
-20
0
20
40
Temperature (°C)
Figure 5-66. Offset Voltage vs Temperature
4
-40
-20
VRSEL = 14
Input Mode = Differential
Figure 5-65. Offset Voltage vs Temperature
-4
-60
-40
D085
-4
-60
-40
-20
0
20
40
Temperature (°C)
VRSEL = 14
Input Mode = Differential
60
80
100
D088
VREF = 2.5 V
Figure 5-68. Gain Error vs Temperature
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
5.26.8 REF_A
Table 5-35 lists the characteristics of the REF_A built-in reference.
Table 5-35. REF_A, Built-In Reference (LDO Operation)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Positive built-in reference
voltage output
VREF+
TYP
MAX
REFVSEL = {0} for 1.2 V, REFON = 1
TEST CONDITIONS
1.62 V
VCC
MIN
1.2
±1%
REFVSEL = {1} for 1.45 V, REFON = 1
1.75 V
1.45
±1%
REFVSEL = {3} for 2.5 V, REFON = 1
2.8 V
2.5
±1%
REFVSEL = {0} for 1.2 V
1.62
REFVSEL = {1} for 1.45 V
1.75
REFVSEL = {3} for 2.5 V
2.8
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
IREF+
Operating supply current into
AVCC terminal (1)
IO(VREF+)
REFVSEL = {0, 1, 3},
VREF maximum load current,
AVCC = AVCC (min) for each reference level,
VREF+ terminal
REFON = REFOUT = 1
IL(VREF+)
Load-current regulation,
VREF+ terminal
REFVSEL = {0, 1, 3},
I(VREF+) = +10 µA or –1000 µA,
AVCC = AVCC (min) for each reference level,
REFON = REFOUT = 1
CVREF±
Capacitance at VREF+,
VREF- terminals
REFON = REFOUT = 1
REFON = 1
3V
UNIT
V
V
15
–1000
20
µA
+10
µA
2500 µV/mA
0
100
pF
PSRR_DC Power supply rejection ratio
(DC) after ADC buffer
REFOUT0
AVCC = AVCC (min) for each reference level,
REFVSEL = {0, 1, 3}, REFON = 1,
REFOUT = 0
50
350
µV/V
PSRR_DC Power supply rejection ratio
(DC) after ADC buffer
REFOUT1
AVCC = AVCC (min) for each reference level,
REFVSEL = {0, 1, 3}, REFON = 1,
REFOUT = 1
50
250
µV/V
PSRR_AC Power supply rejection ratio
(AC) after ADC buffer
REFOUT0
AVCC = AVCC (min) for each reference level,
dAVCC = 0.1 V at 1 kHz,
REFVSEL = {0, 1, 3}, REFON = 1,
REFOUT = 0
2
10
mV/V
PSRR_AC Power supply rejection ratio
(AC) after ADC buffer
REFOUT1
AVCC = AVCC (min) for each reference level,
dAVCC = 0.1 V at 1 kHz,
REFVSEL = {0, 1, 3}, REFON = 1,
REFOUT = 1
2
5
mV/V
TCREF+
tSETTLE
(1)
(2)
(3)
(2)
Temperature coefficient of
built-in reference
REFVSEL = {0, 1, 3}, REFON = 1,
TA = –40°C to 85°C
25
60
ppm/°
C
Settling time of reference
voltage (3)
AVCC = AVCC (min) to AVCC(max)
REFVSEL = {0, 1, 3}, REFON = 0 → 1
70
80
µs
The internal reference current is supplied from the AVCC terminal.
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
The condition is that the error in a ADC conversion started after tSETTLE is less than ±0.5 LSB.
Specifications
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5.26.9 Comparator_E
Table 5-36 lists the characteristics of the comparator.
Table 5-36. Comparator_E
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
IAVCC_COMP
IAVCC_REF
Comparator operating
supply current into
AVCC, excluding
reference resistor
ladder
Quiescent current of
resistor ladder into
AVCC, including
REF_A module
current
Reference voltage
level
VREF
VIC
Common-mode input
range
VOFFSET
Input offset voltage
CIN
Input capacitance
RSIN
Series input
resistance
tPD
TEST CONDITIONS
VCC
Supply voltage
Propagation delay,
response time
MIN
TYP
1.62
3.7
CEPWRMD = 00, CEON = 1,
CERSx = 00 (fast)
2.2 V,
3V
10
15
CEPWRMD = 01, CEON = 1,
CERSx = 00 (medium)
2.2 V,
3V
8
10
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 30°C
2.2 V,
3V
0.5
CEPWRMD = 10, CEON = 1,
CERSx = 00 (slow), TA = 85°C
2.2 V,
3V
0.5
CEREFACC = 0, CEREFLx = 01,
CERSx = 10, REFON = 0, CEON = 0
2.2 V,
3V
25
35
CEREFACC = 1, CEREFLx = 01,
CERSx = 10, REFON = 0, CEON = 0
2.2 V,
3V
10
15
CERSx = 11, CEREFLx = 01,
CEREFACC = 0
1.62 V
1.17
1.2
1.23
CERSx = 11, CEREFLx = 10,
CEREFACC = 0
2.2 V
1.95
2.0
2.05
CERSx = 11, CEREFLx = 11,
CEREFACC = 0
2.7 V
2.40
2.5
2.60
CERSx = 11, CEREFLx = 01,
CEREFACC = 1
1.62 V
1.15
1.2
1.23
CERSx = 11, CEREFLx = 10,
CEREFACC = 1
2.2 V
1.92
2.0
2.05
CERSx = 11, CEREFLx = 11,
CEREFACC = 1
2.7 V
2.4
2.5
2.6
tPD,filter
84
Specifications
V
µA
V
0
VCC–1
CEPWRMD = 00
–10
+10
CEPWRMD = 01
–20
+20
CEPWRMD = 10
–20
+20
CEPWRMD = 00 or CEPWRMD = 01
8
CEPWRMD = 10
8
On (switch closed)
Off (switch open)
UNIT
µA
2
V
mV
pF
4
50
kΩ
MΩ
CEPWRMD = 00, CEF = 0,
Overdrive ≥ 20 mV
330
550
CEPWRMD = 01, CEF = 0,
Overdrive ≥ 20 mV
410
650
ns
CEPWRMD = 10, CEF = 0,
Overdrive ≥ 20 mV
Propagation delay
with filter active
MAX
30
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 00
0.6
0.9
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 01
1.1
1.6
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 10
2
3
CEPWRMD = 00 or 01, CEF = 1,
Overdrive ≥ 20 mV, CEFDLY = 11
4
6
µs
µs
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 5-36. Comparator_E (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tEN_CMP_VREF
tEN_CMP_RL
VCMP_REF
TEST CONDITIONS
Comparator enable
time
tEN_CMP
Comparator and
reference ladder and
reference voltage
enable time
Comparator and
reference ladder
enable time
Reference voltage for
a given tap
TYP
MAX
CEON = 0 to 1, CEPWRMD = 00,
VIN+, VIN- from pins,
Overdrive ≥ 20 mV
0.8
1
CEON = 0 to 1, CEPWRMD = 01,
VIN+, VIN- from pins,
Overdrive ≥ 20 mV
0.9
1.2
CEON = 0 to 1, CEPWRMD = 10,
VIN+, VIN- from pins,
Overdrive ≥ 20 mV
15
25
CEON = 0 to 1, CEPWRMD = 00,
CEREFLx = 10, CERSx = 11,
REFON = 0, Overdrive ≥ 20 mV
90
120
CEON = 0 to 1, CEPWRMD = 01,
CEREFLx = 10, CERSx = 11,
REFON = 0, Overdrive ≥ 20 mV
90
120
CEON = 0 to 1, CEPWRMD = 10,
CEREFLx = 10, CERSx = 11,
REFON = 0, Overdrive ≥ 20 mV
90
120
CEON = 0 to 1, CEPWRMD = 00,
CEREFLx = 10, CERSx = 10,
REFON = 0, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
90
180
CEON = 0 to 1, CEPWRMD = 01,
CEREFLx = 10, CERSx = 10,
REFON = 0, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
90
180
CEON = 0 to 1, CEPWRMD = 10,
CEREFLx = 10, CERSx = 10,
REFON = 0, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
90
180
CEON = 0 to 1, CEPWRMD = 00,
CEREFLx = 10, CERSx = 10,
REFON = 1, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
1.5
2
CEON = 0 to 1, CEPWRMD = 01,
CEREFLx = 10, CERSx = 10,
REFON = 1, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
1.5
2
CEON = 0 to 1, CEPWRMD = 10,
CEREFLx = 10, CERSx = 10,
REFON = 1, CEREF0 = CEREF1 = 0x0F,
Overdrive ≥ 20 mV
15
25
VIN ×
(n + 1)
/ 32
VIN ×
(n + 1.1)
/ 32
VIN = reference into resistor ladder,
n = 0 to 31
VCC
MIN
VIN ×
(n + 0.9)
/ 32
UNIT
µs
µs
µs
V
5.26.10 LCD_F
Table 5-37 lists the operating conditions of the LCD controller.
Table 5-37. LCD Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC,LCD
Supply voltage range,
internal or external
biasing
2.4
fACLK,in
ACLK input frequency
range
10
NOM
32.768
MAX
3.7
V
128
kHz
Specifications
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UNIT
85
MSP432P4111, MSP432P4011, MSP432P411Y
MSP432P401Y, MSP432P411V, MSP432P401V
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Table 5-37. LCD Recommended Operating Conditions (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
1024
Hz
fLCD
LCD frequency range
fFRAME = 1/(2 × mux) × fLCD with
mux = 1 (static) to 8
fFRAME,4mux
LCD frame frequency
range
fFRAME,4mux (MAX) = 1/(2 × 4) × fLCD (MAX)
= 1 / (2 × 4) × 1024 Hz
128
Hz
fFRAME,8mux
LCD frame frequency
range
fFRAME,8mux (MAX) = 1/(2 × 8) × fLCD (MAX)
= 1/(2 × 8) × 1024 Hz
64
Hz
CPanel
Panel capacitance
fLCD = 1024 Hz, all common lines equally
loaded
10000
pF
VR23,1/3bias
Analog input voltage at
R23 with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR13
VR03 + 2/3 ×
(VCC – VR03)
VCC
V
VR13,1/3bias
Analog input voltage at
R13 with 1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03
VR03 + 1/3 ×
(VCC – VR03)
VR23
V
VR13,1/2bias
Analog input voltage at
R13 with 1/2 biasing, 1-4
Mux modes
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1, LCDMXx(2) = 0
VR03
VR03 + 1/2 ×
(VCC – VR03)
VCC
V
VR23,1/4bias
Analog input voltage at
R23 with 1/4 biasing, 4-8
Mux modes
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1, LCDMXx(2) = 1
VR13
3/4 × VCC
VCC
V
VR13,1/4bias
Analog input voltage at
R13 with 1/4 biasing, 4-8
Mux modes
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1, LCDMXx(2) = 1
VR03
1/2 × VCC
VR23
V
VR03,1/4bias
Analog input voltage at
R03 with 1/4 biasing, 4-8
Mux modes
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1, LCDMXx(2) = 1
VSS
1/4 × VCC
VR13
V
VR03,EXT
Analog input voltage at
R03 in 1/2 and 1/3-bias
modes
R0EXT = 1
VSS
VCC
V
Table 5-38 lists the electrical characteristics of the LCD controller.
Table 5-38. LCD Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
NOM
MAX
UNIT
RLCD,Seg
LCD driver output impedance, segment
lines
ILOAD = ±10 μA
2.4 V
10
kΩ
RLCD,COM
LCD driver output impedance, common
lines
ILOAD = ±10 μA
2.4 V
10
kΩ
86
Specifications
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5.26.11 eUSCI
Table 5-39 lists the supported clock frequencies of the eUSCI in UART mode.
Table 5-39. eUSCI (UART Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in MBaud)
VCORE
Internal: SMCLK,
External: UCLK,
Duty cycle = 50% ±10%
VCC
MIN
MAX
1.2 V
12
1.4 V
24
1.2 V
5
1.4 V
7
UNIT
MHz
MHz
Table 5-40 lists the characteristics of the eUSCI in UART mode.
Table 5-40. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
UART receive deglitch time (1)
tt
(1)
TEST CONDITIONS
VCC
MIN
TYP
MAX
UCGLITx = 0
5
UCGLITx = 1
20
60
UCGLITx = 2
30
100
UCGLITx = 3
50
150
UNIT
20
ns
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the maximum useable baud rate. To ensure that pulses are correctly recognized, their duration must exceed the maximum
specification of the deglitch time.
Table 5-41 lists the supported clock frequencies of the eUSCI in SPI master mode.
Table 5-41. eUSCI (SPI Master Mode) Clock Frequency
PARAMETER
feUSCI
eUSCI input clock frequency
TEST CONDITIONS
SMCLK
Duty cycle = 50% ±10%
VCC
MIN
MAX
VCORE = 1.2 V
12
VCORE = 1.4 V
24
Specifications
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UNIT
MHz
87
MSP432P4111, MSP432P4011, MSP432P411Y
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Table 5-42 lists the characteristics of the eUSCI in SPI master mode.
Table 5-42. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCORE
VCC
MIN
MAX
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
1
tSTE,LAG
STE lag time, Last clock to STE inactive
UCSTEM = 1,
UCMODEx = 01 or 10
1
tSTE,ACC
STE access time, STE active to SIMO
data out
UCSTEM = 0,
UCMODEx = 01 or 10
1.62 V
30
3.7 V
20
tSTE,DIS
STE disable time, STE inactive to SIMO
high impedance
UCSTEM = 0,
UCMODEx = 01 or 10
1.62 V
20
3.7 V
15
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
tSTE,LEAD
(1)
(2)
(3)
88
1.2 V
1.62 V
45
1.4 V
3.7 V
30
1.62 V
0
3.7 V
0
UCxCLK
cycles
14
7
3.7 V
0
ns
ns
3.7 V
0
ns
ns
1.62 V
1.62 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-69 and Figure 5-70.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 569 and Figure 5-70.
Specifications
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UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tSTE,DIS
tVALID,MO
SIMO
Figure 5-69. SPI Master Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tHD,MO
tSTE,ACC
tVALID,MO
tSTE,DIS
SIMO
Figure 5-70. SPI Master Mode, CKPH = 1
Specifications
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Table 5-43 lists the characteristics of the eUSCI in SPI slave mode.
Table 5-43. eUSCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note (1))
PARAMETER
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
UCLK edge to SOMI valid,
CL = 20 pF
tHD,SO
SOMI output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
90
VCC
MIN
1.62 V
45
3.7 V
20
1.62 V
1
3.7 V
1
MAX
ns
ns
1.62 V
25
3.7 V
15
1.62 V
18
3.7 V
14
1.62 V
3
3.7 V
2
1.62 V
0
3.7 V
0
35
18
3.7 V
6
ns
ns
3.7 V
10
ns
ns
1.62 V
1.62 V
UNIT
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI))
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 5-71 and Figure 5-72.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 5-71
and Figure 5-72.
Specifications
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SI
tLOW/HIGH
tHD,SI
SIMO
tHD,SO
tSTE,ACC
tSTE,DIS
tVALID,SO
SOMI
Figure 5-71. SPI Slave Mode, CKPH = 0
UCMODEx = 01
tSTE,LEAD
STE
tSTE,LAG
UCMODEx = 10
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tHD,SO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 5-72. SPI Slave Mode, CKPH = 1
Specifications
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Table 5-44 lists the supported clock frequencies of the eUSCI in I2C mode.
Table 5-44. eUSCI (I2C Mode) Clock Frequency
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
Internal: SMCLK,
External: UCLK,
Duty cycle = 50% ±10%
VCORE
VCC
MIN
MAX
1.2 V
12
1.4 V
24
1
UNIT
MHz
MHz
Table 5-45 lists the characteristics of the eUSCI in I2C mode.
Table 5-45. eUSCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-73)
PARAMETER
tHD,STA
TEST CONDITIONS
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
tSU,DAT
Data setup time
tSU,STO
Setup time for STOP
tSP
Pulse duration of spikes suppressed by input filter
tTIMEOUT
Clock low time-out
5.5
fSCL = 400 kHz
1.5
fSCL = 1 MHz
0.6
fSCL = 100 kHz
5.5
fSCL = 400 kHz
1.5
fSCL = 1 MHz
0.6
fSCL = 100 kHz
80
fSCL = 400 kHz
80
TYP
MAX
UNIT
µs
µs
ns
fSCL = 1 MHz
80
fSCL = 100 kHz
5.5
fSCL = 400 kHz
1.5
fSCL = 1 MHz
0.6
fSCL = 100 kHz
5.5
fSCL = 400 kHz
1.5
fSCL = 1 MHz
0.6
UCGLITx = 0
50
120
UCGLITx = 1
25
60
UCGLITx = 2
10
35
UCGLITx = 3
5
µs
µs
ns
20
UCCLTOx = 1
27
UCCLTOx = 2
30
UCCLTOx = 3
33
tSU,STA
tHD,STA
MIN
fSCL = 100 kHz
tHD,STA
ms
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-73. I2C Mode Timing
92
Specifications
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5.26.12 Timer_A
Table 5-46 lists the characteristics of Timer_A.
Table 5-46. Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTA
Timer_A input clock frequency
Internal: SMCLK,
External: TACLK,
Duty cycle = 50% ±10%
tTA,cap
Timer_A capture timing
All capture inputs, minimum pulse
duration required for capture
VCORE
VCC
MIN
MAX
1.2 V
12
1.4 V
24
20
UNIT
MHz
ns
Table 5-47 lists the characteristics of Timer32.
Table 5-47. Timer32
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fT32
(1)
TEST CONDITIONS
Timer32 operating clock frequency (1)
VCORE
VCC
MIN
MAX
1.2 V
24
1.4 V
48
UNIT
MHz
Timer32 operates on the same clock as the Cortex-M4 CPU.
Specifications
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5.26.13 Memories
Table 5-48 lists the general characteristics of the flash memory.
Table 5-48. Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
DVCCPGM/ERS
Supply voltage for program or erase
IPGM/ERS, PEAK
Peak supply current from DVCC during program or erase
NEndurance
Program or erase endurance (1)
tRetention
Data retention duration
NPGM_TO_ERS
Number of program operations supported between erases per sector
(1)
MIN
MAX
1.62
3.7
UNIT
V
10
mA
20000
cycles
20
years
2000
Program or erase cycle for a bit is defined as the value of bit changing from 1 to 0 to 1.
Table 5-49 lists the characteristics of the flash operations using MSP432 peripheral driver libraries.
Table 5-49. Flash Operations Using MSP432 Peripheral Driver Libraries (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPGM_API,
Word
Program time for 32-bit data using
ROM_FlashCtl_programMemory() API
VCORE = 1.4 V, MCLK = 48 MHz
63
390
µs
tPGM_API,
Sector
Program time for 4kB data (one sector)
VCORE = 1.4 V, MCLK = 48 MHz
using ROM_FlashCtl_programMemory() API
5.7
80
ms
9
309 (2)
VCORE = 1.4 V, MCLK = 48 MHz,
Number of erase or program cycles
>1000 and <20000
9
(2)
VCORE = 1.4 V, MCLK = 48 MHz,
Number of erase or program cycles
<1000,
Devices with 2MB of flash memory
38
1292 (3)
VCORE = 1.4 V, MCLK = 48 MHz,
Number of erase or program cycles
<1000,
Devices with 1MB of flash memory
24
816 (3)
VCORE = 1.4 V, MCLK = 48 MHz,
Number of erase or program cycles
<1000,
Devices with 512KB of flash memory
17
578 (3)
tERS_API,
Sector
tERS_API, Mass-Erase
Sector erase time using
ROM_FlashCtl_eraseSector() API
Mass erase time using
ROM_FlashCtl_performMassErase() API
VCORE = 1.4 V, MCLK = 48 MHz,
Number of erase or program cycles
<1000
ms
3035
ms
IAVGPGM_API
Average supply current from DVCC during
program using
ROM_FlashCtl_programMemory() API
VCORE = 1.2 V, MCLK = 3 MHz
5
7
mA
IAVGERS_API
Average supply current from DVCC during
erase using
ROM_FlashCtl_eraseSector() API
VCORE = 1.2 V, MCLK = 3 MHz
2
3
mA
(1)
(2)
(3)
94
MSP432 peripheral driver libraries executed from ROM.
The maximum value is calculated by multiplying the typical value by NMAX_ERS for the specific erase or program endurance.
The maximum value is calculated by multiplying the typical value by NMAX_ERS for the specific erase or program endurance and the total
number of sectors in the flash main memory.
Specifications
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Table 5-50 lists the characteristics of the flash stand-alone operations.
Table 5-50. Flash Stand-Alone Operations
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Program time for one 32-bit data using
immediate write mode
VER_PRE = 0, VER_PST = 1
52
VER_PRE = 1, VER_PST = 1
63
tPGM, Full-word
Program time for one 128-bit word using full
word write mode
VER_PRE = 0, VER_PST = 1
49
VER_PRE = 1, VER_PST = 1
70
tPGM,
Program time for 4×128-bit burst using burst
write mode
AUTO_PRE = 0, AUTO_PST = 1
43
AUTO_PRE = 1, AUTO_PST = 1
64
tPGM,
Immediate
Burst
tERS
Time for sector erase or mass erase
NMAX_PGM
Maximum number of pulses to complete
program operation
NMAX_ERS
Maximum number of pulses to complete
erase operation
MAX
UNIT
µs
µs
µs
9
ms
5
Number of erase or program cycles
<1000
34
Number of erase or program cycles
>1000 and <20000
334
Table 5-51 lists the characteristics of the SRAM.
Table 5-51. SRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ISRAM_EN
Current consumption of one SRAM bank when enabled
ISRAM_RET
Current consumption of one SRAM block under retention
tSRAM_EN,
TYP
MAX
VCORE = 1.2 V
TEST CONDITIONS
MIN
0.55
20.5
VCORE = 1.4 V
1.90
31
VCORE = 1.2 V
29
1700
VCORE = 1.4 V
36
2300
UNIT
µA
nA
one
Time taken to enable one SRAM bank
8
10
µs
tSRAM_DIS, one
Time taken to disable one SRAM bank
8
10
µs
tSRAM_EN,
all
Time taken to enable all SRAM banks except Bank 0
18
21
µs
tSRAM_DIS, all
Time taken to disable all SRAM banks except Bank 0
8
10
µs
Specifications
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5.26.14 Emulation and Debug
Table 5-52 lists the characteristics of the JTAG interface.
Table 5-52. JTAG
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
0
MAX
UNIT
10
MHz
fTCK
TCK clock frequency
tTCK
TCK clock period
tTCK_LOW
TCK clock low time
tTCK/2
tTCK_HIGH
TCK clock high time
tTCK/2
tTCK_RISE
TCK rise time
tTCK_FALL
TCK fall time
tTMS_SU
TMS setup time to TCK rise
tTMS_HLD
TMS hold time from TCK rise
tTDI_SU
TDI setup time to TCK rise
tTDI_HLD
TDI hold time from TCK rise
tTDO_ZDV
TCK fall to data valid from high impedance
9
44
ns
tTDO_DV
TCK fall to data valid from data valid
9
44
ns
tTDO_DVZ
TCK fall to high impedance from data valid
8
38
ns
100
ns
ns
ns
0
10
ns
0
10
ns
30
ns
9
ns
20
ns
7
ns
tTCK
tTCK_LOW
tTCK_HIGH
TCK
tTCK_RISE
tTCK_FALL
Figure 5-74. JTAG Test Clock Input Timing
TCK
tTMS_SU
TMS
tTMS_HLD
TDI
tTDI_HLD
tTDI_SU
TDI Input Valid
tTDO_ZDV
tTMS_HLD
TMS Input Valid
TMS Input Valid
tTDI_SU
TDO
tTMS_SU
tTDI_HLD
TDI Input Valid
tTDO_DV
TDO Output Valid
tTDO_DVZ
TDO Output Valid
Figure 5-75. JTAG Test Access Port (TAP) Timing
96
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6 Detailed Description
6.1
Overview
The MSP432P4x1x microcontroller is an ideal combination of the TI MSP430 low-power DNA, advance
mixed-signal features, and the processing capabilities of the Arm 32-bit Cortex-M4 RISC engine. The
microcontrollers ship with bundled driver libraries and are compatible with standard components of the
Arm ecosystem.
6.2
Processor and Execution Features
The Arm Cortex-M4 processor provides a high-performance low-cost platform that meets system
requirements of minimal memory implementation, reduced pin count, and low power consumption, while
delivering outstanding computational performance and exceptional system response to interrupts. The
Thumb®-2 mixed 16- and 32-bit instruction set of the processor delivers the high performance that is
expected of a 32-bit Arm core in a compact memory size usually associated with 8- and 16-bit devices
(typically in the range of a few kilobytes of memory needed for microcontroller-class applications).
In MSP432P4x1x devices, the Cortex-M4 processor can run up to 48 MHz, delivering high performance
for the targeted class of applications, while at the same time maintaining ultra-low active power
consumption.
6.2.1
Floating-Point Unit (FPU)
The Cortex-M4 processor on MSP432P4x1x devices includes a tightly coupled FPU. The FPU is an
IEEE 754 compliant single-precision floating-point module supporting add, subtract, multiply, divide,
accumulate, and square-root operations. The FPU also provides conversion between fixed-point and
floating-point data formats and floating-point constant instructions.
6.2.2
Memory Protection Unit (MPU)
The Cortex-M4 processor on MSP432P4x1x devices includes a tightly coupled MPU that supports up to
eight protection regions. Applications can use the MPU to enforce memory privilege rules that isolate
processes from each other or enforce memory access rules. These features are typically required for
operating system handling purposes.
6.2.3
Nested Vectored Interrupt Controller (NVIC)
The NVIC supports up to 64 interrupts with eight levels of interrupt priority. The Cortex-M4 NVIC
architecture allows for low latency, efficient interrupt and event handling, and seamless integration to
device-level power-control strategies.
6.2.4
SysTick
The Cortex-M4 includes an integrated system timer, SysTick, which provides a simple, 24-bit, clear-onwrite, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in
several different ways, and it is typically deployed either for use by the operating system or as a generalpurpose alarm mechanism.
6.2.5
Debug and Trace Features
The Cortex-M4 processor implements a complete hardware debug solution and provides high system
visibility of the processor and memory through either a traditional 4-pin JTAG port or a 2-pin Serial Wire
Debug (SWD) port, which is ideal for microcontrollers and other small-package devices. The SWJ-DP
interface combines the SWD and JTAG debug ports into one module, which allows a seamless switch
between the 2-pin and 4-pin modes of operation, depending on application needs.
Detailed Description
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For system trace, the processor integrates an Instrumentation Trace Macrocell (ITM) alongside data
watchpoints and a profiling unit. To enable simple and cost-effective profiling of the system trace events, a
Serial Wire Viewer (SWV) can export a stream of software-generated messages, data trace, and profiling
information through a single pin.
NOTE
For detailed specifications and information on the programmer's model for the Cortex-M4
CPU and the associated peripherals mentioned throughout Section 6.2, see the appropriate
reference manual at www.arm.com.
6.3
Memory Map
The device supports a 4-GB address space that is divided into eight 512-MB zones (see Figure 6-1).
0xFFFF_FFFF
Debug/Trace
Peripherals
0xE000_0000
0xDFFF_FFFF
Unused
0xC000_0000
0xBFFF_FFFF
Unused
0xA000_0000
0x9FFF_FFFF
Unused
0x8000_0000
0x7FFF_FFFF
Unused
0x6000_0000
0x5FFF_FFFF
Peripherals
0x4000_0000
0x3FFF_FFFF
SRAM
0x2000_0000
0x1FFF_FFFF
Code
0x0000_0000
Figure 6-1. Device Memory Zones
6.3.1
Code Zone Memory Map
The region from 0x0000_0000 to 0x1FFF_FFFF is defined as the Code zone, and is accessible through
the ICODE and DCODE buses of the Cortex-M4 processor and through the system DMA. This region
maps the flash, the ROM, and the internal SRAM (permitting optimal single-cycle execution from the
SRAM).
Figure 6-2 shows MSP432P4x1xI-specific memory map of the Code zone, as visible to the user code.
98
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0x1FFF_FFFF
Reserved
0x0210_0000
ROM Region
0x0200_0000
Reserved
0x0110_0000
SRAM Region
0x0100_0000
Reserved
0x0040_0000
Flash Memory
Region
0x0000_0000
Figure 6-2. Code Zone Memory Map
6.3.1.1
Flash Memory Region
The 4-MB region from 0x0000_0000 to 0x003F_FFFF is defined as the flash memory region. This region
is further divided into different types of flash memory regions, which are explained in Section 6.4.1.
6.3.1.2
SRAM Region
The 1-MB region from 0x0100_0000 to 0x010F_FFFF is defined as the SRAM region. This region is also
aliased in the SRAM zone of the device, thereby allowing efficient access to the SRAM, both for
instruction fetches and data reads. See Section 6.4.2 for more details.
6.3.1.3
ROM Region
The 1-MB region from 0x0200_0000 to 0x020F_FFFF is defined as the ROM region. See Section 6.4.4 for
details about the ROM.
6.3.2
SRAM Zone Memory Map
The SRAM zone of the device lies in the address range of 0x2000_0000 to 0x3FFF_FFFF. This is further
divided as shown in Figure 6-3.
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0x3FFF_FFFF
Reserved
0x2400_0000
SRAM
Bit-Band Alias
Region
0x2200_0000
Reserved
0x2010_0000
SRAM Region
0x2000_0000
Figure 6-3. SRAM Zone Memory Map
6.3.2.1
SRAM Region
The 1-MB region from 0x2000_0000 to 0x200F_FFFF is defined as the SRAM region. The SRAM
accessible in this region is also aliased in the Code zone of the device, thereby allowing efficient access to
the SRAM, both for instruction fetches and data reads. See Section 6.4.2 for details about the SRAM.
6.3.2.2
SRAM Bit-Band Alias Region
The 32-MB region from 0x2200_0000 to 0x23FF_FFFF forms the bit-band alias region for the 1-MB
SRAM region. Bit-banding is a feature of the Cortex-M4 processor and allows the application to set or
clear individual bits throughout the SRAM space without using the pipeline bandwidth of the processor to
carry out an exclusive read-modify-write sequence.
6.3.3
Peripheral Zone Memory Map
The Peripheral zone of the device is in the address range of 0x4000_0000 to 0x5FFF_FFFF. This is
further divided as shown in Figure 6-4.
100
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0x5FFF_FFFF
Reserved
0x4400_0000
Peripheral
Bit-Band Alias
Region
0x4200_0000
Reserved
0x4010_0000
Peripheral
Region
0x4000_0000
Figure 6-4. Peripheral Zone Memory Map
6.3.3.1
Peripheral Region
The 1MB region from 0x4000_0000 to 0x400F_FFFF is dedicated to the system and application control
peripherals of the device. On MSP432P4x1x devices, a total of 128KB of this region is dedicated for
peripherals, while the rest is reserved. Table 6-1 lists the peripheral allocation within this 128-KB space.
NOTE
Peripherals that are marked as 16-bit can be accessed through byte or half-word size read or
write only. Any 32-bit access to these peripherals results in a bus error response.
Table 6-1. Peripheral Address Offsets
ADDRESS RANGE
PERIPHERAL
TABLE
REMARKS
0x4000_0000 to 0x4000_03FF
Timer_A0
Table 6-2
16-bit peripheral
0x4000_0400 to 0x4000_07FF
Timer_A1
Table 6-3
16-bit peripheral
0x4000_0800 to 0x4000_0BFF
Timer_A2
Table 6-4
16-bit peripheral
0x4000_0C00 to 0x4000_0FFF
Timer_A3
Table 6-5
16-bit peripheral
0x4000_1000 to 0x4000_13FF
eUSCI_A0
Table 6-6
16-bit peripheral
0x4000_1400 to 0x4000_17FF
eUSCI_A1
Table 6-7
16-bit peripheral
0x4000_1800 to 0x4000_1BFF
eUSCI_A2
Table 6-8
16-bit peripheral
0x4000_1C00 to 0x4000_1FFF
eUSCI_A3
Table 6-9
16-bit peripheral
0x4000_2000 to 0x4000_23FF
eUSCI_B0
Table 6-10
16-bit peripheral
0x4000_2400 to 0x4000_27FF
eUSCI_B1
Table 6-11
16-bit peripheral
0x4000_2800 to 0x4000_2BFF
eUSCI_B2
Table 6-12
16-bit peripheral
0x4000_2C00 to 0x4000_2FFF
eUSCI_B3
Table 6-13
16-bit peripheral
0x4000_3000 to 0x4000_33FF
REF_A
Table 6-14
16-bit peripheral
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Table 6-1. Peripheral Address Offsets (continued)
ADDRESS RANGE
PERIPHERAL
TABLE
REMARKS
0x4000_3400 to 0x4000_37FF
COMP_E0
Table 6-15
16-bit peripheral
0x4000_3800 to 0x4000_3BFF
COMP_E1
Table 6-16
16-bit peripheral
0x4000_3C00 to 0x4000_3FFF
AES256
Table 6-17
16-bit peripheral
0x4000_4000 to 0x4000_43FF
CRC32
Table 6-18
16-bit peripheral
0x4000_4400 to 0x4000_47FF
RTC_C
Table 6-19
16-bit peripheral
0x4000_4800 to 0x4000_4BFF
WDT_A
Table 6-20
16-bit peripheral
0x4000_4C00 to 0x4000_4FFF
Port Module
Table 6-21
16-bit peripheral
0x4000_5000 to 0x4000_53FF
Port Mapping Controller
Table 6-22
16-bit peripheral
0x4000_5400 to 0x4000_57FF
Capacitive Touch I/O 0
Table 6-23
16-bit peripheral
0x4000_5800 to 0x4000_5BFF
Capacitive Touch I/O 1
Table 6-24
0x4000_5C00 to 0x4000_8FFF
Reserved
16-bit peripheral
Read only, always reads 0h
0x4000_9000 to 0x4000_BFFF
Reserved
0x4000_C000 to 0x4000_CFFF
Timer32
Read only, always reads 0h
0x4000_D000 to 0x4000_D7FF
Reserved
0x4000_D800 to 0x4000_DFFF
Utility SRAM
0x4000_E000 to 0x4000_FFFF
DMA
Table 6-26
0x4001_0000 to 0x4001_03FF
PCM
Table 6-27
Table 6-25
Read only, always reads 0h
0x4001_0400 to 0x4001_07FF
CS
Table 6-28
0x4001_0800 to 0x4001_0FFF
PSS
Table 6-29
0x4001_1000 to 0x4001_17FF
FLCTL_A
Table 6-30
0x4001_1800 to 0x4001_1BFF
Reserved
Read only, always reads 0h
0x4001_1C00 to 0x4001_1FFF
Reserved
0x4001_2000 to 0x4001_23FF
Precision ADC
Table 6-31
Read only, always reads 0h
0x4001_2400 to 0x4001_27FF
LCD_F
Table 6-32
0x4001_2800 to 0x4001_2BFF
Reserved
Read only, always reads 0h
0x4001_2C00 to 0x4001_FFFF
Reserved
Read only, always reads 0h
Table 6-2. Timer_A0 Registers (Base Address: 0x4000_0000)
REGISTER NAME
ACRONYM
OFFSET
Timer_A0 Control
TA0CTL
00h
Timer_A0 Capture/Compare Control 0
TA0CCTL0
02h
Timer_A0 Capture/Compare Control 1
TA0CCTL1
04h
Timer_A0 Capture/Compare Control 2
TA0CCTL2
06h
Timer_A0 Capture/Compare Control 3
TA0CCTL3
08h
Timer_A0 Capture/Compare Control 4
TA0CCTL4
0Ah
Timer_A0 Counter
TA0R
10h
Timer_A0 Capture/Compare 0
TA0CCR0
12h
Timer_A0 Capture/Compare 1
TA0CCR1
14h
Timer_A0 Capture/Compare 2
TA0CCR2
16h
Timer_A0 Capture/Compare 3
TA0CCR3
18h
Timer_A0 Capture/Compare 4
TA0CCR4
1Ah
Timer_A0 Interrupt Vector
TA0IV
2Eh
Timer_A0 Expansion 0
TA0EX0
20h
102
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Table 6-3. Timer_A1 Registers (Base Address: 0x4000_0400)
REGISTER NAME
ACRONYM
OFFSET
Timer_A1 Control
TA1CTL
00h
Timer_A1 Capture/Compare Control 0
TA1CCTL0
02h
Timer_A1 Capture/Compare Control 1
TA1CCTL1
04h
Timer_A1 Capture/Compare Control 2
TA1CCTL2
06h
Timer_A1 Capture/Compare Control 3
TA1CCTL3
08h
Timer_A1 Capture/Compare Control 4
TA1CCTL4
0Ah
Timer_A1 Counter
TA1R
10h
Timer_A1 Capture/Compare 0
TA1CCR0
12h
Timer_A1 Capture/Compare 1
TA1CCR1
14h
Timer_A1 Capture/Compare 2
TA1CCR2
16h
Timer_A1 Capture/Compare 3
TA1CCR3
18h
Timer_A1 Capture/Compare 4
TA1CCR4
1Ah
Timer_A1 Interrupt Vector
TA1IV
2Eh
Timer_A1 Expansion 0
TA1EX0
20h
Table 6-4. Timer_A2 Registers (Base Address: 0x4000_0800)
REGISTER NAME
ACRONYM
OFFSET
Timer_A2 Control
TA2CTL
00h
Timer_A2 Capture/Compare Control 0
TA2CCTL0
02h
Timer_A2 Capture/Compare Control 1
TA2CCTL1
04h
Timer_A2 Capture/Compare Control 2
TA2CCTL2
06h
Timer_A2 Capture/Compare Control 3
TA2CCTL3
08h
Timer_A2 Capture/Compare Control 4
TA2CCTL4
0Ah
Timer_A2 Counter
TA2R
10h
Timer_A2 Capture/Compare 0
TA2CCR0
12h
Timer_A2 Capture/Compare 1
TA2CCR1
14h
Timer_A2 Capture/Compare 2
TA2CCR2
16h
Timer_A2 Capture/Compare 3
TA2CCR3
18h
Timer_A2 Capture/Compare 4
TA2CCR4
1Ah
Timer_A2 Interrupt Vector
TA2IV
2Eh
Timer_A2 Expansion 0
TA2EX0
20h
Table 6-5. Timer_A3 Registers (Base Address: 0x4000_0C00)
REGISTER NAME
ACRONYM
OFFSET
Timer_A3 Control
TA3CTL
00h
Timer_A3 Capture/Compare Control 0
TA3CCTL0
02h
Timer_A3 Capture/Compare Control 1
TA3CCTL1
04h
Timer_A3 Capture/Compare Control 2
TA3CCTL2
06h
Timer_A3 Capture/Compare Control 3
TA3CCTL3
08h
Timer_A3 Capture/Compare Control 4
TA3CCTL4
0Ah
Timer_A3 Counter
TA3R
10h
Timer_A3 Capture/Compare 0
TA3CCR0
12h
Timer_A3 Capture/Compare 1
TA3CCR1
14h
Timer_A3 Capture/Compare 2
TA3CCR2
16h
Timer_A3 Capture/Compare 3
TA3CCR3
18h
Timer_A3 Capture/Compare 4
TA3CCR4
1Ah
Timer_A3 Interrupt Vector
TA3IV
2Eh
Detailed Description
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Table 6-5. Timer_A3 Registers (Base Address: 0x4000_0C00) (continued)
REGISTER NAME
ACRONYM
OFFSET
Timer_A3 Expansion 0
TA3EX0
20h
Table 6-6. eUSCI_A0 Registers (Base Address: 0x4000_1000)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_A0 Control Word 0
UCA0CTLW0
00h
eUSCI_A0 Control Word 1
UCA0CTLW1
02h
eUSCI_A0 Baud Rate Control
UCA0BRW
06h
eUSCI_A0 Modulation Control
UCA0MCTLW
08h
eUSCI_A0 Status
UCA0STATW
0Ah
eUSCI_A0 Receive Buffer
UCA0RXBUF
0Ch
eUSCI_A0 Transmit Buffer
UCA0TXBUF
0Eh
eUSCI_A0 Auto Baud Rate Control
UCA0ABCTL
10h
eUSCI_A0 IrDA Control
UCA0IRCTL
12h
eUSCI_A0 Interrupt Enable
UCA0IE
1Ah
eUSCI_A0 Interrupt Flag
UCA0IFG
1Ch
eUSCI_A0 Interrupt Vector
UCA0IV
1Eh
Table 6-7. eUSCI_A1 Registers (Base Address: 0x4000_1400)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_A1 Control Word 0
UCA1CTLW0
00h
eUSCI_A1 Control Word 1
UCA1CTLW1
02h
eUSCI_A1 Baud Rate Control
UCA1BRW
06h
eUSCI_A1 Modulation Control
UCA1MCTLW
08h
eUSCI_A1 Status
UCA1STATW
0Ah
eUSCI_A1 Receive Buffer
UCA1RXBUF
0Ch
eUSCI_A1 Transmit Buffer
UCA1TXBUF
0Eh
eUSCI_A1 Auto Baud Rate Control
UCA1ABCTL
10h
eUSCI_A1 IrDA Control
UCA1IRCTL
12h
eUSCI_A1 Interrupt Enable
UCA1IE
1Ah
eUSCI_A1 Interrupt Flag
UCA1IFG
1Ch
eUSCI_A1 Interrupt Vector
UCA1IV
1Eh
Table 6-8. eUSCI_A2 Registers (Base Address: 0x4000_1800)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_A2 Control Word 0
UCA2CTLW0
00h
eUSCI_A2 Control Word 1
UCA2CTLW1
02h
eUSCI_A2 Baud Rate Control
UCA2BRW
06h
eUSCI_A2 Modulation Control
UCA2MCTLW
08h
eUSCI_A2 Status
UCA2STATW
0Ah
eUSCI_A2 Receive Buffer
UCA2RXBUF
0Ch
eUSCI_A2 Transmit Buffer
UCA2TXBUF
0Eh
eUSCI_A2 Auto Baud Rate Control
UCA2ABCTL
10h
eUSCI_A2 IrDA Control
UCA2IRCTL
12h
eUSCI_A2 Interrupt Enable
UCA2IE
1Ah
eUSCI_A2 Interrupt Flag
UCA2IFG
1Ch
eUSCI_A2 Interrupt Vector
UCA2IV
1Eh
104
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-9. eUSCI_A3 Registers (Base Address: 0x4000_1C00)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_A3 Control Word 0
UCA3CTLW0
00h
eUSCI_A3 Control Word 1
UCA3CTLW1
02h
eUSCI_A3 Baud Rate Control
UCA3BRW
06h
eUSCI_A3 Modulation Control
UCA3MCTLW
08h
eUSCI_A3 Status
UCA3STATW
0Ah
eUSCI_A3 Receive Buffer
UCA3RXBUF
0Ch
eUSCI_A3 Transmit Buffer
UCA3TXBUF
0Eh
eUSCI_A3 Auto Baud Rate Control
UCA3ABCTL
10h
eUSCI_A3 IrDA Control
UCA3IRCTL
12h
eUSCI_A3 Interrupt Enable
UCA3IE
1Ah
eUSCI_A3 Interrupt Flag
UCA3IFG
1Ch
eUSCI_A3 Interrupt Vector
UCA3IV
1Eh
Table 6-10. eUSCI_B0 Registers (Base Address: 0x4000_2000)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_B0 Control Word 0
UCB0CTLW0
00h
eUSCI_B0 Control Word 1
UCB0CTLW1
02h
eUSCI_B0 Bit Rate Control Word
UCB0BRW
06h
eUSCI_B0 Status Word
UCB0STATW
08h
eUSCI_B0 Byte Counter Threshold
UCB0TBCNT
0Ah
eUSCI_B0 Receive Buffer
UCB0RXBUF
0Ch
eUSCI_B0 Transmit Buffer
UCB0TXBUF
0Eh
eUSCI_B0 I2C Own Address 0
UCB0I2COA0
14h
eUSCI_B0 I2C Own Address 1
UCB0I2COA1
16h
eUSCI_B0 I2C Own Address 2
UCB0I2COA2
18h
eUSCI_B0 I2C Own Address 3
UCB0I2COA3
1Ah
eUSCI_B0 Received Address
UCB0ADDRX
1Ch
eUSCI_B0 Address Mask
UCB0ADDMASK
1Eh
eUSCI_B0 I2C Slave Address
UCB0I2CSA
20h
eUSCI_B0 Interrupt Enable
UCB0IE
2Ah
eUSCI_B0 Interrupt Flag
UCB0IFG
2Ch
eUSCI_B0 Interrupt Vector
UCB0IV
2Eh
Table 6-11. eUSCI_B1 Registers (Base Address: 0x4000_2400)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_B1 Control Word 0
UCB1CTLW0
00h
eUSCI_B1 Control Word 1
UCB1CTLW1
02h
eUSCI_B1 Bit Rate Control Word
UCB1BRW
06h
eUSCI_B1 Status Word
UCB1STATW
08h
eUSCI_B1 Byte Counter Threshold
UCB1TBCNT
0Ah
eUSCI_B1 Receive Buffer
UCB1RXBUF
0Ch
eUSCI_B1 Transmit Buffer
UCB1TXBUF
0Eh
eUSCI_B1 I2C Own Address 0
UCB1I2COA0
14h
eUSCI_B1 I2C Own Address 1
UCB1I2COA1
16h
eUSCI_B1 I2C Own Address 2
UCB1I2COA2
18h
eUSCI_B1 I2C Own Address 3
UCB1I2COA3
1Ah
eUSCI_B1 Received Address
UCB1ADDRX
1Ch
Detailed Description
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Table 6-11. eUSCI_B1 Registers (Base Address: 0x4000_2400) (continued)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_B1 Address Mask
UCB1ADDMASK
1Eh
eUSCI_B1 I2C Slave Address
UCB1I2CSA
20h
eUSCI_B1 Interrupt Enable
UCB1IE
2Ah
eUSCI_B1 Interrupt Flag
UCB1IFG
2Ch
eUSCI_B1 Interrupt Vector
UCB1IV
2Eh
Table 6-12. eUSCI_B2 Registers (Base Address: 0x4000_2800)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_B2 Control Word 0
UCB2CTLW0
00h
eUSCI_B2 Control Word 1
UCB2CTLW1
02h
eUSCI_B2 Bit Rate Control Word
UCB2BRW
06h
eUSCI_B2 Status Word
UCB2STATW
08h
eUSCI_B2 Byte Counter Threshold
UCB2TBCNT
0Ah
eUSCI_B2 Receive Buffer
UCB2RXBUF
0Ch
eUSCI_B2 Transmit Buffer
UCB2TXBUF
0Eh
eUSCI_B2 I2C Own Address 0
UCB2I2COA0
14h
eUSCI_B2 I2C Own Address 1
UCB2I2COA1
16h
eUSCI_B2 I2C Own Address 2
UCB2I2COA2
18h
eUSCI_B2 I2C Own Address 3
UCB2I2COA3
1Ah
eUSCI_B2 Received Address
UCB2ADDRX
1Ch
eUSCI_B2 Address Mask
UCB2ADDMASK
1Eh
eUSCI_B2 I2C Slave Address
UCB2I2CSA
20h
eUSCI_B2 Interrupt Enable
UCB2IE
2Ah
eUSCI_B2 Interrupt Flag
UCB2IFG
2Ch
eUSCI_B2 Interrupt Vector
UCB2IV
2Eh
Table 6-13. eUSCI_B3 Registers (Base Address: 0x4000_2C00)
REGISTER NAME
ACRONYM
OFFSET
eUSCI_B3 Control Word 0
UCB3CTLW0
00h
eUSCI_B3 Control Word 1
UCB3CTLW1
02h
eUSCI_B3 Bit Rate Control Word
UCB3BRW
06h
eUSCI_B3 Status Word
UCB3STATW
08h
eUSCI_B3 Byte Counter Threshold
UCB3TBCNT
0Ah
eUSCI_B3 Receive Buffer
UCB3RXBUF
0Ch
eUSCI_B3 Transmit Buffer
UCB3TXBUF
0Eh
eUSCI_B3 I2C Own Address 0
UCB3I2COA0
14h
eUSCI_B3 I2C Own Address 1
UCB3I2COA1
16h
eUSCI_B3 I2C Own Address 2
UCB3I2COA2
18h
eUSCI_B3 I2C Own Address 3
UCB3I2COA3
1Ah
eUSCI_B3 Received Address
UCB3ADDRX
1Ch
eUSCI_B3 Address Mask
UCB3ADDMASK
1Eh
eUSCI_B3 I2C Slave Address
UCB3I2CSA
20h
eUSCI_B3 Interrupt Enable
UCB3IE
2Ah
eUSCI_B3 Interrupt Flag
UCB3IFG
2Ch
eUSCI_B3 Interrupt Vector
UCB3IV
2Eh
106
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-14. REF_A Registers (Base Address: 0x4000_3000)
REGISTER NAME
ACRONYM
OFFSET
REF_A Control 0
REFCTL0
00h
Table 6-15. COMP_E0 Registers (Base Address: 0x4000_3400)
REGISTER NAME
ACRONYM
OFFSET
Comparator_E0 Control 0
CE0CTL0
00h
Comparator_E0 Control 1
CE0CTL1
02h
Comparator_E0 Control 2
CE0CTL2
04h
Comparator_E0 Control 3
CE0CTL3
06h
Comparator_E0 Interrupt
CE0INT
0Ch
Comparator_E0 Interrupt Vector Word
CE0IV
0Eh
Table 6-16. COMP_E1 Registers (Base Address: 0x4000_3800)
REGISTER NAME
ACRONYM
OFFSET
Comparator_E1 Control 0
CE1CTL0
00h
Comparator_E1 Control 1
CE1CTL1
02h
Comparator_E1 Control 2
CE1CTL2
04h
Comparator_E1 Control 3
CE1CTL3
06h
Comparator_E1 Interrupt
CE1INT
0Ch
Comparator_E1 Interrupt Vector Word
CE1IV
0Eh
Table 6-17. AES256 Registers (Base Address: 0x4000_3C00)
REGISTER NAME
ACRONYM
OFFSET
AES Accelerator Control 0
AESACTL0
00h
AES Accelerator Control 1
AESACTL1
02h
AES Accelerator Status
AESASTAT
04h
AES Accelerator Key
AESAKEY
06h
AES Accelerator Data In
AESADIN
08h
AES Accelerator Data Out
AESADOUT
0Ah
AES Accelerator XORed Data In
AESAXDIN
0Ch
AES Accelerator XORed Data In (no trigger)
AESAXIN
0Eh
Table 6-18. CRC32 Registers (Base Address: 0x4000_4000)
REGISTER NAME
ACRONYM
OFFSET
CRC32 Data Input Low
CRC32DI
000h
CRC32 Data In Reverse Low
CRC32DIRB
004h
CRC32 Initialization and Result Low
CRC32INIRES_LO
008h
CRC32 Initialization and Result High
CRC32INIRES_HI
00Ah
CRC32 Result Reverse Low
CRC32RESR_LO
00Ch
CRC32 Result Reverse High
CRC32RESR_HI
00Eh
CRC16 Data Input Low
CRC16DI
010h
CRC16 Data In Reverse Low
CRC16DIRB
014h
CRC16 Initialization and Result
CRC16INIRES
018h
CRC16 Result Reverse
CRC16RESR
01Eh
Detailed Description
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Table 6-19. RTC_C Registers (Base Address: 0x4000_4400)
REGISTER NAME
ACRONYM
OFFSET
Real-Time Clock Control 0
RTCCTL0
00h
Real-Time Clock Control 1, 3
RTCCTL13
02h
Real-Time Clock Offset Calibration
RTCOCAL
04h
Real-Time Clock Temperature Compensation
RTCTCMP
06h
Real-Time Prescale Timer 0 Control
RTCPS0CTL
08h
Real-Time Prescale Timer 1 Control
RTCPS1CTL
0Ah
Real-Time Prescale Timer 0, 1 Counter
RTCPS
0Ch
Real Time Clock Interrupt Vector
RTCIV
0Eh
Real-Time Clock Seconds, Minutes
RTCTIM0
10h
Real-Time Clock Hour, Day of Week
RTCTIM1
12h
Real-Time Clock Date
RTCDATE
14h
Real-Time Clock Year
RTCYEAR
16h
Real-Time Clock Minutes, Hour Alarm
RTCAMINHR
18h
Real-Time Clock Day of Week, Day of Month Alarm
RTCADOWDAY
1Ah
Binary-to-BCD Conversion
RTCBIN2BCD
1Ch
BCD-to-Binary Conversion
RTCBCD2BIN
1Eh
Table 6-20. WDT_A Registers (Base Address: 0x4000_4800)
REGISTER NAME
ACRONYM
OFFSET
Watchdog Timer Control
WDTCTL
0Ch
Table 6-21. Port Registers (Base Address: 0x4000_4C00)
REGISTER NAME
ACRONYM
OFFSET
Port 1 Input
P1IN
000h
Port 2 Input
P2IN
001h
Port 1 Output
P1OUT
002h
Port 2 Output
P2OUT
003h
Port 1 Direction
P1DIR
004h
Port 2 Direction
P2DIR
005h
Port 1 Resistor Enable
P1REN
006h
Port 2 Resistor Enable
P2REN
007h
Port 2 Drive Strength
P2DS
009h
Port 1 Select 0
P1SEL0
00Ah
Port 2 Select 0
P2SEL0
00Bh
Port 1 Select 1
P1SEL1
00Ch
Port 2 Select 1
P2SEL1
00Dh
Port 1 Interrupt Vector
P1IV
00Eh
Port 1 Complement Selection
P1SELC
016h
Port 2 Complement Selection
P2SELC
017h
Port 1 Interrupt Edge Select
P1IES
018h
Port 2 Interrupt Edge Select
P2IES
019h
Port 1 Interrupt Enable
P1IE
01Ah
Port 2 Interrupt Enable
P2IE
01Bh
Port 1 Interrupt Flag
P1IFG
01Ch
Port 2 Interrupt Flag
P2IFG
01Dh
Port 2 Interrupt Vector
P2IV
01Eh
Port 3 Input
P3IN
020h
108
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-21. Port Registers (Base Address: 0x4000_4C00) (continued)
REGISTER NAME
ACRONYM
OFFSET
Port 4 Input
P4IN
021h
Port 3 Output
P3OUT
022h
Port 4 Output
P4OUT
023h
Port 3 Direction
P3DIR
024h
Port 4 Direction
P4DIR
025h
Port 3 Resistor Enable
P3REN
026h
Port 4 Resistor Enable
P4REN
027h
Port 3 Select 0
P3SEL0
02Ah
Port 4 Select 0
P4SEL0
02Bh
Port 3 Select 1
P3SEL1
02Ch
Port 4 Select 1
P4SEL1
02Dh
Port 3 Interrupt Vector
P3IV
02Eh
Port 3 Complement Selection
P3SELC
036h
Port 4 Complement Selection
P4SELC
037h
Port 3 Interrupt Edge Select
P3IES
038h
Port 4 Interrupt Edge Select
P4IES
039h
Port 3 Interrupt Enable
P3IE
03Ah
Port 4 Interrupt Enable
P4IE
03Bh
Port 3 Interrupt Flag
P3IFG
03Ch
Port 4 Interrupt Flag
P4IFG
03Dh
Port 4 Interrupt Vector
P4IV
03Eh
Port 5 Input
P5IN
040h
Port 6 Input
P6IN
041h
Port 5 Output
P5OUT
042h
Port 6 Output
P6OUT
043h
Port 5 Direction
P5DIR
044h
Port 6 Direction
P6DIR
045h
Port 5 Resistor Enable
P5REN
046h
Port 6 Resistor Enable
P6REN
047h
Port 5 Select 0
P5SEL0
04Ah
Port 6 Select 0
P6SEL0
04Bh
Port 5 Select 1
P5SEL1
04Ch
Port 6 Select 1
P6SEL1
04Dh
Port 5 Interrupt Vector
P5IV
04Eh
Port 5 Complement Selection
P5SELC
056h
Port 6 Complement Selection
P6SELC
057h
Port 5 Interrupt Edge Select
P5IES
058h
Port 6 Interrupt Edge Select
P6IES
059h
Port 5 Interrupt Enable
P5IE
05Ah
Port 6 Interrupt Enable
P6IE
05Bh
Port 5 Interrupt Flag
P5IFG
05Ch
Port 6 Interrupt Flag
P6IFG
05Dh
Port 6 Interrupt Vector
P6IV
05Eh
Port 7 Input
P7IN
060h
Port 8 Input
P8IN
061h
Port 7 Output
P7OUT
062h
Port 8 Output
P8OUT
063h
Detailed Description
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Table 6-21. Port Registers (Base Address: 0x4000_4C00) (continued)
REGISTER NAME
ACRONYM
OFFSET
Port 7 Direction
P7DIR
064h
Port 8 Direction
P8DIR
065h
Port 7 Resistor Enable
P7REN
066h
Port 8 Resistor Enable
P8REN
067h
Port 7 Select 0
P7SEL0
06Ah
Port 8 Select 0
P8SEL0
06Bh
Port 7 Select 1
P7SEL1
06Ch
Port 8 Select 1
P8SEL1
06Dh
Port 7 Complement Selection
P7SELC
076h
Port 8 Complement Selection
P8SELC
077h
Port 9 Input
P9IN
080h
Port 10 Input
P10IN
081h
Port 9 Output
P9OUT
082h
Port 10 Output
P10OUT
083h
Port 9 Direction
P9DIR
084h
Port 10 Direction
P10DIR
085h
Port 9 Resistor Enable
P9REN
086h
Port 10 Resistor Enable
P10REN
087h
Port 9 Select 0
P9SEL0
08Ah
Port 10 Select 0
P10SEL0
08Bh
Port 9 Select 1
P9SEL1
08Ch
Port 10 Select 1
P10SEL1
08Dh
Port 9 Complement Selection
P9SELC
096h
Port 10 Complement Selection
P10SELC
097h
Port J Input
PJIN
120h
Port J Output
PJOUT
122h
Port J Direction
PJDIR
124h
Port J Resistor Enable
PJREN
126h
Port J Select 0
PJSEL0
12Ah
Port J Select 1
PJSEL1
12Ch
Port J Complement Select
PJSELC
136h
Table 6-22. PMAP Registers (Base Address: 0x4000_5000)
REGISTER NAME
ACRONYM
OFFSET
Port Mapping Key
PMAPKEYID
00h
Port Mapping Control
PMAPCTL
02h
Port Mapping P2.0
P2MAP0
10h
Port Mapping P2.1
P2MAP1
11h
Port Mapping P2.2
P2MAP2
12h
Port Mapping P2.3
P2MAP3
13h
Port Mapping P2.4
P2MAP4
14h
Port Mapping P2.5
P2MAP5
15h
Port Mapping P2.6
P2MAP6
16h
Port Mapping P2.7
P2MAP7
17h
Port Mapping P3.0
P3MAP0
18h
Port Mapping P3.1
P3MAP1
19h
Port Mapping P3.2
P3MAP2
1Ah
110
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-22. PMAP Registers (Base Address: 0x4000_5000) (continued)
REGISTER NAME
ACRONYM
OFFSET
Port Mapping P3.3
P3MAP3
1Bh
Port Mapping P3.4
P3MAP4
1Ch
Port Mapping P3.5
P3MAP5
1Dh
Port Mapping P3.6
P3MAP6
1Eh
Port Mapping P3.7
P3MAP7
1Fh
Port Mapping P7.0
P7MAP0
38h
Port Mapping P7.1
P7MAP1
39h
Port Mapping P7.2
P7MAP2
3Ah
Port Mapping P7.3
P7MAP3
3Bh
Port Mapping P7.4
P7MAP4
3Ch
Port Mapping P7.5
P7MAP5
3Dh
Port Mapping P7.6
P7MAP6
3Eh
Port Mapping P7.7
P7MAP7
3Fh
Table 6-23. Capacitive Touch I/O 0 Registers (Base Address: 0x4000_5400)
REGISTER NAME
ACRONYM
OFFSET
Capacitive Touch I/O 0 Control
CAPTIO0CTL
0Eh
Table 6-24. Capacitive Touch I/O 1 Registers (Base Address: 0x4000_5800)
REGISTER NAME
ACRONYM
OFFSET
Capacitive Touch I/O 1 Control
CAPTIO1CTL
0Eh
Table 6-25. Timer32 Registers (Base Address: 0x4000_C000)
REGISTER NAME
ACRONYM
OFFSET
Timer 1 Load
T32LOAD1
00h
Timer 1 Current Value
T32VALUE1
04h
Timer 1 Timer Control
T32CONTROL1
08h
Timer 1 Interrupt Clear
T32INTCLR1
0Ch
Timer 1 Raw Interrupt Status
T32RIS1
10h
Timer 1 Interrupt Status
T32MIS1
14h
Timer 1 Background Load
T32BGLOAD1
18h
Timer 2 Load
T32LOAD2
20h
Timer 2 Current Value
T32VALUE2
24h
Timer 2 Timer Control
T32CONTROL2
28h
Timer 2 Interrupt Clear
T32INTCLR2
2Ch
Timer 2 Raw Interrupt Status
T32RIS2
30h
Timer 2 Interrupt Status
T32MIS2
34h
Timer 2 Background Load
T32BGLOAD2
38h
Table 6-26. DMA Registers (Base Address: 0x4000_E000)
REGISTER NAME
ACRONYM
OFFSET
Device Configuration Status
DMA_DEVICE_CFG
000h
Software Channel Trigger
DMA_SW_CHTRIG
004h
Channel 0 Source Configuration
DMA_CH0_SRCCFG
010h
Channel 1 Source Configuration
DMA_CH1_SRCCFG
014h
Channel 2 Source Configuration
DMA_CH2_SRCCFG
018h
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Table 6-26. DMA Registers (Base Address: 0x4000_E000) (continued)
REGISTER NAME
ACRONYM
OFFSET
Channel 3 Source Configuration
DMA_CH3_SRCCFG
01Ch
Channel 4 Source Configuration
DMA_CH4_SRCCFG
020h
Channel 5 Source Configuration
DMA_CH5_SRCCFG
024h
Channel 6 Source Configuration
DMA_CH6_SRCCFG
028h
Channel 7 Source Configuration
DMA_CH7_SRCCFG
02Ch
Interrupt 1 Source Channel Configuration
DMA_INT1_SRCCFG
100h
Interrupt 2 Source Channel Configuration
DMA_INT2_SRCCFG
104h
Interrupt 3 Source Channel Configuration
DMA_INT3_SRCCFG
108h
Interrupt 0 Source Channel Flag
DMA_INT0_SRCFLG
110h
Interrupt 0 Source Channel Clear Flag
DMA_INT0_CLRFLG
114h
Status
DMA_STAT
1000h
Configuration
DMA_CFG
1004h
Channel Control Data Base Pointer
DMA_CTLBASE
1008h
Channel Alternate Control Data Base Pointer
DMA_ALTBASE
100Ch
Channel Wait on Request Status
DMA_WAITSTAT
1010h
Channel Software Request
DMA_SWREQ
1014h
Channel Useburst Set
DMA_USEBURSTSET
1018h
Channel Useburst Clear
DMA_USEBURSTCLR
101Ch
Channel Request Mask Set
DMA_REQMASKSET
1020h
Channel Request Mask Clear
DMA_REQMASKCLR
1024h
Channel Enable Set
DMA_ENASET
1028h
Channel Enable Clear
DMA_ENACLR
102Ch
Channel Primary-Alternate Set
DMA_ALTSET
1030h
Channel Primary-Alternate Clear
DMA_ALTCLR
1034h
Channel Priority Set
DMA_PRIOSET
1038h
Channel Priority Clear
DMA_PRIOCLR
103Ch
Bus Error Clear
DMA_ERRCLR
104Ch
Table 6-27. PCM Registers (Base Address: 0x4001_0000)
REGISTER NAME
ACRONYM
OFFSET
Control 0
PCMCTL0
00h
Control 1
PCMCTL1
04h
Interrupt Enable
PCMIE
08h
Interrupt Flag
PCMIFG
0Ch
Clear Interrupt Flag
PCMCLRIFG
10h
Table 6-28. CS Registers (Base Address: 0x4001_0400)
REGISTER NAME
ACRONYM
OFFSET
Key
CSKEY
00h
Control 0
CSCTL0
04h
Control 1
CSCTL1
08h
Control 2
CSCTL2
0Ch
Control 3
CSCTL3
10h
Clock Enable
CSCLKEN
30h
Status
CSSTAT
34h
Interrupt Enable
CSIE
40h
Interrupt Flag
CSIFG
48h
112
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Table 6-28. CS Registers (Base Address: 0x4001_0400) (continued)
REGISTER NAME
ACRONYM
OFFSET
Clear Interrupt Flag
CSCLRIFG
50h
Set Interrupt Flag
CSSETIFG
58h
DCO External Resistor Calibration 0
CSDCOERCAL0
60h
DCO External Resistor Calibration 1
CSDCOERCAL1
64h
Table 6-29. PSS Registers (Base Address: 0x4001_0800)
REGISTER NAME
ACRONYM
OFFSET
Key
PSSKEY
00h
Control 0
PSSCTL0
04h
Interrupt Enable
PSSIE
34h
Interrupt Flag
PSSIFG
38h
Clear Interrupt Flag
PSSCLRIFG
3Ch
Table 6-30. FLCTL_A Registers (Base Address: 0x4001_1000)
REGISTER NAME
ACRONYM
OFFSET
Power Status
FLCTL_POWER_STAT
000h
Bank 0 Read Control
FLCTL_BANK0_RDCTL
010h
Bank 1 Read Control
FLCTL_BANK1_RDCTL
014h
Read Burst/Compare Control and Status
FLCTL_RDBRST_CTLSTAT
020h
Read Burst/Compare Start Address
FLCTL_RDBRST_STARTADDR
024h
Read Burst/Compare Length
FLCTL_RDBRST_LEN
028h
Read Burst/Compare Fail Address
FLCTL_RDBRST_FAILADDR
03Ch
Read Burst/Compare Fail Count
FLCTL_RDBRST_FAILCNT
040h
Program Control and Status
FLCTL_PRG_CTLSTAT
050h
Program Burst Control and Status
FLCTL_PRGBRST_CTLSTAT
054h
Program Burst Start Address
FLCTL_PRGBRST_STARTADDR
058h
Program Burst Data0 0
FLCTL_PRGBRST_DATA0_0
060h
Program Burst Data0 1
FLCTL_PRGBRST_DATA0_1
064h
Program Burst Data0 2
FLCTL_PRGBRST_DATA0_2
068h
Program Burst Data0 3
FLCTL_PRGBRST_DATA0_3
06Ch
Program Burst Data1 0
FLCTL_PRGBRST_DATA1_0
070h
Program Burst Data1 1
FLCTL_PRGBRST_DATA1_1
074h
Program Burst Data1 2
FLCTL_PRGBRST_DATA1_2
078h
Program Burst Data1 3
FLCTL_PRGBRST_DATA1_3
07Ch
Program Burst Data2 0
FLCTL_PRGBRST_DATA2_0
080h
Program Burst Data2 1
FLCTL_PRGBRST_DATA2_1
084h
Program Burst Data2 2
FLCTL_PRGBRST_DATA2_2
088h
Program Burst Data2 3
FLCTL_PRGBRST_DATA2_3
08Ch
Program Burst Data3 0
FLCTL_PRGBRST_DATA3_0
090h
Program Burst Data3 1
FLCTL_PRGBRST_DATA3_1
094h
Program Burst Data3 2
FLCTL_PRGBRST_DATA3_2
098h
Program Burst Data3 3
FLCTL_PRGBRST_DATA3_3
09Ch
Erase Control and Status
FLCTL_ERASE_CTLSTAT
0A0h
Erase Sector Address
FLCTL_ERASE_SECTADDR
0A4h
Information Memory Bank 0 Write/Erase Protection
FLCTL_BANK0_INFO_WEPROT
0B0h
Information Memory Bank 1 Write/Erase Protection
FLCTL_BANK1_INFO_WEPROT
0C0h
Benchmark Control and Status
FLCTL_BMRK_CTLSTAT
0D0h
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Table 6-30. FLCTL_A Registers (Base Address: 0x4001_1000) (continued)
REGISTER NAME
ACRONYM
OFFSET
Benchmark Instruction Fetch Count
FLCTL_BMRK_IFETCH
0D4h
Benchmark Data Read Count
FLCTL_BMRK_DREAD
0D8h
Benchmark Count Compare
FLCTL_BMRK_CMP
0DCh
Interrupt Flag
FLCTL_IFG
0F0h
Interrupt Enable
FLCTL_IE
0F4h
Clear Interrupt Flag
FLCTL_CLRIFG
0F8h
Set Interrupt Flag
FLCTL_SETIFG
0FCh
Read Timing Control
FLCTL_READ_TIMCTL
100h
Read Margin Timing Control
FLCTL_READMARGIN_TIMCTL
104h
Program Verify Timing Control
FLCTL_PRGVER_TIMCTL
108h
Erase Verify Timing Control
FLCTL_ERSVER_TIMCTL
10Ch
Program Timing Control
FLCTL_PROGRAM_TIMCTL
114h
Erase Timing Control
FLCTL_ERASE_TIMCTL
118h
Mass Erase Timing Control
FLCTL_MASSERASE_TIMCTL
11Ch
Burst Program Timing Control
FLCTL_BURSTPRG_TIMCTL
120h
Main Memory Bank 0 Write/Erase Protection 0
FLCTL_BANK0_MAIN_WEPROT0
200h
Main Memory Bank 0 Write/Erase Protection 1
FLCTL_BANK0_MAIN_WEPROT1
204h
Main Memory Bank 0 Write/Erase Protection 2
FLCTL_BANK0_MAIN_WEPROT2
208h
Main Memory Bank 0 Write/Erase Protection 3
FLCTL_BANK0_MAIN_WEPROT3
20Ch
Main Memory Bank 0 Write/Erase Protection 4
FLCTL_BANK0_MAIN_WEPROT4
210h
Main Memory Bank 0 Write/Erase Protection 5
FLCTL_BANK0_MAIN_WEPROT5
214h
Main Memory Bank 0 Write/Erase Protection 6
FLCTL_BANK0_MAIN_WEPROT6
218h
Main Memory Bank 0 Write/Erase Protection 7
FLCTL_BANK0_MAIN_WEPROT7
21Ch
Main Memory Bank 1 Write/Erase Protection 0
FLCTL_BANK1_MAIN_WEPROT0
240h
Main Memory Bank 1 Write/Erase Protection 1
FLCTL_BANK1_MAIN_WEPROT1
244h
Main Memory Bank 1 Write/Erase Protection 2
FLCTL_BANK1_MAIN_WEPROT2
248h
Main Memory Bank 1 Write/Erase Protection 3
FLCTL_BANK1_MAIN_WEPROT3
24Ch
Main Memory Bank 1 Write/Erase Protection 4
FLCTL_BANK1_MAIN_WEPROT4
250h
Main Memory Bank 1 Write/Erase Protection 5
FLCTL_BANK1_MAIN_WEPROT5
254h
Main Memory Bank 1 Write/Erase Protection 6
FLCTL_BANK1_MAIN_WEPROT6
258h
Main Memory Bank 1 Write/Erase Protection 7
FLCTL_BANK1_MAIN_WEPROT7
25Ch
Table 6-31. Precision ADC Registers (Base Address: 0x4001_2000)
REGISTER NAME
ACRONYM
OFFSET
Control 0
ADC14CTL0
00h
Control 1
ADC14CTL1
04h
Window Comparator Low Threshold 0
ADC14LO0
08h
Window Comparator High Threshold 0
ADC14HI0
0Ch
Window Comparator Low Threshold 1
ADC14LO1
10h
Window Comparator High Threshold 1
ADC14HI1
14h
Memory Control 0
ADC14MCTL0
18h
Memory Control 1
ADC14MCTL1
1Ch
Memory Control 2
ADC14MCTL2
20h
Memory Control 3
ADC14MCTL3
24h
Memory Control 4
ADC14MCTL4
28h
Memory Control 5
ADC14MCTL5
2Ch
Memory Control 6
ADC14MCTL6
30h
114
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-31. Precision ADC Registers (Base Address: 0x4001_2000) (continued)
REGISTER NAME
ACRONYM
OFFSET
Memory Control 7
ADC14MCTL7
34h
Memory Control 8
ADC14MCTL8
38h
Memory Control 9
ADC14MCTL9
3Ch
Memory Control 10
ADC14MCTL10
40h
Memory Control 11
ADC14MCTL11
44h
Memory Control 12
ADC14MCTL12
48h
Memory Control 13
ADC14MCTL13
4Ch
Memory Control 14
ADC14MCTL14
50h
Memory Control 15
ADC14MCTL15
54h
Memory Control 16
ADC14MCTL16
58h
Memory Control 17
ADC14MCTL17
5Ch
Memory Control 18
ADC14MCTL18
60h
Memory Control 19
ADC14MCTL19
64h
Memory Control 20
ADC14MCTL20
68h
Memory Control 21
ADC14MCTL21
6Ch
Memory Control 22
ADC14MCTL22
70h
Memory Control 23
ADC14MCTL23
74h
Memory Control 24
ADC14MCTL24
78h
Memory Control 25
ADC14MCTL25
7Ch
Memory Control 26
ADC14MCTL26
80h
Memory Control 27
ADC14MCTL27
84h
Memory Control 28
ADC14MCTL28
88h
Memory Control 29
ADC14MCTL29
8Ch
Memory Control 30
ADC14MCTL30
90h
Memory Control 31
ADC14MCTL31
94h
Memory 0
ADC14MEM0
98h
Memory 1
ADC14MEM1
9Ch
Memory 2
ADC14MEM2
A0h
Memory 3
ADC14MEM3
A4h
Memory 4
ADC14MEM4
A8h
Memory 5
ADC14MEM5
ACh
Memory 6
ADC14MEM6
B0h
Memory 7
ADC14MEM7
B4h
Memory 8
ADC14MEM8
B8h
Memory 9
ADC14MEM9
BCh
Memory 10
ADC14MEM10
C0h
Memory 11
ADC14MEM11
C4h
Memory 12
ADC14MEM12
C8h
Memory 13
ADC14MEM13
CCh
Memory 14
ADC14MEM14
D0h
Memory 15
ADC14MEM15
D4h
Memory 16
ADC14MEM16
D8h
Memory 17
ADC14MEM17
DCh
Memory 18
ADC14MEM18
E0h
Memory 19
ADC14MEM19
E4h
Memory 20
ADC14MEM20
E8h
Memory 21
ADC14MEM21
ECh
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Table 6-31. Precision ADC Registers (Base Address: 0x4001_2000) (continued)
REGISTER NAME
ACRONYM
OFFSET
Memory 22
ADC14MEM22
F0h
Memory 23
ADC14MEM23
F4h
Memory 24
ADC14MEM24
F8h
Memory 25
ADC14MEM25
FCh
Memory 26
ADC14MEM26
100
Memory 27
ADC14MEM27
104
Memory 28
ADC14MEM28
108
Memory 29
ADC14MEM29
10C
Memory 30
ADC14MEM30
110h
Memory 31
ADC14MEM31
114h
Interrupt Enable 0
ADC14IER0
13Ch
Interrupt Enable 1
ADC14IER1
140h
Interrupt Flag 0
ADC14IFGR0
144h
Interrupt Flag 1
ADC14IFGR1
148h
Clear Interrupt Flag 0
ADC14CLRIFGR0
14Ch
Clear Interrupt Flag 1
ADC14CLRIFGR1
150h
Interrupt Vector
ADC14IV
154h
Table 6-32. LCD_F Registers (Base Address: 0x4001_2400)
REGISTER NAME
ACRONYM
OFFSET
Control
LCDCTL
00h
Blinking and memory control
LCDBMCTL
04h
Voltage control
LCDVCTL
08h
Port control 0
LCDPCTL0
0Ch
Port control 1
LCDPCTL1
10h
COM/SEG select register 0
LCDCSSEL0
14h
COM/SEG select register 1
LCDCSSEL1
18h
Animation Control Register
LCDANMCTL
1Ch
Interrupt enable register
LCDIE
110h
Interrupt flag register
LCDIFG
114h
Set interrupt flag register
LCDSETIFG
118h
Clear interrupt flag register
LCDCLRIFG
11Ch
Memory 0 (L0)
LCDM0
120h
Memory 1 (L1)
LCDM1
121h
Memory 2 (L2)
LCDM2
122h
Memory 3 (L3)
LCDM3
123h
Memory 4 (L4)
LCDM4
124h
Memory 5 (L5)
LCDM5
125h
Memory 6 (L6)
LCDM6
126h
Memory 7 (L7)
LCDM7
127h
Memory 8 (L8)
LCDM8
128h
Memory 9 (L9)
LCDM9
129h
Memory 10 (L10)
LCDM10
12Ah
Memory 11 (L11)
LCDM11
12Bh
Memory 12 (L12)
LCDM12
12Ch
Memory 13 (L13)
LCDM13
12Dh
Memory 14 (L14)
LCDM14
12Eh
116
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-32. LCD_F Registers (Base Address: 0x4001_2400) (continued)
REGISTER NAME
ACRONYM
OFFSET
Memory 15 (L15)
LCDM15
12Fh
Memory 16 (L16)
LCDM16
130h
Memory 17 (L17)
LCDM17
131h
Memory 18 (L18)
LCDM18
132h
Memory 19 (L19)
LCDM19
133h
Memory 20 (L20)
LCDM20
134h
Memory 21 (L21)
LCDM21
135h
Memory 22 (L22)
LCDM22
136h
Memory 23 (L23)
LCDM23
137h
Memory 24 (L24)
LCDM24
138h
Memory 25 (L25)
LCDM25
139h
Memory 26 (L26)
LCDM26
13Ah
Memory 27 (L27)
LCDM27
13Bh
Memory 28 (L28)
LCDM28
13Ch
Memory 29 (L29)
LCDM29
13Dh
Memory 30 (L30)
LCDM30
13Eh
Memory 31 (L31)
LCDM31
13Fh
Memory 32 (L32)
LCDM32
140h
Memory 33 (L33)
LCDM33
141h
Memory 34 (L34)
LCDM34
142h
Memory 35 (L35)
LCDM35
143h
Memory 36 (L36)
LCDM36
144h
Memory 37 (L37)
LCDM37
145h
Memory 38 (L38)
LCDM38
146h
Memory 39 (L39)
LCDM39
147h
Memory 40 (L40)
LCDM40
148h
Memory 41 (L41)
LCDM41
149h
Memory 42 (L42)
LCDM42
14Ah
Memory 43 (L43)
LCDM43
14Bh
Memory 44 (L44)
LCDM44
14Ch
Memory 45 (L45)
LCDM45
14Dh
Memory 46 (L46)
LCDM46
14Eh
Memory 47 (L47)
LCDM47
14Fh
Blinking memory 0 (L0)
LCDBM0
160h
Blinking memory 1 (L1)
LCDBM1
161h
Blinking memory 2 (L2)
LCDBM2
162h
Blinking memory 3 (L3)
LCDBM3
163h
Blinking memory 4 (L4)
LCDBM4
164h
Blinking memory 5 (L5)
LCDBM5
165h
Blinking memory 6 (L6)
LCDBM6
166h
Blinking memory 7 (L7)
LCDBM7
167h
Blinking memory 8 (L8)
LCDBM8
168h
Blinking memory 9 (L9)
LCDBM9
169h
Blinking memory 10 (L10)
LCDBM10
16Ah
Blinking memory 11 (L11)
LCDBM11
16Bh
Blinking memory 12 (L12)
LCDBM12
16Ch
Blinking memory 13 (L13)
LCDBM13
16Dh
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Table 6-32. LCD_F Registers (Base Address: 0x4001_2400) (continued)
REGISTER NAME
ACRONYM
OFFSET
Blinking memory 14 (L14)
LCDBM14
16Eh
Blinking memory 15 (L15)
LCDBM15
17Fh
Blinking memory 16 (L16)
LCDBM16
170h
Blinking memory 17 (L17)
LCDBM17
171h
Blinking memory 18 (L18)
LCDBM18
172h
Blinking memory 19 (L19)
LCDBM19
173h
Blinking memory 20 (L20)
LCDBM20
174h
Blinking memory 21 (L21)
LCDBM21
175h
Blinking memory 22 (L22)
LCDBM22
176h
Blinking memory 23 (L23)
LCDBM23
177h
Blinking memory 24 (L24)
LCDBM24
178h
Blinking memory 25 (L25)
LCDBM25
179h
Blinking memory 26 (L26)
LCDBM26
17Ah
Blinking memory 27 (L27)
LCDBM27
17Bh
Blinking memory 28 (L28)
LCDBM28
17Ch
Blinking memory 29 (L29)
LCDBM29
17Dh
Blinking memory 30 (L30)
LCDBM30
17Eh
Blinking memory 31 (L31)
LCDBM31
17Fh
Blinking memory 32 (L32)
LCDBM32
180h
Blinking memory 33 (L33)
LCDBM33
181h
Blinking memory 34 (L34)
LCDBM34
182h
Blinking memory 35 (L35)
LCDBM35
183h
Blinking memory 36 (L36)
LCDBM36
184h
Blinking memory 37 (L37)
LCDBM37
185h
Blinking memory 38 (L38)
LCDBM38
186h
Blinking memory 39 (L39)
LCDBM39
187h
Blinking memory 40 (L40)
LCDBM40
188h
Blinking memory 41 (L41)
LCDBM41
189h
Blinking memory 42 (L42)
LCDBM42
18Ah
Blinking memory 43 (L43)
LCDBM43
18Bh
Blinking memory 44 (L44)
LCDBM44
18Ch
Blinking memory 45 (L45)
LCDBM45
18Dh
Blinking memory 46 (L46)
LCDBM46
18Eh
Blinking memory 47 (L47)
LCDBM47
18Fh
Animation memory 0
LCDANM0
1A0h
Animation memory 1
LCDANM1
1A1h
Animation memory 2
LCDANM2
1A2h
Animation memory 3
LCDANM3
1A3h
Animation memory 4
LCDANM4
1A4h
Animation memory 5
LCDANM5
1A5h
Animation memory 6
LCDANM6
1A6h
Animation memory 7
LCDANM7
1A7h
118
Detailed Description
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6.3.3.2
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Peripheral Bit Band Alias Region
The 32-MB region from 0x4200_0000 to 0x43FF_FFFF forms the bit-band alias region for the 1MB
Peripheral region. Bit-banding is a feature of the Cortex-M4 processor and allows the application to
set/clear individual bits throughout the peripheral memory space without using the pipeline bandwidth of
the processor to carry out an exclusive read-modify-write sequence.
NOTE
The restriction of accessing 16-bit peripherals only through byte or half-word accesses also
applies to the corresponding bit-band region of these peripherals. In other words, writes to
the bit-band alias region for these peripherals must be in the form of byte or half-word
accesses only.
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Debug and Trace Peripheral Zone
This zone maps the internal and external PPB regions of the Cortex-M4. The following peripherals are
mapped to this zone:
• Core and System debug control registers (internal PPB)
• NVIC and other registers in the System Control space of the Cortex-M4 (internal PPB)
• FPB, DWT, ITM (internal PPB)
• TPIU, Debug ROM table (external PPB)
• Reset Controller (external PPB)
• System Controller (external PPB)
Table 6-33. Debug Zone Memory Map
ADDRESS RANGE
MODULE OR PERIPHERAL
REMARKS
0xE000_0000 to 0xE000_0FFF
ITM
Internal PPB
0xE000_1000 to 0xE000_1FFF
DWT
Internal PPB
0xE000_2000 to 0xE000_2FFF
FPB
Internal PPB
0xE000_3000 to 0xE000_DFFF
Reserved
Internal PPB
0xE000_E000 to 0xE000_EFFF
Cortex-M4 System Control Space
Internal PPB
0xE000_F000 to 0xE003_FFFF
Reserved
Internal PPB
0xE004_0000 to 0xE004_0FFF
TPIU
External PPB
0xE004_1000 to 0xE004_1FFF
Reserved
External PPB
0xE004_2000 to 0xE004_23FF
Reset Controller (see Table 6-34)
External PPB
0xE004_2400 to 0xE004_2FFF
Reserved
External PPB
0xE004_3000 to 0xE004_33FF
System Controller
External PPB
0xE004_3400 to 0xE004_3FFF
Reserved
External PPB
0xE004_4000 to 0xE004_43FF
System Controller
External PPB
External PPB
0xE004_4400 to 0xE00F_EFFF
Reserved
0xE00F_F000 to 0xE00F_FFFF
ROM Table (External PPB)
External PPB
0xE010_0000 to 0xFFFF_FFFF
Reserved
Vendor Space
NOTE
For the address maps of the Arm modules listed in Table 6-33, see Cortex-M4 technical
reference manual at www.arm.com.
Table 6-34. RSTCTL Registers
REGISTER NAME
ACRONYM
OFFSET
Reset Request
RSTCTL_RESET_REQ
000h
Hard Reset Status
RSTCTL_HARDRESET_STAT
004h
Hard Reset Status Clear
RSTCTL_HARDRESET_CLR
008h
Hard Reset Status Set
RSTCTL_HARDRESET_SET
00Ch
Soft Reset Status
RSTCTL_SOFTRESET_STAT
010h
Soft Reset Status Clear
RSTCTL_SOFTRESET_CLR
014h
Soft Reset Status Set
RSTCTL_SOFTRESET_SET
018h
PSS Reset Status
RSTCTL_PSSRESET_STAT
100h
PSS Reset Status Clear
RSTCTL_PSSRESET_CLR
104h
PCM Reset Status
RSTCTL_PCMRESET_STAT
108h
PCM Reset Status Clear
RSTCTL_PCMRESET_CLR
10Ch
Pin Reset Status
RSTCTL_PINRESET_STAT
110h
Pin Reset Status Clear
RSTCTL_PINRESET_CLR
114h
120
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Table 6-34. RSTCTL Registers (continued)
REGISTER NAME
ACRONYM
OFFSET
Reboot Reset Status
RSTCTL_REBOOTRESET_STAT
118h
Reboot Reset Status Clear
RSTCTL_REBOOTRESET_CLR
11Ch
CS Reset Status
RSTCTL_CSRESET_STAT
120h
CS Reset Status Clear
RSTCTL_CSRESET_CLR
124h
Table 6-35. SYSCTL_A Registers
REGISTER NAME
ACRONYM
OFFSET
Reboot Control
SYS_REBOOT_CTL
0000h
NMI Control and Status
SYS_NMI_CTLSTAT
0004h
Watchdog Reset Control
SYS_WDTRESET_CTL
0008h
Peripheral Halt Control
SYS_PERIHALT_CTL
000Ch
SRAM Size
SYS_SRAM_SIZE
0010h
SRAM Number of Banks
SYS_SRAM_NUMBANKS
0014h
SRAM Number of Blocks
SYS_SRAM_NUMBLOCKS
0018h
Flash Main Memory Size
SYS_MAINFLASH_SIZE
0020h
Flash Information Memory Size
SYS_INFOFLASH_SIZE
0024h
Digital I/O Glitch Filter Control
SYS_DIO_GLTFLT_CTL
0030h
IP Protected Secure Zone Data Access Unlock
SYS_SECDATA_UNLOCK
0040h
SRAM Bank Enable Control 0
SYS_SRAM_BANKEN_CTL0
0050h
SRAM Block Retention Control 0
SYS_SRAM_BLKRET_CTL0
0070h
SRAM Status
SYS_SRAM_STAT
0090h
Master Unlock
SYS_MASTER_UNLOCK
1000h
Boot Override Request 0
SYS_BOOTOVER_REQ0
1004h
Boot Override Request 1
SYS_BOOTOVER_REQ1
1008h
Boot Override Acknowledge
SYS_BOOTOVER_ACK
100Ch
Reset Request
SYS_RESET_REQ
1010h
Reset Status and Override
SYS_RESET_STATOVER
1014h
System Status
SYS_SYSTEM_STAT
1020h
6.4
Memories on MSP432P4x1x
MSP432P4x1x devices include flash memory and SRAM for general-application purposes. In addition, the
devices include a backup memory (a portion of total available SRAM) that is retained in low-power modes.
6.4.1
Flash Memory
MSP432P4x1x devices include a high-endurance low-power flash memory that supports up to a minimum
of 20000 write or erase cycles. The flash memory is 128 bits wide, thereby enabling high code execution
performance by virtue of each fetch returning up to four 32-bit instructions (or up to eight 16-bit
instructions). The flash is further divided into two types of subregions: Main Memory and Information
Memory.
From a physical perspective the flash memory comprises of two banks, with the main and information
memory regions divided equally between the two banks. This permits an application to carry out a
simultaneous read or execute operation from one bank while the other bank may be undergoing a
program or erase operation.
The memory map of flash on MSP432P4x1x devices is shown in Figure 6-5.
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0x003F_FFFF
Reserved
0x0020_8000
Information
Memory
0x0020_0000
Main Memory
0x0000_0000
Figure 6-5. Flash Memory Map
6.4.1.1
Flash Main Memory (0x0000_0000 to 0x001F_FFFF)
The flash main memory on MSP432P4x1x devices can be up to 2MB. Flash main memory consists of up
to 512 sectors of 4KB each, with a minimum erase granularity of 4KB (1 sector). The main memory can be
viewed as two independent identical banks of up to 1MB each, allowing simultaneous read or execute
from one bank while the other bank is undergoing a program or erase operation.
6.4.1.2
Flash Information Memory (0x0020_0000 to 0x0020_7FFF)
The flash information memory region is 32KB. Flash information memory consists of eight sectors of 4KB
each, with a minimum erase granularity of 4KB (1 sector). The information memory can be viewed as two
independent blocks of 16KB each, which allows read or execute from one block while the other block is
undergoing a program or erase operation. Table 6-36 describes different regions of flash information
memory and the contents of each of the regions. The flash information memory region that contains the
device descriptor (TLV) is factory configured for protection against write or erase operations. Flash
information memory sectors that are empty are available for user application.
Table 6-36. Flash Information Memory Regions
122
WRITE AND ERASE
PROTECTED?
REGION
ADDRESS RANGE
CONTENTS
Bank 0, Sector 0
0x0020_0000 to 0x0020_0FFF
Flash Boot-override Mailbox
No
Bank 0, Sector 1
0x0020_1000 to 0x0020_1FFF
Device Descriptor (TLV)
Yes
Bank 0, Sector 2
0x0020_2000 to 0x0020_2FFF
TI BSL
No
Bank 0, Sector 3
0x0020_3000 to 0x0020_3FFF
TI BSL
No
Bank 1, Sector 0
0x0020_4000 to 0x0020_4FFF
Empty
No
Bank 1, Sector 1
0x0020_5000 to 0x0020_5FFF
Empty
No
Bank 1, Sector 2
0x0020_6000 to 0x0020_6FFF
Empty
No
Bank 1, Sector 3
0x0020_7000 to 0x0020_7FFF
Empty
No
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Flash Operation
The flash memory provides multiple read and program modes of operation that the application can deploy.
Up to 128 bits (memory word width) can be programmed (set from 1 to 0) in a single program operation.
Although the CPU data buses are 32 bits wide, the flash can buffer 128-bit write data before initiating flash
programming, thereby making it more seamless and power efficient for software to program large blocks
of data at a time. In addition, the flash memory also supports a burst write mode that takes less time when
compared to programming words individually. See Flash Memory for information on timing parameters.
The flash main and information memory regions offer write/erase protection control at a sector granularity
to enable software to optimize operations like mass erase while protecting certain regions of the flash. In
low-power modes of operation, the flash memory is disabled and put in a power-down state to minimize
leakage.
For details on the flash memory and its various modes of operation and configuration, see the Flash
Controller A (FLCTL_A) chapter in the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference
Manual .
NOTE
Depending on the CPU (MCLK) frequency and the active mode in use, the flash may need to
be accessed with single/multiple wait states. Whenever there is a change required in the
operating frequency, the application must ensure that the flash access wait states are
configured correctly before the frequency change is effected. See the electrical specification
for details on flash wait state requirements.
6.4.2
SRAM
MSP432P4x1x devices support up to 256KB of SRAM, with the rest of the 1-MB SRAM region reserved.
The SRAM is aliased in both Code and SRAM zones. This enables fast, single cycle execution of code
from the SRAM, as the Cortex-M4 processor pipelines instruction fetches to memory zones other than the
Code space. As with the flash memory, the SRAM can be powered down or placed in a low-leakage
retention state in low-power modes of operation.
Figure 6-6 shows the memory map of SRAM on MSP432P4x1x devices.
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SRAM Zone
CODE Zone
0x010F_FFFF
0x3FFF_FFFF
Reserved
Reserved
0x2280_0000
SRAM
Bit-Band Alias
Region
0x0104_0000
0x2200_0000
Reserved
SRAM Region
0x2004_0000
SRAM Region
0x0100_0000
0x2000_0000
Figure 6-6. SRAM Map
6.4.2.1
SRAM Bank Enable Configuration
The application can optimize the power consumption of the SRAM. To enable this, the SRAM is divided
into 64-KB banks that can be individually powered down. Banks that are powered down remain powered
down in both active and low-power modes of operation, thereby limiting any unnecessary inrush current
when the device transitions between active and retention-based low-power modes. The application can
also disable one (or more) banks for a certain stage in the processing and enable it for another stage.
When a particular bank is disabled, reads to its address space return 0h, and writes are discarded. To
prevent holes in the memory map, if a particular bank is enabled, all the lower banks are also forced to
enabled. This ensures a contiguous memory map through the set of enabled banks instead of a allowing a
disabled bank to appear between enabled banks. For example:
• If there are four banks in the device, the valid combinations of the BNKxx_EN fields in the
SYS_SRAM_BANKEN_CTL0 register are 0001, 0011, 0111, and 1111.
• Other combination of BNKxx_EN fields like 1011 are not valid, and the resultant bank configuration is
automatically set to 1111.
Figure 6-7 shows valid and invalid combinations of the bank enable fields.
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BNK3_EN = 0
BNK3_EN = 0
BNK3_EN = 0
BNK3_EN = 1
BNK2_EN = 0
BNK2_EN = 0
BNK2_EN = 1
BNK2_EN = 1
BNK1_EN = 0
BNK1_EN = 1
BNK1_EN = 1
BNK1_EN = 1
BNK0_EN = 1
BNK0_EN = 1
BNK0_EN = 1
BNK0_EN = 1
Valid SRAM bank enables for SRAM with 4 banks
BNK3_EN = 0
BNK3_EN = 0
BNK2_EN = 1
BNK2_EN = 1
BNK1_EN = 0
BNK1_EN = 1
BNK0_EN = 1
BNK0_EN = 1
Invalid BNKx_EN setting
Valid BNKx_EN setting
Conversion of invalid bank enables to valid setting
Figure 6-7. Configuring SRAM Bank Enables
Bank 0 of SRAM is always enabled and cannot be disabled. For all other banks, any enable or disable
change results in the BNKEN_RDY bit of the SYS_SRAM_STAT register being set to 0 until the
configuration change is effective. Any accesses to the SRAM is stalled during this time, and access
resumes only after the SRAM banks are ready for read or write operations. This is handled transparently
and does not require any code intervention. See SRAM characteristics in the electrical specification for the
SRAM bank enable or disable latency.
6.4.2.2
SRAM Block Retention Configuration and Backup Memory
The application can optimize the leakage power consumption of the SRAM in LPM3 and LPM4 modes of
operation. To enable this, each SRAM bank is further divided into 8-KB blocks that can be individually
configured for retention. Blocks that are enabled for retention retain their data through the LPM3 and
LPM4 modes. The application can also retain a subset of the blocks in the enabled banks.
For example, the application may need 128KB of SRAM for its processing needs (two banks are kept
enabled). However, of these two banks, only one 8-KB block can contain critical data that must be
retained in LPM3 or LPM4, while the rest are powered off completely to minimize power consumption.
Block 0 of SRAM Bank 0 is always retained and cannot be powered down. Therefore, it also operates as a
possible backup memory in the LPM3, LPM4, and LPM3.5 modes of operation.
6.4.3
Utility SRAM
MSP432P4x1x devices support an additional 2KB of utility SRAM space in the peripheral memory map
region. This space can be used by the application for storing any application related data (for example,
DMA descriptors).
6.4.4
ROM
MSP432P4x1x devices support 32KB of ROM, with the rest of the 1-MB region reserved (for future
upgrades). The lower 2KB of the ROM is reserved for TI internal purposes and accesses to this space
return an error response. The rest of the ROM is used for driver libraries.
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NOTE
The entire ROM region returns an error response for write accesses. The lower 2KB of the
ROM always returns an error response for any access.
6.5
DMA
MSP432P4x1x devices implement an 8-channel Arm µDMA. This allows eight simultaneously active
channels for data transfer between memory and peripherals without needing to use the bandwidth of the
CPU (thereby reducing power by idling the CPU when there is no data processing required). In addition,
the DMA remains active in multiple low-power modes of operation, allowing for a very low power state in
which data can be transferred at low rates.
For maximum flexibility, up to eight DMA event sources can map to any of the eight channels. This is
controlled through configuration registers in the DMA. In addition, the DMA can generate up to four
interrupt requests (described in Section 6.5.2). For details regarding configuration of the DMA, see the
DMA chapter in the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual.
6.5.1
DMA Source Mapping
Each channel of the eight available channels has a control register that can select any of the device-level
DMA sources as the final source for that corresponding channel. Table 6-37 lists the sources available for
mapping to each channel, based on the value of the Source Config Register (SRCCFG).
Table 6-37. DMA Sources
CHANNEL
SRCCFG
0
1
2
3
4
5
6
7
0
Reserved
eUSCI_A0 TX
eUSCI_B0 TX0
eUSCI_B3 TX1
eUSCI_B2 TX2
eUSCI_B1 TX3
TA0CCR0
AES256_Trigger0
1
Reserved
eUSCI_A0 RX
eUSCI_B0 RX0
eUSCI_B3 RX1
eUSCI_B2 RX2
eUSCI_B1 RX3
TA0CCR2
AES256_Trigger1
2
Reserved
eUSCI_A1 TX
eUSCI_B1 TX0
eUSCI_B0 TX1
eUSCI_B3 TX2
eUSCI_B2 TX3
TA1CCR0
AES256_Trigger2
3
Reserved
eUSCI_A1 RX
eUSCI_B1 RX0
eUSCI_B0 RX1
eUSCI_B3 RX2
eUSCI_B2 RX3
TA1CCR2
Reserved
4
Reserved
eUSCI_A2 TX
eUSCI_B2 TX0
eUSCI_B1 TX1
eUSCI_B0 TX2
eUSCI_B3 TX3
TA2CCR0
Reserved
5
Reserved
eUSCI_A2 RX
eUSCI_B2 RX0
eUSCI_B1 RX1
eUSCI_B0 RX2
eUSCI_B3 RX3
TA2CCR2
Reserved
6
Reserved
eUSCI_A3 TX
eUSCI_B3 TX0
eUSCI_B2 TX1
eUSCI_B1 TX2
eUSCI_B0 TX3
TA3CCR0
DMAE0
(External Pin)
7
Reserved
eUSCI_A3 RX
eUSCI_B3 RX0
eUSCI_B2 RX1
eUSCI_B1 RX2
eUSCI_B0 RX3
TA3CCR2
Precision ADC
NOTE
Any source marked as Reserved is unused. It may be used for software-controlled DMA
tasks, but typically it is reserved for enhancement purposes on future devices.
6.5.2
DMA Completion Interrupts
In the case of the Arm µDMA controller, it is usually the responsibility of software to maintain a list of
channels that have completed their operation. To provide further flexibility, MSP432P4x1x DMA supports
four DMA completion interrupts, which are mapped in the following way:
• DMA_INT0: Logical OR of all completion events except those that are already mapped to DMA_INT1,
DMA_INT2, or DMA_INT3.
• DMA_INT1, DMA_INT2, DMA_INT3: Can be mapped to the DMA completion event of any of the eight
channels.
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NOTE
Software must make sure that DMA_INT1, DMA_INT2, and DMA_INT3 are mapped to
different channels, so that the same channel does not result in multiple interrupts at the
NVIC.
6.5.3
DMA Access Privileges
The DMA has access to all of the memories and peripheral configuration interfaces of the device. If the
device is configured for IP protection, DMA access to the flash is restricted to only bank 1 of the flash
main and information memory regions. This restriction prevents the DMA from being used as an
unauthorized access source into bank 0 of the flash, where secure data regions are housed.
6.6
Memory Map Access Details
The bus system on MSP432P4x1x devices incorporates four masters, which can initiate various types of
transactions:
• ICODE: Cortex-M4 instruction fetch bus. Accesses the Code zone only
• DCODE: Cortex-M4 data and literal load/store bus. Accesses the Code zone only. Debugger accesses
to Code zone also appear on this bus.
• SBUS: Cortex-M4 data read and write bus. Accesses to all zones except Code zones and PPB
memory space only. Debugger accesses to this space also appear on this bus.
• DMA: Access to all zones except the PPB memory space
NOTE
The PPB space is dedicated only to the Cortex-M4 Private Peripheral Bus.
6.6.1
Master and Slave Access Priority Settings
Table 6-38 lists all the available masters (rows) and their access permissions to slaves (columns). If
multiple masters can access one slave, the table lists access priorities if arbitration is required. A lower
number in the table indicates a higher arbitration priority (the priority is always fixed).
Table 6-38. Master and Slave Access Priority
FLASH MEMORY
ROM
SRAM
PERIPHERALS
3
2
4
NA
1
2
NA
NA
3
2
ICODE
DCODE
(1)
(2)
(3)
2
(1)
SBUS
NA
DMA
1
(2)
NA
1
(3)
1
Access from the DCODE to flash memory may be restricted if the device is operating in a secure
mode
Access from DMA to flash memory is restricted to Bank 1 if the device is operating in a secure mode
with IP protection enabled. In such cases, access to Bank 0 returns an error response
Although the SRAM is mapped to both Code and System spaces, accesses from DMA to SRAM must
use the System space addressing only.
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6.6.2
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Memory Map Access Response
Table 6-39 summarizes the access responses to the entire memory map of MSP432P4x1x devices.
Table 6-39. Memory Map Access Response
ADDRESS RANGE
DESCRIPTION
0x0000_0000 to 0x001F_FFFF
Flash Main Memory
(3)
(4)
(5)
6.7
(1)
OK
WRITE
OK
(1)
(2) (3)
,
OK
(3)
INSTRUCTION
FETCH (1)
OK
0x0020_0000 to 0x0020_7FFF
Flash Information Memory
OK
0x0020_8000 to 0x00FF_FFFF
Reserved
Error
Error
Error
0x0100_0000 to 0x0103_FFFF
SRAM
OK
OK
OK
0x0104_0000 to 0x01FF_FFFF
Reserved
Error
Error
Error
0x0200_0000 to 0x0200_07FF
ROM (Reserved)
Error
Error
Error
0x0200_0800 to 0x0200_7FFF
ROM
OK
Error
OK
0x0200_8000 to 0x1FFF_FFFF
Reserved
Error
Error
Error
OK
0x2000_0000 to 0x2003_FFFF
SRAM
OK
OK
OK
0x2004_0000 to 0x21FF_FFFF
Reserved
Error
Error
Error
0x2200_0000 to 0x23FF_FFFF
SRAM bit-band alias
OK
Error
OK
(4)
0x2400_0000 to 0x3FFF_FFFF
Reserved
Error
Error
Error
0x4000_0000 to 0x4001_FFFF
Peripheral
OK
OK
Error
0x4002_0000 to 0x41FF_FFFF
Reserved
Error
Error
Error
0x4200_0000 to 0x43FF_FFFF
Peripheral bit-band alias
0x4400_0000 to 0xDFFF_FFFF
Reserved
0xE000_0000 to 0xE003_FFFF
Internal PPB
OK
Error
Error
Error
OK
OK
Error
TPIU (External PPB)
OK
OK
Error
0xE004_1000 to 0xE004_1FFF
Reserved
Reserved
Reserved
Error
0xE004_2000 to 0xE004_23FF
Reset Controller (External
PPB)
OK
OK
Error
0xE004_2400 to 0xE004_2FFF
Reserved
Reserved
Reserved
Error
0xE004_3000 to 0xE004_33FF
SYSCTL_A (External PPB)
OK
OK
Error
0xE004_3400 to 0xE004_3FFF
Reserved
Reserved
Reserved
Error
0xE004_4000 to 0xE004_43FF
SYSCTL_A (External PPB)
OK
OK
Error
(5)
OK
(4)
Error
0xE004_0000 to 0xE004_0FFF
(1)
(2)
READ
0xE004_4400 to 0xE00F_EFFF
Reserved
Reserved
Reserved
Error
0xE00F_F000 to 0xE00F_FFFF
ROM Table (External PPB)
OK
OK
Error
0xE010_0000 to 0xFFFF_FFFF
Reserved
Error
Error
Error
A reserved memory region returns 0h on reads and instruction fetches. Writes to this region are ignored.
If the user memory address is part of a secure region, this access returns an error if it is initiated by an unauthorized source. For more
details, see the device security application note.
Writes to this address are ignored if the sector has write protection enabled.
Reads from the bit-band region return 00h if the bit is clear and 01h if the bit is set.
See the Cortex-M4 technical reference manual at www.arm.com for details of the memory map of the internal PPB.
Interrupts
The Cortex-M4 processor on MSP432P4x1x devices implements an NVIC with 64 external interrupt lines
and 8 levels of priority. From an application perspective, the interrupt sources at the device level are
divided into two classes, the NMI and the User Interrupts. Internally, the CPU exception model handles the
various exceptions (internal and external events including CPU instruction, memory, and bus fault
conditions) in a fixed and configurable order of priority. For details on the handling of various exception
priorities (including CPU reset and fault models), see the Arm-V7M architecture reference manual at
www.arm.com.
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6.7.1
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NMI
The NMI input of the NVIC has the following possible sources:
• External NMI pin (if configured in NMI mode)
• Oscillator fault condition
• Power Supply System (PSS) generated interrupts
• Power Control Manager (PCM) generated interrupts
6.7.2
Device-Level User Interrupts
Table 6-40 lists the various interrupt sources and their connection to the NVIC inputs.
NOTE
Some sources may have multiple interrupt conditions, in which case the appropriate interrupt
status/flag register of the source must be examined to differentiate between the generating
conditions.
Table 6-40. NVIC Interrupts
NVIC INTERRUPT INPUT
(2)
FLAGS IN SOURCE
(1)
PSS
INTISR[1]
CS
INTISR[2]
PCM
INTISR[3]
WDT_A
INTISR[4]
(1)
SOURCE
INTISR[0]
(1)
(1)
FPU_INT
(2)
Combined interrupt from flags in the FPSCR (part of Cortex-M4 FPU)
INTISR[5]
FLCTL_A
FLCTL_A interrupt flags
INTISR[6]
COMP_E0
Comparator_E0 interrupt flags
INTISR[7]
COMP_E1
Comparator_E1 interrupt flags
INTISR[8]
Timer_A0
TA0CCTL0.CCIFG
INTISR[9]
Timer_A0
TA0CCTLx.CCIFG (x = 1 to 4), TA0CTL.TAIFG
INTISR[10]
Timer_A1
TA1CCTL0.CCIFG
INTISR[11]
Timer_A1
TA1CCTLx.CCIFG (x = 1 to 4), TA1CTL.TAIFG
INTISR[12]
Timer_A2
TA2CCTL0.CCIFG
INTISR[13]
Timer_A2
TA2CCTLx.CCIFG (x = 1 to 4), TA2CTL.TAIFG
INTISR[14]
Timer_A3
TA3CCTL0.CCIFG
INTISR[15]
Timer_A3
TA3CCTLx.CCIFG (x = 1 to 4), TA3CTL.TAIFG
INTISR[16]
eUSCI_A0
UART or SPI mode TX, RX, and status flags
INTISR[17]
eUSCI_A1
UART or SPI mode TX, RX, and status flags
INTISR[18]
eUSCI_A2
UART or SPI mode TX, RX, and status flags
INTISR[19]
eUSCI_A3
UART or SPI mode TX, RX, and status flags
INTISR[20]
eUSCI_B0
SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)
INTISR[21]
eUSCI_B1
SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)
INTISR[22]
eUSCI_B2
SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)
INTISR[23]
eUSCI_B3
SPI or I2C mode TX, RX, and status flags (I2C in multiple-slave mode)
INTISR[24]
Precision ADC
IFG[0-31], LOIFG, INIFG, HIIFG, RDYIFG, OVIFG, TOVIFG
INTISR[25]
Timer32_INT1
Timer32 interrupt for Timer 1
INTISR[26]
Timer32_INT2
Timer32 interrupt for Timer 2
INTISR[27]
Timer32_INTC
Timer32 combined interrupt
This source can also be mapped to the system NMI. See the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual
for more details.
The FPU of the Cortex-M4 can generate interrupts due to multiple floating-point exceptions. It is the responsibility of software to process
and clear the interrupt flags in the FPSCR.
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Table 6-40. NVIC Interrupts (continued)
NVIC INTERRUPT INPUT
SOURCE
FLAGS IN SOURCE
INTISR[28]
AES256
AESRDYIFG
INTISR[29]
RTC_C
OFIFG, RDYIFG, TEVIFG, AIFG, RT0PSIFG, RT1PSIFG
INTISR[30]
DMA_ERR
DMA error interrupt
INTISR[31]
DMA_INT3
DMA completion interrupt 3
INTISR[32]
DMA_INT2
DMA completion interrupt 2
INTISR[33]
DMA_INT1
DMA completion interrupt 1
INTISR[34]
(3)
DMA_INT0
(3)
DMA completion interrupt 0
INTISR[35]
I/O Port P1
P1IFG.x (x = 0 to 7)
INTISR[36]
I/O Port P2
P2IFG.x (x = 0 to 7)
INTISR[37]
I/O Port P3
P3IFG.x (x = 0 to 7)
INTISR[38]
I/O Port P4
P4IFG.x (x = 0 to 7)
INTISR[39]
I/O Port P5
P5IFG.x (x = 0 to 7)
INTISR[40]
I/O Port P6
P6IFG.x (x = 0 to 7)
INTISR[41]
LCD_F
LCD interrupt flags
INTISR[42]
Reserved
INTISR[43]
Reserved
INTISR[44]
Reserved
INTISR[45]
Reserved
INTISR[46]
Reserved
INTISR[47]
Reserved
INTISR[48]
Reserved
INTISR[49]
Reserved
INTISR[50]
Reserved
INTISR[51]
Reserved
INTISR[52]
Reserved
INTISR[53]
Reserved
INTISR[54]
Reserved
INTISR[55]
Reserved
INTISR[56]
Reserved
INTISR[57]
Reserved
INTISR[58]
Reserved
INTISR[59]
Reserved
INTISR[60]
Reserved
INTISR[61]
Reserved
INTISR[62]
Reserved
INTISR[63]
Reserved
DMA_INT0 has a different functionality from DMA_INT1, DMA_INT2, or DMA_INT3. See Section 6.5.2 for more details.
NOTE
The Interrupt Service Routine (ISR) must ensure that the relevant interrupt flag in the source
peripheral is cleared before returning from the ISR. If this is not done, the same interrupt
may be incorrectly triggered again as a new event, even though the event has already been
processed by the ISR. As there may be a few cycles of delay between the execution of the
write command and the actual write reflecting in the interrupt flag register of the peripheral,
TI recommends performing the write and waiting for a few cycles before exiting the ISR.
Alternatively, the application can read the flag to ensure that it is cleared before exiting the
ISR.
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6.8
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
System Control
System Control comprises the modules that govern the overall behavior of the device, including power
management, operating modes, clocks, reset handling, and user configuration settings.
6.8.1
Device Resets
MSP432P4x1x devices support multiple classes of reset. Each class results in a different level of initiation
of device logic, thus allowing the application developer to initiate different resets based reset requirements
during code development and debug. The following subsections cover the classes of reset in the device.
6.8.1.1
Power On/Off Reset (POR)
The POR initiates a complete initialization of the application settings and device configuration information.
This class of reset may be initiated either by the PSS, the PCM, the RSTn pin, the Clock System upon
DCO external resistor short-circuit fault, or the device emulation logic (through the debugger). From an
application perspective, all sources of POR return the device to the same state of initialization.
NOTE
Depending on the source of the reset, the device may exhibit different wake-up latencies
from the POR. This implementation enables optimization of the reset recovery time.
6.8.1.2
Reboot Reset
The Reboot Reset is identical to the POR and allows the application to emulate a POR class reset without
needing to reset the device or activate the RSTn pin. A Reboot Reset can also be initiated through the
debugger and, hence, does not affect the debug connection to the device, while a POR terminates the
debug connection.
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Hard Reset
The hard reset resets all modules that are set up or modified by the application. This includes all
peripherals and the nondebug logic of the Cortex-M4. MSP432P4x1x devices support up to 16 sources of
hard reset. Table 6-41 lists the reset source allocation. The Reset Controller registers can be used to
identify the source of reset in the device. For further details, see the Reset Controller chapter in the
MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual.
Table 6-41. MSP432P4x1x Hard Reset Sources
RESET SOURCE
NUMBER
SOURCE
0
SYSRESETREQ (system reset output of Cortex-M4)
(1)
(2)
(3)
(4)
(5)
132
(1)
1
WDT_A time-out
2
WDT_A password violation
3
FLCTL_A
(2)
4
Reserved
(3)
5
Reserved
(3)
6
Reserved
(3)
7
Reserved
(3)
8
Reserved
(3)
9
Reserved
(3)
10
Reserved
(3)
11
Reserved
(3)
12
Reserved
(3)
13
Reserved
(3)
14
CS
(4)
15
PCM
(1)
(5)
The WDT_A generated resets can be mapped either as a hard reset or a soft reset.
The flash controller can generate a reset if a voltage anomaly is detected that can corrupt only flash
reads and not the rest of the system.
Reserved indicates that this source of hard reset is currently unused and left for future expansion.
The CS cannot initiate a hard reset, but if a hard reset occurs during clock source or frequency
changes, the CS can extend the reset to allow the clocks to settle before releasing the system. This
reduces the chance of nondeterministic behavior.
The PCM cannot initiate a hard reset, but if a hard reset causes power mode changes, the PCM can
extend the reset to allow the system to settle before releasing the Reset. This reduces the chance of
nondeterministic behavior.
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6.8.1.4
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Soft Reset
The soft reset resets only the execution component of the system, which is the nondebug logic in the
Cortex-M4 and the WDT_A. This reset remains nonintrusive to all other peripherals and system
components. MSP432P4x1x devices support up to 16 sources of soft reset. Table 6-42 lists the reset
source allocation. The Reset Controller registers can be used to identify the source of reset in the design.
For further details, see the Reset Controller chapter in the MSP432P4xx SimpleLink™ Microcontrollers
Technical Reference Manual.
Table 6-42. MSP432P4x1x Soft Reset Sources
RESET SOURCE
NUMBER
SOURCE
0
CPU LOCKUP condition (LOCKUP output of Cortex-M4)
(1)
(2)
(1)
1
WDT_A time-out
2
WDT_A password violation
3
Reserved
(2)
4
Reserved
(2)
5
Reserved
(2)
6
Reserved
(2)
7
Reserved
(2)
8
Reserved
(2)
9
Reserved
(2)
10
Reserved
(2)
11
Reserved
(2)
12
Reserved
(2)
13
Reserved
(2)
14
Reserved
(2)
15
Reserved
(2)
(1)
The WDT_A generated resets can be mapped either as a hard reset or a soft reset.
Reserved indicates that this source of soft reset is currently unused and left for future expansion.
NOTE
To support and enhance debug of reset conditions, the Reset Controller is located on the
PPB of the device. This allows the Reset Controller to remain accessible even if the device is
stuck in a hard or soft reset state. The Reset Controller permits overrides for hard and soft
resets, thereby allowing an application to regain control of the device and isolate the cause
of the stuck reset.
6.8.2
Power Supply System (PSS)
The PSS controls all the power supply related functionality of the device. The PSS consists of the
components in the following sections.
6.8.2.1
VCCDET
The VCCDET monitors the input voltage applied at the DVCC and AVCC pins of the device. When the
VCC is found to be below the operating range of the VCCDET trip points, it generates a brownout
condition, thereby initiating a device reset (POR class reset).
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Supply Supervisor and Monitor for High Side (SVSMH)
The SVSMH supervises and monitors the VCC. SVSMH has a programmable threshold setting and can be
used by the application to generate a reset or an interrupt if the VCC dips below the desired threshold. In
supervisor mode, the SVSMH generates a device reset (POR class reset). In monitor mode, the SVSMH
generates an interrupt. The SVSMH can also be disabled if monitoring and supervision of the supply
voltage are not required (offers further power savings).
6.8.2.3
Core Voltage Regulator
MSP432P4x1x devices can be programmed to operate with either the LDO or the DC/DC as the voltage
regulator for the digital logic in the core domain of the device. The DC/DC offers significant boost in power
efficiency for high-current high-performance applications. The LDO is a highly efficient regulator that offers
power advantages at lower VCC ranges and in the ultra-low-power modes of operation.
The core operating voltage (output of the LDO or DC/DC) is automatically set by the device depending on
the selected operating mode of the device (see Table 6-43 for further details). The device offers seamless
switching between LDO and DC/DC operating modes and also implements a seamless DC/DC fail-safe
mechanism.
6.8.3
Power Control Manager (PCM)
The PCM controls the operating modes of the device and the switching between the modes. Mode
selection is controlled by the application, which can choose modes to meet its power and performance
requirements. Table 6-43 lists the operating modes of the device.
Table 6-43. MSP432P4x1x Operating Modes
OPERATING MODE
AM_LDO_VCORE0
LPM0_LDO_VCORE0
AM_LDO_VCORE1
DESCRIPTION
LDO-based active mode, medium performance, core voltage level 0
Same as AM_LDO_VCORE0, except that CPU is off (no code execution)
LDO-based active mode, maximum performance, core voltage level 1
LPM0_LDO_VCORE1
Same as AM_LDO_VCORE1, except that CPU is off (no code execution)
AM_DCDC_VCORE0
DC/DC-based active mode, medium performance, core voltage level 0
LPM0_DCDC_VCORE0
AM_DCDC_VCORE1
LPM0_DCDC_VCORE1
AM_LF_VCORE0
LPM0_LF_VCORE0
AM_LF_VCORE1
LPM0_LF_VCORE1
134
Same as AM_DCDC_VCORE0, except that CPU is off (no code execution)
DC/DC-based active mode, maximum performance, core voltage level 1
Same as AM_DCDC_VCORE1, except that CPU is off (no code execution)
LDO-based low-frequency active mode, core voltage level 0
Same as AM_LF_VCORE0, except that CPU is off (no code execution)
LDO-based low-frequency active mode, core voltage level 1
Same as AM_LF_VCORE1, except that CPU is off (no code execution)
LPM3_VCORE0
LDO-based low-power mode with full state retention, core voltage level 0. In addition to RTC_C and WDT_A,
other peripherals can be operational with an external or internal low-frequency clocks up to 128 kHz. See
Table 6-44 for peripherals that are available in this mode.
LPM3_VCORE1
LDO-based low-power mode with full state retention, core voltage level 1. In addition to RTC_C and WDT_A,
other peripherals can be operational with an external or internal low-frequency clocks up to 128 kHz. See
Table 6-44 for peripherals that are available in this mode.
LPM4_VCORE0
LDO-based low-power mode with full state retention, core voltage level 0.Peripherals can be operational out of
external clocks up to 128 kHz. See Table 6-44 for peripherals that are available in this mode.
LPM4_VCORE1
LDO-based low-power mode with full state retention, core voltage level 1.Peripherals can be operational out of
external clocks up to 128 kHz. See Table 6-44 for peripherals that are available in this mode.
LPM3.5
LDO-based low-power mode, core voltage level 0, no retention of peripheral registers, RTC_C and WDT_A can
be active
LPM4.5
Core voltage off, wakeup only through pin reset or wakeup-capable I/Os
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Peripherals in LPM3 and LPM4
Most peripherals in MSP432P4x1x devices can be activated in LPM3 out of low-frequency internal or
external clocks. LPM4 mode is LPM3 with peripherals not clocked from internal clock sources. Some
analog modules can be operational in LPM4, because they do not require a clock to operate (for example,
the comparator). Activating a peripheral in LPM3 or LPM4 increases the current consumption due to its
active supply current contribution but also due to an additional idle current. To limit the idle current adder,
certain peripherals are combined into power islands within the device. To achieve optimal current
consumption, use modules within one group and limit the number of groups with active modules. The
grouping is shown in Table 6-44 . Modules not listed in this table are either already included in the
standard LPM3 current consumption or cannot be used in LPM3 or LPM4. The idle current adder is very
small at room temperature (25°C) but increases at high temperatures (85°C); see the idle current
parameters in the electrical characteristics section for details.
Table 6-44. Peripheral Groups (PG)
PG1
Timer_A0
eUSCI_A0
eUSCI_B0
Clock output on pins
6.8.4
PG2
PG3
Timer_A1, Timer_A2
eUSCI_A1, eUSCI_A2, eUSCI_A3
eUSCI_B1, eUSCI_B2, eUSCI_B3
Timer_A3
Precision ADC
Comp_E0, Comp_E1
REF_A
LCD_F
Clock System (CS)
The CS contains the sources of the various clocks in the device and also controls the mapping between
sources and the clock domains in the device.
6.8.4.1
LFXT
The LFXT supports 32.768-kHz low-frequency crystals.
6.8.4.2
HFXT
The HFXT supports high-frequency crystals up to 48 MHz.
6.8.4.3
DCO
The DCO is a power-efficient tunable internal oscillator that generates up to 48 MHz. It also supports a
high-precision mode when using an external precision resistor.
6.8.4.4
Very Low-Power Low-Frequency Oscillator (VLO)
The VLO is an ultra-low-power internal oscillator that generates a low-accuracy clock at typical frequency
of 9.4 kHz.
6.8.4.5
Low-Frequency Reference Oscillator (REFO)
The REFO can be used as an alternate low-power lower-accuracy source of a 32.768-kHz clock instead of
the LFXT. REFO can also be programmed to generate a 128-kHz clock.
6.8.4.6
Module Oscillator (MODOSC)
The MODOSC is an internal clock source that has a very low latency wake-up time. MODOSC is factorycalibrated to a frequency of 25 MHz. The MODOSC is typically used to supply a clock on request to
modules like the ADC (when in 1-Msps conversion mode).
6.8.4.7
System Oscillator (SYSOSC)
The SYSOSC is a lower-frequency version of the MODOSC and is factory-calibrated to a frequency of 5
MHz. It drives the ADC sampling clock in the 200-ksps conversion mode. In addition, it is also used for
timing of various system-level control and management operations.
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Fail-Safe Mechanisms
All clock sources that operate with external components have a built-in fail-safe mechanism that
automatically switches to the relevant backup source, thereby ensuring that spurious or unstable clocks
never impact the device behavior. Table 6-45 lists the different types of clock source faults and the
corresponding fail-safe clocks.
Table 6-45. Fail-Safe Clocks
FAULT TYPE
136
FAIL-SAFE CLOCK
LFXT oscillator fault
REFO clock
HFXT oscillator fault
SYSOSC clock
DCO external resistor open-circuit fault
DCO clock in internal resistor mode
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6.8.5
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
System Controller (SYSCTL_A)
The SYSCTL_A is a set of various miscellaneous features of the device, including device memory
configuration, RSTn/NMI function selection, clock run/stop control, watchdog configuration for selecting
reset classes and device NMI source configuration and status. In addition, the SYSCTL_A enables device
security features like JTAG and SWD lock and IP protection, which can be used to protect unauthorized
accesses either to the entire device memory map or to certain selected regions of the flash.
NOTE
Like with the Cortex-M4 system control registers (in the internal PPB space), the System
Controller module registers are mapped to the Cortex-M4 external PPB. This keeps the
System Controller module accessible even when hard or soft resets are active.
6.9
Peripherals
The following sections describe the peripherals that are available on the MSP432P4x1x devices. For
details on these peripherals, see the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference
Manual.
6.9.1
Digital I/O
Up to 10 8-bit I/O ports are implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports
• Edge-selectable interrupt capability is available on ports P1 to P6.
• Wake-up capability from LPM3, LPM4, LPM3.5, and LPM4.5 modes on ports P1 to P6.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or in pairs (16-bit width).
• Capacitive Touch functionality is supported on all pins of ports P1 to P10 and PJ.
• Four 20-mA high-drive I/Os on pins P2.0 to P2.3
• Glitch filtering capability on selected digital I/Os
6.9.1.1
Glitch Filtering on Digital I/Os
Some of the interrupt and wake-up capable digital I/Os can suppress glitches through the use of analog
glitch filter to prevent unintentional interrupt or wake-up during device operation. The analog filter
suppresses a minimum of 250-ns wide glitches. The glitch filter on these selected digital I/Os is enabled
by default. If the glitch filtering capability is not required in the application, it can be bypassed using the
SYS_DIO_GLTFLT_CTL register. When GLTFLT_EN bit in this register is cleared, the glitch filters on all
the digital I/Os are bypassed. The glitch filter is automatically bypassed on a digital I/O when it is
configured for peripheral or analog functionality by programming the respective PySEL0.x and PySEL1.x
registers.
NOTE
The glitch filter is implemented on the following digital I/Os on MSP432P4x1x devices: P1.0,
P1.4, P1.5, P3.0, P3.4, P3.5, P6.6, and P6.7.
6.9.2
Port Mapping Controller (PMAPCTL)
The port mapping controller allows flexible and reconfigurable mapping of digital functions.
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
6.9.2.1
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Port Mapping Definitions
The port mapping controller on MSP432P4x1x devices allows reconfigurable mapping of digital functions
on ports P2, P3, and P7.
Table 6-46. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
1
PM_UCA0CLK
eUSCI_A0 clock input/output (direction controlled by eUSCI)
PM_UCA0RXD
eUSCI_A0 UART RXD (direction controlled by eUSCI – input)
PM_UCA0SOMI
eUSCI_A0 SPI slave out master in (direction controlled by eUSCI)
2
3
4
5
6
eUSCI_A0 UART TXD (direction controlled by eUSCI – output)
PM_UCA0SIMO
eUSCI_A0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0CLK
eUSCI_B0 clock input/output (direction controlled by eUSCI)
PM_UCB0SDA
eUSCI_B0 I2C data (open drain and direction controlled by eUSCI)
PM_UCB0SIMO
eUSCI_B0 SPI slave in master out (direction controlled by eUSCI)
PM_UCB0SCL
eUSCI_B0 I2C clock (open drain and direction controlled by eUSCI)
PM_UCB0SOMI
eUSCI_B0 SPI slave out master in (direction controlled by eUSCI)
7
PM_UCA1STE
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
8
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
9
10
PM_UCA1RXD
eUSCI_A1 UART RXD (direction controlled by eUSCI – input)
PM_UCA1SOMI
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
PM_UCA1TXD
eUSCI_A1 UART TXD (direction controlled by eUSCI – output)
PM_UCA1SIMO
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
11
PM_UCA2STE
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
12
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
13
PM_UCA2RXD
eUSCI_A2 UART RXD (direction controlled by eUSCI – input)
PM_UCA2SOMI
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
PM_UCA2TXD
eUSCI_A2 UART TXD (direction controlled by eUSCI – output)
PM_ UCA2SIMO
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
15
PM_UCB2STE
eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
16
PM_UCB2CLK
eUSCI_B2 clock input/output (direction controlled by eUSCI)
PM_UCB2SDA
eUSCI_B2 I2C data (open drain and direction controlled by eUSCI)
14
17
18
PM_UCB2SIMO
eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)
PM_UCB2SCL
eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI)
PM_UCB2SOMI
eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)
19
PM_TA0CCR0A
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
20
PM_TA0CCR1A
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
21
PM_TA0CCR2A
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
22
PM_TA0CCR3A
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
23
PM_TA0CCR4A
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
24
PM_TA1CCR1A
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
25
PM_TA1CCR2A
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
26
PM_TA1CCR3A
TA1 CCR3 capture input CCI3A
TA1 CCR3 compare output Out3
27
PM_TA1CCR4A
TA1 CCR4 capture input CCI4A
TA1 CCR4 compare output Out4
PM_TA0CLK
Timer_A0 external clock input
None
Comparator-E0 output
28
29
138
PM_UCA0TXD
PM_C0OUT
None
PM_TA1CLK
Timer_A1 external clock input
None
PM_C1OUT
None
Comparator-E1 output
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-46. Port Mapping Mnemonics and Functions (continued)
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_DMAE0
DMAE0 input
None
None
SMCLK
30
31 (0FFh)
(1)
PM_SMCLK
(1)
PM_ANALOG
Disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
The value of the PM_ANALOG mnemonic is 31. The port mapping registers are 5 bits wide, and the upper bits are ignored, which
results in a read value of 31.
Table 6-47. Default Mapping
PIN NAME
PxMAPy MNEMONIC
P2.0/PM_UCA1STE/L11
PM_UCA1STE
P2.1/PM_UCA1CLK/L10
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
eUSCI_A1 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA1CLK
eUSCI_A1 clock input/output (direction controlled by eUSCI)
P2.2/PM_UCA1RXD/
PM_UCA1SOMI/L9
PM_UCA1RXD/
PM_UCA1SOMI
eUSCI_A1 UART RXD (direction controlled by eUSCI – input)
eUSCI_A1 SPI slave out master in (direction controlled by eUSCI)
P2.3/PM_UCA1TXD/
PM_UCA1SIMO/L8
PM_UCA1TXD/
PM_UCA1SIMO
eUSCI_A1 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A1 SPI slave in master out (direction controlled by eUSCI)
P2.4/PM_TA0.1/L23
(1)
PM_TA0CCR1A
TA0 CCR1 capture input CCI1A
TA0 CCR1 compare output Out1
P2.5/PM_TA0.2/L22
(1)
PM_TA0CCR2A
TA0 CCR2 capture input CCI2A
TA0 CCR2 compare output Out2
P2.6/PM_TA0.3/L21
(1)
PM_TA0CCR3A
TA0 CCR3 capture input CCI3A
TA0 CCR3 compare output Out3
P2.7/PM_TA0.4/L20
(1)
PM_TA0CCR4A
TA0 CCR4 capture input CCI4A
TA0 CCR4 compare output Out4
P3.0/PM_UCA2STE/L7
PM_UCA2STE
P3.1/PM_UCA2CLK/L6
eUSCI_A2 SPI slave transmit enable (direction controlled by eUSCI)
PM_UCA2CLK
eUSCI_A2 clock input/output (direction controlled by eUSCI)
P3.2/PM_UCA2RXD/
PM_UCA2SOMI/L5
PM_UCA2RXD/
PM_UCA2SOMI
eUSCI_A2 UART RXD (direction controlled by eUSCI – input)/
eUSCI_A2 SPI slave out master in (direction controlled by eUSCI)
P3.3/PM_UCA2TXD/
PM_UCA2SIMO/L4
PM_UCA2TXD/
PM_UCA2SIMO
eUSCI_A2 UART TXD (direction controlled by eUSCI – output)/
eUSCI_A2 SPI slave in master out (direction controlled by eUSCI)
P3.4/PM_UCB2STE/L3
PM_UCB2STE
eUSCI_B2 SPI slave transmit enable (direction controlled by eUSCI)
P3.5/PM_UCB2CLK/L2
PM_UCB2CLK
eUSCI_B2 clock input/output (direction controlled by eUSCI)
P3.6/PM_UCB2SIMO/
PM_UCB2SDA/L1
PM_UCB2SIMO/
PM_UCB2SDA
eUSCI_B2 SPI slave in master out (direction controlled by eUSCI)/
eUSCI_B2 I2C data (open drain and direction controlled by eUSCI)
P3.7/PM_UCB2SOMI/
PM_UCB2SCL/L0
PM_UCB2SOMI/
PM_UCB2SCL
eUSCI_B2 SPI slave out master in (direction controlled by eUSCI)/
eUSCI_B2 I2C clock (open drain and direction controlled by eUSCI)
P7.0/PM_SMCLK/
PM_DMAE0/R03
PM_SMCLK/
PM_DMAE0
DMAE0 input
SMCLK
P7.1/PM_C0OUT/
PM_TA0CLK/R13
PM_C0OUT/
PM_TA0CLK
Timer_A0 external clock input
Comparator-E0 output
P7.2/PM_C1OUT/
PM_TA1CLK/R23
PM_C1OUT/
PM_TA1CLK
Timer_A1 external clock input
Comparator-E1 output
P7.3/PM_TA0.0
PM_TA0CCR0A
TA0 CCR0 capture input CCI0A
TA0 CCR0 compare output Out0
P7.4/PM_TA1.4/C0.5/L31
(1)
PM_TA1CCR4A
TA1 CCR4 capture input CCI4A
TA1 CCR4 compare output Out4
P7.5/PM_TA1.3/C0.4/L30
(1)
PM_TA1CCR3A
TA1 CCR3 capture input CCI3A
TA1 CCR3 compare output Out3
P7.6/PM_TA1.2/C0.3/L29
(1)
PM_TA1CCR2A
TA1 CCR2 capture input CCI2A
TA1 CCR2 compare output Out2
P7.7/PM_TA1.1/C0.2/L28
(1)
PM_TA1CCR1A
TA1 CCR1 capture input CCI1A
TA1 CCR1 compare output Out1
(1)
Not available on the 64-pin RGC package.
6.9.3
Timer_A
Timers TA0, TA1, TA2, and TA3 are 16-bit timers and counters (Timer_A type) with five capture/compare
registers each. Each timer supports multiple captures and compares, PWM outputs, and interval timing.
Each has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow
conditions and from each capture/compare register.
Detailed Description
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6.9.3.1
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Timer_A Signal Connection Tables
Table 6-48 to Table 6-51 list the interface signals of the Timer_A modules on the device and connections
of the interface signals to the corresponding pins or internal signals. The following rules apply to the
naming conventions used.
• The first column lists the device level pin or internal signal that sources the clocks or triggers into the
Timer. The default assumption is that these are pins, unless specifically marked as (internal).
Nomenclature used for internal signals is as follows:
– CxOUT: Output from Comparator x
– TAx_Cy: Output from Timer x, Capture/Compare module y
• The second column lists the input signals of the timer module.
• The third column lists the submodule of the timer and also implies the functionality [timer, capture
(inputs or triggers), or compare (outputs or PWM)].
• The fourth column lists the output signals of the timer module.
• The fifth column lists the device-level pin or internal signal that is driven by the outputs of the timer.
The default assumption is that these are pins, unless specifically marked as (internal).
NOTE
The pin names listed in the tables are the complete names. It is the responsibility of the
software to ensure that the pin is used in the intended mode for the targeted timer
functionality.
NOTE
Internal signals that are sourced by the timer outputs may connect to other modules (for
example, other timers or the ADC) in the device (as trigger sources).
Table 6-48. TA0 Signal Connections
DEVICE INPUT PIN OR INTERNAL
SIGNAL
MODULE INPUT
SIGNAL
P7.1/PM_C0OUT/PM_TA0CLK
TACLK
140
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
C0OUT (internal)
INCLK
P7.3/PM_TA0.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
P2.4/PM_TA0.1
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
P2.5/PM_TA0.2
CCI2A
C0OUT (internal)
CCI2B
DVSS
GND
DVCC
VCC
P2.6/PM_TA0.3
CCI3A
C1OUT (internal)
CCI3B
DVSS
GND
DVCC
VCC
Detailed Description
MODULE
BLOCK
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT PIN OR
INTERNAL SIGNAL
Timer
N/A
N/A
CCR0
TA0
P7.3/PM_TA0.0
TA0_C0 (internal)
CCR1
TA1
P2.4/PM_TA0.1
TA0_C1 (internal)
Precision ADC (internal)
ADC14SHSx = {1}
CCR2
TA2
P2.5/PM_TA0.2
TA0_C2 (internal)
Precision ADC (internal)
ADC14SHSx = {2}
CCR3
TA3
P2.6/PM_TA0.3
TA0_C3 (internal)
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-48. TA0 Signal Connections (continued)
DEVICE INPUT PIN OR INTERNAL
SIGNAL
MODULE INPUT
SIGNAL
P2.7/PM_TA0.4
CCI4A
TA1_C4 (Internal)
CCI4B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT PIN OR
INTERNAL SIGNAL
CCR4
TA4
P2.7/PM_TA0.4
TA0_C4 (internal)
Detailed Description
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Table 6-49. TA1 Signal Connections
DEVICE INPUT PIN OR INTERNAL
SIGNAL
MODULE INPUT
SIGNAL
P7.2/PM_C1OUT/PM_TA1CLK
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
142
C1OUT (internal)
INCLK
P8.0/UCB3STE/TA1.0/C0.1
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
P7.7/PM_TA1.1/C0.2
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
P7.6/PM_TA1.2/C0.3
CCI2A
C0OUT (internal)
CCI2B
DVSS
GND
DVCC
VCC
P7.5/PM_TA1.3/C0.4
CCI3A
C1OUT (internal)
CCI3B
DVSS
GND
DVCC
VCC
P7.4/PM_TA1.4/C0.5
CCI4A
TA0_C4 (internal)
CCI4B
DVSS
GND
DVCC
VCC
Detailed Description
MODULE
BLOCK
MODULE
OUTPUT SIGNAL
DEVICE OUTPUT PIN OR
INTERNAL SIGNAL
Timer
N/A
N/A
CCR0
TA0
P8.0/UCB3STE/TA1.0/C0.1
TA1_C0 (internal)
CCR1
TA1
P7.7/PM_TA1.1/C0.2
TA1_C1 (internal)
Precision ADC (internal)
ADC14SHSx = {3}
CCR2
TA2
P7.6/PM_TA1.2/C0.3
TA1_C2 (internal)
Precision ADC (internal)
ADC14SHSx = {4}
CCR3
TA3
P7.5/PM_TA1.3/C0.4
TA1_C3 (internal)
CCR4
TA4
P7.4/PM_TA1.4/C0.5
TA1_C4 (internal)
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Table 6-50. TA2 Signal Connections
DEVICE INPUT PIN OR INTERNAL SIGNAL
MODULE
INPUT SIGNAL
P4.2/ACLK/TA2CLK/A11
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive Touch I/O 0 (internal)
INCLK
P8.1/UCB3CLK/TA2.0/C0.0
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
P5.6/TA2.1/VREF+/VeREF+/C1.7
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
P5.7/TA2.2/VREF-/VeREF-/C1.6
CCI2A
C0OUT (internal)
CCI2B
DVSS
GND
DVCC
VCC
P6.6/TA2.3/UCB3SIMO/UCB3SDA/C1.1
CCI3A
TA3_C3 (internal)
CCI3B
DVSS
GND
DVCC
VCC
P6.7/TA2.4/UCB3SOMI/UCB3SCL/C1.0
CCI4A
From Capacitive Touch I/O 0 (internal)
CCI4B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
DEVICE OUTPUT PIN OR
INTERNAL SIGNAL
Timer
N/A
N/A
CCR0
TA0
P8.1/UCB3CLK/TA2.0/C0.0
TA2_C0 (internal)
TA1
P5.6/TA2.1/VREF+/VeREF+/C1.7
TA2_C1 (internal)
Precision ADC (internal)
ADC14SHSx = {5}
CCR2
TA2
P5.7/TA2.2/VREF-/VeREF-/C1.6
TA2_C2 (internal)
Precision ADC (internal)
ADC14SHSx = {6}
CCR3
TA3
P6.6/TA2.3/UCB3SIMO/
UCB3SDA/C1.1
TA2_C3 (internal)
CCR4
TA4
P6.7/TA2.4/UCB3SOMI/
UCB3SCL/C1.0
TA2_C4 (internal)
CCR1
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Table 6-51. TA3 Signal Connections
DEVICE INPUT PIN OR INTERNAL
SIGNAL
MODULE INPUT
SIGNAL
P8.3/TA3CLK/A22
TACLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive Touch I/O 1 (internal)
INCLK
P10.4/TA3.0/C0.7
CCI0A
DVSS
CCI0B
DVSS
GND
DVCC
VCC
P10.5/TA3.1/C0.6
CCI1A
ACLK (internal)
CCI1B
DVSS
GND
DVCC
VCC
P8.2/TA3.2/A23
CCI2A
C0OUT (internal)
CCI2B
DVSS
GND
DVCC
VCC
P9.2/TA3.3
CCI3A
TA2_C3 (internal)
CCI3B
DVSS
GND
DVCC
VCC
P9.3/TA3.4
CCI4A
From Capacitive Touch I/O 1 (internal)
CCI4B
DVSS
GND
DVCC
VCC
6.9.4
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT PIN OR
INTERNAL SIGNAL
Timer
N/A
N/A
CCR0
TA0
P10.4/TA3.0/C0.7
TA3_C0 (internal)
CCR1
TA1
P10.5/TA3.1/C0.6
TA3_C1 (internal)
Precision ADC (internal)
ADC14SHSx = {7}
CCR2
TA2
P8.2/TA3.2/A23
TA3_C2 (internal)
CCR3
TA3
P9.2/TA3.3
TA3_C3 (internal)
CCR4
TA4
P9.3/TA3.4
TA3_C4 (internal)
Timer32
Timer32 is an Arm dual 32-bit timer module. It contains two 32-bit timers, each of which can be configured
as two independent 16-bit timers. The two timers can generate independent events or a combined event,
which can be processed according to application requirements.
6.9.5
Enhanced Universal Serial Communication Interface (eUSCI)
The eUSCI modules are used for serial data communication. The eUSCI module supports synchronous
communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication
protocols such as UART, enhanced UART with automatic baud-rate detection, and IrDA.
The eUSCI_An module provides support for SPI (3-pin or 4-pin), UART, enhanced UART, and IrDA.
The eUSCI_Bn module provides support for SPI (3-pin or 4-pin) and I2C.
MSP432P4x1x devices offer up to four eUSCI_A and four eUSCI_B modules.
6.9.6
Real-Time Clock (RTC_C)
The RTC_C module contains an integrated real-time clock. It integrates an internal calendar which
compensates for months with less than 31 days and includes leap year correction. The RTC_C also
supports flexible alarm functions, offset calibration, and temperature compensation. The RTC_C operation
is available in LPM3 and LPM3.5 modes to minimize power consumption.
144
Detailed Description
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6.9.7
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart if a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals.
The watchdog can generate a reset on either a time-out or a password violation. This reset can be
configured to generate either a hard reset or a soft reset into the system. See the WDT_A chapter in the
MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual for more details.
Table 6-52. WDT_A Clocks
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
BCLK
CAUTION
The WDT must be set to interval mode before transitioning into the LPM3 or
LPM3.5 modes of operation. This allows the WDT event to wake the device
and return it to active modes of operation. Using the WDT in watchdog mode
may result in nondeterministic behavior due to the generated reset.
6.9.8
Precision ADC
The Precision ADC module can achieve up to 16-bit precision with software oversampling, up to 1-Msps
sampling rate with differential and single-ended inputs. The module implements a native 14-bit SAR core,
sample-and-hold circuit, reference generator, and a conversion result buffer. The window comparators
with lower and upper limits allow CPU-independent result monitoring through different window comparator
interrupt flags.
Table 6-53 summarizes the available Precision ADC external trigger sources.
Table 6-53. Precision ADC Trigger Signal Connections
ADC14SHSx
BINARY
DECIMAL
CONNECTED TRIGGER
SOURCE
000
0
Software (ADC14SC)
001
1
TA0_C1
010
2
TA0_C2
011
3
TA1_C1
100
4
TA1_C2
101
5
TA2_C1
110
6
TA2_C2
111
7
TA3_C1
Detailed Description
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Table 6-54 and Table 6-55 list the available multiplexing between internal and external analog inputs of
the Precision ADC.
Table 6-54. Precision ADC Channel Mapping on 100-Pin PZ Devices
PRECISION ADC CHANNEL
EXTERNAL CHANNEL
SOURCE
(CONTROL BIT = 0)
INTERNAL CHANNEL
SOURCE
(CONTROL BIT = 1) (1)
Channel 23
A23
Battery Monitor
Channel 22
A22
Temperature Sensor
ADC14TCMAP
Channel 21
A21
N/A (Reserved)
ADC14CH0MAP
Channel 20
A20
N/A (Reserved)
ADC14CH1MAP
Channel 19
A19
N/A (Reserved)
ADC14CH2MAP
Channel 18
A18
N/A (Reserved)
ADC14CH3MAP
(1)
(2)
CONTROL BIT
(2)
ADC14BATMAP
If an internal source is marked as N/A or Reserved, it indicates that only the external source is available for that channel.
See the Precision ADC chapter in the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual for details on the
registers that contain the control bits listed in the table.
Table 6-55. Precision ADC Channel Mapping on 64-Pin RGC Devices
PRECISION ADC CHANNEL
EXTERNAL CHANNEL
SOURCE
(CONTROL BIT = 0)
Channel 23
N/A
Battery Monitor
Channel 22
N/A
Temperature Sensor
ADC14TCMAP
Channel 11
A11
N/A (Reserved)
ADC14BATMAP
Channel 10
A10
N/A (Reserved)
ADC14TCMAP
Channel 9
A9
N/A (Reserved)
ADC14CH0MAP
Channel 8
A8
N/A (Reserved)
ADC14CH1MAP
Channel 7
A7
N/A (Reserved)
ADC14CH2MAP
Channel 6
A6
N/A (Reserved)
ADC14CH3MAP
(1)
(2)
INTERNAL CHANNEL
SOURCE
(CONTROL BIT = 1) (1)
CONTROL BIT
(2)
ADC14BATMAP
If an internal source is marked as N/A or Reserved, only the external source is available for that channel.
See the Precision ADC chapter in the MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual for details on the
registers that contain the control bits listed in the table.
6.9.9
Comparator_E (COMP_E)
The primary function of the COMP_E module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
Two COMP_E modules are available on MSP432P4x1x devices.
6.9.10 Shared Reference (REF_A)
The REF_A generates all critical reference voltages that can be used by the various analog peripherals in
the device. The reference voltage from REF_A can also be output on a device pin for external use.
6.9.11 LCD Controller (LCD_F)
The LCD_F driver generates the segment and common signals that are required to drive a liquid crystal
display (LCD). The LCD_F controller has dedicated data memories to hold segment drive information.
Common and segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, 4-mux, and
8-mux LCDs are supported. The module also provides an automatic blinking capability for individual
segments. The module provides for automatic animation capability over eight of the segment lines.
6.9.12 CRC32
The CRC32 module produces a signature based on a sequence of entered data values and can be used
for data checking purposes. It supports both a CRC32 and a CRC16 computation.
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The CRC16 computation signature is based on the CRC16-CCITT standard.
The CRC32 computation signature is based on the CRC32-ISO 3309 standard.
6.9.13 AES256 Accelerator
The AES accelerator module performs encryption and decryption of 128-bit data with 128-, 192-, or 256bit keys according to the Advanced Encryption Standard (AES) (FIPS PUB 197) in hardware.
6.9.14 True Random Seed
The Device Descriptor Information (TLV) contains a 128-bit true random seed that can be used to
implement a deterministic random number generator.
6.10 Code Development and Debug
MSP432P4x1x devices support various methods through which the user can carry out code development
and debug on the device.
6.10.1 JTAG and Serial Wire Debug (SWD) Based Development, Debug and Trace
The device supports both 4-pin JTAG and the 2-pin SWD modes of operation. The device is compatible
with all standard Cortex-M4 debuggers available in the market today. The debug logic in the device has
been designed to remain minimally intrusive to the application state. In low-power modes, the user can
enable the debugger to override the state of the PSS, thereby gaining access to debug and trace features.
In 2-pin SWD mode, the TDO pin can be used to export serial wire trace output (SWO) data. In addition,
the TDI and TDO pins of the device can be reassigned as user I/Os. See Section 6.12.24 and
Section 6.12.25 for more details.
NOTE
If the device has activated debug security, debugger accesses into the device is completely
disabled. The debugger, however, is still be able to scan the run/halt state of the CPU.
Further control of and visibility into the device is possible only after initiating a mass erase of
the device flash contents.
6.10.2 Peripheral Halt Control
The Peripheral Halt Control register in the System Controller module gives the user independent control
over the functionality of device peripherals during code development and debug. When the CPU is halted,
the bits in this register can control whether the corresponding peripheral freezes its operation (such as
incrementing, transmit, and receive) or continues its operation (debug remains nonintrusive). The registers
of the peripheral remain accessible without regard to the values in the Peripheral Halt Control register.
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6.10.3 Bootloader (BSL)
The BSL enables users to program flash or SRAM on the device using a UART or I2C or SPI serial
interface. Access to the device memory through the BSL is protected by a user-defined password.
Table 6-56 lists the required BSL pins.
Table 6-56. BSL Pins and Functions
DEVICE PIN
BSL FUNCTION
P1.2
UART BSLRXD
P1.3
UART BSLTXD
P1.4
SPI BSLSTE
P1.5
SPI BSLCLK
P1.6
SPI BSLSIMO
P1.7
SPI BSLSOMI
P3.6
I2C BSLSDA
P3.7
I2C BSLSCL
The BSL is invoked under any of the following conditions:
• Erasure of flash main memory
• Hardware invocation of BSL
• Software-based API calls to BSL functions
The user can perform hardware invocation of BSL using any pin of ports P1, P2, or P3. The pin selected
for this purpose must not be one of the pins used for BSL. The user can configure the device pin and its
polarity through the flash boot-override mailbox. The BSL can then be invoked on a power cycle or POR
reset event with the configured pin.
For the complete description of the BSL features and its implementation, see the MSP432P4xx
SimpleLink™ Microcontrollers Bootloader (BSL) User's Guide.
6.10.4 Device Security
The MSP432P4x1x MCUs offer the following two types of device security for the user application code
programmed on to the device.
• JTAG and SWD lock
• IP protection
JTAG and SWD lock as the name indicates locks the JTAG and SWD interface of the device. IP
protection is useful for protection of customer software IP, for example, in multiple-vendor development
scenarios. It is possible to have up to four IP protected zones with configurable start address and size.
The security configurations of the device are done using the flash boot-override mailbox.
Also the SYSCTL_A module provides infrastructure for encrypted in-field updates to the application code
on devices that are JTAG and SWD locked or have defined IP protection zones. For complete details of
the device security features, see SYSCTL_A chapter in the MSP432P4xx SimpleLink™ Microcontrollers
Technical Reference Manual.
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6.11 Performance Benchmarks
The MSP432P4x1x MCUs achieve the following performance benchmarks under the software
configurations and profile configurations in the following sections. These performance benchmarks were
measured with system supply voltage of 2.97 V at ambient temperature of 25°C.
6.11.1 ULPBench Performance: 150.6 ULPMark™-CP
Table 6-57 lists the software configuration for the ULPBench benchmark.
Table 6-57. Software Configuration
ITEM
DETAILS
Compiler name and version
IAR EWARM v7.50.3
Compiler flags
--endian=little --cpu=Cortex-M4F -e --fpu=VFPv4_sp -Ohs --no_size_constraints --mfc
ULPBench profile and version
v1.1.x
EnergyMonitor software version
1.1.3
Table 6-58 lists the profile configuration for the ULPBench benchmark.
Table 6-58. Profile Configuration
CONFIGURATION
DETAILS
Wakeup Timer Module
RTC
Wakeup Timer Clock Source
External crystal
Wakeup Timer Frequency
32768 Hz
Wakeup Timer Accuracy
20 ppm
Active Power Mode Name
Active mode
Active Mode Clock Configuration
CPU: 21 MHz, RTC: 32 kHz
Active Mode Voltage Integrity
1.62 V
Inactive Power Mode Name
LPM3
Inactive Clock Configuration
CPU: off, RTC: 32 kHz
Inactive Mode Voltage Integrity
1.62 V
6.11.2 CoreMark/MHz Performance: 3.41
Table 6-59 lists the software configuration for the CoreMark benchmark.
Table 6-59. Software Configuration
ITEM
DETAILS
Compiler Name and Version
IAR EWARM v6.70.3
Compiler Flags
--no_size_constraints --debug --endian=little --cpu=Cortex-M4F -e --fpu=None --dlib_config
C:\Program Files (x86)\IAR Systems\Embedded Workbench
6.\arm\INC\c\DLib_Config_Normal.h -Ohs
CoreMark Profile and Version
v1.0
Table 6-60 lists the profile configuration for the CoreMark benchmark.
Table 6-60. Profile Configuration
CONFIGURATION
DETAILS
Active Power Mode Name
Active mode
Active Mode Clock Configuration
CPU: 3 MHz
Active Mode Voltage Integrity
1.62 V
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6.11.3 DMIPS/MHz (Dhrystone 2.1) Performance: 1.22
Table 6-61 lists the software configuration for the Dhrystone benchmark.
Table 6-61. Software Configuration
ITEMS
DETAILS
Compiler Name and Version
Keil µVision Arm Compiler v5.06(build 20)
Compiler Flags
-c --cpu Cortex-M4.fp -g -O3 -Otime --apcs=interwork --asm --interleave --asm_dir
Dhrystone Profile and Version
v2.1
Table 6-62 lists the profile configuration for the Dhrystone benchmark.
Table 6-62. Profile Configuration
CONFIGURATION
DETAILS
Active Power Mode Name
Active Mode
Active Mode Clock Configuration
CPU: 3 MHz
Active Mode Voltage Integrity
150
Detailed Description
1.62 V
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6.12 Input/Output Diagrams
6.12.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 6-8 shows the port schematic. Table 6-63 lists the settings to select the port functions.
Pad Logic
Lz
LCDSz
PyREN.x
PyDIR.x
From USCI
00
01
10
Direction
0: Input
1: Output
11
PyOUT.x
DVSS
0
DVCC
1
1
00
From USCI
01
DVSS
10
DVSS
11
Py.x/USCI/Lz
PySEL1.x
PySEL0.x
PyIN.x
Bus
Keeper
EN
To USCI
D
Functional representation only.
Figure 6-8. Py.x/USCI/Lz Port Schematic
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Table 6-63. Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)
x
FUNCTION
P1.0 (I/O)
UCA0STE
P1.0/UCA0STE/L19
0
L19
(3)
1
L18
(3)
L17
(3)
L16
(3)
(1)
(2)
(3)
(4)
152
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
X
I: 0; O: 1
X
(2)
X
I: 0; O: 1
X
(2)
X
0
DVSS
1
L15
(3)
I: 0; O: 1
X
(4)
X
N/A
0
DVSS
1
L14
(3)
I: 0; O: 1
X
(4)
X
N/A
0
DVSS
1
L13
(3)
I: 0; O: 1
X
(4)
X
N/A
0
DVSS
1
UCB0SOMI/UCB0SCL
7
1
1
(2)
N/A
P1.7 (I/O)
P1.7/UCB0SOMI/UCB0SCL/L
12
0
0
X
1
UCB0SIMO/UCB0SDA
6
0
I: 0; O: 1
DVSS
P1.6 (I/O)
P1.6/UCB0SIMO/UCB0SDA/L
13
1
0
UCB0CLK
5
1
N/A
P1.5 (I/O)
P1.5/UCB0CLK/L14
0
1
UCB0STE
4
1
X
0
P1.4 (I/O)
P1.4/UCB0STE/L15
1
(2)
DVSS
UCA0TXD/UCA0SIMO
3
0
0
X
N/A
P1.3 (I/O)
P1.3/UCA0TXD/UCA0SIMO/L
16
P1SEL0.x
0
1
UCA0RXD/UCA0SOMI
2
P1SEL1.x
DVSS
P1.2 (I/O)
P1.2/UCA0RXD/UCA0SOMI/L
17
P1DIR.x
0
UCA0CLK
L12
(3)
(1)
I: 0; O: 1
N/A
P1.1 (I/O)
P1.1/UCA0CLK/L18
CONTROL BITS OR SIGNALS
I: 0; O: 1
X
(4)
X
N/A
0
DVSS
1
X = Don't care
Direction controlled by eUSCI_A0 module.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Direction controlled by eUSCI_B0 module.
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6.12.2 Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-8
Table 6-64 lists the settings to select the port functions.
Table 6-64. Port P2 (P2.0 to P2.3) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.0 (I/O)
UCA1STE
P2.0/PM_UCA1STE/L11
0
L11
(3)
L10
(3)
(1)
(2)
(3)
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
X
(2)
X
I: 0; O: 1
X
(2)
X
0
DVSS
1
L9
(3)
I: 0; O: 1
X
(2)
X
N/A
0
DVSS
1
UCA1TXD/UCA1SIMO
3
0
N/A
P2.3 (I/O)
P2.3/PM_UCA1TXD/PM_U
CA1SIMO/L8
P2SEL0.x
0
1
UCA1RXD/UCA1SOMI
2
P2SEL1.x
0
P2.2 (I/O)
P2.2/PM_UCA1RXD/PM_U
CA1SOMI/L9
P2DIR.x
DVSS
UCA1CLK
1
L8
(3)
(1)
I: 0; O: 1
N/A
P2.1 (I/O)
P2.1/PM_UCA1CLK/L10
CONTROL BITS OR SIGNALS
I: 0; O: 1
X
(2)
X
N/A
0
DVSS
1
P2MAPx
X = Don't care
Direction controlled by eUSCI_A1 module.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
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6.12.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-8
Table 6-65 lists the settings to select the port functions.
Table 6-65. Port P3 (P3.0 to P3.7) Pin Functions
PIN NAME (P3.x)
x
FUNCTION
P3.0 (I/O)
UCA2STE
P3.0/PM_UCA2STE/L7
0
L7
(3)
L6
(3)
L5
(3)
(1)
(2)
(3)
(4)
154
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
I: 0; O: 1
X
(2)
X
I: 0; O: 1
X
(2)
X
1
L4
(3)
I: 0; O: 1
X
(2)
X
N/A
0
DVSS
1
L3
(3)
I: 0; O: 1
X
(4)
X
N/A
0
DVSS
1
L2
(3)
I: 0; O: 1
X
(4)
X
N/A
0
DVSS
1
UCB2SIMO/UCB2SDA
6
X
0
P3.6 (I/O)
P3.6/PM_UCB2SIMO/PM_
UCB2SDA/L1
0
DVSS
UCB2CLK
5
1
X
N/A
P3.5 (I/O)
P3.5/PM_UCB2CLK/L2
default
1
UCB2STE
4
1
(2)
DVSS
P3.4 (I/O)
P3.4/PM_UCB2STE/L3
X
0
X
0
UCA2TXD/UCA2SIMO
3
0
N/A
P3.3 (I/O)
P3.3/PM_UCA2TXD/PM_U
CA2SIMO/L4
P3SEL0.x
0
1
UCA2RXD/UCA2SOMI
2
P3SEL1.x
0
P3.2 (I/O)
P3.2/PM_UCA2RXD/PM_U
CA2SOMI/L5
P3DIR.x
DVSS
UCA2CLK
1
L1
(3)
(1)
I: 0; O: 1
N/A
P3.1 (I/O)
P3.1/PM_UCA2CLK/L6
CONTROL BITS OR SIGNALS
I: 0; O: 1
X
(4)
X
N/A
0
DVSS
1
P3MAPx
X = Don't care
Direction controlled by eUSCI_A2 module.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Direction controlled by eUSCI_B2 module.
Detailed Description
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Table 6-65. Port P3 (P3.0 to P3.7) Pin Functions (continued)
PIN NAME (P3.x)
x
FUNCTION
P3.7 (I/O)
UCB2SOMI/UCB2SCL
P3.7/PM_UCB2SOMI/PM_
UCB2SCL/L0
7
L0
(3)
CONTROL BITS OR SIGNALS
(1)
P3DIR.x
P3SEL1.x
P3SEL0.x
I: 0; O: 1
0
0
X
0
1
default
1
0
X
1
1
X
X
(4)
X
N/A
0
DVSS
1
P3MAPx
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6.12.4 Port P9 (P9.4 to P9.7) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-8
Table 6-66 lists the settings to select the port functions.
Table 6-66. Port P9 (P9.4 to P9.7) Pin Functions
PIN NAME (P9.x)
x
FUNCTION
P9.4 (I/O)
UCA3STE
P9.4/UCA3STE/L43
(2)
4
L43
(4)
5
L42
(4)
(1)
(2)
(3)
(4)
156
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
(3)
X
I: 0; O: 1
X
(3)
X
0
DVSS
1
L41
(4)
I: 0; O: 1
X
(3)
X
N/A
0
DVSS
1
UCA3TXD/UCA3SIMO
7
0
0
X
N/A
P9.7 (I/O)
P9.7/UCA3TXD/UCA3SIMO/L4
0 (2)
P9SEL0.x
0
1
UCA3RXD/UCA3SOMI
6
P9SEL1.x
0
P9.6 (I/O)
P9.6/UCA3RXD/UCA3SOMI/L4
1 (2)
P9DIR.x
DVSS
UCA3CLK
(2)
L40
(4)
(1)
I: 0; O: 1
N/A
P9.5 (I/O)
P9.5/UCA3CLK/L42
CONTROL BITS OR SIGNALS
I: 0; O: 1
X
(3)
X
N/A
0
DVSS
1
X = Don't care
Not available on the 64-pin RGC package.
Direction controlled by eUSCI_A3 module.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Detailed Description
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6.12.5 Port P10 (P10.0 to P10.3) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-8
Table 6-67 lists the settings to select the port functions.
Table 6-67. Port P10 (P10.0 to P10.3) Pin Functions
PIN NAME (P10.x)
x
FUNCTION
P10.0 (I/O)
UCB3STE
P10.0/UCB3STE/L39
(2)
0
L39
(4)
1
L38
(4)
(1)
(2)
(3)
(4)
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
X
I: 0; O: 1
X
(3)
X
0
DVSS
1
L37
(4)
I: 0; O: 1
X
(3)
X
N/A
0
DVSS
1
UCB3SOMI/UCB3SCL
3
1
1
(3)
N/A
P10.3 (I/O)
P10.3/UCB3SOMI/UCB3SCL/L
36 (2)
0
0
X
1
UCB3SIMO/UCB3SDA
2
P10SEL0.x
0
0
P10.2 (I/O)
P10.2/UCB3SIMO/UCB3SDA/L
37 (2)
P10SEL1.x
I: 0; O: 1
DVSS
UCB3CLK
(2)
L36
(4)
(1)
P10DIR.x
N/A
P10.1 (I/O)
P10.1/UCB3CLK/L38
CONTROL BITS OR SIGNALS
I: 0; O: 1
X
(3)
X
N/A
0
DVSS
1
X = Don't care
Not available on the 64-pin RGC package.
Direction controlled by eUSCI_B3 module.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Detailed Description
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6.12.6 Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
Figure 6-9 shows the port schematic. Table 6-68 lists the settings to select the port functions.
Pad Logic
Lz
LCDSz
PyREN.x
PyDIR.x
00
01
10
Direction
0: Input
1: Output
11
PyOUT.x
00
From module
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/Mod/Lz
PySEL1.x
PySEL0.x
PyIN.x
EN
To modules
Bus
Keeper
D
Functional representation only.
Figure 6-9. Py.x/Mod/Lz Port Schematic
158
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-68. Port P2 (P2.4 to P2.7) Pin Functions
PIN NAME (P2.x)
x
FUNCTION
P2.4 (I/O)
P2.4/PM_TA0.1/L23
(2)
4
(2)
5
(2)
6
P2.7/PM_TA0.4/L20
(1)
(2)
(3)
7
P2SEL0.x
P2MAPx
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
1
(3)
X
N/A
0
DVSS
1
I: 0; O: 1
TA0.CCI2A
0
TA0.2
1
L22
(3)
X
N/A
0
DVSS
1
I: 0; O: 1
TA0.CCI3A
0
TA0.3
1
L21
(3)
X
N/A
0
DVSS
1
P2.7 (I/O)
(2)
P2SEL1.x
TA0.1
P2.6 (I/O)
P2.6/PM_TA0.3/L21
P2DIR.x
0
L23
I: 0; O: 1
TA0.CCI4A
0
TA0.4
1
L20
(3)
(1)
I: 0; O: 1
TA0.CCI1A
P2.5 (I/O)
P2.5/PM_TA0.2/L22
CONTROL BITS OR SIGNALS
X
N/A
0
DVSS
1
X = Don't care
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Detailed Description
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6.12.7 Port P7 (P7.0 to P7.2) Input/Output With Schmitt Trigger
Figure 6-10 shows the port schematic. Table 6-69 lists the settings to select the port functions.
Pad Logic
To LCD_F
From LCD_F
PyREN.x
PyDIR.x
00
01
10
Direction
0: Input
1: Output
11
PyOUT.x
DVSS
0
DVCC
1
1
00
From module
01
DVSS
10
DVSS
11
P7.0/PM_SMCLK/PM_DMAE0/R03
P7.1/PM_C0OUT/PM_TA0CLK/R13/LCDREF
P7.2/PM_C1OUT/PM_TA1CLK/R23
PySEL1.x
PySEL0.x
PyIN.x
Bus
Keeper
EN
To modules
D
Figure 6-10. P7.0, P7.1 and P7.2 Port Schematic
Table 6-69. Port P7 (P7.0 to P7.2) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.0 (I/O)
P7.0/PM_SMCLK/
PM_DMAE0
R03
P7.1/PM_C0OUT/
PM_TA0CLK
R13
(1)
(2)
160
0
1
CONTROL BITS OR SIGNALS
P7DIR.x
P7SEL1.x
P7SEL0.x
P7MAPx
I: 0; O: 1
0
0
X
0
1
default
1
0
X
1
1
X
0
0
X
0
1
default
1
0
X
1
1
X
DMAE0
0
SMCLK
1
R03
(2)
X
N/A
0
DVSS
1
P7.1 (I/O)
I: 0; O: 1
TA0CLK
0
C0OUT
1
R13
(2)
(1)
X
N/A
0
DVSS
1
X = Don't care
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-69. Port P7 (P7.0 to P7.2) Pin Functions (continued)
PIN NAME (P7.x)
P7.2/PM_C1OUT/
PM_TA1CLK
R23
x
2
FUNCTION
CONTROL BITS OR SIGNALS
(1)
P7DIR.x
P7SEL1.x
P7SEL0.x
P7MAPx
P7.2 (I/O)
I: 0; O: 1
0
0
X
TA1CLK
0
C1OUT
1
0
1
default
1
0
X
1
1
X
R23
(2)
X
N/A
0
DVSS
1
Detailed Description
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6.12.8 Port P7 (P7.3) Input/Output With Schmitt Trigger
Figure 6-11 shows the port schematic. Table 6-70 lists the settings to select the port functions.
Pad Logic
PyREN.x
PyDIR.x
00
01
Direction
0: Input
1: Output
10
11
PyOUT.x
00
From module
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/Mod1/Mod2
PySEL1.x
PySEL0.x
PyIN.x
EN
D
To module
Figure 6-11. P7.3 Port Schematic
Table 6-70. Port P7 (P7.3) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.3 (I/O)
P7.3/PM_TA0.0
(1)
162
3
CONTROL BITS OR SIGNALS
(1)
P7DIR.x
P7SEL1.x
P7SEL0.x
P7MAPx
I: 0; O: 1
0
0
X
0
1
default
1
0
X
1
1
X
TA0.CCI0A
0
TA0.0
1
N/A
X
N/A
0
DVSS
1
X = Don't care
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
6.12.9 Port P9 (P9.2 and P9.3) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-9
Table 6-71 lists the settings to select the port functions.
Table 6-71. Port P9 (P9.2 and P9.3) Pin Functions
PIN NAME (P9.x)
x
FUNCTION
P9.2 (I/O)
P9.2/TA3.3/L33
(1)
2
(1)
(2)
(1)
3
P9DIR.x
P9SEL1.x
P9SEL0.x
I: 0; O: 1
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
TA3.CCI3A
0
TA3.3
1
L33
(2)
X
N/A
0
DVSS
1
P9.3 (I/O)
P9.3/TA3.4/L32
CONTROL BITS OR SIGNALS
I: 0; O: 1
TA3.CCI4A
0
TA3.4
1
L32
(2)
X
N/A
0
DVSS
1
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Detailed Description
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6.12.10 Port P4 (P4.2 to P4.7) Input/Output With Schmitt Trigger
Figure 6-12 shows the port schematic. Table 6-72 lists the settings to select the port functions.
Pad Logic
To ADC
From ADC
PyREN.x
PyDIR.x
00
01
10
Direction
0: Input
1: Output
11
PyOUT.x
00
From module 1†
01
From module 2†
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/Mod1/Mod2/Az
PySEL1.x
PySEL0.x
PyIN.x
EN
To modules
†
Bus
Keeper
D
Output is DVSS if module 1 or module 2 function is not available. See the pin function tables.
Functional representation only.
Figure 6-12. Py.x/Mod1/Mod2/Az Port Schematic
164
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-72. Port P4 (P4.2 to P4.7) Pin Functions
PIN NAME (P4.x)
x
FUNCTION
P4.2 (I/O)
P4.2/ACLK/TA2CLK/A11
2
5
6
7
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
N/A
0
MCLK
1
N/A
0
RTCCLK
1
(2)
N/A
0
HSMCLK
1
N/A
0
SVMHOUT
1
(2)
X
1
1
P4.5 (I/O)
I: 0; O: 1
0
0
0
1
1
0
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
1
1
P4.6 (I/O)
I: 0; O: 1
0
0
0
1
1
0
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
1
1
P4.7 (I/O)
I: 0; O: 1
0
0
0
1
1
0
1
1
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
A6
(1)
(2)
1
1
A7
P4.7/A6
1
0
A8
P4.6/A7
0
DVSS
A9
P4.5/A8
0
TA2CLK
P4.4 (I/O)
4
P4SEL0.x
0
1
A10
P4.4/HSMCLK/SVMHOUT/
A9
P4SEL1.x
ACLK
P4.3 (I/O)
3
P4DIR.x
0
(2)
(1)
I: 0; O: 1
N/A
A11
P4.3/MCLK/RTCCLK/A10
CONTROL BITS OR SIGNALS
X = Don't care
Setting P4SEL1.x and P4SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Detailed Description
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6.12.11 Port P5 (P5.0 to P5.5) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-12
Table 6-73 lists the settings to select the port functions.
Table 6-73. Port P5 (P5.0 to P5.5) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5.0 (I/O)
P5.0/A5
0
1
2
3
4
5
166
0
1
1
0
0
DVSS
1
(2)
X
1
1
P5.1 (I/O)
I: 0; O: 1
0
0
0
1
1
0
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
1
1
P5.2 (I/O)
I: 0; O: 1
0
0
0
1
1
0
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
1
1
P5.3 (I/O)
I: 0; O: 1
0
0
0
1
1
0
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
1
1
P5.4 (I/O)
I: 0; O: 1
0
0
0
1
1
0
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
1
1
P5.5 (I/O)
I: 0; O: 1
0
0
0
1
1
0
1
1
N/A
0
DVSS
1
N/A
0
DVSS
1
(2)
X
A0
(1)
(2)
0
N/A
A1
P5.5/A0
P5SEL0.x
0
1
A2
P5.4/A1
P5SEL1.x
DVSS
A3
P5.3/A2
P5DIR.x
I: 0; O: 1
0
A4
P5.2/A3
(1)
N/A
A5
P5.1/A4
CONTROL BITS OR SIGNALS
X = Don't care
Setting P5SEL1.x and P5SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
6.12.12 Port P4 (P4.0 and P4.1) Input/Output With Schmitt Trigger
Figure 6-13 shows the port schematic. Table 6-74 lists the settings to select the port functions.
Pad Logic
Lz
LCDSz
To ADC
From ADC
PyREN.x
PyDIR.x
00
01
10
Direction
0: Input
1: Output
11
PyOUT.x
00
From module†
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/Mod/Az/Lz
PySEL1.x
PySEL0.x
PyIN.x
EN
To module
†
A.
Bus
Keeper
D
Output is DVSS if module function is not available. See the pin function tables.
Functional representation only.
Figure 6-13. Py.x/Mod/Az/Lz Port Schematic
Detailed Description
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Table 6-74. Port P4 (P4.0 and P4.1) Pin Functions
PIN NAME (P4.x)
x
CONTROL BITS OR SIGNALS
FUNCTION
P4.0 (I/O)
P4.0/A13/L13
(2)
0
(1)
(2)
(3)
(4)
(2)
1
P4DIR.x
P4SEL1.x
P4SEL0.x
I: 0; O: 1
0
0
0
1
N/A
0
DVSS
1
L13
(3)
X
1
0
A13
(4)
X
1
1
I: 0; O: 1
0
0
0
1
P4.1 (I/O)
P4.1/A12/L12
(1)
N/A
0
DVSS
1
L12
(3)
X
1
0
A12
(4)
X
1
1
X = Don't care
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Setting P4SEL1.x and P4SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
NOTE
Take special care on the pins with ADC and LCD multiplexing to ensure that only one of
these functions is enabled at any time.
168
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
6.12.13 Port P6 (P6.0 and P6.1) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-13
Table 6-75 lists the settings to select the port functions.
Table 6-75. Port P6 (P6.0 and P6.1) Pin Functions
PIN NAME (P6.x)
x
CONTROL BITS OR SIGNALS
FUNCTION
P6.0 (I/O)
P6.0/A15/L15
(2)
0
(1)
(2)
(3)
(4)
(2)
1
P6DIR.x
P6SEL1.x
P6SEL0.x
I: 0; O: 1
0
0
0
1
N/A
0
DVSS
1
L15
(3)
X
1
0
A15
(4)
X
1
1
I: 0; O: 1
0
0
0
1
P6.1 (I/O)
P6.1/A14/L14
(1)
N/A
0
DVSS
1
L14
(3)
X
1
0
A14
(4)
X
1
1
X = Don't care
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
NOTE
Take special care on the pins with ADC and LCD multiplexing to ensure that only one of
these functions is enabled at any time.
Detailed Description
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6.12.14 Port P8 (P8.2 to P8.7) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-13
Table 6-76 lists the settings to select the port functions.
Table 6-76. Port P8 (P8.2 to P8.7) Pin Functions
PIN NAME (P8.x)
x
CONTROL BITS OR SIGNALS
FUNCTION
P8.2 (I/O)
P8.2/TA3.2/A23/L47
(2)
P8.3/TA3CLK/A22/L46
(2)
2
3
(2)
4
(2)
5
(2)
6
(1)
(2)
(3)
(4)
(2)
7
0
0
1
1
L47
(3)
X
1
0
A23
(4)
X
1
1
P8.3 (I/O)
I: 0; O: 1
0
0
TA3CLK
0
DVSS
1
0
1
X
1
0
X
1
1
I: 0; O: 1
0
0
0
1
L46
(3)
A22
(4)
N/A
0
DVSS
1
L45
(3)
X
1
0
A21
(4)
X
1
1
I: 0; O: 1
0
0
0
1
X
1
0
X
1
1
I: 0; O: 1
0
0
0
1
N/A
0
DVSS
1
L44
(3)
A20
(4)
N/A
0
DVSS
1
L19
(3)
X
1
0
A19
(4)
X
1
1
I: 0; O: 1
0
0
0
1
P8.7 (I/O)
P8.7/A18/L18
P8SEL0.x
0
TA3.2
P8.6 (I/O)
P8.6/A19/L19
P8SEL1.x
0
P8.5 (I/O)
P8.5/A20/L44
P8DIR.x
I: 0; O: 1
TA3.CCI2A
P8.4 (I/O)
P8.4/A21/L45
(1)
N/A
0
DVSS
1
L18
(3)
X
1
0
A18
(4)
X
1
1
X = Don't care
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Setting P8SEL1.x and P8SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
NOTE
Take special care on the pins with ADC and LCD multiplexing to ensure that only one of
these functions is enabled at any time.
170
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
6.12.15 Port P9 (P9.0 and P9.1) Input/Output With Schmitt Trigger
Port Schematic: see Figure 6-13
Table 6-77 lists the settings to select the port functions.
Table 6-77. Port P9 (P9.0 and P9.1) Pin Functions
PIN NAME (P9.x)
x
CONTROL BITS OR SIGNALS
FUNCTION
P9.0 (I/O)
P9.0/A17/L17
(2)
0
(1)
(2)
(3)
(4)
(2)
1
P9DIR.x
P9SEL1.x
P9SEL0.x
I: 0; O: 1
0
0
0
1
N/A
0
DVSS
1
L17
(3)
X
1
0
A17
(4)
X
1
1
I: 0; O: 1
0
0
0
1
P9.1 (I/O)
P9.1/A16/L16
(1)
N/A
0
DVSS
1
L16
(3)
X
1
0
A16
(4)
X
1
1
X = Don't care
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Setting P9SEL1.x and P9SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
NOTE
Take special care on the pins with ADC and LCD multiplexing to ensure that only one of
these functions is enabled at any time.
Detailed Description
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6.12.16 Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
Figure 6-14 shows the port schematic. Table 6-78 lists the settings to select the port functions.
Pad Logic
ADC Reference
To Comparator
From Comparator
CPD.q
PyREN.x
PyDIR.x
00
01
10
Direction
0: Input
1: Output
11
PyOUT.x
DVSS
0
DVCC
1
1
00
From module
01
DVSS
10
DVSS
11
Py.x/Mod/VREF/VeREF/Cp.q
PySEL1.x
PySEL0.x
PyIN.x
EN
To module
Bus
Keeper
D
Functional representation only.
Figure 6-14. Py.x/Mod/VREF/VeREF/Cp.q Port Schematic
172
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-78. Port P5 (P5.6 and P5.7) Pin Functions
PIN NAME (P5.x)
x
FUNCTION
P5.6 (I/O)
P5.6/TA2.1/VREF+/VeREF+/
C1.7
6
(3)
P5SEL0.x
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
1
N/A
0
DVSS
1
TA2.CCI2A
0
TA2.2
1
N/A
0
DVSS
1
VREF-, VeREF-, C1.6
(1)
(2)
P5SEL1.x
TA2.1
P5.7 (I/O)
7
P5DIR.x
0
(2) (3)
(2) (3)
(1)
I: 0; O: 1
TA2.CCI1A
VREF+, VeREF+, C1.7
P5.7/TA2.2/VREF-/VeREF/C1.6
CONTROL BITS OR SIGNALS
X
X = Don't care
Setting P5SEL1.x and P5SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C1.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
Detailed Description
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6.12.17 Port P6 (P6.2 to P6.5) Input/Output With Schmitt Trigger
Figure 6-15 shows the port schematic. Table 6-79 lists the settings to select the port functions.
Pad Logic
Lz
LCDSz
To Comparator
From Comparator
CPD.q
PyREN.x
PyDIR.x
00
01
From USCI
10
Direction
0: Input
1: Output
11
PyOUT.x
00
From USCI
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/USCI/Cp.q/Lz
PySEL1.x
PySEL0.x
PyIN.x
Bus
Keeper
EN
To USCI
D
Functional representation only.
Figure 6-15. Py.x/USCI/Cp.q Port Schematic
174
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-79. Port P6 (P6.2 to P6.5) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.2 (I/O)
P6.2/UCB1STE/C1.5/L27
(2)
2
UCB1STE
L27
(4)
C1.5
(5) (6)
P6.3 (I/O)
P6.3/UCB1CLK/C1.4/L26
(2)
3
UCB1CLK
L26
(4)
C1.4
(5) (6)
P6.4 (I/O)
P6.4/UCB1SIMO/UCB1SDA/C1
.3/L25 (2)
4
UCB1SIMO/UCB1SDA
L25
(4)
C1.3
(5) (6)
P6.5 (I/O)
P6.5/UCB1SOMI/UCB1SCL/C1.
2/L24 (2)
5
UCB1SOMI/UCB1SCL
L24
(4)
C1.2
(1)
(2)
(3)
(4)
(5)
(6)
(5) (6)
CONTROL BITS OR SIGNALS
(1)
P6DIR.x
P6SEL1.x
P6SEL0.x
I: 0; O: 1
0
0
0
1
X
1
0
X
1
1
I: 0; O: 1
0
0
X
X
(3)
(3)
0
1
X
1
0
X
1
1
I: 0; O: 1
0
0
0
1
X
1
0
X
1
1
I: 0; O: 1
0
0
0
1
X
1
0
X
1
1
X
X
(3)
(3)
X = Don't care
Not available on the 64-pin RGC package.
Direction controlled by eUSCI_B1 module.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C1.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
Detailed Description
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6.12.18 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
Figure 6-16 shows the port schematic. Table 6-80 lists the settings to select the port functions.
Pad Logic
To Comparator
From Comparator
CPD.q
PyREN.x
PyDIR.x
00
01
From USCI
10
Direction
0: Input
1: Output
11
PyOUT.x
00
From module
01
From USCI
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/Mod/USCI/Cp.q
PySEL1.x
PySEL0.x
PyIN.x
Bus
Keeper
EN
To modules
D
Functional representation only.
Figure 6-16. Py.x/Mod/USCI/Cp.q Port Schematic
176
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-80. Port P6 (P6.6 and P6.7) Pin Functions
PIN NAME (P6.x)
x
FUNCTION
P6.6 (I/O)
P6.6/TA2.3/UCB3SIMO/UCB
3SDA/C1.1
6
0
0
1
(3) (4)
X
(2)
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
TA2.CCI4A
0
TA2.4
1
C1.0
(4)
P6SEL0.x
0
1
UCB3SOMI/UCB3SCL
(1)
(2)
(3)
P6SEL1.x
TA2.3
P6.7 (I/O)
7
P6DIR.x
0
C1.1
(3) (4)
(1)
I: 0; O: 1
TA2.CCI3A
UCB3SIMO/UCB3SDA
P6.7/TA2.4/UCB3SOMI/UCB
3SCL/C1.0
CONTROL BITS OR SIGNALS
X
(2)
X
X = Don't care
Direction controlled by eUSCI_B3 module.
Setting P6SEL1.x and P6SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C1.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
Detailed Description
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6.12.19 Port P8 (P8.0 and P8.1) Input/Output With Schmitt Trigger
Figure 6-17 shows the port schematic. Table 6-81 lists the settings to select the port functions.
Pad Logic
To Comparator
From Comparator
CPD.q
PyREN.x
PyDIR.x
00
From USCI
01
10
Direction
0: Input
1: Output
11
PyOUT.x
00
From USCI
01
From module
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/USCI/Mod/Cp.q
PySEL1.x
PySEL0.x
PyIN.x
Bus
Keeper
EN
To modules
D
Functional representation only.
Figure 6-17. Py.x/USCI/Mod/Cp.q Port Schematic
178
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-81. Port P8 (P8.0 and P8.1) Pin Functions
PIN NAME (P8.x)
x
FUNCTION
P8.0 (I/O)
UCB3STE
P8.0/UCB3STE/TA1.0/C0.1
0
0
0
1
1
0
X
1
1
I: 0; O: 1
0
0
0
1
1
0
1
1
X
(2)
X
(2)
TA2.CCI0A
0
TA2.0
1
C0.0
(4)
P8SEL0.x
0
1
UCB3CLK
(1)
(2)
(3)
P8SEL1.x
0
P8.1 (I/O)
1
P8DIR.x
TA1.0
(3) (4)
(3) (4)
(1)
I: 0; O: 1
TA1.CCI0A
C0.1
P8.1/UCB3CLK/TA2.0/C0.0
CONTROL BITS OR SIGNALS
X
X = Don't care
Direction controlled by eUSCI_B3 module.
Setting P8SEL1.x and P8SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C0.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
Detailed Description
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6.12.20 Port P10 (P10.4 and P10.5) Input/Output With Schmitt Trigger
Figure 6-18 shows the port schematic. Table 6-82 lists the settings to select the port functions.
Pad Logic
Lz
LCDSz
To Comparator
From Comparator
CPD.q
PyREN.x
PyDIR.x
00
01
10
Direction
0: Input
1: Output
11
PyOUT.x
00
From module
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
Py.x/Mod/Cp.q/Lz
PySEL1.x
PySEL0.x
PyIN.x
EN
To module
Bus
Keeper
D
Functional representation only.
Figure 6-18. Py.x/Mod/Cp.q/Lz Port Schematic
180
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-82. Port P10 (P10.4 and P10.5) Pin Functions
PIN NAME (P10.x)
P10.4/TA3.0/C0.7/L35
(2)
x
4
FUNCTION
P10DIR.x
P10SEL1.x
P10SEL0.x
I: 0; O: 1
0
0
TA3.CCI0A
0
TA3.0
1
0
1
X
1
0
X
1
1
P10.5 (I/O)
I: 0; O: 1
0
0
TA3.CCI1A
0
TA3.1
1
0
1
X
1
0
X
1
1
(3)
C0.7
(2)
5
L34
(4)
(5)
(4) (5)
(3)
C0.6
(1)
(2)
(3)
(1)
P10.4 (I/O)
L35
P10.5/TA3.1/C0.6/L34
CONTROL BITS OR SIGNALS
(4) (5)
X = Don't care
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Setting P10SEL1.x and P10SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C0.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
Detailed Description
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6.12.21 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
Figure 6-19 shows the port schematic. Table 6-83 lists the settings to select the port functions.
Pad Logic
Lz
LCDSz
To Comparator
From Comparator
CPD.q
PyMAP.x = PMAP_ANALOG
PyREN.x
PyDIR.x
00
DVSS
0
DVCC
1
1
01
Direction
0: Input
1: Output
10
11
PyOUT.x
00
From module
01
DVSS
10
DVSS
11
Py.x/Mod/Cp.q/Lz
PySEL1.x
PySEL0.x
PyIN.x
EN
To module
Bus
Keeper
D
Functional representation only.
Figure 6-19. Py.x/Mod/Cp.q/Lz Port Schematic
182
Detailed Description
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MSP432P401Y, MSP432P411V, MSP432P401V
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-83. Port P7 (P7.4 to P7.7) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
P7.4 (I/O)
P7.4/PM_TA1.4/C0.5/L3
1 (2)
4
(4) (5) (6)
(3)
(4) (5) (6)
1
0
X
X
1
1
X
I: 0; O: 1
0
0
X
0
1
default
X
1
0
X
X
1
1
X
I: 0; O: 1
0
0
X
0
1
default
X
1
0
X
X
1
1
X
I: 0; O: 1
0
0
X
0
1
default
X
1
0
X
X
1
1
X
TA1.2
1
(3)
(4) (5) (6)
TA1.CCI1A
0
TA1.1
1
L28
(3)
C0.2
(6)
X
0
P7.7 (I/O)
(5)
default
TA1.CCI2A
C0.3
(4)
1
1
L29
(1)
(2)
(3)
0
TA1.3
P7.6 (I/O)
7
X
0
C0.4
P7.7/PM_TA1.1/C0.2/L2
8 (2)
P7MAPx
0
TA1.CCI3A
L30
6
P7SEL0.x
0
1
P7.5 (I/O)
P7.6/PM_TA1.2/C0.3/L2
9 (2)
P7SEL1.x
TA1.4
C0.5
5
P7DIR.x
0
(3)
(4) (5) (6)
(1)
I: 0; O: 1
TA1.CCI4A
L31
P7.5/PM_TA1.3/C0.4/L3
0 (2)
CONTROL BITS OR SIGNALS
X = Don't care
Not available on the 64-pin RGC package.
Setting the PSEL1.x and PSEL0.x bits to 10 disables both the output driver and input Schmitt trigger to prevent leakage when analog
signals are applied.
Setting P7SEL1.x and P7SEL0.x disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
Setting the CEPD.q bit of the comparator disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals. Selecting the C0.q input pin to the comparator multiplexer with the CEIPSEL or CEIMSEL bits
automatically disables the output driver and input buffer for that pin, regardless of the state of the associated CEPD.q bit.
Setting P7MAPx = PM_ANALOG disables the output driver and the input Schmitt trigger independent of P7SEL1.x and P7SEL0.x
settings.
Detailed Description
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6.12.22 Port PJ (PJ.0 and PJ.1) Input/Output With Schmitt Trigger
Figure 6-20 and Figure 6-21 show the port schematics. Table 6-84 lists the settings to select the port
functions.
Pad Logic
To LFXT XIN
PJREN.0
PJDIR.0
00
01
10
Direction
0: Input
1: Output
11
PJOUT.0
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.0/LFXIN
PJSEL0.0
PJSEL1.0
PJIN.0
Bus
Keeper
EN
To modules
D
Functional representation only.
Figure 6-20. Port PJ (PJ.0) Port Schematic
184
Detailed Description
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Pad Logic
To LFXT XOUT
PJSEL0.0
PJSEL1.0
LFXTBYPASS
PJREN.1
PJDIR.1
00
01
10
Direction
0: Input
1: Output
11
PJOUT.1
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
PJ.1/LFXOUT
PJSEL0.1
PJSEL1.1
PJIN.1
Bus
Keeper
EN
To modules
D
Functional representation only.
Figure 6-21. Port PJ (PJ.1) Port Schematic
Detailed Description
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Table 6-84. Port PJ (PJ.0 and PJ.1) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (PJ.x)
x
FUNCTION
PJ.0 (I/O)
PJ.0/LFXIN
0
(2)
(2)
186
PJSEL0.0
LFXT
BYPASS
I: 0; O: 1
X
X
0
0
X
X
X
1
X
X
X
X
X
0
1
0
X
X
X
0
1
1
0
0
1
X
X
X
I: 0; O: 1
N/A
LFXOUT crystal mode
(3)
(4)
PJSEL1.0
1
0
DVSS
(1)
(2)
PJSEL0.1
0
PJ.1 (I/O)
1
PJSEL1.1
DVSS
LFXIN bypass mode
PJ.1/LFXOUT
PJDIR.x
N/A
LFXIN crystal mode
1
(2)
(1)
X
0
See
See
X
0
(4)
(4)
See
See
X
(4)
(4)
0
0
1
X
X
X
0
0
1
X
X
X
0
1
0
1
(3)
0
1
(3)
0
1
(3)
0
X = Don't care
Setting PJSEL1.0 = 0 and PJSEL0.0 = 1 causes the general-purpose I/O to be disabled. When LFXTBYPASS = 0, PJ.0 and PJ.1 are
configured for crystal operation and PJSEL1.1 and PJSEL0.1 are don't care. When LFXTBYPASS = 1, PJ.0 is configured for bypass
operation and PJ.1 is configured as general-purpose I/O.
When PJ.0 is configured in bypass mode, PJ.1 is configured as general-purpose I/O.
With PJSEL0.1 = 1 or PJSEL1.1 = 1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
Detailed Description
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6.12.23 Port PJ (PJ.2 and PJ.3) Input/Output With Schmitt Trigger
Figure 6-23 and Figure 6-22 show the port schematics. Table 6-85 lists the settings to select the port
functions.
Pad Logic
To HFXT XOUT
PJSEL0.3
PJSEL1.3
HFXTBYPASS
PJREN.2
PJDIR.2
00
01
10
Direction
0: Input
1: Output
11
PJOUT.2
DVSS
0
DVCC
1
1
00
DVSS
01
DVSS
10
DVSS
11
PJ.2/HFXOUT
PJSEL0.2
PJSEL1.2
PJIN.2
Bus
Keeper
EN
To modules
D
Functional representation only.
Figure 6-22. Port PJ (PJ.2) Port Schematic
Detailed Description
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Pad Logic
To HFXT XIN
PJREN.3
PJDIR.3
00
01
10
Direction
0: Input
1: Output
11
PJOUT.3
00
DVSS
01
DVSS
10
DVSS
11
DVSS
0
DVCC
1
1
PJ.3/HFXIN
PJSEL0.3
PJSEL1.3
PJIN.3
Bus
Keeper
EN
To modules
D
Functional representation only.
Figure 6-23. Port PJ (PJ.3) Port Schematic
188
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-85. Port PJ (PJ.2 and PJ.3) Pin Functions
CONTROL BITS OR SIGNALS
PIN NAME (PJ.x)
x
FUNCTION
PJ.3 (I/O)
PJ.3/HFXIN
3
(2)
(2)
PJSEL0.3
HFXT
BYPASS
I: 0; O: 1
X
X
0
0
X
X
X
1
X
X
X
X
X
0
1
0
X
X
X
0
1
1
0
0
1
X
X
X
I: 0; O: 1
N/A
HFXOUT crystal mode
(3)
(4)
PJSEL1.3
1
0
DVSS
(1)
(2)
PJSEL0.2
0
PJ.2 (I/O)
2
PJSEL1.2
DVSS
HFXIN bypass mode
PJ.2/HFXOUT
PJDIR.x
N/A
HFXIN crystal mode
1
(2)
(1)
X
0
See
See
X
0
(4)
(4)
See
See
X
(4)
(4)
0
0
1
X
X
X
0
0
1
X
X
X
0
1
0
1
(3)
0
1
(3)
0
1
(3)
0
X = Don't care
Setting PJSEL1.3 = 0 and PJSEL0.3 = 1 causes the general-purpose I/O to be disabled. When HFXTBYPASS = 0, PJ.2 and PJ.3 are
configured for crystal operation and PJSEL1.2 and PJSEL0.2 are don't care. When HFXTBYPASS = 1, PJ.3 is configured for bypass
operation and PJ.2 is configured as general-purpose I/O.
When PJ.3 is configured in bypass mode, PJ.2 is configured as general-purpose I/O.
With PJSEL0.2 = 1 or PJSEL1.2 = 1 the general-purpose I/O functionality is disabled. No input function is available. When configured as
output, the pin is actively pulled to zero.
Detailed Description
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6.12.24 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
Table 6-86 lists the settings to select the port functions.
Table 6-86. Port PJ (PJ.4 to PJ.5) Pin Functions
PIN NAME (P7.x)
x
FUNCTION
PJ.4 (I/O)
PJ.4/TDI
(2)
4
TDI
DVcc
DVcc
PJ.5 (I/O)
PJ.5/TDO/SWO
(5)
(4)
,
5
TDO
SWO
Hi-Z
(1)
(2)
(3)
(4)
(5)
190
CONTROL BITS OR SIGNALS
(1)
PJDIR.x
PJSEL1.x
PJSEL0.x
PJMAPx
SWJ MODE OF
OPERATION (1)
I: 0; O: 1
0
0
X
X
X
0
1
X
1
X
X
I: 0; O: 1
0
0
X
X
0
1
X
1
X
default
default
(3)
JTAG (4 wire)
SWD (2 wire)
X
X
(3)
JTAG (4 wire)
SWD (2 wire)
X
X
X indicates that the value of the control signal or mode of operation has no effect on the functionality.
This pin is internally pulled up if PJSEL0 is 1.
The 'default' value in the table indicates the functionality that is selected whenever a hard reset (or higher class reset) occurs.
This pin is has no internal pull feature. If used in User IO mode or left unused, it must be pulled to GND through an external pulldown
resistor.
After any hard reset (or higher class reset), this pin returns to TDO functionality with the SWJ in JTAG (4 wire) mode of operation. If
used as a User IO, it reflects the value of the external pullup until the PJSELx bits are reconfigured to the value 00.
Detailed Description
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6.12.25 Ports SWCLKTCK and SWDIOTMS With Schmitt Trigger
Table 6-87 lists the SWCLKTCK and SWDIOTMS pin functions.
Table 6-87. Ports SWCLKTCK and SWDIOTMS Pin Functions
PIN NAME
(1)
(2)
SWCLKTCK
(1)
SWDIOTMS
(2)
FUNCTION
SWJ MODE OF OPERATION
TCK (input)
JTAG (4 wire)
SWCLK (input)
SWD (2 wire)
TMS (input)
JTAG (4 wire)
SWDIO (I/O)
SWD (2 wire)
This pin is internally pulled to DVSS.
This pin is internal pulled to DVCC.
Detailed Description
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6.13 Device Descriptors (TLV)
Table 6-88 lists the Device IDs of the MSP432P4x1xI devices.
Table 6-88. Device IDs
DEVICE
DEVICE ID
MSP432P4111IPZ
0000A010h
MSP432P411YIPZ
0000A012h
MSP432P411VIPZ
0000A016h
MSP432P4011IRGC
0000A019h
MSP432P401YIRGC
0000A01Bh
MSP432P401VIRGC
0000A01Fh
Table 6-89 lists the contents of the device descriptor tag-length-value (TLV) structure for MSP432P4x1xI
devices.
Table 6-89. Device Descriptors (1)
DESCRIPTION
Info Block
Die Record
(1)
192
ADDRESS
VALUE
TLV checksum
00201000h
Per unit
Device info tag
00201004h
0000000Bh
Device info length
00201008h
00000004h
Device ID
0020100Ch
See Table 6-88.
Hardware revision
00201010h
00000041h
Boot code revision
00201014h
00430044h
ROM driver library revision
00201018h
03400011h
Die record tag
0020101Ch
0000000Ch
Die record length
00201020h
00000008h
Die X position
00201024h
Per unit
Die Y position
00201028h
Per unit
Wafer ID
0020102Ch
Per unit
Lot ID
00201030h
Per unit
Reserved
00201034h
Per unit
Reserved
00201038h
Per unit
Reserved
0020103Ch
Per unit
Test results
00201040h
FFFFFFFFh
Per unit = the contents can differ from device to device
Detailed Description
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SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Table 6-89. Device Descriptors(1) (continued)
DESCRIPTION
ADDRESS
VALUE
00201044h
00000003h
Clock system calibration length
00201048h
00000010h
DCO IR mode: frequency calibration for DCORSEL 0 to 4
0020104Ch
Per unit
DCO IR mode: frequency calibration for DCORSEL 5
00201050h
Per unit
Reserved
00201054h
000000C0h
Reserved
00201058h
000002C0h
Reserved
0020105Ch
0000002Ah
Reserved
00201060h
000002C0h
DCO IR mode: DCO constant (K) for DCORSEL 0 to 4
00201064h
Per unit
DCO IR mode: DCO constant (K) for DCORSEL 5
00201068h
Per unit
DCO ER mode: frequency calibration for DCORSEL 0 to 4
0020106Ch
Per unit
DCO ER mode: frequency calibration for DCORSEL 5
00201070h
Per unit
Reserved
00201074h
000000B4h
Reserved
00201078h
000002C0h
Reserved
0020107Ch
00000028h
Reserved
00201080h
000002C0h
DCO ER mode: DCO constant (K) for DCORSEL 0 to 4
00201084h
Per unit
DCO ER mode: DCO constant (K) for DCORSEL 5
00201088h
Per unit
ADC14 calibration tag
0020108Ch
00000005h
ADC14 calibration length
00201090h
00000018h
Reserved
00201094h
FFFFFFFFh
Reserved
00201098h
FFFFFFFFh
Reserved
0020109Ch
FFFFFFFFh
Reserved
002010A0h
FFFFFFFFh
Reserved
002010A4h
FFFFFFFFh
Reserved
002010A8h
FFFFFFFFh
Reserved
002010ACh
FFFFFFFFh
Reserved
002010B0h
FFFFFFFFh
Reserved
002010B4h
FFFFFFFFh
Reserved
002010B8h
FFFFFFFFh
Reserved
002010BCh
FFFFFFFFh
Reserved
002010C0h
FFFFFFFFh
Reserved
002010C4h
FFFFFFFFh
Reserved
002010C8h
FFFFFFFFh
Reserved
002010CCh
FFFFFFFFh
Reserved
002010D0h
FFFFFFFFh
Reserved
002010D4h
FFFFFFFFh
Reserved
002010D8h
FFFFFFFFh
ADC 1.2-V reference temperature sensor 30°C
002010DCh
Per unit
ADC 1.2-V reference temperature sensor 85°C
002010E0h
Per unit
ADC 1.45-V reference temperature sensor 30°C
002010E4h
Per unit
ADC 1.45-V reference temperature sensor 85°C
002010E8h
Per unit
ADC 2.5-V reference temperature sensor 30°C
002010ECh
Per unit
ADC 2.5-V reference temperature sensor 85°C
002010F0h
Per unit
REF calibration tag
002010F4h
00000008h
Clock system calibration tag
Clock System
Calibration
ADC14 Calibration
REF Calibration
REF calibration length
002010F8h
00000003h
Reserved
002010FCh
FFFFFFFFh
Reserved
00201100h
FFFFFFFFh
Reserved
00201104h
FFFFFFFFh
Detailed Description
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Table 6-89. Device Descriptors(1) (continued)
DESCRIPTION
Flash Info
ADDRESS
VALUE
Flash info tag
00201108h
00000004h
Flash info length
0020110Ch
00000002h
Flash maximum programming pulses
00201110h
00000005h
Flash maximum erase pulses
00201114h
0000014Eh
128-bit random number tag
00201118h
0000000Dh
128-bit random number length
0020111Ch
00000004h
00201120h
Per unit
00201124h
Per unit
00201128h
Per unit
Random Number
128-bit random number (2)
BSL Configuration
TLV End
0020112Ch
Per unit
BSL configuration tag
00201130h
0000000Fh
BSL configuration length
00201134h
00000004h
BSL peripheral interface selection
00201138h
FFC2D0C0h
BSL port interface configuration for UART
0020113Ch
FCFFFDA0h
BSL port interface configuration for SPI
00201140h
F0FF9770h
BSL port interface configuration for I2C
00201144h
FCFFFF72h
00201148h
0BD0E11Dh
0020114Ch to 00201FFFh
FFFFFFFFh
TLV end word
Reserved
(2)
194
128-bit random number: The random number is generated during production test using the CryptGenRandom() function from Microsoft®
Detailed Description
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6.14 Identification
6.14.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this
data sheet, see Section 8.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Hardware Revision entry in the Device Descriptor structure (see
Section 6.13).
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
Section 8.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the Device ID entry in the Device Descriptor structure (see Section 6.13).
6.14.3 Arm Cortex-M4F ROM Table Based Part Number
MSP432P4xx family of devices incorporate a part number for the device in addition to the device IDs
specified in the device descriptors (TLV) for the IDEs to recognize the device. This section describes how
this information is organized on the device.
The IEEE 1149.1 standard defines the use of a IDCODE register in the JTAG chain that provides the
fields in Table 6-90
Table 6-90. Structure of Device Identification Code
BIT POSITION
FIELD DESCRIPTION
31-28
Version
27-12
Part Number of the device
11-1
Manufacturer Identity
0
Reserved (Always tied to 1)
On MSP432P4xx devices all the fields in Table 6-90 are implemented on the Arm Cortex-M4 ROM table.
The part number can be read by the IDE tools to determine the device with which it is working.
Figure 6-24 shows the Peripheral ID register bit descriptions according to the Arm Cortex-M4
specifications.
Figure 6-24. Arm Cortex-M4 Peripheral ID Register Description
See the Arm Debug Interface V5 Architecture Specification for bit-level details on the Arm Cortex-M4
Peripheral ID registers.
Detailed Description
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From Figure 6-24 it is evident that a one-to-one mapping is not possible for the following fields from
Table 6-90
1. Version: IEEE 1149.1 defines a 4-bit field, whereas the CoreSight™ compliant PID registers have
4 bits each for Revision (major revision) and RevAnd (minor revision).
2. Part Number: IEEE 1149.1 defines a 16-bit entity. However, the PID registers in the ROM table have
only 12 bits reserved for this purpose (part number in the PID1 and PID0 registers).
For the MSP432P4xx family, the Revision and RevAnd fields are the major and minor revisions. Also the
4-bit customer-modified field extends the part number to 16 bits by accommodating all the fields needed
by IEEE 1149.1 into the ROM table.
The ROM table with IEEE 1149.1-complaint device IDCODE for MSP432P4x1x device example is 00001011-1011-0100-1101-0000-0010-1111 (see Figure 6-25).
Conceptual 64-bit Peripheral ID
ID7 register
7
ID6 register
0 7
ID5 register
0 7
ID4 register
0
7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
63
5655
48 47
40 39
ID3 register
0
7
ID2 register
0 7
0 0 0 0 0 0 0 0 1 0 1 1
36 35
32 31
28 27
JEP106
RevAnd
Continuation
Code
24 23
Customer
Modified
ID0 register
0
7
0
0 0 0 0 1 0 0 1 0 1 1 1 1 0 1 1 0 1 0 0 1 1 0 1
20 19 18
Reserved, RAZ
4KB
count
ID1 register
0 7
Revision
12 11
JEP106
ID code
0
Part Number
JEP106 code is used
Bits with no value shown are IMPLEMENTATION DEFINED.
Other bits not shown as Reserved are for an implementation designed by Arm Limited.
Figure 6-25. ROM PID Entries for MSP432P4x1x Device
196
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7 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers must validate and test
their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section describes the recommended guidelines when designing with the MSP432 microcontrollers.
These guidelines are to make sure that the device has proper connections for powering, programming,
debugging, and optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 4.7-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to each AVCC and DVCC pin (see Figure 7-1). Higher-value capacitors may be used but can
affect supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that
they decouple (within a few millimeters). Additionally, TI recommends separated grounds with a singlepoint connection for better noise isolation from digital-to-analog circuits on the board and to achieve high
analog accuracy.
DVCC
Digital
Power Supply
Decoupling
+
4.7 µF
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
+
4.7 µF 100 nF
AVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
The device supports a low-frequency crystal (32.768 kHz) on the LFXT pins and a high-frequency crystal
on the HFXT pins. External bypass capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes.
Figure 7-2 shows a typical connection diagram.
LFXIN
or
HFXIN
CL1
LFXOUT
or
HFXOUT
CL2
Figure 7-2. Typical Crystal Connection
Applications, Implementation, and Layout
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See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP432 devices.
7.1.3
General Layout Recommendations
•
•
•
•
7.1.4
Use proper grounding and short traces for the external crystal to reduce parasitic capacitance. See
MSP430 32-kHz Crystal Oscillators for recommended layout guidelines.
Use specified bypass capacitors on DVCC, AVCC, and reference pins, if used.
Do not route any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit.
Design in proper ESD level protection to protect the device from unintended high-voltage electrostatic
discharge. See MSP430 System-Level ESD Considerations for guidelines.
Do's and Don'ts
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up,
power down, and device operation, the voltage difference between AVCC and DVCC must not exceed the
limits specified in Section 5.1. Exceeding the specified limits may cause malfunction of the device.
7.2
Peripheral and Interface-Specific Design Information
7.2.1
Precision ADC Peripheral
7.2.1.1
Partial Schematic
Figure 7-3 shows the recommended circuit for grounding and noise reduction.
AVSS
Using an external
positive reference
VREF+/VeREF+
+
5 µF
50 nF
VeREFConnection to onboard ground
Figure 7-3. Precision ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, follow appropriate PCB layout and grounding techniques to eliminate
ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Section 7.2.1.1 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
Figure 7-3 shows the recommended decoupling circuit when an external voltage reference is used.
198
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 5-µF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A 50-nF bypass capacitor is used to filter out any high-frequency noise.
7.2.1.3
Layout Guidelines
Place components that are shown in the partial schematic (see Figure 7-3) as close as possible to the
respective device pins. Avoid long traces, because they add additional parasitic capacitance, inductance,
and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
If differential mode is used for the Precision ADC, the analog differential input signals must be routed
closely together to minimize the effect of noise on the resulting signal.
Applications, Implementation, and Layout
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8 Device and Documentation Support
8.1
Getting Started and Next Steps
For more information on the MSP432 family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started with MSP432P4x page.
8.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP432 MCU devices and support tools. Each MSP432 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP432P4111). TI recommends two of three possible
prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of
product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully
qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI internal qualification testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. TI recommends that these devices not be used in any production system because
their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZ) and temperature range (for example, T). Figure 8-1 provides a legend for
reading the complete device name for any family member.
200
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MSP432P401Y, MSP432P411V, MSP432P401V
www.ti.com
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MSP
432
P
4111
I
PZ
T
XX
Processor Family
Optional: Additional Features
MCU Platform
Optional: Distribution Format
Packaging
Series
Feature Set
Optional: Temperature Range
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
MCU Platform
432 = TI’s 32-bit Low-Power SimpleLink Microcontroller Platform
Series
P = Performance and Low-Power Series
Feature Set
First Digit
Second Digit
Third Digit
Fourth Digit
4 = Flash-based
devices
0 = General
purpose
1 = LCD
1 = ADC14
1 = 2048KB of flash
256KB of SRAM
Y = 1024KB of flash
256KB of SRAM
V = 512KB of flash
128KB of SRAM
Optional:
Temperature
Range
S = 0°C to 50°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional:
Distribution
Format
T = Small reel
R = Large reel
No markings = Tube or tray
Optional:
Additional
Features
-EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 8-1. Device Nomenclature
8.3
Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at Overview for Low Power +
Performance.
Table 8-1 lists the supported debug features. See the Code Composer Studio™ IDE for SimpleLink™
MSP432™ MCUs User's Guide for details on the available hardware features.
Table 8-1. Hardware Debug Features
FAMILY
JTAG
SWD
NUMBER OF
BREAKPOINTS
ITM
DWT
FPB
MSP432P4xx
Yes
Yes
4
Yes
Yes
Yes
EnergyTrace technology is supported with Code Composer Studio version 6.0 and newer. It requires
specialized debugger circuitry, which is supported with the second-generation onboard eZ-FET flash
emulation tool and second-generation stand-alone MSP-FET JTAG emulator.
Device and Documentation Support
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Design Kits and Evaluation Modules
MSP432P4111 LaunchPad Development Kit The MSP432P4111 LaunchPad development kit enables
you to develop high-performance applications that benefit from low-power operation. The kit
features the MSP432P4111, which includes a 48-MHz Arm Cortex-M4F, 100-µA/MHz active
power, and 820-nA RTC operation, 14-bit 1-Msps differential SAR ADC, and an AES256
accelerator.
100-Pin Target Development Board for MSP432P4x MCUs The MSP-TS432PZ100 is a stand-alone
ZIF socket target board used to program and debug the MSP432 in-system through the
JTAG interface or the Serial Wire Debug (SWD 2-wire JTAG) protocol. The development
board supports all MSP432P4x1x flash parts in a 100-pin LQFP package (TI package code:
PZ).
Software
SimpleLink MSP432™ Software Development Kit (SDK)
The SimpleLink MSP432 SDK is a
comprehensive software package that enables engineers to quickly develop highly functional
applications on MSP432 MCUs. The SDK comprises multiple compatible software
components including RTOS, drivers, middleware, and examples of how to use these
components together. Examples demonstrate each functional area and each supported
device and can be a starting point for your own projects. The SimpleLink MSP432 SDK is
part of TI’s SimpleLink platform allowing 100 percent code reuse between SimpleLink MCUs.
RTOS for MSP432™ Microcontrollers MSP432 MCUs offer compatibility with several TI and third party
Real-Time Operating Systems (RTOS). Visit this link to learn about the key features of each
to suit your design needs.
MSP EnergyTrace™ Technology EnergyTrace technology for MSP430 microcontrollers is an energybased code analysis tool that measures and displays the energy profile of the application
and helps to optimize it for ultra-low-power consumption.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code
Composer Studio is an integrated development environment (IDE) that supports all MSP
microcontroller devices. Code Composer Studio comprises a suite of embedded software
utilities used to develop and debug embedded applications. It includes an optimizing C/C++
compiler, source code editor, project build environment, debugger, profiler, and many other
features. For more information, see the Code Composer Studio™ IDE for SimpleLink™
MSP432™ MCUs User's Guide.
Arm® Keil® MDK – Free 32KB IDE The Arm Keil MDK is a complete debugger and C/C++ compiler
toolchain for building and debugging embedded applications. Keil MDK supports the lowpower + high performance MSP432 MCU family, and includes a fully integrated debugger for
source and disassembly level debugging with support for complex code and data breakpoint.
For more information, see the Arm® Keil® MDK Version 5 for SimpleLink™ MSP432™
MCUs User's Guide.
IAR Embedded Workbench® Kickstart IAR Embedded Workbench Kickstart for MSP is a complete
debugger and C/C++ compiler toolchain for building and debugging embedded applications
based on MSP430 and MSP432 microcontrollers. The code size limitation of C/C++ compiler
is set to 8KB for MSP430 devices and 32KB for MSP432 devices. For more information, see
the IAR Embedded Workbench for Arm 7.x for SimpleLink™ MSP432™ MCUs User's Guide.
MSP432P4xx CMSIS Device Family Pack TI provides a CMSIS-compliant device family pack for
MSP432P4xx devices. This pack adds MSP432P4xx device support to IAR EWARM 8.x, Keil
MDK 5.x, and Atollic TrueSTUDIO® 7.x. In IAR EWARM this pack is optional as the IDE
supports the devices natively.
Debuggers for MSP432™ MCUs MSP432 MCUs are designed to work with a variety of debuggers from
Texas Instruments and third-party vendors.
MSP MCU Programmer and Debugger The MSP-FET is a powerful emulation development tool – often
called a debug probe – which lets users quickly begin application development on MSP
MCUs.
202
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MSP-GANG Production Programmer The MSP Gang Programmer is an MSP430 and MSP432 device
programmer that can program up to eight identical MSP430 or MSP432 flash or FRAM
devices at the same time. The MSP Gang Programmer connects to a host PC using a
standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
Pin Mux Tool The Pin Mux Utility is a software tool that provides a graphical user interface for
configuring pin multiplexing settings, resolving conflicts, and specifying I/O cell
characteristics for TI MPUs. Results are output as C header and code files that can be
imported into SDKs or used to configure customer's custom software.
ULP (Ultra-Low Power) Advisor ULP Advisor™ software is a tool for guiding developers to write more
efficient code to fully use the unique ultra-low-power features of MSP430 and MSP432
microcontrollers. Aimed at both experienced and new microcontroller developers, ULP
Advisor checks your code against a thorough ULP checklist to squeeze every last nano amp
out of your application.
8.4
Documentation Support
The following documents describe the MCUs. Copies of these documents are available on the TI website.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (for links to the product folders, see Section 8.5). In the upper right corner, click the
"Alert me" button. This registers you to receive a weekly digest of product information that has changed (if
any). For change details, check the revision history of any revised document.
Errata
MSP432P4111 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP432P411Y Device Erratasheet Describes the known exceptions to the functional specifications.
MSP432P411V Device Erratasheet Describes the known exceptions to the functional specifications.
MSP432P4011 Device Erratasheet Describes the known exceptions to the functional specifications.
MSP432P401Y Device Erratasheet Describes the known exceptions to the functional specifications.
MSP432P401V Device Erratasheet Describes the known exceptions to the functional specifications.
User's Guides
MSP432P4xx SimpleLink™ Microcontrollers Technical Reference Manual Detailed description of all
modules and peripherals available in this device family.
Code Composer Studio™ IDE for SimpleLink™ MSP432™ Microcontrollers User's Guide
This
manual describes the use of the TI Code Composer Studio IDE (CCS) version 7.1 and later
with the MSP432 low-power microcontrollers.
IAR Embedded Workbench for Arm 7.x for SimpleLink™ MSP432™ Microcontrollers User's Guide
This manual describes the use of IAR Embedded Workbench for Arm (EWARM) version 7.x
with the MSP432 low-power microcontrollers.
Arm® Keil® MDK Version 5 for SimpleLink™ MSP432™ Microcontrollers User's Guide This user's
guide describes the use of the Arm Keil MDK version 5 with the MSP432 low-power
microcontrollers.
GCC Arm® Embedded Toolchain for SimpleLink™ MSP432™ Microcontrollers User's Guide
This
manual describes the setup and basic operation of the MSP432 programming and debug
using GCC Arm compiler and the GDB debugger.
Device and Documentation Support
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MSP432™ SimpleLink™ Microcontrollers Bootloader (BSL) User's Guide The MSP432 BSL lets
users communicate with embedded memory in the MSP432 microcontroller during the
prototyping phase, final production, and in service. Both the programmable memory (flash
memory) and the data memory (RAM) can be modified as required.
MSP432™ Capacitive Touch Software Library Programmer's Guide MSP432 microcontrollers are
equipped with the peripherals needed to perform a capacitance measurement. The purpose
of the capacitive touch software library is to create a single interface that can be integrated
with the peripheral set found in MSP432 devices. This document explains the capacitive
touch library configuration and use with MSP432 devices.
Application Reports
Platform Migrating to the SimpleLink™ MSP432™ Family The goals for this porting guide is to help
developers accurately assess the effort to port an existing application from one MSP
platform to another, ultimately to derive a porting strategy with complete hardware and
software coverage that properly ports the existing application without introducing bugs due to
platform differences yet taking advantages of the unique features or performance
improvements introduced in the new platform.
Designing an Ultra-Low-Power (ULP) Application With SimpleLink™ MSP432™ Microcontrollers
With the growing system complexity in ultra-low-power microcontroller applications,
minimizing the overall energy consumption is one of the most difficult problems to solve.
Multiple aspects including silicon, other onboard hardware components, and application
software must be considered. There are some obvious generic techniques that can be used
to reduce energy consumption such as reducing operating voltage or frequency. Many of
these generic techniques may not greatly reduce energy consumption independently, but
taken as a whole, the results can be significant, as there are many interdependencies across
these components.
Maximizing MSP432P4xx Voltage Regulator Efficiency
This application report describes the
relationship of the MSP432P4xx DC/DC and LDO, provides guidelines on choosing which is
most efficient for your application, and gives board layout considerations for the DC/DC.
Leveraging Low-Frequency Power Modes on SimpleLink™ MSP432P4xx Microcontrollers
Low
power consumption is very important in all battery-powered embedded applications. But the
operating frequency of these embedded applications can be diverse based the needs of the
application. Some applications might require operating at higher frequencies, in the order of
several megahertz, while some other applications might require operating at lower
frequencies, in the order of a few tens or a few hundreds of kilohertz. There are several
microcontrollers in the market that offer good active mode power consumption when the
operating frequency is in the order of several megahertz. But it is a challenge to get the
power consumption low when the operating frequency is in the order of kilohertz. The lowfrequency power modes available on the MSP432P4xx microcontrollers offer very low power
consumption when low frequency of operation is used by the target application.
Software IP Protection on MSP432P4xx Microcontrollers Differentiations in embedded software
applications enable differentiated products. Companies invest significant money in building
differentiated software application. Hence, protecting this investment (application or portions
of the application) is extremely important. This application note describes how to protect
software intellectual property (IP) running on the Texas Instruments MSP432P4xx family of
microcontrollers.
204
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8.5
SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018
Related Links
Table 8-2 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 8-2. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP432P4111
Click here
Click here
Click here
Click here
Click here
MSP432P4011
Click here
Click here
Click here
Click here
Click here
MSP432P411Y
Click here
Click here
Click here
Click here
Click here
MSP432P401Y
Click here
Click here
Click here
Click here
Click here
MSP432P411V
Click here
Click here
Click here
Click here
Click here
MSP432P401V
Click here
Click here
Click here
Click here
Click here
8.6
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.7
Trademarks
MSP432, SimpleLink, LaunchPad, EnergyTrace, ULP Advisor, E2E are trademarks of Texas Instruments.
CoreSight is a trademark of Arm Limited.
Arm, Cortex, Thumb, Keil are registered trademarks of Arm Limited.
Atollic TrueSTUDIO is a registered trademark of Atollic.
Bluetooth is a registered trademark of Bluetooth SIG.
ULPBench is a trademark of Embedded Microprocessor Benchmark Consortium.
Microsoft is a registered trademark of Microsoft Corporation.
Wi-Fi is a registered trademark of Wi-Fi Alliance.
8.8
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.9
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
Device and Documentation Support
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8.10 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation.
206
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP432P4011IRGCR
PREVIEW
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
P4011
MSP432P4011IRGCT
PREVIEW
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
P4011
MSP432P401VIRGCR
PREVIEW
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
P401V
MSP432P401VIRGCT
PREVIEW
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
P401V
MSP432P401YIRGCR
PREVIEW
VQFN
RGC
64
2000
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
P401Y
MSP432P401YIRGCT
PREVIEW
VQFN
RGC
64
250
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
P401Y
MSP432P4111IPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
MSP432P4111
MSP432P4111IPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
MSP432P4111
MSP432P411VIPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
MSP432P411V
MSP432P411VIPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
MSP432P411V
MSP432P411YIPZ
ACTIVE
LQFP
PZ
100
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
MSP432P411Y
MSP432P411YIPZR
ACTIVE
LQFP
PZ
100
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
MSP432P411Y
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jan-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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