Revised May 2005 MM74HC573 3-STATE Octal D-Type Latch General Description Features The MM74HC573 high speed octal D-type latches utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. ■ Typical propagation delay: 18 ns ■ Wide operating voltage range: 2 to 6 volts ■ Low input current: 1 PA maximum ■ Low quiescent current: 80 PA maximum (74HC Series) ■ Compatible with bus-oriented systems ■ Output drive capability: 15 LS-TTL loads When the LATCH ENABLE(LE) input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a HIGH logic level is applied to the OUTPUT CONTROL OC input, all outputs go to a HIGH impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function and pinout compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Ordering Code: Order Number Package Number MM74HC573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC573SJ MM74HC573MTC MM74HC573N MTC20 N20A Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table H L Q0 Z X Output Latch Data Output Control Enable L L H H H H L L L L X Q0 H X X Z HIGH Level LOW Level Level of output before steady-state input conditions were established. High Impedance Don't Care Top View © 2005 Fairchild Semiconductor Corporation DS005212 www.fairchildsemi.com MM74HC573 3-STATE Octal D-Type Latch September 1983 MM74HC573 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions (Note 2) 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Min Max Supply Voltage (VCC) 2 6 V DC Input or Output Voltage 0 VCC V 40 85 qC (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Symbol VIH VIL VOH Parameter ns VCC 6.0V 400 ns Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. VCC TA 25qC Typ TA 40 to 85qC TA 55 to 125qC Guaranteed Limits Units 2.0V 1.5 1.5 1.5 Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V V V Maximum LOW Level Input 2.0V 0.5 0.5 0.5 Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Minimum HIGH Level Output VIN Voltage |IOUT| d 20 PA VIH or VIL 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| d 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| d 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V VIH or VIL Maximum LOW Level Output VIN VIH or VIL Voltage |IOUT| d 20 PA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V V VIH or VIL |IOUT| d 6.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT| d 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V VIN 6.0V r0.1 r1.0 r1.0 PA 6.0V r0.5 r5.0 r10 PA 8.0 80 160 PA 1.5 1.8 2.0 mA IIN Maximum Input Current IOZ Maximum 3-STATE Output VOUT Leakage Current OC VIH Maximum Quiescent Supply VIN VCC or GND Current IOUT 0 PA 6.0V Quiescent Supply Current VCC 5.5V OE 'ICC ns 500 Minimum HIGH Level Input VIN ICC 1000 4.5V (Note 4) Conditions VIN VOL 2.0V VCC Note 2: Unless otherwise specified all voltages are referenced to ground. 260qC DC Electrical Characteristics VCC Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Lead Temperature (TL) (Soldering 10 seconds) Units per Input Pin VIN VCC or GND VCC or GND 1.0 2.4V LE 0.6 0.8 1.0 1.1 mA or 0.4V (Note 4) DATA 0.4 0.5 0.6 0.7 mA Note 4: For a power supply of 5V r10% the worst-case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst-case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst-case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2 VCC 5V, TA 25qC, tr tf 6 ns Symbol Parameter Conditions Typ Guaranteed Limit Units tPHL, tPLH Maximum Propagation Delay, Data to Q CL 45 pF 16 20 ns tPHL, tPLH Maximum Propagation Delay, LE to Q CL 45 pF 14 22 ns tPZH, tPZL Maximum Output Enable Time RL 1 k: 15 27 ns CL 45 pF RL 1 k: 13 23 ns CL 5 pF tPHZ, tPLZ Maximum Output Disable Time tS Minimum Set Up Time, Data to LE 10 15 ns tH Minimum Hold Time, LE to Data 2 5 ns tW Minimum Pulse Width, LE or Data 10 16 ns AC Electrical Characteristics Symbol tPHL, tPLH tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tS tH Parameter Conditions VCC TA tTLH, tTHL CIN 40 to 85qC TA 55 to 125qC Guaranteed Limits Units CL 50 pF 2.0V 45 110 138 165 ns Delay Data to Q CL 150 pF 2.0V 58 150 188 225 ns CL 50 pF 4.5V 17 22 28 33 ns CL 150 pF 4.5V 21 30 38 40 ns CL 50 pF 6.0V 15 19 24 29 ns CL 150 pF 6.0V 19 26 33 39 ns Maximum Propagation CL 50 pF 2.0V 46 115 138 165 ns Delay, LE to Q CL 150 pF 2.0V 60 155 194 233 ns CL 50 pF 4.5V 14 23 29 35 ns CL 150 pF 4.5V 21 31 47 47 ns CL 50 pF 6.0V 12 20 25 30 ns CL 150 pF 6.0V 19 27 34 41 ns Maximum Output Enable RL 1 k: Time CL 50 pF 2.0V 55 140 175 210 ns CL 150 pF 2.0V 67 180 225 270 ns CL 50 pF 4.5V 15 28 35 42 ns CL 150 pF 4.5V 24 36 45 54 ns CL 50 pF 6.0V 14 24 30 36 ns CL 150 pF 6.0V 22 31 39 47 ns Maximum Output Disable RL 1 k: 2.0V 40 125 156 188 ns Time CL 50 pF 4.5V 13 25 31 38 ns ns 6.0V 12 21 27 32 Minimum Set Up Time 2.0V 30 75 95 110 ns Data to LE 4.5V 10 15 19 22 ns 6.0V 9 13 16 19 ns Minimum Hold Time 2.0V 25 31 38 ns LE to Data 4.5V 5 6 7 ns 4 5 6 ns Minimum Pulse Width LE, 2.0V 30 80 100 120 ns or Data 4.5V 9 16 20 24 ns 6.0V 8 14 18 20 ns 2.0V 25 60 75 90 ns 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 Maximum Output Rise CL 50 pF and Fall Time, Clock CPD TA Maximum Propagation 6.0V tW 25qC Typ Power Dissipation Capacitance OC VCC 5 (Note 5) (per latch) OC GND 52 Maximum Input 5 ns pF pF 10 10 10 pF Capacitance 3 www.fairchildsemi.com MM74HC573 AC Electrical Characteristics MM74HC573 AC Electrical Characteristics Symbol COUT Parameter (Continued) Conditions VCC Maximum Output TA 25qC Typ 15 TA 40 to 85qC TA 55 to 125qC 20 20 20 Capacitance Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f I CC. www.fairchildsemi.com CPD VCC2 f ICC VCC, and the no load dynamic current consumption, 4 Units Guaranteed Limits pF MM74HC573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HC573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HC573 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HC573 3-STATE Octal D-Type Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8