ON MC74HC373ANG Octal 3−state non−inverting transparent latch high−performance silicon−gate cmo Datasheet

MC74HC373A
Octal 3−State Non−Inverting
Transparent Latch
High−Performance Silicon−Gate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
high−impedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the non−inverting version of the HC533A.
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MARKING
DIAGRAMS
20
20
PDIP−20
N SUFFIX
CASE 738
1
1
20
20
1
Features
•
•
•
•
•
•
•
•
MC74HC373AN
AWLYYWWG
SOIC−20
DW SUFFIX
CASE 751D
74HC373A
AWLYYWWG
1
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7.0 A Requirements
Chip Complexity: 186 FETs or 46.5 Equivalent Gates
Pb−Free Packages are Available*
20
20
1
HC
373A
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
1
20
1
20
SOEIAJ−20
F SUFFIX
CASE 967
1
74HC373A
AWLYWWG
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
July, 2005 − Rev. 12
1
Publication Order Number:
MC74HC373A/D
MC74HC373A
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
11
1
Q0
Q1
Q2
Q3
NONINVERTING
OUTPUTS
Q4
VCC
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
D2
7
14
D5
D3
8
13
D4
Q3
9
12
Q4
10
11
LATCH
ENABLE
GND
Q7
FUNCTION TABLE
PIN 20 = VCC
PIN 10 = GND
Inputs
Output
Enable
Units
Internal Gate Count*
46.5
ea
Internal Gate Propagation Delay
1.5
ns
5.0
mW
0.0075
pJ
Speed Power Product
20
Q6
Value
Internal Gate Power Dissipation
1
Q5
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Design Criteria
OUTPUT
ENABLE
Q0
*Equivalent to a two−input NAND gate.
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2
Latch
Enable
L
H
L
H
L
L
H
X
X = Don’t Care
Z = High Impedance
Output
D
Q
H
L
X
X
H
L
No Change
Z
MC74HC373A
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 35
mA
ICC
DC Supply Current, VCC and GND Pins
± 75
mA
PD
Power Dissipation in Still Air,
750
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
Plastic DIP†
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
Min
Max
Unit
2.0
6.0
V
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 1)
0
VCC
V
– 55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
ORDERING INFORMATION
Package
Shipping †
MC74HC373AN
PDIP−20
18 Units / Box
MC74HC373ANG
PDIP−20
(Pb−Free)
18 Units / Box
MC74HC373ADW
SOIC−20 WIDE
38 Units / Rail
MC74HC373ADWG
SOIC−20 WIDE
(Pb−Free)
38 Units / Rail
MC74HC373ADWR2
SOIC−20 WIDE
1000 Units / Reel
MC74HC373ADWR2G
SOIC−20 WIDE
(Pb−Free)
1000 Units / Reel
MC74HC373ADT
TSSOP−20*
75 Units / Rail
MC74HC373ADTG
TSSOP−20*
75 Units / Rail
MC74HC373ADTR2
TSSOP−20*
2500 Units / Reel
MC74HC373ADTR2G
TSSOP−20*
2500 Units / Reel
MC74HC373AF
SOEIAJ−20
40 Units / Rail
MC74HC373AFG
SOEIAJ−20
(Pb−Free)
40 Units / Rail
MC74HC373AFEL
SOEIAJ−20
2000 Units / Reel
MC74HC373AFELG
SOEIAJ−20
(Pb−Free)
2000 Units / Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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3
MC74HC373A
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DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VIH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
Vout = VCC – 0.1 V
|Iout| v 20 mA
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V
|Iout| v 20 mA
VOH
Minimum High−Level Output
Voltage
Vin = VIH
|Iout| v 20 mA
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VIH
VOL
Maximum Low−Level Output
Voltage
Vin = VIL
|Iout| v 20 mA
|Iout| v 2.4 mA
|Iout| v 6.0 mA
|Iout| v 7.8 mA
Vin = VIL
Iin
IOZ
Maximum Input Leakage Current
Maximum Three−State
Leakage Current
Vin = VCC or GND
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
– 55 to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
± 0.1
± 0.5
v 85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
± 1.0
± 5.0
v 125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
± 1.0
± 10
Unit
V
V
V
V
mA
mA
Maximum Quiescent Supply
Vin = VCC or GND
6.0
4.0
40
160
mA
Current (per Package)
Iout = 0 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
ICC
Symbol
tPLH
tPHL
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Parameter
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
tPLH
tPHL
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
tPLZ
tPHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tPZL
tPZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
tTLH
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
Cin
Cout
Guaranteed Limit
– 55 to 25_C
125
80
25
21
140
90
28
24
150
100
30
26
150
100
30
26
60
23
12
10
10
15
v 85_C
155
110
31
26
175
120
35
30
190
125
38
33
190
125
38
33
75
27
15
13
10
15
v 125_C
190
130
38
32
210
140
42
36
225
150
45
38
225
150
45
38
90
32
18
15
10
15
Unit
ns
ns
ns
ns
ns
Maximum Input Capacitance
pF
Maximum Three−State Output Capacitance
pF
(Output in High−Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
36
CPD
Power Dissipation Capacitance (Per Enabled Output)*
pF
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
MC74HC373A
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TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Figure
VCC
Volts
v 85_C
– 55 to 25_C
Min
Max
Min
v 125_C
Max
Min
Max
Unit
tsu
Minimum Setup Time, Input D to Latch Enable
4
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
th
Minimum Hold Time, Latch Enable to Input D
4
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
50
5.0
5.0
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Latch Enable
2
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tr, tf
Maximum Input Rise and Fall Times
1
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
tr
tf
INPUT D
tPLH
tPHL
90%
50%
10%
Q
tw
VCC
90%
50%
10%
LATCH ENABLE
GND
GND
Q
50%
Figure 1.
OUTPUT
ENABLE
VCC
GND
tPLZ
50%
tPZH
Q
Figure 2.
50%
tPZL
Q
tPHL
tPLH
tTHL
tTLH
VCC
50%
HIGH
IMPEDANCE
10%
VOL
90%
VOH
tPHZ
1.3 V
VALID
INPUT D
tsu
LATCH ENABLE
Figure 4.
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5
th
50%
HIGH
IMPEDANCE
Figure 3.
VCC
50%
GND
VCC
GND
MC74HC373A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
C L*
C L*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
D0
3
Figure 6.
D1
4
D
Q
D2
7
D
LE
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
OUTPUT
Q
D3
8
D
LE
Q
D4
13
D
LE
Q
D5
14
D
LE
Q
D6
17
D
LE
Q
D7
18
D
LE
Q
D
LE
Q
LE
11
1
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
Figure 7. EXPANDED LOGIC DIAGRAM
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6
15
Q5
16
Q6
19
Q7
MC74HC373A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
−A−
20
11
1
10
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
0.25 (0.010)
20 PL
0.25 (0.010)
M
T A
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
M
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
20
11
X 45 _
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
A
B
M
D
18X
e
A1
SEATING
PLANE
C
T
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7
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HC373A
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
S
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
11
J J1
B
−U−
L
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
N
0.15 (0.006) T U
S
M
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
D
G
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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8
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
−−− 0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC74HC373A
PACKAGE DIMENSIONS
SOEIAJ−20
F SUFFIX
CASE 967−01
ISSUE O
20
LE
11
Q1
E HE
1
M_
L
10
DETAIL P
Z
D
VIEW P
e
A
c
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
0.10 (0.004)
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9
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.81
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
0_
10 _
0.028
0.035
−−− 0.032
MC74HC373A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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