INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4041B buffers Quadruple true/complement buffer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4041B buffers Quadruple true/complement buffer DESCRIPTION The HEF4041B is a quadruple true/complement buffer which provides both an inverted active LOW output (O) and a non-inverted active HIGH output (O) for each input (I). The buffers exhibit high current output capability suitable for driving TTL or high capacitive loads. Fig.2 Pinning diagram. HEF4041BP(N): 14-lead DIL; plastic (SOT27-1) HEF4041BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4041BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one buffer). APPLICATION INFORMATION Some examples of applications for the HEF4041B are: • LOCMOS to DTL/TTL converter • High current sink and source driver Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category BUFFERS See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4041B buffers Quadruple true/complement buffer DC CHARACTERISTICS VSS = 0 V; VI = VSS or VDD Tamb (°C) VDD V VOH V VOL V −40 SYMBOL +25 +85 MIN. MAX. MIN. TYP. Output (source) current HIGH HIGH Output (sink) current LOW 5 4,6 10 9,5 15 13,5 5 2,5 1,6 −IOH 4,75 0,4 10 0,5 15 1,5 1,3 2,6 MIN. MAX. 1,0 mA 4,5 3,6 7,0 2,7 mA 16,0 14,0 30,0 10,0 mA −IOH 5,0 4,0 8,0 3,0 mA 2,0 1,7 4,0 1,35 mA IOL 7,5 6,0 12,0 4,5 mA 23,0 20,0 35,0 15,0 mA AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays In → On HIGH to LOW 30 65 ns 17 ns + (0,27 ns/pF) CL 20 40 ns 14 ns + (0,11 ns/pF) CL 15 30 ns 12 ns + (0,08 ns/pF) CL 30 55 ns 17 ns + (0,27 ns/pF) CL 15 30 ns 9 ns + (0,11 ns/pF) CL 15 10 20 ns 7 ns + (0,08 ns/pF) CL 5 35 75 ns 22 ns + (0,27 ns/pF) CL 5 10 tPHL 15 5 LOW to HIGH In → On HIGH to LOW LOW to HIGH Output transition times On → On HIGH to LOW LOW to HIGH 10 tPLH 20 40 ns 14 ns + (0,11 ns/pF) CL 15 15 30 ns 12 ns + (0,08 ns/pF) CL 5 35 75 ns 22 ns + (0,27 ns/pF) CL 10 tPHL 20 40 ns 14 ns + (0,11 ns/pF) CL 15 15 30 ns 12 ns + (0,08 ns/pF) CL 5 25 50 ns 5 ns + (0,40 ns/pF) CL 10 tPLH 12 25 ns 2 ns + (0,21 ns/pF) CL 15 8 20 ns 1 ns + (0,14 ns/pF) CL 5 25 45 ns 5 ns + (0,40 ns/pF) CL 12 25 ns 2 ns + (0,21 ns/pF) CL 8 20 ns 1 ns + (0,14 ns/pF) CL 10 10 tTHL tTLH 15 January 1995 3 Philips Semiconductors Product specification HEF4041B buffers Quadruple true/complement buffer VDD V Dynamic power 5 TYPICAL FORMULA FOR P (µW) 3100 fi + ∑(foCL) × VDD2 dissipation per 10 12 700 fi + ∑(foCL) × package (P) 15 33 800 fi + ∑(foCL) × VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4