19-2861; Rev 3; 2/07 KIT ATION EVALU E L B AVAILA Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Features The MAX1540A/MAX1541 dual pulse-width modulation (PWM) controllers provide the high efficiency, excellent transient response, and high DC-output accuracy necessary for stepping down high-voltage batteries to generate low-voltage chipset and RAM power supplies in notebook computers. The Maxim proprietary Quick-PWM™ controllers are free running, constant on-time with input feed forward. This configuration provides ultra-fast transient response, wide input-output (I/O) differential range, low supply current, and tight load-regulation characteristics. The controllers can accurately sense the inductor current across an external current-sense resistor in series with the output to ensure reliable overload and inductor saturation protection. Alternatively, the controllers can use the synchronous rectifier itself or lossless inductor current-sensing methods to provide overload protection with lower power dissipation. ♦ Inductor-Saturation Protection ♦ Accurate Differential Current-Sense Inputs ♦ Dual Ultra-High-Efficiency Quick-PWMs with 100ns Load-Step Response ♦ MAX1540A 1.8V/1.2V Fixed or 0.7V to 5.5V Adjustable Output (OUT1) 2.5V/1.5V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Fixed 5V, 100mA Linear Regulator ♦ MAX1541 External Reference Input (REFIN1) Dynamically Selectable Output Voltage—0.7V to 5.5V (OUT1) 2.5V/1.8V Fixed or 0.7V to 5.5V Adjustable Output (OUT2) Optional Power-Good and Fault Blanking During Transitions Fixed 5V or Adjustable 100mA Linear Regulator ♦ 1% VOUT Accuracy over Line and Load ♦ 2V to 28V Battery Input Range ♦ 170kHz to 620kHz Selectable Switching Frequency ♦ Overvoltage/Undervoltage-Protection Option ♦ 1.7ms Digital Soft-Start ♦ Drives Large Synchronous-Rectifier FETs ♦ 2V ±0.7% Reference Output ♦ Separate Power-Good Window Comparators For a single step-down PWM controller with inductorsaturation protection, external-reference input voltage, and dynamically selectable output voltages, refer to the MAX1992/MAX1993 data sheet. Applications Notebook Computers Core/I/O Supplies as Low as 0.7V 0.7V to 5.5V Supply Rails CPU/Chipset/GPU with Dynamic Voltage Core Supplies (MAX1541) Pin Configurations T4066-5 +Denotes a lead-free package. LX1 LDOON DL1 LDOOUT V+ DL2 GND 22 21 20 19 18 17 29 12 OUT2 CSP1 30 11 FB2 ON2 31 10 CSN2 ON1 32 9 CSP2 MAX1540A 8 40 Thin QFN 6mm x 6mm PGOOD2 CSN1 REF -40°C to +85°C 13 7 MAX1541ETL+ 28 ILIM2 T4066-5 DH2 FB1 6 40 Thin QFN 6mm x 6mm 14 ILIM1 -40°C to +85°C 27 5 MAX1541ETL LX2 OUT1 VCC T3255-4 BST2 15 4 -40°C to +85°C T3255-4 16 26 3 MAX1540AETJ+ 32 Thin QFN 5mm x 5mm MAX1540AETJ 25 TON -40°C to +85°C 32 Thin QFN 5mm x 5mm DH1 PGOOD1 LSAT PKG CODE 1 PINPACKAGE 2 TEMP RANGE SKIP PART BST1 Ordering Information 23 TOP VIEW OVP/UVP Active Termination Buses (MAX1541) 24 DDR Memory Termination (MAX1541) THIN QFN A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. Quick-PWM is a trademark of Maxim Integrated Products, Inc. Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX1540A/MAX1541 General Description MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator ABSOLUTE MAXIMUM RATINGS V+, LDOON to GND ...............................................-0.3V to +28V LDOOUT to GND (MAX1540A, Note 1)....................-0.3V to +6V LDOOUT to GND (MAX1541, Note 1) ....................-0.3V to +28V VDD to GND (MAX1541, Note 1) ..............................-0.3V to +6V VCC, ON_ to GND.....................................................-0.3V to +6V SKIP, PGOOD_ to GND............................................-0.3V to +6V FB_, CSP_, ILIM_ to GND.........................................-0.3V to +6V TON, OVP/UVP, LSAT to GND ...................-0.3V to (VCC + 0.3V) REF, OUT_ to GND.....................................-0.3V to (VCC + 0.3V) LDOIN to GND (MAX1541).....................................-0.3V to +28V REFIN1, GATE, OD, FBLDO to GND (MAX1541).....-0.3V to +6V FBLANK, CC1 to GND (MAX1541).............-0.3V to (VCC + 0.3V) DL_ to GND (Note 1) ..................................-0.3V to (VDD + 0.3V) CSN_ to GND ............................................................-2V to +30V DH_ to LX_..................................................-0.3V to (BST + 0.3V) LX_ to GND................................................................-2V to +30V BST_ to LX_ ..............................................................-0.3V to +6V REF Short Circuit to GND ...........................................Continuous Continuous Power Dissipation (TA = +70°C) 32-Pin 5mm x 5mm Thin QFN (derated 21.3mW/°C above +70°C).............................................................1702mW 40-Pin 6mm x 6mm Thin QFN (derated 26.3mW/°C above +70°C).............................................................2105mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Note 1: For the MAX1540A, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT), and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+). Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN MAX1540A: battery voltage, V+ > VLDOOUT 5.5 TYP MAX UNITS INPUT SUPPLIES (Note 1) VIN Input Voltage Range VBIAS VLDOIN MAX1541: battery voltage, V+ > VLDOOUT 2 28 VCC, VDD (MAX1541) 4.5 5.5 MAX1541: LDO input supply, VLDOIN > VLDOOUT 4.5 28 FB1 and FB2 forced above the regulation point, LSAT = GND Quiescent Supply Current (VCC) Quiescent Supply Current (VDD, MAX1541 Only) Quiescent Supply Current (V+) ICC IDD IV+ Standby Supply Current (VCC) 2 ILDOIN 0.7 V 1.5 mA FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLSAT > 0.5V FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC 1.8 <1 MAX1540A: FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V MAX1541: ON1 or ON2 = VCC, VLDOON = V+ = 28V Quiescent Supply Current (LDOIN, MAX1541 Only) 28 µA 150 µA 25 FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V ON1 = ON2 = GND, VLDOON = V+ = 28V 5 <1 _______________________________________________________________________________________ 40 110 µA 5 µA Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Standby Supply Current (VDD, MAX1541 Only) CONDITIONS MIN ON1 = ON2 = GND, VLDOON = V+ = 28V TYP MAX UNITS <1 5 µA MAX1540A: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = 0 or 5V Standby Supply Current (V+) 105 µA MAX1541: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = VDD = 0 or 5V Standby Supply Current (LDOIN, MAX1541 Only) ON1 = ON2 = GND, VLDOON = V+ = 28V Shutdown Supply Current (VCC) ON1 = ON2 = LDOON = GND Shutdown Supply Current (VDD, MAX1541 Only) ON1 = ON2 = LDOON = GND <1 MAX1540A: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = 0 or 5V Shutdown Supply Current (V+) 100 µA <1 5 µA <1 5 µA 4 15 µA MAX1541: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = VDD = 0 or 5V Shutdown Supply Current (LDOIN, MAX1541 Only) 5 LDOON = GND <1 5 4 10 µA PWM CONTROLLERS MAX1540A Main Output-Voltage Accuracy (OUT1) (Note 2) 1.782 1.80 1.818 FB1 = VCC 1.188 1.20 1.212 0.693 0.70 0.707 FB2 = GND 2.475 2.50 2.525 FB2 = VCC 1.485 1.50 1.515 VFB2 Adjustable output, V+ = 5.5V to 28V, SKIP = VCC 0.693 0.70 0.707 VFB1 V+ = 4.5V to 28V, SKIP = VCC REFIN1 = 0.35 x REF 0.693 0.70 0.707 Preset output, V+ = 4.5V to 28V, SKIP = VCC FB2 = GND 2.475 2.50 2.525 VOUT2 FB2 = VCC 1.782 1.80 1.818 0.693 0.70 0.707 VFB1 MAX1540A Secondary OutputVoltage Accuracy (OUT2) (Note 2) MAX1541 Main FeedbackVoltage Accuracy (FB1) MAX1541 Secondary OutputVoltage Accuracy (OUT2) (Note 2) Preset output, V+ = 5.5V to 28V, SKIP = VCC FB1 = GND VOUT1 VOUT2 VFB2 Adjustable output, V+ = 5.5V to 28V, SKIP = VCC Preset output, V+ = 5.5V to 28V, SKIP = VCC Adjustable output, V+ = 4.5V to 28V, SKIP = VCC Load-Regulation Error ILOAD = 0 to 3A, SKIP = VCC 0.1 Line-Regulation Error VCC = 4.5V to 5.5V, V+ = 4.5V to 28V 0.25 FB_ Input Bias Current Output Adjust Range IFB_ V V V V % % -0.1 +0.1 µA 0.7 5.5 V _______________________________________________________________________________________ 3 MAX1540A/MAX1541 ELECTRICAL CHARACTERISTICS (continued) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MAX1540A OUT_ Input Resistance ROUT_ MAX1541 OUT_ Discharge Mode OnResistance MIN TYP MAX FB_ = GND 70 145 350 FB_ = VCC or adjustable 50 115 220 FB1 = OUT1 400 700 1500 FB2 = GND 90 170 350 FB2 = VCC or adjustable 60 130 270 10 25 Ω 0.3 0.4 V RDISCHARGE OUT_ Synchronous-Rectifier Discharge-Mode Turn-On Level 0.2 Soft-Start Ramp Time tSS DH1 On-Time tON1 DH2 On-Time tON2 Rising edge on ON_ to full current limit V+ = 15V, VOUT1 = 1.5V (Note 3) V+ = 15V, VOUT2 = 1.5V (Note 3) Minimum Off-Time ms 149 169 190 TON = REF (485kHz) 191 216 242 TON = open (345kHz) 274 304 335 TON = VCC (235kHz) 402 447 491 TON = GND (460kHz) 201 228 256 TON = REF (355kHz) 260 296 331 TON = open (255kHz) 371 412 453 556 618 679 120 135 150 % 400 500 ns 5.0 5.10 tON2 with respect to tON1 (Note 3) tOFF(MIN) kΩ TON = GND (620kHz) TON = VCC (170kHz) On-Time Tracking 1.7 UNITS (Note 3) ns ns LINEAR REGULATOR (LDO) (Note 1) MAX1540A LDO Output-Voltage Accuracy VLDOOUT ON1 = ON2 = GND, V+ = 6V to 28V 0 < ILDOOUT < 10mA 4.85 0 < ILDOOUT < 100mA 4.70 MAX1541 LDO Output-Voltage Accuracy (Fixed VLDOOUT) FBLDO = ON1 = ON2 = GND, VLDOIN = 6V to 28V 0 < ILDOOUT < 10mA 4.85 VLDOOUT 0 < ILDOOUT < 100mA 4.70 FBLDO = LDOOUT, ON1 = ON2 = GND, VLDOIN = 4.5V to 28V 0 < ILDOOUT < 10mA 1.212 0 < ILDOOUT < 100mA 1.175 1.275 1.175 24 MAX1541 LDO Feedback Accuracy (Adjustable VLDOOUT) VFBLDO 4 5.10 5.10 1.25 1.275 V LDOOUT Short-Circuit Current Dropout Voltage 5.0 V V MAX1541 LDO Output Adjust Range FBLDO Input Bias Current 5.10 130 IFBLDO -0.1 mA +0.1 MAX1540A: V+ - VLDOOUT, ILDOOUT = 50mA 500 800 MAX1541: VLDOIN - VLDOOUT, ILDOOUT = 50mA 500 800 _______________________________________________________________________________________ V µA mV Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX TA = +25°C to +85°C 1.986 2.00 2.014 TA = 0°C to +85°C 1.983 2.00 2.017 UNITS REFERENCE (REF) Reference Voltage VREF Reference Load Regulation REF Lockout Voltage ΔVREF VCC = 4.5V to 5.5V, IREF = 0V IREF = -10µA to +50µA -0.01 VREF(UVLO) Rising edge, hysteresis = 350mV REFIN1 (MAX1541) Voltage Range VREFIN REFIN1 (MAX1541) Input Bias Current IREFIN1 +0.01 1.95 0.7 V V V VREF V 0.01 0.05 µA 16 20 % FAULT DETECTION With respect to error-comparator threshold, OVP/UVP = VCC Overvoltage Trip Threshold Overvoltage Fault-Propagation Delay tOVP Output Undervoltage-Protection Trip Threshold Output Undervoltage-Protection Blanking Time Output Undervoltage FaultPropagation Delay tBLANK 12 FB forced 2% above trip threshold 10 With respect to error-comparator threshold, OVP/UVP = VCC 65 From rising edge of ON_ 10 70 µs 75 % 35 ms 10 tUVP µs PGOOD_ Lower Trip Threshold With respect to error-comparator threshold, hysteresis = 1% -13 -10 -7 % PGOOD_ Upper Trip Threshold With respect to error-comparator threshold, hysteresis = 1% +7 +10 +13 % PGOOD_ Propagation Delay tPGOOD_ PGOOD_ Output Low Voltage PGOOD_ Leakage Current Fault-Blanking Time (MAX1541 Only) VCC Undervoltage-Lockout Threshold 10 ISINK = 4mA IPGOOD_ tFBLANK Thermal-Shutdown Threshold FB forced 2% beyond PGOOD_ trip threshold TSHDN VUVLO(VCC) FB = REF (PGOOD high impedance), PGOOD forced to 5.5V µs 0.3 V 1 µA FBLANK = VCC 120 220 320 FBLANK = open 80 140 205 FBLANK = REF 35 65 95 Hysteresis = 10°C LDOON = VCC +150 LDOON = GND +160 Rising edge, PWM disabled below this level, hysteresis = 20mV 4.1 4.25 µs °C 4.4 V 2 V CURRENT LIMIT ILIM_ Adjustment Range Current-Limit Input Range CSP_/CSN_ Input Current 0.25 CSP_ 0 2.7 CSN_ -0.3 +28 0.5 V µA _______________________________________________________________________________________ 5 MAX1540A/MAX1541 ELECTRICAL CHARACTERISTICS (continued) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 45 50 55 mV VILIM_ = 250mV 15 25 35 VILIM_ = 2.00V 170 200 230 -90 -65 -45 Valley Current-Limit Threshold (Fixed) VLIM_ (VAL) VCSP_ - VCSN_, ILIM_ = VCC Valley Current-Limit Threshold (Adjustable) VLIM_ (VAL) VCSP_ - VCSN_ Current-Limit Threshold (Negative) VNEG Current-Limit Threshold (Zero Crossing) VZX With respect to valley current-limit threshold, VCSP_ - VCSN _, SKIP = GND, ILIM_ = VCC With respect to valley currentlimit threshold, ILIM_ = VCC Inductor-Saturation Current-Limit Threshold ILIM_ Saturation Fault Sink Current VCSP_ - VCSN _, SKIP = ILIM_ = VCC, TA = +25°C IILIM_ (LSAT) 2.5 mV mV LSAT = VCC 180 200 220 LSAT = open 157 175 193 LSAT = REF 135 150 165 4 6 8 µA 0.1 µA Ω VCSP - VCSN > inductor saturation current limit, 0.25V < VILIM_ < 2.0V VCSP_ - VCSN _ < inductor saturation current limit ILIM_ Leakage Current mV % GATE DRIVERS DH_ Gate-Driver On-Resistance RDH DL_ Gate-Driver On-Resistance RDL DH_ Gate-Driver Source/Sink Current IDH BST_-LX_ forced to 5V 1.5 5 DL_, high state 1.5 5 DL_, low state 0.6 3 Ω DH_ forced to 2.5V, BST_-LX_ forced to 5V 1 A 1 A A DL_ Gate-Driver Source Current IDL (SOURCE) DL_ forced to 2.5V DL_ Gate-Driver Sink Current IDL (SINK) DL_ forced to 2.5V 3 DL_ rising 35 DH_ rising 26 GATE = VCC 10 25 Ω OD Leakage Current GATE = GND, OD forced to 5.5V 1 200 nA Logic Input Threshold ON1, ON2, SKIP, GATE rising edge, hysteresis = 225mV 1.2 1.7 2.2 V LDOON Input Trip Level Rising edge, hysteresis = 250mV 1.20 1.25 1.30 V Logic Input Current ON1, ON2, LDOON, SKIP, GATE -1 +1 µA FB1 (MAX1540A), High FB2 (MAX1540A/ Low MAX1541) 1.9 2.0 2.1 Dual Mode™ Threshold Voltage 0.05 0.1 0.15 Dead Time tDEAD ns INPUTS AND OUTPUTS OD On-Resistance ROD V Dual Mode is a trademark of Maxim Integrated Products, Inc. 6 _______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS TON, OVP/UVP, LSAT, SKIP, FBLANK Four-Level Input Logic Levels MIN MAX UNITS V High VCC 0.4V Open 3.15 3.85 REF 1.65 2.35 Low TON, OVP/UVP, LSAT, SKIP, FBLANK forced to GND or VCC Four-Level Logic Input Current TYP 0.5 -3 +3 µA ELECTRICAL CHARACTERISTICS (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40°C to +85°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS MIN MAX MAX1540A: battery voltage, V+ > VLDOOUT 5.5 28 2 28 VCC, VDD (MAX1541) 4.5 5.5 MAX1541: LDO input supply, VLDOIN > VLDOOUT 4.5 28 UNITS INPUT SUPPLIES (Note 1) VIN Input Voltage Range VBIAS VLDOIN Quiescent Supply Current (VCC) Quiescent Supply Current (VDD, MAX1541 Only) ICC IDD MAX1541: battery voltage, V+ > VLDOOUT FB1 and FB2 forced above the regulation point, LSAT = GND 1.5 FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLSAT > 0.5V 1.8 FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC 5 V mA µA MAX1540A: FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V 150 MAX1541: ON1 or ON2 = VCC, VLDOON = V+ = 28V 40 FB1 and FB2 forced above the regulation point, ON1 or ON2 = VCC, VLDOON = V+ = 28V 110 µA Standby Supply Current (VDD) ON1 = ON2 = GND, VLDOON = V+ = 28V 5 µA Standby Supply Current (VDD, MAX1541 Only) ON1 = ON2 = GND, VLDOON = V+ = 28V 5 µA Quiescent Supply Current (V+) Quiescent Supply Current (LDOIN, MAX1541 Only) Standby Supply Current (V+) Standby Supply Current (LDOIN, MAX1541 Only) IV+ ILDOIN MAX1540A: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = 0 or 5V µA 105 µA MAX1541: ON1 = ON2 = GND, LDOON = V+ = 28V, VCC = VDD = 0 or 5V 5 ON1 = ON2 = GND, VLDOON = V+ = 28V 100 µA _______________________________________________________________________________________ 7 MAX1540A/MAX1541 ELECTRICAL CHARACTERISTICS (continued) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40°C to +85°C, unless otherwise noted.) (Note 4) MAX UNITS Shutdown Supply Current (VCC) PARAMETER SYMBOL ON1 = ON2 = LDOON = GND 5 µA Shutdown Supply Current (VDD, MAX1541 Only) ON1 = ON2 = LDOON = GND 5 µA MAX1540A: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = 0 or 5V 15 MAX1541: ON1 = ON2 = LDOON = GND, V+ = 28V, VCC = VDD = 0 or 5V 5 LDOON = GND 10 Shutdown Supply Current (V+) Shutdown Supply Current (LDOIN, MAX1541 Only) CONDITIONS MIN µA µA PWM CONTROLLERS MAX1540A Main Output-Voltage Accuracy (OUT1) (Note 2) VOUT1 VFB1 MAX1540A Secondary OutputVoltage Accuracy (OUT2) (Note 2) VOUT2 1.773 1.827 FB1 = VCC 1.182 1.218 0.689 0.711 FB2 = GND 2.462 2.538 FB2 = VCC 1.477 1.523 0.689 0.711 Adjustable output, V+ = 5.5V to 28V, SKIP = VCC Preset output, V+ = 5.5V to 28V, SKIP = VCC VFB2 VFB1 V+ = 4.5V to 28V, SKIP = VCC REFIN1 = 0.35 x REF 0.689 0.711 REFIN1 = REF 1.97 2.03 Preset output, V+ = 4.5V to 28V, SKIP = VCC FB2 = GND 2.462 2.538 VOUT2 FB2 = VCC 1.773 1.827 0.689 0.711 TON = GND (620kHz) 149 190 TON = REF (485kHz) 191 242 TON = open (345kHz) 274 335 TON = VCC (235kHz) 402 491 TON = GND (460kHz) 201 256 TON = REF (355kHz) 260 331 TON = open (255kHz) 371 453 TON = VCC (170kHz) 556 679 VFB2 DH1 On-Time (Note 3) tON1 DH2 On-Time (Note 3) tON2 On-Time Tracking Minimum Off-Time FB1 = GND Adjustable output, V+ = 5.5V to 28V, SKIP = VCC MAX1541 Main Feedback Voltage Accuracy (FB1) MAX1541 Secondary OutputVoltage Accuracy (OUT2) (Note 2) Preset output, V+ = 5.5V to 28V, SKIP = VCC Adjustable output, V+ = 4.5V to 28V, SKIP = VCC V+ = 15V, VOUT1 = 1.5V V+ = 15V, VOUT2 = 1.5V tON2 with respect to tON1 (Note 3) tOFF(MIN) 118 (Note 3) V V V V ns ns 152 % 500 ns LINEAR REGULATOR (LDO) (Note 1) MAX1540A LDO Output-Voltage Accuracy 8 VLDOOUT ON1 = ON2 = GND, V+ = 6V to 28V 0 < ILDOOUT < 10mA 4.85 5.10 0 < ILDOOUT < 100mA 4.65 5.10 _______________________________________________________________________________________ V Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40°C to +85°C, unless otherwise noted.) (Note 4) PARAMETER MAX1541 LDO Output-Voltage Accuracy (Fixed VLDOOUT) MAX1541 LDO Feedback Accuracy (Adjustable VLDOOUT) SYMBOL VLDOOUT VFBLDO Dropout Voltage CONDITIONS FBLDO = ON1 = ON2 = GND, VLDOIN = 6V to 28V FBLDO = LDOOUT, ON1 = ON2 = GND, VLDOIN = 4.5V to 28V MIN MAX 0 < ILDOOUT < 10mA 4.85 5.10 0 < ILDOOUT < 100mA 4.65 5.10 0 < ILDOOUT < 10mA 1.212 1.275 0 < ILDOOUT < 100mA 1.175 1.275 UNITS V V MAX1540A: V+ - VLDOOUT, ILDOOUT = 50mA 800 MAX1541: VLDOIN - VLDOOUT, ILDOOUT = 50mA 800 mV REFERENCE (REF) Reference Voltage VREF REFIN1 Input Bias Current VCC = 4.5V to 5.5V, IREF = 0 1.98 IREFIN1 2.02 V 0.05 µA FAULT DETECTION Overvoltage Trip Threshold With respect to error-comparator threshold, OVP/UVP = VCC 10 21 % Output Undervoltage-Protection Trip Threshold With respect to error-comparator threshold, OVP/UVP = VCC 64 76 % PGOOD_ Lower Trip Threshold With respect to error-comparator threshold, hysteresis = 1% -14 -5 % PGOOD_ Upper Trip Threshold With respect to error-comparator threshold, hysteresis = 1% +5 +14 % PGOOD_ Output Low Voltage ISINK = 4mA 0.3 V 4.1 4.4 V CSP_ 0 2.7 CSN_ -0.3 +28.0 VCC Undervoltage-Lockout Threshold VUVLO(VCC) Rising edge, PWM disabled below this level, hysteresis = 20mV CURRENT LIMIT Current-Limit Input Range V Valley Current-Limit Threshold (Fixed) VLIM_ (VAL) VCSP_ - VCSN_, ILIM_ = VCC 40 60 mV Valley Current-Limit Threshold (Adjustable) VLIM_ (VAL) VCSP_ - VCSN_, VILIM_ = 2.00V 160 240 mV 1.2 2.2 V V INPUTS AND OUTPUTS Logic Input Threshold ON1, ON2, SKIP, GATE, rising edge, hysteresis = 225mV LDOON Input Trip Level Rising edge, hysteresis = 250mV Dual Mode Threshold Voltage FB1 (MAX1540A), FB2 (MAX1540A/MAX1541) 1.2 1.3 High 1.9 2.1 Low 0.05 0.15 V _______________________________________________________________________________________ 9 MAX1540A/MAX1541 ELECTRICAL CHARACTERISTICS (continued) ELECTRICAL CHARACTERISTICS (continued) (V+ = 15V, VCC = VDD = ON1 = ON2 = 5V, SKIP = GND, LDOIN (MAX1541) = V+, TA = -40°C to +85°C, unless otherwise noted.) (Note 4) PARAMETER SYMBOL CONDITIONS TON, OVP/UVP, LSAT, SKIP, FBLANK Four-Level Input Logic Levels MIN MAX UNITS V High VCC 0.4V Open 3.15 3.85 REF 1.65 2.35 Low 0.5 Note 1: For the MAX1540A, the gate-driver input supply (VDD) is internally connected to the fixed 5V linear-regulator output (LDOOUT), and the linear-regulator input supply (LDOIN) is internally connected to the battery voltage input (V+). Note 2: When the inductor is in continuous conduction, the output voltage has a DC regulation level higher than the error-comparator threshold by 50% of the ripple. In discontinuous conduction (SKIP = GND, light load), the output voltage has a DC regulation level higher than the trip level by approximately 1.5% due to slope compensation. Note 3: On-time and off-time specifications are measured from 50% point to 50% point at the DH_ pin with LX_ = GND, VBST_ = 5V, and a 250pF capacitor connected from DH_ to LX_. Actual in-circuit times may differ due to MOSFET switching speeds. Note 4: Specifications to -40°C are guaranteed by design, not production tested. Typical Operating Characteristics (MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.) 2.5V OUTPUT VOLTAGE (OUT2) vs. LOAD CURRENT 80 75 VIN = 7V VIN = 12V 70 65 VIN = 20V 60 2.51 2.50 2.49 SKIP = GND SKIP = VCC 55 SKIP = GND SKIP = VCC 2.48 50 0.01 0.1 1 LOAD CURRENT (A) 10 90 2.53 2.52 SKIP = GND SKIP = VCC 95 EFFICIENCY (%) 85 100 MAX1540A toc02 90 2.54 OUTPUT VOLTAGE (V) 95 10 2.55 MAX1540A toc01 100 OUT1 EFFICIENCY vs. LOAD CURRENT (VOUT1 = 1.0V) MAX1540A toc03 OUT2 EFFICIENCY vs. LOAD CURRENT (VOUT2 = 2.5V) EFFICIENCY (%) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator 85 80 75 70 65 VIN = 7V 60 VIN = 12V 55 VIN = 20V 50 0 1 2 3 LOAD CURRENT (A) 4 5 0.01 0.1 1 LOAD CURRENT (A) ______________________________________________________________________________________ 10 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator 1.01 1.00 0.99 500 400 300 200 100 0.98 600 1 2 3 5 4 500 400 300 200 100 SKIP = GND SKIP = VCC SKIP = GND SKIP = VCC 0 0 0 1 2 3 0 5 4 MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (FORCED-PWM OPERATION) 5.4 5.2 5.0 4.8 4.6 MAX1540A toc09 16 IBIAS 12 IIN 8 4 4.4 200 SKIP = ON1 = ON2 = VCC 0 4.0 8 12 16 20 24 28 0 4 8 INPUT VOLTAGE (V) 12 16 20 NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE (PULSE-SKIPPING OPERATION) 0.10 IN SKIP = GND ON1 = ON2 = VCC 16 20 INPUT VOLTAGE (V) 24 28 12 16 20 24 28 MAX1540A toc11 REFERENCE DISTRIBUTION 3 2 1 0 -1 -2 50 SAMPLE SIZE = 50 40 30 20 10 -3 -4 0.01 8 INPUT VOLTAGE (V) 4 REFERENCE VOLTAGE DEVIATION (mV) IBIAS 12 4 2.0V REFERENCE LOAD REGULATION MAX1540Atoc10 1.00 8 0 28 24 INPUT VOLTAGE (V) SAMPLE PERCENTAGE (%) 4 MAX1540A toc12 250 5.6 SUPPLY CURRENT (mA) NO LOAD 300 2.5V OUTPUT 5.8 20 MAX1540A toc08 MAX1540A toc07 4A LOAD 350 6.0 4.2 SUPPLY CURRENT (mA) 5 4 SWITCHING FREQUENCY vs. INPUT VOLTAGE 400 4 3 LOAD CURRENT (A) 2.5V OUTPUT SKIP = VCC 0 2 LOAD CURRENT (A) 450 0 1 LOAD CURRENT (A) MAXIMUM OUTPUT CURRENT (A) 0 MAX1540A toc06 MAX1540A toc05 600 SWITCHING FREQUENCY (kHz) OUTPUT VOLTAGE (V) SKIP = GND SKIP = VCC SWITCHING FREQUENCY (kHz) MAX1540A toc04 1.02 SWITCHING FREQUENCY (kHz) OUT1 SWITCHING FREQUENCY vs. LOAD CURRENT (VOUT1 = 1.0V) OUT2 SWITCHING FREQUENCY vs. LOAD CURRENT (VOUT2 = 2.5V) 1.0V OUTPUT VOLTAGE (OUT1) vs. LOAD CURRENT -20 0 20 40 60 80 REFERENCE LOAD CURRENT (μA) 100 0 1.990 1.995 2.000 2.005 2.010 REFERENCE VOLTAGE (V) ______________________________________________________________________________________ 11 MAX1540A/MAX1541 Typical Operating Characteristics (continued) (MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.) LINEAR-REGULATOR OUTPUT (LDOOUT) vs. LOAD CURRENT STARTUP WAVEFORM (HEAVY LOAD) MAX1540A toc14 MAX1540A toc13 3.36 3.34 LDO OUTPUT VOLTAGE (V) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator 3.32 3.3V A 0 4A 3.30 B 2A VLDOIN = 5V 3.28 0 3.26 2.5V VLDOIN = 12V C 3.24 0 3.22 D 0 3.20 0 20 40 60 80 100 400μs/div LDO LOAD CURRENT (mA) A. ON2, 5V/div B. INDUCTOR CURRENT, 2A/div C. OUT2, 2V/div D. PGOOD2, 5V/div 0.5Ω LOAD SHUTDOWN WAVEFORM (DISCHARGE MODE DISABLED) STARTUP WAVEFORM (LIGHT LOAD) MAX1540A toc15 3.3V MAX1540A toc16 A 3.3V A 0 0 2.5V 4A B B 2A 0 C 0 0 5V 2.5V D C 0 0 5V D 0 10ms/div 200μs/div A. ON2, 5V/div B. INDUCTOR CURRENT, 2A/div E 0 C. OUT2, 2V/div D. PGOOD2, 5V/div A. ON2, 5V/div B. OUT2, 2V/div C. INDUCTOR CURRENT, 2A/div D. DL2, 5V/div E. PGOOD2, 5V/div 100Ω LOAD 100Ω LOAD, OVP/UVP = REF OR GND 12 ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator SHUTDOWN WAVEFORM (DISCHARGE MODE ENABLED) 2.5V OUTPUT LOAD TRANSIENT (FORCED PWM) MAX1540A toc17 3.3V MAX1540A toc18 A 4A B 0 2.6V 0 2.5V 0 A 2.5V C 0 5V D 0 B 2.4V 4A C 0 12V 5V D E 0 0 1ms/div A. ON2, 5V/div B. OUT2, 2V/div C. INDUCTOR CURRENT, 2A/div 40μs/div D. DL2, 5V/div E. PGOOD2, 5V/div A. IOUT2 = 0 TO 4A, 5A/div B. VOUT2 = 2.5V, 100mV/div C. INDUCTOR CURRENT, 5A/div D. LX2, 10V/div SKIP = VCC 100Ω LOAD, OVP/UVP = VCC OR OPEN LINEAR-REGULATOR LOAD TRANSIENT 2.5V OUTPUT LOAD TRANSIENT (PULSE SKIPPING) MAX1540A toc20 MAX1540A toc19 4A A 100mA 0 2.6V A 2.5V B 2.4V 4A 0 3.4V C B 3.3V 0 12V 3.2V D 0 100μs/div 40μs/div A. IOUT2 = 0.1A TO 4A, 5A/div C. INDUCTOR CURRENT, 5A/div B. VOUT2 = 2.5V, 100mV/div D. LX2, 10V/div A. ILDOOUT = 1mA TO 100mA, 50mA/div B. VLDOOUT = 3.3V, 100mV/div SKIP = GND SKIP = GND ______________________________________________________________________________________ 13 MAX1540A/MAX1541 Typical Operating Characteristics (continued) (MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Typical Operating Characteristics (continued) (MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.) OUTPUT OVERLOAD (UVP DISABLED) LINEAR-REGULATOR LINE TRANSIENT MAX1540A toc21 20V MAX1540A toc22 20A A 10A A 0 10V 20V B 5A 0 B 10V 2.5V 3.8V C C 3.3V 0 5V 2.8V D 0 40μs/div 200μs/div A. INPUT (VIN), 10V/div B. LDOIN (10V TO 20V), 10V/div C. LDOOUT (3.3V), 500mV/div 20mA LOAD A. LOAD (0 TO 150mΩ), 10A/div C. 2.5V OUTPUT, 2V/div B. INDUCTOR CURRENT, 10A/div D. PGOOD2, 5V/div OVP/UVP = OPEN OR GND OUTPUT OVERLOAD (UVP ENABLED) INDUCTOR-SATURATION PROTECTION (LSAT DISABLED) MAX1540A toc23 20A MAX1540A toc24 5A 10A A 0 5A 0 5V B 0 A 0 B 2.5V C 0.67V D 7.5A C 2.5V D 5V E 0 20μs/div A. LOAD (0 TO 150mΩ), 10A/div D. 2.5V OUTPUT, 2V/div B. INDUCTOR CURRENT, 10A/div E. PGOOD2, 5V/div C. DL2, 5V/div 0 20μs/div A. IOUT2 = 0 TO 5A, 5A/div B. 2.5V OUTPUT, 200mV/div C. ILIM, 100mV/div D. INDUCTOR CURRENT, 5A/div LSAT = GND, L = 3.3μH 3.5A OVP/UVP = VCC OR REF 14 ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator INDUCTOR-SATURATION PROTECTION (ΔVILIM = 200mV) INDUCTOR-SATURATION PROTECTION (ΔVILIM = 400mV) MAX1540A toc25 5A MAX1540A toc26 A 0 5A A 0 2.5V 0.67V B 2.5V B C 1.5V 5V C 0.67V 0.47V 7.5A D D 0.27V 5A E 0 0 20μs/div A. IOUT2 = 0 TO 5A, 5A/div B. 2.5V OUTPUT, 200mV/div 20μs/div C. ILIM, 200mV/div D. INDUCTOR CURRENT, 5A/div A. IOUT2 = 0 TO 5A, 5A/div B. 2.5V OUTPUT, 1V/div C. PGOOD, 5V/div D. ILIM, 400mV/div E. INDUCTOR CURRENT, 5A/div LSAT = REF, L = 3.3μH 3.5A LSAT = REF, L = 3.3μH 3.5A MAX1541 DYNAMIC OUTPUT-VOLTAGE TRANSITION (CREFIN1 = 100pF) MAX1541 DYNAMIC OUTPUT-VOLTAGE TRANSITION (CREFIN1 = 1nF) MAX1540A toc27 5V MAX1540A toc28 A 0 5V A 0 1.5V B 1.5V 1.5V B 1.5V C 1V 5V 5A D 0 C 1V 5V 5A D 0 E E -5A -5A 40μs/div 100μs/div A. GATE, 5V/div D. PGOOD1, 5V/div B. OUT1 (1.0V TO 1.5V), 0.5V/div E. INDUCTOR CURRENT, 5A/div C. REFIN1, 0.5V/div A. GATE, 5V/div D. PGOOD1, 5V/div B. OUT1 (1.0V TO 1.5V), 0.5V/div E. INDUCTOR CURRENT, 5A/div C. REFIN1, 0.5V/div 200mA LOAD, SKIP = GND 200mA LOAD, SKIP = GND ______________________________________________________________________________________ 15 MAX1540A/MAX1541 Typical Operating Characteristics (continued) (MAX1541 circuit of Figure 12, VIN = 12V, VDD = VCC = 5V, SKIP = GND, TON = REF, TA = +25°C, unless otherwise noted.) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Pin Description PIN MAX1540A 1 2 16 MAX1541 1 2 NAME FUNCTION OVP/UVP Overvoltage/Undervoltage Protection and Discharge-Mode Control Input. This fourlevel logic input selects between various output fault-protection options (Table 7) by selectively enabling OVP protection and UVP protection. When enabled, the OVP limit defaults at 116% of the nominal output voltage, and the UVP limit defaults at 70% of the nominal output voltage. Discharge mode is enabled when OVP protection is also enabled. Connect OVP/UVP to the following pins for the desired function: VCC = enable OVP and discharge mode, enable UVP. Open = enable OVP and discharge mode, disable UVP. REF = disable OVP and discharge mode, enable UVP. GND = disable OVP and discharge mode, disable UVP. See the Fault Protection and (ON_) sections. SKIP Pulse-Skipping Control Input. This four-level logic input enables or disables the lightload pulse-skipping operation of each output: VCC = OUT1 and OUT2 in forced-PWM mode. Open = OUT1 in forced-PWM mode, OUT2 in pulse-skipping mode. REF = OUT1 in pulse-skipping mode, OUT2 in forced-PWM mode. GND = OUT1 and OUT2 in pulse-skipping mode. 3 3 LSAT 4 4 TON 5 5 VCC — 6 GATE — 7 CC1 Inductor-Saturation Control Input. This four-level logic input sets the inductor-current saturation limit as a multiple of the valley current-limit threshold set by ILIM, or disables the function if not required. Connect LSAT to the following pins to set the saturation current limit: VCC = 2 x ILIM(VAL) Open = 1.75 x ILIM(VAL) REF = 1.5 x ILIM(VAL) GND = disable LSAT protection See the Inductor Saturation Limit and Setting the Current Limit sections. On-Time Selection Control Input. This four-level logic input sets the K-factor value used to determine the DH_ on-time (see the On-Time One-Shot (TON) section). Connect to analog ground (GND), REF, or VCC; or leave TON unconnected to select the following nominal switching frequencies: VCC = 235kHz (OUT1) / 170kHz (OUT2) Open = 345kHz (OUT1) / 255kHz (OUT2) REF = 485kHz (OUT1) / 355kHz (OUT2) GND = 620kHz (OUT1) / 460kHz (OUT2) Analog Supply Input. Connect to the system supply voltage (+4.5V to +5.5V) through a series 20Ω resistor. Bypass VCC to analog ground with a 1µF or greater ceramic capacitor. Buffered N-Channel MOSFET Gate Input. A logic low on GATE turns off the internal MOSFET so OD appears as high impedance. A logic high on GATE turns on the internal MOSFET, pulling OD to ground. Integrator Capacitor Connection for Controller 1. Connect a 47pF to 470pF (47pF typ) capacitor from CC1 to analog ground (GND) to set the integration time constant for the main MAX1541 controller (OUT1). ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator PIN MAX1540A 6 7 MAX1541 8 9 NAME ILIM1 Valley Current-Limit Threshold Adjustment for Controller 1. The valley current-limit threshold defaults to 50mV if ILIM1 is tied to VCC. In adjustable mode, the valley current-limit threshold across CSP1 and CSN1 is precisely 1/10 the voltage seen at ILIM1 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. When the inductor-saturation protection threshold is exceeded, ILIM1 sinks 6µA. See the Current-Limit Protection section. ILIM2 Valley Current-Limit Threshold Adjustment for Controller 2. The valley current-limit threshold defaults to 50mV if ILIM2 is tied to VCC. In adjustable mode, the valley current-limit threshold across CSP2 and CSN2 is precisely 1/10th the voltage seen at ILIM2 over a 250mV to 2.5V range. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. When the inductor-saturation protection threshold is exceeded, ILIM2 sinks 6µA. See the Current-Limit Protection section. 2.0V Reference Voltage Output. Bypass REF to analog ground with a 0.1µF or greater ceramic capacitor. The reference can source up to 50µA for external loads. Loading REF degrades output voltage accuracy according to the REF load-regulation error. The reference is disabled when the MAX1540A/MAX1541 are shut down. 8 10 REF — 11 REFIN1 — 12 OD 9 10 11 13 14 15 FUNCTION External Reference Input for Controller 1. REFIN1 sets the main feedback regulation voltage (VFB1 = VREFIN1) of the MAX1541. Open-Drain Output. Controlled by GATE. CSP2 Positive Current-Sense Input for Controller 2. Connect to the positive terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM2. CSN2 Negative Current-Sense Input for Controller 2. Connect to the negative terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM2. FB2 Feedback Input for Controller 2: MAX1540A: Connect to VCC for a +1.5V fixed output or to analog ground (GND) for a +2.5V fixed output. For an adjustable output (0.7V to 5.5V), connect FB2 to a resistive divider from OUT2. The FB2 regulation level is +0.7V. MAX1541: Connect to VCC for a +1.8V fixed output or to analog ground (GND) for a +2.5V fixed output. For an adjustable output (0.7V to 5.5V), connect FB2 to a resistive divider from OUT2. The FB2 regulation level is +0.7V. 12 16 OUT2 Output Voltage-Sense Connection for Controller 2. Connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (Figures 1 and 12). OUT2 senses the output voltage to determine the on-time for the high-side switching MOSFET. OUT2 also serves as the feedback input when using the preset internal output voltages as shown in Figure 10. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through an internal 10Ω resistor connected between OUT2 and ground. ______________________________________________________________________________________ 17 MAX1540A/MAX1541 Pin Description (continued) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Pin Description (continued) PIN MAX1540A NAME FUNCTION Open-Drain Power-Good Output. PGOOD2 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. After the soft-start circuit has terminated, PGOOD2 becomes high impedance if the output is in regulation. 13 17 PGOOD2 14 18 DH2 High-Side Gate-Driver Output for Controller 2. DH2 swings from LX2 to BST2. 15 19 LX2 Inductor Connection for Controller 2. Connect to the switched side of the inductor. LX2 serves as the lower supply rail for the DH2 high-side gate driver. 16 20 BST2 Boost Flying-Capacitor Connection for Controller 2. Connect to an external capacitor and diode as shown in Figure 8. An optional resistor in series with BST2 allows the DH2 pullup current to be adjusted. 17 21 GND Analog and Power Ground. Connect backside pad to GND. 18 22 DL2 Low-Side Gate-Driver Output for Controller 2. DL2 swings from GND to LDOOUT (MAX1540A) or GND to VDD (MAX1541). 19 23 V+ Battery Voltage Input. The controller uses V+ to set the on-time one-shot timing. The DH on-time is inversely proportional to input voltage over a range of 2V to 28V. For the MAX1540A, V+ also serves as the linear-regulator input supply. — 18 MAX1541 24 LDOIN Internal Linear-Regulator Input Supply. Power LDOIN from a 4.5V to 28V voltage source. Bypass LDOIN to GND with a 4.7µF or greater capacitor. For the MAX1540A, LDOIN is internally connected to V+. For the MAX1541, LDOIN must be connected to VDD when LDO is not used. MAX1541 Supply Voltage Input for the DL_ Gate Driver. Connect to the system supply voltage (+4.5V to +5.5V). Bypass VDD to power ground with a 1µF or greater ceramic capacitor. For the MAX1540A, LDOOUT supplies the DL_ gate drivers (VDD = LDOOUT). — 25 VDD 20 26 LDOOUT Linear Regulator Output. Bypass LDOOUT with a 1µF or greater capacitor per 5mA of load (internal and external), with a minimum of 4.7µF. For the MAX1540A, LDOOUT powers the DL_ gate drivers (VDD internally connected to LDOOUT). Feedback Input for the Linear Regulator. Connect to GND for a fixed 5V output. For an adjustable output (1.25V to VLDOIN - 0.6V), connect FBLDO to a resistive voltagedivider from LDOOUT to analog ground (GND). The FBLDO regulation voltage is +1.25V. For the MAX1540A, FBLDO is internally connected to GND for a fixed 5V output. — 27 FBLDO 21 28 DL1 22 29 LDOON 23 30 BST1 Low-Side Gate-Driver Output for Controller 1. DL1 swings from GND to LDOOUT (MAX1540A) or GND to VDD (MAX1541). Linear-Regulator Enable Input. For automatic startup, connect to V+ or LDOIN (MAX1541). Connect to GND to shut down the linear regulator. Boost Flying-Capacitor Connection for Controller 1. Connect to an external capacitor and diode as shown in Figure 8. An optional resistor in series with BST1 allows the DH1 pullup current to be adjusted. ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator PIN NAME MAX1540A MAX1541 24 31 LX1 25 32 DH1 26 33 PGOOD1 27 34 OUT1 28 35 FB1 29 30 — 36 37 38 FUNCTION Inductor Connection for Controller 1. Connect to the switched side of the inductor. LX1 serves as the lower supply rail for the DH1 high-side gate driver. High-Side Gate-Driver Output for Controller 1. DH1 swings from LX1 to BST1. Open-Drain Power-Good Output. PGOOD1 is low when the output voltage is more than 10% (typ) above or below the normal regulation point, during soft-start, and in shutdown. After the soft-start circuit has terminated, PGOOD1 becomes high impedance if the output is in regulation. For the MAX1541, PGOOD1 is blanked—forced high-impedance state—when FBLANK is enabled and the controller detects a transition on GATE. Output Voltage-Sense Connection for Controller 1. Connect directly to the positive terminal of the output capacitors as shown in the standard application circuits (Figures 1 and 12). OUT1 senses the output voltage to determine the on-time for the high-side switching MOSFET. For the MAX1540A, OUT1 also serves as the feedback input when using the preset internal output voltages as shown in Figure 10. When discharge mode is enabled by OVP/UVP, the output capacitor is discharged through i t l 10Ω i t t db t OUT1 d d Feedback Input for Controller 1: MAX1540A: Connect to VCC for a +1.2V fixed output or to analog ground (GND) for a +1.8V fixed output. For an adjustable output (0.7V to 5.5V), connect FB1 to a resistive divider from OUT1. The FB1 regulation level is +0.7V. MAX1541: The FB1 regulation level is set by the voltage at REFIN1. CSN1 Negative Current-Sense Input for Controller 1. Connect to the negative terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM1. CSP1 Positive Current-Sense Input for Controller 1. Connect to the positive terminal of the current-sense element. Figure 14 and Table 9 describe several current-sensing options. The PWM controller does not begin a cycle unless the current sensed is less than the valley current-limit threshold programmed at ILIM1. FBLANK Fault-Blanking Control Input. This four-level logic input enables or disables fault blanking, and sets the forced-PWM operation time (tFBLANK). When fault blanking is enabled, PGOOD1 and the OVP/UVP protection for controller 1 are blanked for the selected time period after the MAX1541 detects a transition on GATE. Additionally, controller 1 enters forced-PWM mode for the duration of tFBLANK anytime GATE changes states. Connect FBLANK as follows: VCC = 220µs tFBLANK, fault blanking enabled. Open = 140µs tFBLANK, fault blanking enabled. REF = 65µs tFBLANK, fault blanking enabled. GND = 140µs tFBLANK, fault blanking disabled. See the Electrical Characteristics table for the tFBLANK limits. ______________________________________________________________________________________ 19 MAX1540A/MAX1541 Pin Description (continued) MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Pin Description (continued) PIN MAX1540A MAX1541 31 39 NAME FUNCTION ON2 OUT2 Enable Input. Pull ON2 to GND to shut down controller 2 (OUT2). Connect to VCC for normal operation. When discharge mode is enabled by OVP/UVP, the output is discharged through a 10Ω resistor between OUT2 and GND, and DL2 is forced high after VOUT2 drops below 0.3V. When discharge mode is disabled by OVP/UVP, OUT2 remains a high-impedance input and DL2 is forced low so LX2 also appears as a high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch. OUT1 Enable Input. Pull ON1 to GND to shut down controller 1 (OUT1). Connect to VCC for normal operation. When discharge mode is enabled by OVP/UVP, the output is discharged through a 10Ω resistor between OUT1 and GND, and DL1 is forced high after VOUT1 drops below 0.3V. When discharge mode is disabled by OVP/UVP, OUT1 remains a high-impedance input and DL1 is forced low so LX1 also appears as high impedance. A rising edge on ON1 or ON2 clears the fault-protection latch. 32 40 ON1 — — EP Exposed Backside Pad. Connect the exposed backside pad to analog ground. Table 1. Component Selection for Standard Applications COMPONENT MAX1540A MAX1541 PWM1 PWM2 PWM1 PWM2 Input Voltage (VIN) 7V to 24V 7V to 24V 7V to 24V 7V to 24V Output Voltage (VOUT_) 1.8V 2.5V 1.0V/1.5V 2.5V Load Current (IOUT_) 4A 8A 4A 4A Switching Frequency (fSW_) TON = REF (485kHz) TON = REF (355kHz) TON = REF (485kHz) TON = REF (355kHz) Input Capacitor (CIN) (2) 4.7µF, 25V Taiyo Yuden TMK325BJ475KM Output Capacitor (COUT_) 220µF, 6.3V, 12mΩ Sanyo POSCAP 6TPD220M 330µF, 4V, 12mΩ Sanyo POSCAP 4TPD330M 470µF, 4V, 10mΩ Sanyo POSCAP 4TPD470M 220µF, 6.3V, 12mΩ Sanyo POSCAP 6TPD220M High-Side MOSFET (NH_) 35mΩ, 30V Fairchild 1/2 FDS6982S 20mΩ, 30V Fairchild FDS6690 35mΩ, 30V Fairchild 1/2 FDS6982S 35mΩ, 30V Fairchild 1/2 FDS6982S Low-Side MOSFET (NL_) 22mΩ, 30V Fairchild 1/2 FDS6982S 12.5mΩ, 30V Fairchild FDS6670S 22mΩ, 30V Fairchild 1/2 FDS6982S 22mΩ, 30V Fairchild 1/2 FDS6982S Low-Side Schottky (DL_) (if needed) 1A, 30V Schottky Nihon EP10QS03L 1A, 30V Schottky Nihon EP10QS03L 1A, 30V Schottky Nihon EP10QS03L 1A, 30V Schottky Nihon EP10QS03L Inductor (L_) 2.5µH, 6.2A, 15mΩ Sumida CDEP105(H)-2R5 2.2µH, 10A, 4.4mΩ Sumida CDEP105(L)-2R2 1.8µH, 9.0A, 6.2mΩ Sumida CDEP105(S)-1R8 4.3µH, 6.8A, 8.7mΩ Sumida CDEP105(L)-4R3 RSENSE_ 20 (2) 10µF, 25V Taiyo Yuden TMK432BJ106KM 15mΩ ±1%, 0.5W 5mΩ ±1%, 0.5W 15mΩ ±1%, 0.5W 15mΩ ±1%, 0.5W IRC LR2010-01-R015F IRC LR2010-01-R005F IRC LR2010-01-R015F IRC LR2010-01-R015F or Dale WSL-2010-R015F or Dale WSL-2010-R005F or Dale WSL-2010-R015F or Dale WSL-2010-R015F ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator INPUT (VIN)* 7V TO 20V CIN (2) 10μF C1 22μF LDOOUT DBST NH1 V+ DBST MAX1540A DH1 DH2 BST1 BST2 CBST1 0.1μF NL1 DL1 L1 2.5μH MAX1540A/MAX1541 +5V BIAS SUPPLY NH2 CBST2 0.1μF LX1 LX2 DL1 DL2 NL2 DL2 GND CSP1 L2 2.2μH CSP2 RCS2 5mΩ RCS1 15mΩ OUTPUT 1 1.8V, 4A (MAX) COUT1 220μF CSN1 CSN2 OUT1 OUT2 FB1 OVP/UVP LSAT R2 100kΩ OFF R1 20Ω +5V BIAS SUPPLY VCC C2 1μF R3 49.9kΩ R6 100kΩ R4 200kΩ ILIM2 R5 49.9kΩ ON LDOON ON1 ON2 ILIM1 C4 470pF OPEN (ILIM(VAL) x 1.75) TON REF C3 470pF COUT2 330μF FB2 SKIP REF CREF (485kHz/355kHz) 0.22μF OUTPUT 2 2.5V, 8A (MAX) PGOOD1 EP PGOOD2 R7 100kΩ POWER-GOOD POWER GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. Figure 1. MAX1540A Standard Application Circuit ______________________________________________________________________________________ 21 MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Table 2. Component Suppliers SUPPLIER PHONE Central Semiconductor 631-435-1110 (USA) www.centralsemi.com Coilcraft 800-322-2645 (USA) www.coilcraft.com Fairchild Semiconductor 888-522-5372 (USA) www.fairchildsemi.com International Rectifier 310-322-3331 (USA) www.irf.com Kemet 408-986-0424 (USA) www.kemet.com Panasonic 65-6231-3226 (Singapore), 408-749-9714 (USA) WEBSITE www.panasonic.com Sanyo 619-661-6835 (USA) www.sanyovideo.com Siliconix (Vishay) 203-268-6261 (USA) www.vishay.com Sumida 408-982-9660 (USA) www.sumida.com Taiyo Yuden TDK TOKO 03-3667-3408 (Japan), 408-573-4150 (USA) 847-803-6100 (USA), 81-3-5201-7241 (Japan) 858-675-8013 (USA) www.t-yuden.com www.component.tdk.com www.tokoam.com Standard Application Circuits The MAX1540A standard application circuit (Figure 1) generates a 1.8V and 2.5V rail for general-purpose use in a notebook computer. The MAX1541 Standard Application Circuit (Figure 12) generates a dynamically adjustable output voltage (OUT1), typical of a graphicsprocessor core requirement, and a fixed 2.5V output (OUT2). See Table 1 for component selections. Table 2 lists the component manufacturers. 22 Detailed Description The MAX1540A/MAX1541 provide three independent outputs with independent enable controls. They contain two Quick-PWM step-down controllers ideal for low-voltage power supplies for notebook computers, and a 100mA linear regulator. Maxim’s proprietary Quick-PWM pulsewidth modulators in the MAX1540A/ MAX1541 are specifically designed for handling fast load steps while maintaining a relatively constant operating frequency and inductor operating point over a wide range of input voltages. The Quick-PWM architecture circumvents the poor load-transient timing problems of fixed-frequency currentmode PWMs, while also avoiding the problems caused by widely varying switching frequencies in conventional constant-on-time and constant-off-time PWM schemes. The MAX1540A linear regulator draws power from the battery voltage and generates a preset 5V, which can be used to bootstrap the buck controllers for automatic startup. The MAX1541’s linear regulator can be connected to any input source from 4.5V to 28V to generate an adjustable output voltage as low as 1.25V, or as high as the input source with 800mV of dropout at 50mA load. Single-stage buck conversion allows the MAX1540A/ MAX1541 to directly step down high-voltage batteries for the highest possible efficiency. Alternatively, twostage conversion (stepping down from another system supply rail instead of the battery at a higher switching frequency) allows the minimum possible physical size. The MAX1540A generates chipset, dynamic randomaccess memory (DRAM), CPU I/O, or other low-voltage supplies down to 0.7V. The MAX1541 powers chipsets and graphics processor cores that require dynamically adjustable output voltages, or generates the active termination bus that must track the input reference. The MAX1540A is available in a 32-pin thin QFN package with optional inductor-saturation protection and overvoltage/undervoltage protection. The MAX1541 is available in a 40-pin thin QFN package with optional inductor-saturation protection and overvoltage/undervoltage protection. +5V Bias Supply (VCC and VDD) The MAX1540A/MAX1541 require a 5V bias supply in addition to the battery. This 5V bias supply is either the MAX1540A/MAX1541s’ internal linear regulator or the notebook’s 95%-efficient 5V system supply. Keeping the bias supply external to the IC can improve efficiency and allows the fixed 5V or adjustable linear regulator (MAX1541) to be used for other applications. For the MAX1540A, the gate-driver input supply (VDD) is con- ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator The 5V bias supply must provide VCC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW (QG(LOW) + QG(HIGH)) = 4mA to 50mA (typ) where ICC is 1.1mA (typ), fSW is the switching frequency, and Q G(LOW) and Q G(HIGH) are the MOSFET data sheet’s total gate-charge specification limits at VGS = 5V. The V+ battery input and 5V bias inputs (VCC and VDD) can be connected together if the input source is a fixed 4.5V to 5.5V supply. If the 5V bias supply powers up prior to the battery supply, the enable signals (ON1 and ON2 going from low to high) must be delayed until the battery voltage is present in order to ensure startup. Free-Running, Constant On-Time, PWM Controller with Input Feed Forward The Quick-PWM control architecture is a pseudofixedfrequency, constant on-time, current-mode regulator with voltage feed forward (Figure 2). This architecture relies on the output filter capacitor’s ESR to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. The Quick-PWM algorithm is simple: the high-side switch on-time relies solely on an adjustable one-shot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. Another one-shot sets a fixed minimum off-time (400ns typ). The controller triggers the on-time one-shot when the error comparator is low, the inductor current is below the valley current-limit threshold, and the minimum off-time one-shot has timed out. On-Time One-Shot (TON) The heart of the PWM core is the one-shot that sets the high-side switch on-time. This fast, low-jitter, adjustable one-shot includes circuitry that varies the on-time in response to the battery and output voltages. The highside switch on-time is inversely proportional to the battery voltage as measured by the V+ input (VIN = V+), and proportional to the output voltage as measured by the OUT_ input: ⎛V ⎞ On- Time = K ⎜ OUT ⎟ ⎝ VIN ⎠ where K (switching period) is set by the TON pin-strap connection (Table 3). This algorithm results in a nearly constant switching frequency despite the lack of a fixedfrequency clock generator. The benefits of a constant switching frequency are twofold: 1) the frequency can be selected to avoid noise-sensitive regions such as the 455kHz IF band and 2) the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-time for the main controller (DH1) is set 15% higher than the nominal frequency setting (200kHz, 300kHz, 420kHz, or 540kHz), while the on-time for the secondary controller (DH2) is set 15% lower than the nominal setting. This prevents audio-frequency “beating” between the two asynchronous regulators. The on-time one-shot has good accuracy at the operating points specified in the Electrical Characteristics (approximately ±12.5% at 540kHz and 420kHz nominal settings, and ±10% with the 300kHz and 200kHz settings). On-times at operating points far removed from the conditions specified in the Electrical Characteristics can vary over a wider range. The constant on-time translates only roughly to a constant switching frequency. The on-times guaranteed in the Electrical Characteristics are influenced by resistive losses and by switching delays in the high-side MOSFET. Resistive losses—including the inductor, both MOSFETs, and PC board copper losses in the output and ground— tend to raise the switching frequency as the load increases. The dead-time effect increases the effective on-time, reducing the switching frequency as one or both dead times add to the effective on-time. It occurs only in PWM mode (SKIP = VCC) and during dynamic output-voltage transitions when the inductor current reverses at light- or negative-load currents. With reversed inductor current, the inductor’s EMF causes LX_ to go high earlier than normal, extending the on-time by a period equal to the driver dead time. For loads above the critical conduction point, where the dead-time effect no longer occurs, the actual switching frequency is: fSW = VOUT_ + VDROP1 t ON ( VIN + VDROP1 - VDROP2 ) where VDROP1 is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PC board resistances; VDROP2 is the sum of the resistances in the charging path, includ- ______________________________________________________________________________________ 23 MAX1540A/MAX1541 nected internally to the fixed 5V linear-regulator output (LDOOUT). MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator *V+ MAX1540A/MAX1541 TON LSAT SKIP ILIM2 ILIM1 CURRENT LIMIT 1 (FIGURE 5) CSP1 CURRENT LIMIT 2 (FIGURE 5) CSP2 CSN2 CSN1 VALLEY CURRENT LIMIT ZERO SATURATION CROSSING LIMIT SATURATION LIMIT VALLEY CURRENT LIMIT ZERO CROSSING BST1 BST2 DH1 DH2 LX1 PWM CONTROLLER 1 (FIGURE 3) *VDD FAULT1 DL1 GND INT FB1 INT REF1 LX2 PWM CONTROLLER 2 (FIGURE 3) *VDD FAULT2 DL2 INT FB2 GND INT REF2 **CC1 REF 2.0V REF **REFIN1 0.7V INTERNAL MAX1540A/MAX1541 OPTION FB1 FB1 DECODE (FIGURE 10) OUT1 13R 7R FB2 FB2 DECODE (FIGURE 10) OUT2 ON2 ON1 POWER-GOOD AND FAULT PROTECTION 1 (FIGURE 9) POWER-GOOD AND FAULT PROTECTION 2 (FIGURE 9) PGOOD2 PGOOD1 **FBLANK VCC QUAD-LEVEL DECODE AND TIMER BLANK ENABLE OVP ENABLE UVP QUAD-LEVEL DECODE OVP/UVP **OD *LDOIN **GATE MAX1541 CONTROLLER 1 ONLY *LDOOUT LINEAR REGULATOR (FIGURE 13) **FBLDO LDOON *FOR THE MAX1540A: LDOIN IS CONNECTED TO V+. LDOOUT IS CONNECTED TO VDD. **MAX1541 CONTROLLER ONLY. Figure 2. MAX1540A/MAX1541 Functional Diagram 24 ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator CONTROLLER 1 (OUT1) NOMINAL TON SETTING (kHz) 200kHz (TON = VCC) CONTROLLER 2 (OUT2) K-FACTOR ERROR (%) TYPICAL K-FACTOR (µs) MINIMUM VIN AT VOUT1 = 1.8V* (V) TYPICAL K-FACTOR (µs) MINIMUM VIN AT VOUT2 = 2.5V* (V) ±10 4.5 (235kHz) 2.28 6.2 (170kHz) 2.96 300kHz (TON = open) ±10 3.0 (345kHz) 2.52 4.1 (255kHz) 3.18 420kHz (TON = REF) ±12.5 2.2 (485kHz) 2.91 3.0 (355kHz) 3.48 540kHz (TON = GND) ±12.5 1.7 (620kHz) 3.42 2.3 (460kHz) 3.87 *See the Step-Down Converter Dropout Performance section (h = 1.5 and worst-case K-factor value used). Table 4. SKIP Configuration Table SKIP OUT1 MODE OUT2 MODE VCC Forced PWM Forced PWM Open Forced PWM Pulse skipping REF Pulse skipping Forced PWM GND Pulse skipping Pulse skipping ing the high-side switch, inductor, and PC board resistances; and t ON is the on-time calculated by the MAX1540A/MAX1541. Light-Load Operation (SKIP) The four-level SKIP input selects light-load, pulse-skipping operation by independently enabling or disabling the zero-crossing comparator for each controller (Table 4). When the zero-crossing comparator is enabled, the controller forces DL_ low when the current-sense inputs detect zero inductor current. This keeps the inductor from discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. When the zero-crossing comparator is disabled, the controller maintains PWM operation under light-load conditions (see the ForcedPWM Mode section). Automatic Pulse-Skipping Mode In skip mode, an inherent automatic switchover to PFM takes place at light loads (Figure 3). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current’s zero crossing. The zero-crossing comparator differentially senses the inductor current across the current-sense inputs (CSP_ to CSN_). Once VCSP_ - VCSN_ drops below 5% of the current-limit threshold (2.5mV for the default 50mV current-limit threshold), the comparator forces DL_ low (Figure 3). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between con- tinuous and discontinuous inductor-current operation (also known as the “critical-conduction” point). The load-current level at which PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half the peak-to-peak ripple current, which is a function of the inductor value (Figure 4). This threshold is relatively constant, with only a minor dependence on battery voltage: ⎞ K ⎞⎛ V - V ⎛V ILOAD(SKIP) ≈ ⎜ OUT ⎟ ⎜ IN OUT ⎟ ⎝ 2L ⎠ ⎝ VIN ⎠ where K is the on-time scale factor (Table 3). For example, in the MAX1541 Standard Application Circuit (Figure 12) (K = 3.0µs, VOUT2 = 2.5V, VIN = 12V, and L = 4.3µH), the pulse-skipping switchover occurs at: ⎛ 2.5V × 3.0μs ⎞ ⎛ 12V - 2.5V ⎞ ⎟ = 0.69A ⎜ ⎟⎜ ⎝ 2 × 4.3μH ⎠ ⎝ 12V ⎠ The crossover point occurs at an even lower value if a swinging (soft-saturation) inductor is used. The switching waveforms may appear noisy and asynchronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs in PFM noise vs. light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response (especially at low input-voltage levels). DC-output accuracy specifications refer to the threshold of the error comparator. When the inductor is in continuous conduction, the MAX1540A/MAX1541 regulate the valley of the output ripple, so the actual DC output voltage is higher than the trip level by 50% of the output ripple voltage. In discontinuous conduction ______________________________________________________________________________________ 25 MAX1540A/MAX1541 Table 3. Approximate K-Factor Errors MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator *MAIN MAX1541 CONTROLLER (OUT1) ONLY SLOPE COMP CC1CC1 R ERROR AMP INT FB_ tOFF(MIN) 7R A Gm = 80 V INT REF_ Q TRIG 1-SHOT S VALLEY CURRENT LIMIT Q DH DRIVER R tON SATURATION LIMIT TRIG Q 1-SHOT DL DRIVER S Q V+ ON-TIME COMPUTE TON FAULT PROTECTION R OUT_ ZERO CROSSING Figure 3. MAX1540A/MAX1541 PWM-Controller Functional Diagram VIN - VOUT L IPEAK INDUCTOR CURRENT ΔI = Δt ILOAD = IPEAK/2 0 ON-TIME TIME Figure 4. Pulse-Skipping/Discontinuous Crossover Point (IOUT < ILOAD(SKIP)), the output voltage has a DC regulation level higher than the error-comparator threshold by approximately 1.5% due to slope compensation. Forced-PWM Mode The low-noise forced-PWM mode disables the zerocrossing comparator, which controls the low-side switch on-time. This forces the low-side gate-drive waveform to be constantly the complement of the highside gate-drive waveform, so the inductor current 26 reverses at light loads while DH_ maintains a duty factor of VOUT_ / VIN. The benefit of forced-PWM mode is to keep the switching frequency fairly constant. However, forced-PWM operation comes at a cost: the no-load 5V bias current remains between 4mA to 40mA, depending on the external MOSFETs and switching frequency. Forced-PWM mode is most useful for reducing audiofrequency noise, improving load-transient response, and providing sink-current capability for dynamic output-voltage adjustment. The MAX1541 uses forcedPWM operation during all dynamic output-voltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. Since forced-PWM operation disables the zero-crossing comparator, the inductor current reverses under light loads, quickly discharging the output capacitors. FBLANK determines how long the MAX1541 maintains forced-PWM operation—typically 220µs (FBLANK = VCC), 140µs (FBLANK = open or GND), or 65µs (FBLANK = REF). Current-Limit Protection (ILIM_) Valley Current Limit The current-limit circuit employs a unique “valley” current-sensing algorithm that uses a current-sense resistor between CSP_ and CSN_ as the current-sensing ele- ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541 QUAD-LEVEL DECODE LSAT SATURATION LIMIT VCC - 1.0V ILIM_ 9R DH DRIVER R 6μA 0.5V S VALLEY CURRENT LIMIT Q R CSP_ ZERO CROSSING CSN_ SKIP Figure 5. MAX1540A/MAX1541 Current-Limit Functional Diagram IPEAK ILOAD INDUCTOR CURRENT ment (Figure 1). If the magnitude of the current-sense signal is above the valley current-limit threshold, the PWM controller is not allowed to initiate a new cycle (Figures 3 and 5). The actual peak current is greater than the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense resistance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance. Figure 6 shows the valley current-limit threshold point. In forced-PWM mode, the MAX1540A/MAX1541 also implement a negative current limit to prevent excessive reverse inductor currents when VOUT is sinking current. The negative current-limit threshold is set to approximately 120% of the positive current limit and tracks the positive current limit when ILIM is adjusted. The current-limit threshold is adjusted with an external resistor-divider at ILIM_. A 2µA to 20µA divider current is recommended for accuracy and noise immunity. The current-limit threshold adjustment range is from 25mV to 200mV. In the adjustable mode, the current-limit threshold voltage is precisely 1/10th the voltage seen at ILIM_. The threshold defaults to 50mV when ILIM_ is ILIMIT ( LIR2 ) ILIM(VAL) = ILOAD(MAX) 1- 0 TIME Figure 6. Valley Current-Limit Threshold Point connected to VCC. The logic threshold for switchover to the 50mV default value is approximately VCC - 1V. Carefully observe the PC board layout guidelines to ensure that noise and DC errors do not corrupt the differential current-sense signals seen by CSP_ and CSN_. Place the IC close to the sense resistor with short, direct traces, making a Kelvin-sense connection to the current-sense resistor. ______________________________________________________________________________________ 27 MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Inductor-Saturation Limit The LSAT connection selects an upper current-sense limit as the inductor-saturation threshold, or disables the inductor-saturation protection feature altogether (LSAT = GND). When enabled, the inductor-saturation threshold is a multiple of the positive valley current-limit threshold (Table 5) and tracks the valley current limit when ILIM is adjusted. The selected inductor-saturation threshold should give sufficient headroom above the peak inductor current so switching noise does not accidentally trip the saturation protection. Selecting an excessively high threshold may allow inductor saturation to go undetected. For an inductor with a low LIR (the ratio of the inductor ripple current to the designed maximum load current) near 20%, select the lowest saturation threshold of 1.5 x ILIM(VAL) (LSAT = REF). When using an inductor with a higher LIR, increase the inductor-saturation threshold accordingly. When inductor-saturation protection is enabled, the MAX1540A/MAX1541 continuously monitor the inductor current through the voltage across the current-sense resistor. When the inductor-saturation threshold is exceeded, the MAX1540A/MAX1541 immediately turn off the high-side gate driver and enable a 6µA discharge current on ILIM_ (Figure 7) at the beginning of the next DH_ on-time. This reduces the voltage on ILIM_ by ΔVILIM where: ⎛ R R ⎞ ΔVILIM = - ⎜ A B ⎟ IILIM(LSAT) ⎝ RA +RB ⎠ MAX1540A MAX1541 CREF REF where the ILIM saturation fault sink current (IILIM(LSAT)) is typically 6µA (see the Electrical Characteristics table). When using the default 50mV valley current-limit threshold (ILIM_ = VCC), the ILIM_ saturation fault sink current does not lower the current-limit threshold (Figure 5). If the inductor current remains below the saturation threshold during the next cycle, the controller disables the ILIM_ discharge current, allowing the ILIM_ voltage to return to its nominal set point. The inductor should not remain in saturation once the controller reduces the valley current limit. If the inductor remains saturated, the output voltage may drop low enough to trip the undervoltage fault protection (UVP enabled), causing the MAX1540A/MAX1541 to set the fault latch and shut down both outputs. Adding a capacitor from ILIM_ to GND slows the ILIM_ voltage change by the time constant τ = (RA || RB) x CILIM, where τ is between 5 to 10 switching periods. If the inductor saturation occurs only during a short load transient, the time constant allows the power supply to recover before the output voltage drops below the output undervoltage threshold. Set ΔVILIM to be at least 30% of the ILIM_ set voltage. Calculate RA and RB using the equations below: RA = ⎛ ΔV ⎞ VREF ⎛ ΔVILIM ⎞ ILIM ⎜ ⎟ with ⎜ ⎟ set at 30% IILIM(LSAT) ⎝ VILIM(SET) ⎠ V ⎝ ILIM(SET) ⎠ RB = RA ⎛ V ⎞ REF - 1⎟ ⎜V ⎝ ILIM(SET) ⎠ Inductor-saturation sensing works best when using a current-sense resistor in series with the inductor. See the Setting the Current Limit section for various current-sense configurations (Figure 14) and LSAT recommendations. RA TO VALLEY CURRENT-LIMIT COMPARATOR (FIGURE 2) CILIM ILIM 6μA Table 5. LSAT Configuration Table RB FROM LSAT COMPARATOR AND LOGIC (FIGURE 2) LSAT INDUCTOR-SATURATION THRESHOLD VCC 2.00 x ILIM(VAL) Open 1.75 x ILIM(VAL) REF 1.50 x ILIM(VAL) GND Disabled Figure 7. Adjustable Current-Limit Threshold 28 ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator ⎛C ⎞ VGS(TH) > VIN ⎜ RSS ⎟ ⎝ CISS ⎠ Lot-to-lot variation of the threshold voltage can cause problems in marginal designs. Alternatively, adding a resistor less than 10Ω in series with BST_ can remedy the problem by increasing the turn-on time of the high-side MOSFET without degrading the turn-off time (Figure 8). POR, UVLO, and Soft-Start Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and soft-start counter, powering-up the reference, and preparing the PWM for operation. Until VCC reaches 4.25V (typ), VCC undervoltage lockout (UVLO) circuitry inhibits switching. The controller inhibits switching by pulling DH_ low, and holding DL_ low when OVP and shutdown discharge are disabled or forcing DL_ high when OVP and shutdown discharge are enabled (Table 7). When VCC rises above 4.25V and ON_ is driven high, the controller activates the PWM controller and initializes soft-start. MAX1540A/MAX1541 MOSFET Gate Drivers (DH_, DL_) The DH_ and DL_ drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications where a large VIN - VOUT differential exists. An adaptive dead-time circuit monitors the DL_ output and prevents the high-side MOSFET from turning on until DL_ is off. A similar adaptive deadtime circuit monitors the DH_ output, preventing the lowside MOSFET from turning on until DH_ is off. There must be a low-resistance, low-inductance path from the DL_ and DH_ drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX1540A/MAX1541 interprets the MOSFET gates as “off” while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver). The internal pulldown transistor that drives DL_ low is robust, with a 0.6Ω (typ) on-resistance. This helps prevent DL_ from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX_) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces may require additional gateto-source capacitance to ensure fast-rising LX_ edges do not pull up the low-side MOSFETs gate, causing shoot-through currents. The capacitive coupling between LX_ and DL_ created by the MOSFET’s gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS-CRSS), and additional board parasitics should not exceed the following minimum threshold: CBYP MAX1540A MAX1541 VDD BST (RBST)* DBST INPUT (VIN) CBST DH NH L LX VDD DL NL (CNL)* PGND (RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS. Figure 8. Optional Gate-Driver Circuitry Soft-start allows a gradual increase of the internal currentlimit level during startup to reduce the input surge currents. The MAX1540A/MAX1541 divide the soft-start period into five phases. During the first phase, the controller limits the current limit to only 20% of the full current limit. If the output does not reach regulation within 425µs, soft-start enters the second phase, and the current limit is increased by another 20%. This process is repeated until the maximum current limit is reached after 1.7ms or when the output reaches the nominal regulation voltage, whichever occurs first (see the soft-start waveforms in the Typical Operating Characteristics). Power-Good Output (PGOOD_) PGOOD_ is the open-drain output for a window comparator that continuously monitors the output. PGOOD_ is actively held low in shutdown and during soft-start. After the digital soft-start terminates, PGOOD_ becomes high impedance as long as the respective output voltage is within ±10% of the nominal regulation voltage set by FB_. When the output voltage drops 10% below or rises 10% above the nominal regulation voltage, the MAX1540A/MAX1541 pull the respective power-good output (PGOOD_) low by turning on the MOSFET (Figure 9). Any fault condition forces both PGOOD1 and PGOOD2 low until the fault latch is cleared by toggling ______________________________________________________________________________________________________ 29 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541 Table 6. FBLANK Configuration Table POWER-GOOD 0.9 x INT REF_ 1.1 x INT REF_ FAULT PROTECTION 0.7 x INT REF_ 1.16 x INT REF_ INT FB_ ENABLE OVP FBLANK OUT1 FAULT BLANKING FORCED-PWM DURATION (MIN/TYP) (µs) VCC Enabled 120/220 Open Enabled 80/140 REF Enabled 35/65 GND Disabled 80/140 ENABLE UVP *BLANK 20ms TIMER FAULT LATCH FAULT POWERGOOD POR *MAIN MAX1541 CONTROLLER (OUT1) ONLY Figure 9. Power-Good and Fault Protection ON1 or ON2, or cycling VCC power below 1V. For logiclevel output voltages, connect an external pullup resistor between PGOOD_ and VCC. A 100kΩ resistor works well in most applications. Note that the power-good window detectors are completely independent of the overvoltage and undervoltage-protection fault detectors. Fault Blanking (MAX1541 FBLANK) The main MAX1541 controller (OUT1) automatically enters forced-PWM operation during all dynamic outputvoltage transitions (GATE transition detected) in order to ensure fast, accurate transitions. FBLANK determines how long the main MAX1541 controller maintains forcedPWM operation (Table 6—typically 220µs (FBLANK = V CC ), 140µs (FBLANK = open or GND), or 65µs (FBLANK = REF). When fault blanking is enabled (FBLANK = VCC, open, or REF), the MAX1541 also disables the overvoltage and undervoltage fault protection for OUT1, and forces PGOOD1 to a high-impedance state during the transition period selected by FBLANK (Table 6). This prevents fault protection from latching off the MAX1541 and the PGOOD1 signal from going low when the output voltage change (ΔVOUT1) cannot occur as fast as the REFIN1 voltage change (ΔVREFIN1). 30 Shutdown and Output Discharge (ON_) When the output discharge mode is enabled (OVP/UVP connected to V CC or left open), and either ON_ is pulled low or an OVP fault or thermal fault sets the fault latch (Table 7), the controller discharges each output through an internal 10Ω switch connected between OUT_ and ground. While the output discharges, DL_ is forced low and the PWM controller is disabled. Once the output voltage drops below 0.3V, the low-side driver pulls DL_ high, effectively clamping the output and LX_ switching node to ground. The reference remains active until both output voltages are below 0.3V to provide an accurate 0.3V discharge threshold. When OVP/UVP is connected to REF or GND, the controller does not actively discharge either output, and the DL_ driver remains low until the system reenables the controller. Under these conditions, the output discharge rate is determined by the load current and output capacitance. The controller detects and latches the discharge-mode state set by OVP/UVP on startup. Fault Protection The MAX1540A/MAX1541 provide over/undervoltage fault protection (Figure 9). Drive OVP/UVP to enable and disable fault protection as shown in Table 7. Once activated, the controller continuously monitors the output for undervoltage and overvoltage fault conditions. Overvoltage Protection (OVP) When the output voltage rises above 116% of the nominal regulation voltage and OVP is enabled (OVP/UVP = VCC or open), the OVP circuit sets the fault latch, shuts down both the Quick-PWM controllers, immediately pulls DH1 and DH2 low, and forces DL1 and DL2 high. This turns on the synchronous-rectifier MOSFETs with 100% duty, rapidly discharging the output capacitors and clamping both outputs to ground. Note that immediately latching DL_ high can cause the output voltages to go slightly negative due to energy stored in the output LC at the instant the OV fault occurs. If the load ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator OVP is disabled when OVP/UVP is connected to REF or GND (Table 7). Undervoltage Protection (UVP) When the output voltage drops below 70% of the nominal regulation voltage and UVP is enabled (OVP/UVP = VCC or REF), the controller sets the fault latch and activates the output discharge sequence (see the Shutdown and Output Discharge (ON_) section) of both outputs. When the output voltage drops to 0.3V, the driver pulls DL high so the synchronous rectifier turns on, clamping the output to GND. UVP is ignored for at least 10ms (min) after startup (ON_ rising edge), and when transitions are detected on GATE (MAX1541 only, FBLANK enabled). Toggle ON1 or ON2, or cycle VCC power below 1V to clear the fault latch and restart the controller. UVP is disabled when OVP/UVP is left open or connected to GND (Table 7). Thermal Fault Protection The MAX1540A/MAX1541 feature a thermal fault-protection circuit. When the linear regulator is disabled (LDOON = GND), the controller sets the thermal limit at +160°C. When the linear regulator is enabled (LDOON = VCC), the controller sets the thermal limit at +150°C to protect the internal linear regulator from continuous short-circuit conditions. Once the junction temperature exceeds the thermal limit, the thermal-protection circuit activates the fault latch, pulls PGOOD1 and PGOOD2 low, disables the linear regulator, and activates the output discharge sequence of both outputs regardless of the OVP/UVP setting. Toggle ON1 or ON2, or cycle VCC power below 1V to reactivate the controller after the junction temperature cools by 10°C. Output Voltage Preset Output Voltages The MAX1540A/MAX1541s’ Dual Mode operation allows the selection of common voltages without requiring external components (Figure 10). For the main controller (OUT1) of the MAX1540A, connect FB1 to GND for a fixed 1.8V output, to VCC for a fixed 1.2V output, or connect FB1 directly to OUT1 for a fixed 0.7V output. For the secondary controller (OUT2) of the MAX1540A, connect FB2 to GND for a fixed 2.5V output, to VCC for a fixed 1.5V output, or connect FB2 directly to OUT2 for a fixed 0.7V output. The main controller (OUT1) of the MAX1541 regulates to the voltage set at REFIN1 (VFB1 = VREFIN1) and does not support Dual Mode operation. For the secondary controller (OUT2) of the MAX1541, connect FB2 to GND for a fixed 2.5V output, to VCC for a fixed 1.8V output, or connect FB2 directly to OUT2 for a fixed 0.7V output. Table 8 shows the output voltage configuration. Table 7. Fault Protection and Shutdown Setting Truth Table OVP/UVP ON_ DISCHARGE* UVP PROTECTION OVP PROTECTION THERMAL PROTECTION VCC Yes. Output discharged through a 10Ω resistor, and DL forced high when output drops below 0.3V. Yes. UVP fault activates Yes. DH pulled low and DL the discharge sequence. forced high immediately. Yes. Thermal fault activates the discharge sequence. Open Yes. Output discharged through a 10Ω resistor, and DL forced high when output drops below 0.3V. No. UVP disabled. Yes. DH pulled low and DL forced high immediately. Yes. Thermal fault activates the discharge sequence. REF No. DL forced low when shut down. Yes. UVP fault activates No. OVP disabled. the discharge sequence. Yes. Thermal fault activates the discharge sequence. GND No. DL forced low when shut down. No. UVP disabled. Yes. Thermal fault activates the discharge sequence. No. OVP disabled. *Discharge-mode state latched on power-up. ______________________________________________________________________________________ 31 MAX1540A/MAX1541 cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reversepolarity clamp. If the condition that caused the overvoltage persists (such as a shorted high-side MOSFET), the input fuse blows. The MAX1541 ignores OVP faults on OUT1 when it detects a transition on GATE (FBLANK enabled). Toggle ON1 or ON2, or cycle VCC power below 1V to clear the fault latch and restart the controller. MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541 OUT_ TO ERROR AMPLIFIER FIXED OUTPUT FB = VCC FB_ FIXED OUTPUT FB = GND REF (2.0V) 9R R Figure 10. MAX1540A/MAX1541 Dual Mode Feedback Decoder Table 8. Output Voltage Configuration OUT1 OUT2 MAX1540A MAX1541 MAX1540A MAX1541 FB_ = VCC Fixed 1.2V Not allowed Fixed 1.5V Fixed 1.8V FB_ = GND Fixed 1.8V Not allowed Fixed 2.5V Fixed 2.5V FB_ = OUT_ or adjustable 0.7V VREFIN1 0.7V 0.7V Setting VOUT with a Resistive Voltage-Divider at FB_ The output voltage can be adjusted from 0.7V to 5.5V using a resistive voltage-divider (Figure 11). The MAX1540A regulates FB1 and FB2 to a fixed 0.7V reference voltage. The MAX1541 regulates FB1 to the voltage set at REFIN1 and regulates FB2 to a fixed 0.7V reference voltage. This makes the main MAX1541 controller (OUT1) ideal for memory applications where the termination supply must track the supply voltage. The adjusted output voltage is: ⎛ R ⎞ VOUT_ = VFB_ ⎜1+ C ⎟ ⎝ RD ⎠ where V FB_ = 0.7V for the MAX1540A, and V FB1 = VREFIN1 and VFB2 = 0.7V for the MAX1541. 32 Dynamic Output Voltages (MAX1541 OUT1 Only) The MAX1541 regulates FB1 to the voltage set at REFIN1. By changing the voltage at REFIN1, the MAX1541 can be used in applications that require dynamic output-voltage changes between two set points. Figure 12 shows a dynamically adjustable resistive voltage-divider network at REFIN1. Using the GATE signal and open-drain output (OD), a resistor can be switched in and out of the REFIN1 resistor-divider, changing the voltage at REFIN1. A logic high on GATE turns on the internal N-channel MOSFET, forcing OD to a low-impedance state. A logic low on GATE disables the N-channel MOSFET, so OD is high impedance. The two output voltages (FB1 = OUT1) are determined by the following equations: ⎛ R9 ⎞ VOUT1(LOW) = VREF ⎜ ⎟ ⎝ R8+R9 ⎠ ⎡ (R9+R10) ⎤ VOUT1(HIGH) = VREF ⎢ ⎥ ⎣ R8+(R9+R10) ⎦ The main MAX1541 controller (OUT1) automatically enters forced-PWM operation on the rising and falling edges of GATE, and remains in forced-PWM mode for a minimum time selected by FBLANK (Table 6). ForcedPWM operation is required to ensure fast, accurate negative voltage transitions when REFIN1 is lowered. Since forced-PWM operation disables the zero-crossing comparator, the inductor current may reverse under ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator RSENSE MAX1540A/MAX1541 COUT DL_ NL GND and the time constant for a negative REFIN1 voltage transition is: CSP_ CSN_ OUT_ RC ⎛ R8 × R9 ⎞ τNEG = ⎜ ⎟C ⎝ R8+R9 ⎠ REFIN1 FB_ Linear Regulator (LDO) RD Figure 11. Setting VOUT with a Resistive Voltage-Divider at FB_ light loads, quickly discharging the output capacitors. If fault blanking is enabled, the MAX1541 also disables the main controller’s (OUT1) overvoltage and undervoltage fault protection, and forces PGOOD1 to a highimpedance state for the period selected by FBLANK (Table 6). For a step-voltage change at REFIN1, the rate of change of the output voltage is limited by the inductor current ramp, the total output capacitance, the current limit, and the load during the transition. The inductor current ramp is limited by the voltage across the inductor and the inductance. The total output capacitance determines how much current is needed to change the output voltage. Additional load current slows down the output-voltage change during a positive REFIN1 voltage change, and speeds up the output-voltage change during a negative REFIN1 voltage change. For fast positive output-voltage transitions, the current limit must be greater than the load current plus the transition current: d ILIMIT > ILOAD + COUT V dt Adding a capacitor across REFIN1 and GND filters noise and controls the rate of change of the REFIN1 The maximum input voltage for the linear regulator is 28V, while the minimum input voltage is determined by the 800mV (max) dropout voltage (V LDOIN(MIN) = VLDOOUT + VDROPOUT) at 50mA load. Bypass the linear regulator’s output (LDOOUT) with a 4.7µF or greater capacitor, providing at least 1µF per 5mA of internal and external load on the linear regulator. The LDO can source up to 100mA for powering the controller or supplying a small external load. For the MAX1540A, the linear regulator provides the 5V bias supply that powers the gate drivers and analog controller (Figure 1), providing stand-alone capability. The linear regulator’s input is internally connected to the battery voltage input (LDOIN = V+), and the gatedriver input supply is internally connected to the linear regulator’s output (VDD = LDOOUT). Figure 13 is the internal linear-regulator functional diagram. For the MAX1541, the linear regulator supports Dual Mode operation to allow the selection of a 5V output voltage without requiring external components (Figure 1). Connect FBLDO to GND for a fixed 5.0V output. The linear regulator’s output voltage can be adjusted from 1.25V to 5.5V using a resistive voltage-divider (Figure 12). The MAX1541 regulates FBLDO to a 1.25V feedback voltage. The adjusted output voltage is: ⎛ R11 ⎞ VLDOOUT = VFBLDO ⎜1+ ⎟ ⎝ R12 ⎠ where VFBLDO = 1.25V. If unused, disable the MAX1541 linear regulator by connecting LDOON to GND. ______________________________________________________________________________________ 33 MAX1540A/MAX1541 L LX_ voltage during dynamic transitions. With the additional capacitance, the REFIN1 voltage slews between the two set points with a time constant given by R EQ x CREFIN1, where REQ is the equivalent parallel resistance seen by the slew capacitor. Looking at Figure 12, the time constant for a positive REFIN1 voltage transition is: ⎡ R8 × (R9+R10) ⎤ τPOS = ⎢ ⎥ CREFIN1 ⎣ R8+(R9+R10) ⎦ MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator +5V BIAS SUPPLY INPUT (VIN)* 7V TO 20V CIN (2) 4.7μF C1 1μF V+ VDD DBST NH1 DBST MAX1541 DH1 DH2 BST1 BST2 LX1 LX2 DL1 DL2 SKIP GND CSP1 CSP2 CBST1 0.1μF NL1 DL1 L1 1.8μH NH2 CBST 0.1μF NL2 DL2 RCS2 15mΩ RCS1 15mΩ OUTPUT 1 VOUT(HIGH) = 1.5V VOUT(LOW) = 1.0V ( COUT1 470μF CSN1 CSN2 OUT1 OUT2 CCC1 47pF ) COUT2 220μF FB2 FB1 R9 VOUT(LOW) = VREF (R8 + R9 ) VOUT(HIGH) = VREF L2 4.3μH OUTPUT 2 VOUT2 = 2.5V OVP/UVP CC1 LSAT CREF 0.22μF (R9 + R10) [R8 + (R9 + R10)] TON OPEN (ILIM(VAL) x 1.75) REF (485kHz/355kHz) REF CILIM1 470pF ILIM1 OFF R1 20Ω R3 49.9kΩ CILIM2 470pF ON LDOON ON1 ON2 R2 100kΩ +5V BIAS SUPPLY VCC C2 1μF R4 100kΩ R7 100kΩ R6 100kΩ ILIM2 R5 49.9kΩ PGOOD1 POWER-GOOD PGOOD2 VOUT(LOW) R13 10Ω GATE VOUT(HIGH) OPEN (ENABLED, 140μs) +5V BIAS SUPPLY LDOIN C3 4.7μF FBLANK REFIN1 REF R8 75kΩ LDOOUT R9 75kΩ R11 32.4kΩ OD CREFIN 470pF C4 22μF LDO OUTPUT VLDOOUT = 3.3V FBLDO EP R10 150kΩ R12 20kΩ POWER GROUND SEE TABLE 1 FOR COMPONENT SPECIFICATIONS. ANALOG GROUND *LOWER INPUT VOLTAGES REQUIRE ADDITIONAL INPUT CAPACITANCE. Figure 12. MAX1541 Standard Application Circuit 34 ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541 INTERNAL LDOIN OPTION BETWEEN THE MAX1540A/MAX1541 V+ *LDOIN LDOOUT VL REG AND REF LDOON INTERNAL VDD OPTION BETWEEN THE MAX1540A/MAX1541 GATE DRIVER AND ERROR AMP *VDD FIXED 5V *FBDLO INTERNAL FBLDO OPTION BETWEEN THE MAX1540A/MAX1541 0.2V *MAX1541 ONLY. Figure 13. Internal Linear-Regulator Functional Diagram Design Procedure Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: • Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case, high AC-adapter voltage. The minimum value (VIN(MIN)) must account for the lowest battery voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency. • Maximum load current: There are two values to consider. The peak load current (ILOAD(MAX)) determines the instantaneous component stresses and filtering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses and thus drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. • Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target, due to rapid improvements in MOSFET technology that are making higher frequencies more practical. • Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further sizereduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. When pulse skipping (SKIP low and light loads), the inductor value also determines the load-current value at which PFM/PWM switchover occurs. ______________________________________________________________________________________ 35 MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Inductor Selection Setting the Current Limit The switching frequency and inductor operating point determine the inductor value as follows: The minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: L= VOUT (VIN - VOUT ) VIN × fSW x ILOAD(MAX) × LIR For example: ILOAD(MAX) = 4A, VIN = 12V, VOUT2 = 2.5V, fSW = 355kHz, 30% ripple current or LIR = 0.3: L= 2.5V × (12V - 2.5V) = 4.65μH 12V × 355kHz x 4 A × 0.3 Find a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Ferrite cores are often the best choice, although powdered iron is inexpensive and can work well at 200kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): ⎛ LIR ⎞ IPEAK = ILOAD(MAX) ⎜1 + ⎟ ⎝ 2 ⎠ Most inductor manufacturers provide inductors in standard values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also look for nonstandard values, which can provide a better compromise in LIR across the input voltage range. If using a swinging inductor (where the no-load inductance decreases linearly with increasing current), evaluate the LIR with properly scaled inductance values. Transient Response The inductor ripple current also impacts transientresponse performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the ontime and minimum off-time: ⎡⎛ V ⎤ ×K⎞ L(ΔILOAD(MAX) )2 ⎢⎜ OUT + t OFF(MIN) ⎥ ⎟ ⎢⎣⎝ VIN ⎠ ⎥⎦ VSAG = ⎡⎛ ( VIN - VOUT ) × K ⎞ ⎤ 2COUT × VOUT ⎢⎜ ⎟ - t OFF(MIN) ⎥ VIN ⎢⎝ ⎥ ⎠ ⎣ ⎦ where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics) and K is from Table 3. The amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: VSOAR 36 2 ΔILOAD(MAX) ) L ( ≈ 2COUT × VOUT ⎛ VOUT (VIN(MIN) - VOUT ) ⎞ ILIM(VAL) > ILOAD(MAX) - ⎜ ⎟ 2VIN(MIN) fSW L ⎠ ⎝ where ILIM(VAL) equals the minimum valley current-limit threshold voltage divided by the current-sense resistance (RSENSE). For the 50mV default setting, the minimum valley current-limit threshold is 40mV. Connect ILIM_ to VCC for a default 50mV valley currentlimit threshold. In adjustable mode, the valley currentlimit threshold is precisely 1/10th the voltage seen at ILIM_. For an adjustable threshold, connect a resistive divider from REF to analog ground (GND) with ILIM_ connected to the center tap. The external 250mV to 2V adjustment range corresponds to a 25mV to 200mV valley current-limit threshold. When adjusting the current limit, use 1% tolerance resistors and a divider current of approximately 10µA to prevent significant inaccuracy in the valley current-limit tolerance. The current-sense method (Figure 14) and magnitude determine the achievable current-limit accuracy and power loss (Table 9). Typically, higher current-sense voltage limits provide tighter accuracy, but also dissipate more power. Most applications employ a valley current-sense voltage (VLIM(VAL)) of 50mV to 100mV, so the sense resistor may be determined by: RSENSE = VLIM(VAL) / ILIM(VAL) For the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in Figure 14a. This configuration constantly monitors the inductor current, allowing accurate valley current-limiting and inductor-saturation protection. For low-output-voltage applications that require higher efficiency, the current-sense resistor can be connected between the source of the low-side MOSFET (NL_) and power ground (Figure 14b) with CSN_ connected to the drain of NL_ and CSP_ connected to power ground. In this configuration, the additional current-sense resistance only dissipates power when NL_ is conducting current. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on. ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator L = CEQ × REQ RL where RL is the inductor’s series DC resistance. In this configuration, the current-sense resistance is equivalent to the inductor’s DC resistance (RSENSE = RL). Use the worst-case inductance and RL values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. In all cases, ensure an acceptable valley current-limit threshold voltage and inductor-saturation configurations despite inaccuracies in sense-resistance values. Output Capacitor Selection The output filter capacitor must have low enough equivalent series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements. For processor-core voltage converters and other applications where the output is subject to violent load transients, the output capacitor’s size depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance: RESR ≤ VSTEP ΔILOAD(MAX) In applications without large and fast load transients, the output capacitor’s size often depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. The output ripple voltage of a stepdown controller equals the total inductor ripple current multiplied by the output capacitor’s ESR. Therefore, the maximum ESR required to meet ripple specifications is: VRIPPLE RESR ≤ ΔILOAD(MAX) × LIR The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of tantalums, OS-CONs, polymers, and other electrolytics). When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section). However, lowcapacity filter capacitors typically have high-ESR zeros that may affect the overall stability (see the OutputCapacitor Stability Considerations section). Table 9. Current-Sense Configurations CURRENT-SENSE ACCURACY INDUCTOR-SATURATION PROTECTION CURRENT-SENSE POWER LOSS (EFFICIENCY) a) Output current-sense resistor High Allowed (highest accuracy) RSENSE x IOUT2 b) Low-side current-sense resistor High Not allowed (LSAT = GND) ⎛ VOUT ⎞ 2 ⎜1- V ⎟ × RSENSE × IOUT ⎝ IN ⎠ c) Low-side MOSFET on-resistance Low Not allowed (LSAT = GND) No additional loss d) Equivalent inductor DC resistance Low Allowed No additional loss METHOD ______________________________________________________________________________________ 37 MAX1540A/MAX1541 For high-power applications that do not require highaccuracy current sensing or inductor-saturation protection, the MAX1540A/MAX1541 can use the low-side MOSFET’s on-resistance as the current-sense element (RSENSE = RDS(ON)) by connecting CSN_ to the drain of NL_ and CSP_ to the source of NL_ (Figure 14c). Use the worst-case maximum value for RDS(ON) from the MOSFET data sheet, and add some margin for the rise in RDS(ON) with temperature. A good general rule is to allow 0.5% additional resistance for each °C of temperature rise. Inductor-saturation protection must be disabled with this configuration (LSAT = GND) since the inductor current is only properly sensed when the lowside MOSFET is turned on. Alternatively, high-power applications that require inductor saturation can constantly detect the inductor current by connecting a series RC circuit across the inductor (Figure 14d) with an equivalent time constant: MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator VIN DH CIN RSENSE L VOUT LX COUT MAX1540A DL MAX1541 GND CONNECT TO PREFERRED LSAT SETTING CSP LSAT CSN a) OUTPUT SERIES RESISTOR SENSING VIN CIN DH L VOUT LX COUT MAX1540A DL MAX1541 CSN RSENSE DISABLE LSAT CSP GND LSAT b) LOW-SIDE SERIES RESISTOR SENSING VIN DH CIN L VOUT LX COUT CSN MAX1540A DL MAX1541 DISABLE LSAT VIN CSP LSAT DH GND CIN INDUCTOR RL L VOUT LX c) LOW-SIDE MOSFET SENSING MAX1540A DL MAX1541 GND CONNECT TO PREFERRED LSAT SETTING COUT REQ CEQ CSP LSAT CSN d) LOSSLESS INDUCTOR SENSING RBIAS = REQ Figure 14. Current-Sense Configurations 38 ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Input-Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents: f fESR ≤ SW π where: fESR = 1 2πRESR COUT For a typical 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum and OS-CON capacitors in widespread use at the time of publication have typical ESR zero frequencies of 25kHz. In the design example used for inductor selection, the ESR needed to support 25mVP-P ripple is 25mV/1.2A = 20.8mΩ. One 220µF/4V Sanyo polymer (TPE) capacitor provides 15mΩ (max) ESR. This results in a zero at 48kHz, well within the bounds of stability. Do not put high-value ceramic capacitors directly across the feedback sense point without taking precautions to ensure stability. Large ceramic capacitors can have a high-ESR zero frequency and cause erratic, unstable operation. However, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. Unstable operation manifests itself in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This “fools” the error comparator into triggering a new cycle immediately after the 400ns minimum offtime period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to monitor simultaneously the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot. 2 Σ IRMS = I2OUTX VOUTX (VIN - VOUTX) X=1 VIN For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to power-up surge currents typical of systems with a mechanical switch or connector in series with the input. If the MAX1540A/MAX1541 are operated as the second stage of a two-stage power conversion system, tantalum input capacitors are acceptable. In either configuration, choose a capacitor that has less than 10°C temperature rise at the RMS input current for optimal reliability and lifetime. Power MOSFET Selection Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20V) AC adapters. Low-current applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Ideally, the losses at VIN(MIN) should be roughly equal to the losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher, consider increasing the size of NH. Conversely, if the losses at VIN(MAX) are significantly higher, consider reducing the size of NH. If VIN does not vary over a wide range, maximum efficiency is achieved by selecting a high-side MOSFET (NH) that has conduction losses equal to the switching losses. Choose a low-side MOSFET (NL) that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., 8-pin SO, DPAK, or D2PAK), and is reasonably priced. Ensure that the MAX1540A/MAX1541 DL_ gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems may occur. Switching losses are not an issue for the low-side MOSFET since it is a zero-voltage switched device when used in the step-down topology. ______________________________________________________________________________________ 39 MAX1540A/MAX1541 Output-Capacitor Stability Considerations For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Power-MOSFET Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at minimum input voltage: ⎛V ⎞ PD (NH Resistance) = ⎜ OUT ⎟ (ILOAD )2 × RDS(ON) V ⎝ IN ⎠ Generally, use a small high-side MOSFET to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power-dissipation limits often restricts how small the MOSFET can be. The optimum occurs when the switching losses equal the conduction (R DS(ON) ) losses. High-side switching losses do not become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFETs (NH) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PC board layout characteristics. The following switching loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH: PD (NH 2 VIN(MAX) ) CRSS × fSW × ILOAD ( Switching) = IGATE where CRSS is the reverse transfer capacitance of NH, and IGATE is the peak gate-drive source/sink current (1A typ). Switching losses in the high-side MOSFET can become a heat problem when maximum AC adapter voltages are applied due to the squared term in the switchingloss equation (C ✕ VIN2 ✕ fSW). If the high-side MOSFET chosen for adequate R DS(ON) at low-battery voltages becomes extraordinarily hot when subjected to VIN(MAX), consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum battery voltage: ⎡ ⎛ V ⎞⎤ PD (NL Resistance) = ⎢1- ⎜ OUT ⎟ ⎥ (ILOAD )2 × RDS(ON) ⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦ 40 The absolute worst case for MOSFET power dissipation occurs under heavy overload conditions that are greater than ILOAD(MAX) but are not high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, “overdesign” the circuit to tolerate: ⎛V (V − VOUT ) ⎞ ILOAD = IVALLEY(MAX) + ⎜ OUT IN ⎟ 2VIN fSW L ⎝ ⎠ where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and sense-resistance variation. The MOSFETs must have a relatively large heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward-voltage drop low enough to prevent the low-side MOSFET’s body diode from turning on during the dead time. As a general rule, select a diode with a DC current rating equal to 1/3 the load current. This diode is optional and can be removed if efficiency is not critical. Applications Information Step-Down Converter Dropout Performance The output-voltage adjustable range for continuousconduction operation is restricted by the nonadjustable minimum off-time one-shot. For best dropout performance, use the slower (200kHz) on-time setting. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on- and off-times. Manufacturing tolerances and internal propagation delays introduce an error to the TON K-factor. This error is greater at higher frequencies (Table 3). Also, keep in mind that transient-response performance of buck regulators operated too close to dropout is poor, and bulk output capacitance must often be added (see the VSAG equation in the Design Procedure section). The absolute point of dropout is when the inductor current ramps down during the minimum off-time (ΔIDOWN) as much as it ramps up during the on-time (ΔIUP). The ratio h = ΔIUP/ΔIDOWN indicates the controller’s ability to slew the inductor current higher in response to increased load, and must always be greater than 1. As h approaches 1, the absolute minimum dropout point, the inductor current cannot increase as much during each switching cycle, and V SAG greatly increases unless additional output capacitance is used. ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator VIN(MIN) = VOUT + VDROP1 ⎛ h × t OFF(MIN) ⎞ 1- ⎜ ⎟ K ⎝ ⎠ where V DROP1 is the parasitic voltage drop in the charge path (see the On-Time One-Shot (TON) section), tOFF(MIN) is from the Electrical Characteristics, and K is taken from Table 3. The absolute minimum input voltage is calculated with h = 1. If the calculated VIN(MIN) is greater than the required minimum input voltage, then operating frequency must be reduced or output capacitance added to obtain an acceptable VSAG. If operation near dropout is anticipated, calculate VSAG to be sure of adequate transient response. Dropout Design Example • VOUT2 = 2.5V • fSW = 355kHz • K = 3.0µs, worst-case KMIN = 3.3µs • tOFF(MIN) = 500ns • VDROP1 = 100mV • h = 1.5 VIN(MIN) = put voltages, it can produce three or more output voltages if required by using discrete logic or a DAC. Figure 15 shows an application circuit providing four voltage levels using discrete logic. Switching resistors in and out of the resistor network changes the voltage at REFIN1. An edge-detection circuit is added to generate a 1µs pulse on GATE to trigger the fault blanking and forced-PWM operation. When using PWM mode (SKIP = VCC or open) on the main controller, the edgedetection circuit is only required if fault blanking is enabled. Otherwise, leave OD unconnected. Active Bus Termination (MAX1541 OUT1 Only) Active-bus-termination power supplies generate a voltage rail that tracks a set reference. They are required to source and sink current. DDR memory architecture requires active bus termination. In DDR memory architecture, the termination voltage is set at exactly half the memory supply voltage. Configure the main MAX1541 controller (OUT1) to generate the termination voltage using a resistive voltage-divider at REFIN1. In such an application, the main MAX1541 controller (OUT1) must be kept in PWM mode (SKIP = VCC or open) in order for it to source and sink current. Figure 16 shows the main MAX1541 controller configured as a DDR termination regulator. Connect GATE and FBLANK to GND when unused. REF 2.5V + 0.1V = 3.47V ⎛ 1.5 × 500ns ⎞ 1- ⎜ ⎟ ⎝ 3.0μs ⎠ R4 R1 REFIN1 B Calculating again with h = 1 and the typical K-factor value (K = 3.3µs) gives the absolute limit of dropout: VIN(MIN) = R3 C1 2.5V + 0.1V = 3.06V ⎛ 1 × 500ns ⎞ 1- ⎜ ⎟ ⎝ 3.3μs ⎠ Therefore, VIN must be greater than 3.06V, even with very large output capacitance, and a practical input voltage with reasonable output capacitance would be 3.47V. Multi-Output Voltage Settings (MAX1541 OUT1 Only) R2 MAX1541 A GND 1.5kΩ 1000pF GATE 1.5kΩ 1000pF While the main MAX1541 controller (OUT1) is optimized to work with applications that require two dynamic outFigure 15. Multi-Output Voltage Settings ______________________________________________________________________________________ 41 MAX1540A/MAX1541 A reasonable minimum value for h is 1.5, but adjusting this up or down allows trade-offs between VSAG, output capacitance, and minimum operating voltage. For a given value of h, the minimum operating voltage can be calculated as: MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator VDDQ VCC VIN SKIP DH1 CIN L 10kΩ RSENSE V VTT = DDQ 2 LX1 REFIN1 10nF COUT DL1 MAX1541 GND 10kΩ CSP1 OD CSN1 GATE OUT1 FBLANK FB1 VDDQ = DDR MEMORY SUPPLY VOLTAGE VTT = TERMINATION SUPPLY VOLTAGE Figure 16. Active Bus Termination Voltage Positioning In applications where fast load transients occur, the output voltage changes instantly by ESRCOUT x ΔILOAD. Voltage positioning allows the use of fewer output capacitors for such applications, and maximizes the output voltage AC and DC tolerance window in tight-tolerance applications. Figure 17 shows the connection of OUT_ and FB_ in voltage-positioned and nonvoltage-positioned circuits. In nonvoltage-positioned circuits, the MAX1540A/ MAX1541 regulate at the output capacitor. In voltagepositioned circuits, the MAX1540A/MAX1541 regulate on the inductor side of the current-sense resistor. VOUT_ is reduced to: VOUT(VPS) = VOUT(NO LOAD) - RSENSE x ILOAD Figure 18 shows the voltage-positioning transient response. PC board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single milliohm of excess trace resistance causes a measurable efficiency penalty. • Minimize current-sensing errors by connecting CSP_ and CSN_ directly across the current-sense resistor (RSENSE_). • When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. • Route high-speed switching nodes (BST_, LX_, DH_, and DL_) away from sensitive analog areas (REF, FB_, CSP_, CSN_). PC Board Layout Guidelines Layout Procedure Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention (Figure 19). If possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. Follow these guidelines for good PC board layout: • Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. 1) Place the power components first, with ground terminals adjacent (NL _ source, CIN, COUT_, and DL _ anode). If possible, make all these connections on the top layer with wide, copper-filled areas. • 42 Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing 2) Mount the controller IC adjacent to the low-side MOSFET, preferably on the back side opposite NL _ and NH_ in order to keep LX_, GND, DH_, and the DL_ gate-drive lines short and wide. The DL_ and DH_ gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC) to keep the driver impedance low and for proper adaptive dead-time sensing. ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator MAX1540A/MAX1541 R1 +5V BIAS SUPPLY C2 VDD VCC DBST C1 V+ INPUT (VIN) CIN BST_ NH DH_ CBST MAX1540A LX_ MAX1541 L1 NL VOLTAGE-POSITIONED OUTPUT (VOUT(VPS)) RSENSE COUT DL DL_ GND CSP_ OUT_ FB CSN_ VOUT(VPS) = VOUT(NO LOAD) - RSENSEIOUT Figure 17. Voltage Positioning VOLTAGE POSITIONING THE OUTPUT CAPACITIVE SOAR (dV/dt = IOUT/COUT) ESR VOLTAGE STEP (ISTEP x RESR) A 1.4 VOUT 1.4 B CAPACITIVE SAG (dV/dt = IOUT/COUT) RECOVERY 50mV/div A. CONVENTIONAL CONVERTER B. VOLTAGE-POSITIONED OUTPUT ILOAD Figure 18. Voltage-Positioning Transient Response ______________________________________________________________________________________ 43 MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator VIA TO POWER GROUND CONNECT GND AND PGND TO THE CONTROLLER AT ONE POINT ONLY AS SHOWN CONNECT THE EXPOSED PAD TO ANALOG GROUND VIA TO VCC BYPASS CAPACITOR VIA TO VCC PIN VIA TO REF PIN VIA TO REF BYPASS CAPACITOR MAX1540A TOP LAYER MAX1540A BOTTOM LAYER KELVIN-SENSE VIAS UNDER THE SENSE RESISTOR (REFER TO EVALUATION KIT) DUAL N-CHANNEL MOSFET INDUCTOR SINGLE N-CHANNEL MOSFETS INDUCTOR DH LX DL COUT CIN CIN INPUT COUT OUTPUT COUT OUTPUT INPUT GROUND GROUND HIGH-POWER LAYOUT LOW-POWER LAYOUT Figure 19. PC Board Layout 3) Group the gate-drive components (BST_ diode and capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in Figures 1 and 12. This diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go, and an analog ground plane for sensitive analog components. The analog ground plane and power ground plane must meet only at a single point directly at the IC. 44 5) Connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close to the load as is practical. Chip Information TRANSISTOR COUNT: 8612 PROCESS: BiCMOS ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator LDOOUT LDOIN V+ DL2 GND 24 23 22 21 27 VDD FBLDO 28 25 DL1 29 26 BST1 LDOON 30 TOP VIEW LX1 31 20 BST2 DH1 32 19 LX2 PGOOD1 33 18 DH2 OUT1 34 17 PGOOD2 FB1 35 16 OUT2 CSN1 36 15 FB2 CSP1 37 14 CSN2 FBLANK 38 13 CSP2 ON2 39 12 OD ON1 40 11 REFIN1 9 10 REF 6 GATE ILIM2 5 VCC 8 4 TON 7 3 LSAT CC1 2 SKIP ILIM1 1 OVP/UVP MAX1541 MAX1540A/MAX1541 Pin Configurations (continued) THIN QFN A "+" SIGN WILL REPLACE THE FIRST PIN INDICATOR ON LEAD-FREE PACKAGES. ______________________________________________________________________________________ 45 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm 21-0140 46 ______________________________________________________________________________________ K 1 2 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm 21-0140 K 2 2 ______________________________________________________________________________________ 47 MAX1540A/MAX1541 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QFN THIN.EPS MAX1540A/MAX1541 Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator 48 ______________________________________________________________________________________ Dual Step-Down Controllers with Saturation Protection, Dynamic Output, and Linear Regulator Revision History Pages changed at Rev 3: 1, 10–15, 18, 20, 21, 22, 24, 34, 46–49 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 49 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX1540A/MAX1541 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)