NTHS5402T1 Power MOSFET N−Channel ChipFETE 4.9 Amps, 30 Volts Features • Low RDS(on) for Higher Efficiency • Miniature ChipFET Surface Mount Package http://onsemi.com 4.9 AMPS 30 VOLTS RDS(on) = 35 mW Applications • Power Management in Portable and Battery−Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards D MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol Steady State 5 secs Unit Drain−Source Voltage VDS 30 V Gate−Source Voltage VGS "20 V Continuous Drain Current (TJ = 150°C) (Note 1.) TA = 25°C TA = 85°C ID IDM Continuous Source Current (Diode Conduction) (Note 1.) IS Maximum Power Dissipation (Note 1.) TA = 25°C TA = 85°C PD Operating Junction and Storage Temperature Range A "6.7 "4.8 Pulsed Drain Current 2.1 S "4.9 "3.5 N−Channel MOSFET A "20 1.1 A W 2.5 1.3 TJ, Tstg G 1.3 0.7 −55 to +150 ChipFET CASE 1206A STYLE 1 °C 1. Surface Mounted on 1″ x 1″ FR4 Board. MARKING DIAGRAM PIN CONNECTIONS 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 S 5 4 G 4 A8 D 6 5 A8 = Specific Device Code ORDERING INFORMATION © Semiconductor Components Industries, LLC, 2005 February, 2005 − Rev. XXX 1 Device Package Shipping NTHS5402T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5402T1/D NTHS5402T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction−to−Ambient (Note 2.) t v 5 sec Steady State RthJA Maximum Junction−to−Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit °C/W °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = 250 µA 1.0 − − V Gate−Body Leakage IGSS VDS = 0 V, VGS = "20 V − − "100 nA Zero Gate Voltage Drain Current IDSS VDS = 24 V, VGS = 0 V − − 1.0 µA VDS = 24 V, VGS = 0 V, TJ = 85°C − − 5.0 ID(on) VDS w 5.0 V, VGS = 10 V 20 − − A rDS(on) ( ) VGS = 10 V, ID = 4.9 A − 0.030 0.035 Ω VGS = 4.5 V, ID = 3.9 A − 0.045 0.055 gfs VDS = 10 V, ID = 4.9 A − 15 − S VSD IS = 1.1 A, VGS = 0 V − 0.8 1.2 V − 13 20 nC − 1.3 − − 3.1 − − 10 15 − 10 15 − 25 40 − 10 15 − 30 60 Static Gate Threshold Voltage On−State Drain Current (Note 3.) Drain−Source On−State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) Dynamic (Note 4.) Total Gate Charge Qg VDS = 15 V V, VGS = 10 V V, ID = 4.9 A Gate−Source Charge Qgs Gate−Drain Charge Qgd Turn−On Delay Time td(on) Rise Time Turn−Off Delay Time tr td(off) Fall Time tf Source−Drain Reverse Recovery Time trr VDD = 15 V, RL = 15 Ω ID ^ 1.0 10A A, VGEN = 10 V, V RG = 6 Ω IF = 1.1 A, di/dt = 100 A/µs 2. Surface Mounted on 1″ x 1″ FR4 Board. 3. Pulse Test: Pulse Width v 300 µs, Duty Cycle v 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 ns NTHS5402T1 TYPICAL CHARACTERISTICS 20 20 4V 16 ID,Drain Current (A) ID,Drain Current (A) VGS = 10 thru 5 V 16 12 8 3V 12 8 TC125°C 4 4 0 0 25°C TC = −55°C 0 0.5 1.0 1.5 2.0 2.5 VDS, Drain−to−Source Voltage (V) 3.0 0 0.5 Figure 1. Output Characteristics C, Capacitance (pF) r DS(on),On−Resistance ( Ω ) 1000 0.06 VGS = 4.5 V 0.04 VGS = 10 V 0.02 2.5 3.0 3.5 4.0 Ciss 800 600 400 Coss 200 Crss 0 4 8 12 ID, Drain Current (A) 16 0 20 0 6 12 18 24 VDS, Drain−to−Source Voltage (V) Figure 3. On−Resistance vs. Drain Current 30 Figure 4. Capacitance 1.6 10 VDS = 15 V ID = 4.9 A 8 r DS(on),On−Resistance ( Ω ) (Normalized) VGS,Gate−to−Source Voltage (V) 2.0 1200 0.08 6 4 2 0 1.5 Figure 2. Transfer Characteristics 0.10 0 1.0 VGS, Gate−to−Source Voltage (V) 0 3 6 9 Qg, Total Gate Charge (nC) 12 1.4 1.2 1.0 0.8 0.6 −50 15 VGS = 10 V ID = 4.9 A Figure 5. Gate Charge −25 0 25 50 75 100 TJ, Junction Temperature (°C) Figure 6. On−Resistance vs. Junction Temperature http://onsemi.com 3 125 150 NTHS5402T1 TYPICAL CHARACTERISTICS 0.10 20 rDS(on),On−Resistance ( Ω ) I S,Source Current (A) TJ = 150°C 10 TJ = 25°C 1 0 0.2 0.4 0.6 0.8 1.0 VSD, Source−to−Drain Voltage (V) 0.08 ID = 4.9 A 0.06 0.04 0.02 0 1.2 0 Figure 7. Source−Drain Diode Forward Voltage 50 0.2 40 ID = 250 µA −0.0 Power (W) V GS (th),Varience (V) 10 Figure 8. On−Resistance vs. Gate−to−Source Voltage 0.4 −0.2 −0.4 30 20 10 −0.6 −0.8 −50 2 4 6 8 VGS, Gate−to−Source Voltage (V) −25 0 25 50 75 100 TJ, Temperature (°C) 125 150 0 10−3 Figure 9. Threshold Voltage 10−2 10 −1 1 Time (sec) 10 100 Figure 10. Single Pulse Power http://onsemi.com 4 600 NTHS5402T1 TYPICAL CHARACTERISTICS Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 Notes: 0.2 0.1 PDM t1 0.1 t1 1. Duty Cycle, D = t 2 2. Per Unit Base = RthJA = 80°C/W 3. TJM − TA = PDMZthJA(t) 4. Surface Mounted 0.05 0.02 Single Pulse 0.01 10−4 10−3 10−2 t2 10 −1 1 Square Wave Pulse Duration (sec) 10 100 600 Figure 11. Normalized Thermal Transient Impedance, Junction−to−Ambient Normalized Effective Transient Thermal Impedance 2 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10−4 10−3 10−2 10 −1 Square Wave Pulse Duration (sec) 1 Figure 12. Normalized Thermal Transient Impedance, Junction−to−Foot http://onsemi.com 5 10 NTHS5402T1 80 mm 80 mm 18 mm 25 mm 68 mm 26 mm 28 mm 26 mm Figure 13. 28 mm Figure 14. BASIC PAD PATTERNS confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 13. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 14 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the http://onsemi.com 6 NTHS5402T1 PACKAGE DIMENSIONS ChipFET CASE 1206A−03 ISSUE C A 8 7 M 6 K 5 S 1 L 5 6 7 8 4 3 2 1 B 2 3 G 4 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A−01 AND 1206A−02 OBSOLETE. NEW STANDARD IS 1206A−03. J DIM A B C D G J K L M S C 0.05 (0.002) STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. http://onsemi.com 7 MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 ° NOM 1.80 2.00 DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 ° NOM 0.072 0.080 NTHS5402T1 ChipFET is a trademark of Vishay Siliconix ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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