Dallas DS1044-6 4-in-1 high-speed silicon delay line Datasheet

DS1044
DS1044
4–in–1 High–Speed Silicon Delay Line
FEATURES
PIN ASSIGNMENT
• All–silicon timing circuit
IN1
1
14
VCC
NC
2
13
NC
IN2
3
12
OUT1
IN3
4
11
NC
IN4
5
10
OUT2
NC
6
9
OUT3
GND
7
8
OUT4
• Four independent buffered delays
• Initial delay tolerance ±1.5 ns
• Stable and precise over temperature and voltage
• Leading
and trailing edge precision preserves the
input symmetry
• Standard 14–pin DIP, 14–pin SOIC (150 mil)
DS1044 14–PIN DIP
DS1044R 14–PIN SOIC (150 MIL)
See Mech. Drawings
Section
• Vapor phase, IR and wave solderable
• Available in Tape and Reel
PIN DESCRIPTION
IN1–IN4
OUT1–OUT4
NC
VCC
GND
–
–
–
–
–
Input Signals
Output Signals
No Connection
+5 Volt Supply
Ground
DESCRIPTION
The DS1044 series is a 4–in–1 version of the low–
power, +5 Volt, high speed, DS1035.
The DS1044 series of delay lines have four independent
logic buffered delays in a single package. The device is
Dallas Semiconductor’s fastest 4–in–1 delay line. It is
available in a standard 14–pin DIP and 14–pin SOIC.
delay line solution. The DS1044’s nominal tolerance is
±1.5 ns and an additional tolerance over temperature
and voltage of ±1.0 ns for the faster delays. Each output
is capable of driving up to 10 LS loads.
Standard delay values are indicated in Table 1. Customers may contact Dallas Semiconductor at (972)
371–4348 for further information.
The device features precise leading and trailing edge
accuracies. It has the inherent reliability of an all–silicon
021798 1/6
DS1044
LOGIC DIAGRAM Figure 1
IN
OUT
TIME DELAY
ONE OF FOUR
PART NUMBER DELAY TABLE (tPLH, tPHL) Table 1
PART NUMBER
DELAY PER OUTPUT
(ns)
INITIAL TOLERANCE
TOLERANCE OVER
(temp and voltage)
DS1044–5
5
±1.5 ns
±1.0 ns
DS1044–6
6
±1.5 ns
±1.0 ns
DS1044–7
7
±1.5 ns
±1.0 ns
DS1044–8
8
±1.5 ns
±1.0 ns
DS1044–10
10
±1.5 ns
±1.0 ns
DS1044–12
12
±1.5 ns
±1.0 ns
DS1044–14
14
±1.5 ns
±1.5 ns
DS1044–18
18
±1.5 ns
±1.5 ns
DS1044–20
20
±1.5 ns
±1.5 ns
DS1044–25
25
±2.0 ns
±1.5 ns
NOTES:
1. Nominal conditions are +25°C and VCC=+5.0 volts.
2. Temperature range of 0°C to 70°C and voltage range of 4.75 volts to 5.25 volts.
3. Delay accuracy are for both leading and trailing edges.
021798 2/6
DS1044
TEST SETUP DESCRIPTION
Figure 2 illustrates the hardware configuration used for
measuring the timing parameters of the DS1044. The
input waveform is produced by a precision pulse generator under software control. Time delays are measured
by a time interval counter (20 ps resolution) connected
to the output. The DS1044 output taps are selected and
connected to the interval counter by a VHF switch control unit. All measurements are fully automated with
each instrument controlled by the computer over an
IEEE 488 bus.
DS1044 TEST CIRCUIT Figure 2
PULSE
GENERATOR
START
4
INPUTS
TIME INTERVAL
COUNTER
50Ω
STOP
VHF
SWITCH
CONTROL
UNIT
UNIT UNDER
TEST
OUT
50Ω
OUTPUTS 1–4
021798 3/6
DS1044
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
Short Circuit Output Current
–1.0V to +7.0V
0°C to 70°C
–55°C to +125°C
260°C for 10 seconds
50 mA for 1 second
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
(0°C to 70°C; VCC=+5V ± 5%)
DC ELECTRICAL CHARACTERISTICS
TEST
CONDITION
PARAMETER
SYMBOL
Supply Voltage
VCC
Active Current
ICC
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
–1.0
Input Leakage
MIN
TYP
MAX
4.75
5.00
5.25
V
45
mA
2.2
VCC+0.5
V
–0.5
0.8
V
1.0
µA
–1.0
mA
VCC=5.25V
Period=1µs
IL
0V<VI<VCC
High Level Output Current
IOH
VCC=4.75V
VOH=4V
Low Level Output Current
IOL
VCC=4.75V
VOL=0.5V
12
mA
(+25°C; VCC=5V ± 5%)
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Period
Input Pulse Width
Input–to–Tap Output Delay
Output Rise or Fall Time
Power–up Time
SYMBOL
MIN
UNITS
NOTES
tPERIOD
2 (tWI)
TYP
ns
3
tWI
100% of
Tap Delay
ns
3
tPLH, tPHL
Table 1
tOR, tOF
2.0
tPU
MAX
ns
2.5
ns
100
ms
MAX
UNITS
10
pF
CAPACITANCE
PARAMETER
Input Capacitance
021798 4/6
UNITS
(tA=25°C)
SYMBOL
CIN
MIN
TYP
NOTES
DS1044
TEST CONDITIONS
Ambient Temperature: 25°C ± 3°C
Supply Voltage (VCC): 5.0V ± 0.1V
Input Pulse:
High: 3.0V ± 0.1V
Low: 0.0V ± 0.1V
Source Impedance: 50Ω Max.
Rise and Fall Time: 3.0 ns Max. – Measured between 0.6V and 2.4V.
Pulse Width: 500 ns
Pulse Period: 1 µs
Output Load Capacitance: 15 pF
Output: Each output is loaded with the equivalent of one 74F04 input gate.
Data is measured at the 1.5V level on the rising and falling edges.
Note: The above conditions are for test only and do not restrict the devices under other data sheet conditions.
TIMING DIAGRAM
PERIOD
tFALL
tRISE
80%
1.5V
1.5V
1.5V
20%
IN
tWI
tWI
tPHL
tPLH
1.5V
1.5V
OUT
NOTES:
1. All voltages are referenced to ground.
2. @ VCC=5 volts and 25°C, delay accuracy on both the rising and falling edges within tolerances given in
Table 1.
3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive
with respect to de–coupling, layout, etc.
021798 5/6
DS1044
TERMINOLOGY
Period: The time elapsed between the leading edge of
the first pulse and the leading edge of the following
pulse.
tWI (Pulse Width): The elapsed time on the pulse
between the 1.5 volt point on the leading edge and the
1.5 volt point on the trailing edge or the 1.5 volt point on
the trailing edge and the 1.5 volt point on the leading
edge.
tRISE (Input Rise Time): The elapsed time between the
20% and the 80% point on the leading edge of the input
pulse.
021798 6/6
tFALL (Input Fall Time): The elapsed time between the
80% and the 20% point on the trailing edge on the input
pulse.
tPLH (Time Delay, Rising): The elapsed time between
the 1.5 volt point on the leading edge of the input pulse
and the 1.5 volt point on the leading edge of the output
pulse.
tPHL (Time Delay, Falling): The elapsed time between
the 1.5 volt point on the falling edge of the input pulse
and the 1.5 volt point on the falling edge of the output
pulse.
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