Micro Linear ML2008IQ μp compatible logarithmic gain/attenuator Datasheet

March 1997
ML2008*, ML2009**
µP Compatible Logarithmic Gain/Attenuator
GENERAL DESCRIPTION
FEATURES
The ML2008 and ML2009 are digitally controlled
logarithmic gain/attenuators with a range of –24 to +24dB
in 0.1dB steps.
■
Easy interface to microprocessors is provided by an input
latch and control signals consisting of chip select and
write.
The interface for gain setting of the ML2008 is by an 8-bit
data word, while the ML2009 is designed to interface to a
16-bit data bus with a single write operation by hardwiring the gain/attenuation pin or LSB pin. The ML2008
can be power downed by the microprocessor utilizing a
bit in the second write operation.
■
■
■
■
■
■
■
Low noise
0dBrnc max with +24dB gain
Low harmonic distortion
–60dB max
Gain range
–24 to +24dB
Resolution
0.1dB steps
Flat frequency response
±0.05dB from 0.3-4kHz
±0.10dB from 0.1-20kHz
Low supply current
4mA max from ±5V supplies
TTL/CMOS compatible digital interface
ML2008 is designed to interface to an 8-bit data bus;
ML2009 to 16-bit data bus
Absolute gain accuracy is 0.05dB max over supply
tolerance of ±10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for
a wide variety of applications in telecom, audio, sonar or
general purpose function generation.
* This Part Is End Of Life As Of August 1, 2000
** This Part Is Obsolete
BLOCK DIAGRAM
ML2008
VCC
VSS
+5
–5
GND
ML2009*
AGND
VIN
VCC
VSS
+5
–5
AGND
VIN
+
+
+
FINE
–
COARSE
–
RESISTORS/
SWITCHES
+
BUFFER
–
VOUT
RESISTORS/
SWITCHES
VOUT
RESISTORS/
SWITCHES
16
DECODERS
16
DECODERS
9
1
REGISTER 0
+
BUFFER
–
FINE
–
16
8
+
COARSE
–
RESISTORS/
SWITCHES
16
WR
CS
A0
GND
PDN
1
REGISTER 1
WR
CS
REGISTER 0
9
D0–D8
8
D1–D8
1
ML2008, ML2009
PIN CONFIGURATION
ML2008
18-Pin DIP (P18)
ML2009*
18-Pin DIP (P18)
D7
1
18
D8
D6
2
17
VCC
D7
1
18
D8
D6
2
17
D5
3
16
VOUT
VCC
D5
3
16
D4
4
15
VSS
VOUT
D4
4
15
WR
5
14
AGND
VSS
WR
5
14
D3
6
13
VIN
AGND
D3
6
13
D2
7
12
VIN
NC
D2
7
12
D1
8
11
NC
CS
D1
8
11
GND
9
10
CS
A0
GND
9
10
D0
TOP VIEW
TOP VIEW
D4
19
18
VCC
VCC
20
D8
D8
1
D7
D7
2
D6
D6
3
4
20-Pin PLCC (Q20)
D5
D5
20-Pin PLCC (Q20)
3
2
1
20
19
VOUT
D4
4
18
VOUT
5
17
VSS
16
AGND
D3
7
15
NC
D3
7
15
NC
D2
8
14
NC
D2
8
14
NC
12
13
9
10 11
12
13
D0
10 11
A0
9
VIN
6
CS
WR
D1
AGND
GND
16
VIN
VSS
6
CS
17
WR
GND
5
NC
D1
NC
TOP VIEW
TOP VIEW
PIN DESCRIPTION
2
NAME
FUNCTION
NAME
FUNCTION
VSS
Negative supply. –5Volts ±10%
D3
Data bit, F3
VCC
Positive supply. 5Volts ±10%
D2
Data bit, PDN, F2 ML2008; F2 ML2009
GND
Digital ground. 0Volts. All digital
inputs are referenced to this ground.
D1
Data bit, F0, F1 ML2008; F1 ML2009
D0
Data bit, F0 ML2009 only
AGND
Analog ground. 0Volts. Analog input
and output are referenced to this
ground.
WR
VIN
Analog input
Write enable. This input latches the
data bits into the registers on rising
edges of WR.
VOUT
Analog output
CS
D8
Data bit, ATTEN/GAIN
Chip select. This input selects the
device by only allowing the WR signal
to latch in data when CS is low.
D7
Data bit, C3
A0
(ML2008 only)
D6
Data bit, C2
Address select. This input determines
which data word is being written into
the registers.
D5
Data bit, C1
D4
Data bit, C0
ML2008, ML2009
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
(Note 1)
Supply Voltage
VCC .................................................................... +6.5V
VSS ......................................................................–6.5V
AGND with Respect to GND....................... V CC to VSS
Analog Inputs and Outputs ..... VSS –0.3V to VCC +0.3V
Digital Inputs and Outputs ... GND –0.3V to VCC +0.3V
Input Current Per Pin ........................................ ±25mA
Power Dissipation ........................................... 750mW
Storage Temperature Range ............... –65°C to +150°C
Lead Temperature (Soldering 10 sec.) ................. 300°C
Temperature Range (Note 2)
ML2008CX, ML2009CX .......................... 0°C to +70°C
ML2008IX, ML2009IX ......................... –40°C to +85°C
Supply Voltage
VCC ................................................................ 4V to 6V
VSS ............................................................. –4V to –6V
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = TMIN to TMAX, VCC = 5V ±10%, VSS = –5V ±10%, Data Word: D8 (ATTEN/GAIN) = 1,
Other Bits = 0, (0dB Ideal Gain), CL = 100pF, R L = 600Ω, dBm measurements use 600Ω as reference load, digital timing
measured at 1.4V.
SYMBOL
PARAMETER
NOTES
CONDITIONS
MIN
TYP
NOTE 3
MAX
UNITS
Analog
AG
Absolute Gain Accuracy
4
VIN = 8dBm, 1kHz
–0.05
+0.05
dB
RG
Relative Gain Accuracy
4
100000001
000000000
000000001
All other gain settings
All values referenced to 100000000
gain when D8 (ATTEN/GAIN) = 1,
VIN = 8dBm when D8 (ATTEN/GAIN) = 0,
VIN = (8dBm – Ideal Gain) in dB
–0.05
–0.05
–0.05
–0.1
+0.05
+0.05
+0.05
+0.1
dB
dB
dB
dB
FR
Frequency Response
4
300-4000Hz
100-20,000Hz
Relative to 1kHz
–0.05
–0.1
+0.05
+0.1
dB
dB
VOS
Output Offset Voltage
4
VIN = 0, +24dB gain
±100
mV
ICN
Idle Channel Noise
4
5
VIN = 0, +24dB, C msg weighted
VIN = 0, +24dB, 1kHz
0
900
dBrnc
nv/√Hz
HD
Harmonic Distortion
4
VIN = 8dBm, 1kHz
Measure 2nd, 3rd, harmonic relative
to fundamental
–60
dB
SD
Signal to Distortion
4
VIN = 8dBm, 1kHz
C msg weighted
PSRR
Power Supply Rejection
4
200mVP-P, 1kHz sine, VIN = 0
on VCC
on VSS
–6
450
+60
dB
–60
–60
–40
–40
dB
dB
ZIN
Input Impedance, VIN
4
1
Meg
VINR
Input Voltage Range
4
±3.0
V
VOSW
Output Voltage Swing
4
±3.0
V
3
ML2008, ML2009
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
NOTES
CONDITIONS
MIN
TYP
NOTE 3
MAX
UNITS
VIL
Digital Input Low Voltage
4
VIH
Digital Input High Voltage
4
IIN
Input Current, Low
4
VIH = GND
–10
µA
IIN
Input Current, High
4
VIH = VCC
10
µA
ICC
VCC Supply Current
4
No output load, VIL = GND,
VIH = VCC, VIN = 0
4
mA
ISS
VSS Supply Current
4
No output load, VIL = GND,
VIH = VCC, VIN = 0
–4
mA
ICCP
VCC Supply Current, ML2008
Powerdown Mode Only
4
No output load, VIL = GND,
VIH = VCC
0.5
mA
ISSP
VSS Supply Current, ML2008
Powerdown Mode Only
4
No output load, VIL = GND,
VIH = VCC
–0.1
mA
Digital and DC
0.8
2.0
V
V
AC Characteristics
tSET
VOUT Settling Time
4
VIN = 0.185V. Change gain from –24
to +24dB. Measure from WR rising
edge to when VOUT settles to within
0.05dB of final value.
20
µs
tSTEP
VOUT Step Response
4
Gain = +24dB. VIN = –3V to +3V step.
Measure from VIN = –3V to when VOUT
settles to within 0.05dB of final value.
20
µs
tDS
Data Setup Time
4
50
ns
tDH
Data Hold Time
4
50
ns
tAS
A0 Setup Time
4
0
ns
tAH
A0 Hold Time
4
0
ns
tCSS
CS* Setup Time
4
0
ns
tCSH
CS* Hold Time
4
0
ns
tPW
WR* Pulse Width
4
50
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
4
Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with
respect to ground.
0°C to +70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Typicals are parametric norm at 25°C.
Parameter guaranteed and 100% production tested.
Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
ML2008, ML2009
TIMING DIAGRAM
DATA
VALID
D0-D8
tDH
tDS
tPW
WR
tAH
tAS
A0
tCSS
tCSH
CS
TYPICAL PERFORMANCE CURVES
0
–0.5
–.10
0
ATTEN: VIN = 0.5VRMS
GAIN: VIN = 0.5VRMS/GAIN SETTING
–0.5
GAIN = +24dB
GAIN = +24dB
–.15
–.15
GAIN = +18dB
–.20
AMPLITUDE (dB)
AMPLITUDE (dB)
ATTEN: VIN = 2VRMS
GAIN: VIN = 2VRMS/GAIN SETTING
–.10
GAIN = +12dB
–.25
GAIN = +0, –24dB
–.30
–.35
–.40
GAIN = 0dB
–.20
GAIN = –24dB
–.25
–.30
–.35
–.40
–.45
–.50
100
–.45
1K
10K
100K
–.50
100
FREQUENCY (Hz)
1K
10K
100K
FREQUENCY (Hz)
Figure 2. Amplitude vs Frequency
(VIN/VOUT = 0.5VRMS)
Figure 3. Amplitude vs Frequency
(VIN/VOUT = 2VRMS)
–2
VIN = 0
1.8
–3
1.6
CMSG OUTPUT (NOISE) (dBrnc)
OUTPUT NOISE VOLTAGE (µV/√Hz)
2
GAIN = +24dB
1.4
GAIN = +12dB
1.2
GAIN = –24dB
1
0.8
0.6
0.4
–4
–5
–6
–7
–8
–9
0.2
0
–10
10
100
1K
FREQUENCY (Hz)
Figure 4. Output Noise Voltage vs Frequency
10K
–24
–18
–12
–6
0
6
12
18
24
GAIN SETTING (dB)
Figure 5. CMSG Output Noise vs Gain Setting
5
ML2008, ML2009
TYPICAL PERFORMANCE CURVES (Continued)
100
.08
.06
80
GAIN ERROR (dB)
CMSG S/N (DB)
90
0.1
ATTEN: VIN = 8dBm
GAIN: VIN = 8dBm/GAIN SETTING
1kHZ
70
60
.04
.02
0
–.02
–.04
–.06
50
–.08
40
–24
–18
–12
–6
0
6
12
18
–1.0
–24
24
–18
–12
GAIN SETTING (dB)
–6
0
6
12
18
24
GAIN SETTING (dB)
Figure 7. Gain Error vs Gain Setting
Figure 6. CMSG S/N vs Gain Setting
80
80
VIN = 1kHz
70
VIN = 20kHz
60
VIN = 20kHz
60
S/N + D (dB)
S/N + D (dB)
VIN = 1kHz
70
50
40
VIN = 50kHz
50
40
30
VIN = 50kHz
20 ATTEN: V = 2V
IN
RMS
GAIN: VIN = 2VRMS/GAIN SETTING
10
–24
–18
–12
–6
0
6
12
30
18
24
ATTEN: VIN = 0.5VRMS
GAIN: VIN = 0.5VRMS/GAIN SETTING
20
–24
–18
Figure 8. S/N +D vs Gain Setting (VIN/V OUT = 2VRMS)
–12
–6
0
6
12
18
24
GAIN SETTING (dB)
GAIN SETTING (dB)
Figure 9. S/N +D vs Gain Setting (VIN/VOUT = 0.5VRMS)
1.0 FUNCTIONAL DESCRIPTION
The ML2008, ML2009 consists of a coarse gain stage, a
fine gain stage, an output buffer, and a µP compatible
parallel digital interface.
1.1 Gain Stages
The analog input, VIN, goes directly into the op amp input
in the coarse gain stage. The coarse gain stage has a gain
range of 0 to 22.5dB in 1.5dB steps.
The fine gain stage is cascaded onto the coarse section.
The fine gain stage has a gain range of 0 to 1.5dB in 0.1dB
steps.
Both stages can be programmed for either gain or
attenuation, thus doubling the effective gain range.
6
The logarithmic steps in each gains stage are generated by
placing the input signal across a resistor string of 16 series
resistors. Analog switches allow the voltage to be tapped
from the resistor string at 16 points. The resistors are sized
such that each output voltage is at the proper logarithmic
ratio relative to the input signal at the top of the string.
Attenuation is implemented by using the resistor string as
a simple voltage divider, and gain is implemented by
using the resistor string as a feedback resistor around an
internal op amp.
1.2 Gain Settings
Since the coarse and fine gain stages are cascaded, their
gains can be summed logarithmically. Thus, any gain from
–24dB to +24dB in 0.1dB steps can be obtained by
combining the coarse and fine gain setting to yield the
ML2008, ML2009
desired gain setting. The relationship between the register
0 and 1 bits and the corresponding analog gain values is
shown in Tables 1 and 2. Note that C3-C0 select the
coarse gain, F3-F0 select the fine gain, and ATTEN/GAIN
selects either gain or attenuation.
1.3 Output Buffer
The final analog stage is the output buffer. This amplifier
has internal gain of 1 and is designed to drive 600Ω,
100pF loads. Thus, it is suitable for driving a telephone
hybrid circuit directly without any external amplifier.
1.4 Power Supplies
The digital section is powered between VCC and GND,
or 5V. The analog section is powered between V CC and
VSS and uses AGND as the reference point, or ±5V.
GND and AGND are totally isolated inside the device to
minimize coupling from the digital section into the analog
section. Typically this is less than 100µV. However, AGND
and GND should be tied together physically near the
device and ideally close to the common power supply
ground connection.
Typically, the power supply rejection of VCC and VSS
to the analog output is greater than –60dB at 1KHz. If
decoupling of the power supplies is still necessary in a
system, VCC and VSS should be decoupled with respect
to AGND.
Table 1. Fine Gain Settings (C3 – C0 = 0)
F3
F2
F1
F0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Table 2. Coarse Gain Settings (F3 – F0 = 0)
Ideal Gain (dB)
ATTEN/GAIN = 1 ATTEN/GAIN = 0
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
C3
C2
C1
C0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Ideal Gain (dB)
ATTEN/GAIN = 1 ATTEN/GAIN = 0
0.0
–1.5
–3.0
–4.5
–6.0
–7.5
–9.0
–10.5
–12.0
–13.5
–15.0
–16.5
–18.0
–19.5
–21.0
–22.5
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
16.5
18.0
19.5
21.0
22.5
2.0 DIGITAL INTERFACE
The architecture of the digital section is shown in the
preceding black diagram.
The structure of the data registers or latches is shown in
Figures 10 and 11 for the ML2008 and ML2009,
respectively. The registers control the attenuation/gain
setting bits and with the ML2008 the power down bit.
Tables 1 and 2 describe how the data word programs the
gain.
The difference between the ML2008 and ML2009 is in the
register structure. The ML2008 is an 8-bit data bus
version. This device has one 8-bit register and one 2-bit
register to store the 9 gain setting bits and 1 powerdown
bit. Two write operations are necessary to program the full
10 data bits from eight external data pins. The address pin
A0 controls which register is being written into. The
powerdown bit, PDN, causes the device to be placed in
powerdown. When PDN = 1, the device is powered
down. In this state, the power consumption is reduced by
removing power from the analog section and forcing the
analog output, VOUT, to a high impedance state. While the
device is in powerdown, the digital section is still
functional and the current data word remains stored in the
registers. When PDN = 0, device is in normal operation.
The ML2009 is a 9-bit data bus version. This device has
one 9-bit register to store the 9 gain setting bits. The full 9
data bits can be programmed with one write operation
from nine external data pins.
The internal registers or latches are edge triggered. The
data is transferred from the external pins to the register
output on the rising edge of WR. The address pin, A0,
controls which register the data will be written into as
shown in Figures 1 and 2. The CS control signal selects
the device by allowing the WR signal to latch in the data
only when CS is low. When CS is high, WR is inhibited
from latching in new data into the registers.
7
ML2008, ML2009
A0 = 0
D8
D7
D6
D5
D4
D3
D2
D1
BIT
ATTEN/GAIN
C3
C2
C1
C0
F3
F2
F1
REG 0
PDN
F0
REG 1
A0 = 1
Figure 10. ML2008 Register Structure
D8
ATTEN/GAIN
D7
D6
D5
D4
D3
D2
D1 D0
BIT
C3
C2
C1
C0
F3
F2
F1
REG 0
Figure 11. ML2009 Register Structure
ML2008
VIN
ML2009
VIN
VOUT
CS WR
A0
F0
VOUT
D1-D8 D0
CS WR
D1-D8
+5V
µP
µP
8
8
Figure 12. Typical 8-Bit µP Interface, Double Write
Figure 13. Typical 8-Bit µP Interface, Single Write
ML2009
ML2009
VIN
VOUT
D0-D8 WR CS
CS WR
D0-D8
VIN
ML2233
12-BIT
+ SIGN
A/D
µP
OR
DSP
µP
9
Figure 14. Typical 16-Bit µP Interface
8
Figure 15. AGC for DSP or Modem Front End
ML2008, ML2009
ML2008
+5V
D1-D8 CS A0
2.5V
REF
ML2008
VIN
VIN
ML2009
D1-D8 CS A0
A0
VOUT
D0-D8
WR
µP
–5V
ADDRESS
Figure 16. Operation as Logarithmic D/A Converter
D
E CS1
C
O CS2
D
E
R
Figure 17. Controlling Multiple Gain/Attenuators
9
ML2008, ML2009
PHYSICAL DIMENSIONS inches (millimeters)
Package: Q20
20-Pin PLCC
0.385 - 0.395
(8.89 - 10.03)
0.042 - 0.056
(1.07 - 1.42)
0.350 - 0.356
(8.89 - 9.04)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
1
0.042 - 0.048
(1.07 - 1.22)
6
PIN 1 ID
16
0.350 - 0.356
(8.89 - 9.04)
0.385 - 0.395
(8.89 - 10.03)
0.200 BSC
(5.08 BSC)
0.290 - 0.330
(7.36 - 8.38)
11
0.009 - 0.011
(0.23 - 0.28)
0.050 BSC
(1.27 BSC)
0.026 - 0.032
(0.66 - 0.81)
0.165 - 0.180
(4.19 - 4.57)
0.146 - 0.156
(3.71 - 3.96)
0.100 - 0.110
(2.54 - 2.79)
0.013 - 0.021
(0.33 - 0.53)
SEATING PLANE
10
ML2008, ML2009
PHYSICAL DIMENSIONS inches (millimeters)
Package: P18
18-Pin PDIP
0.890 - 0.910
(22.60 - 23.12)
18
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.26)
PIN 1 ID
1
0.045 MIN
(1.14 MIN)
(4 PLACES)
0.050 - 0.065
(1.27 - 1.65)
0.100 BSC
(2.54 BSC)
0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.016 - 0.022
(0.40 - 0.56)
SEATING PLANE
0.008 - 0.012
(0.20 - 0.31)
0º - 15º
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE
ML2008IP
ML2008IQ
–40°C to 85°C
–40°C to 85°C
Molded PDIP (P18) (EOL)
Molded PLCC (Q20) (EOL)
ML2008CP
ML2008CQ
0°C to +70°C
0°C to +70°C
Molded PDIP (P18) (EOL)
Molded PLCC (Q20) (EOL)
ML2009IP
ML2009IQ
–40°C to 85°C
–40°C to 85°C
Molded PDIP (P18) (OBS)
Molded PLCC (Q20) (OBS)
ML2009CP
ML2009CQ
0°C to +70°C
0°C to +70°C
Molded PDIP (P18) (OBS)
Molded PLCC (Q20) (OBS)
© Micro Linear 1997
is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
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DS2008_09-01