N Comlinear CLC949 Very Low-Power, 12-Bit, 20MSPS Monolithic A/D Convertter General Description Features The Comlinear CLC949 is a 12-bit analog-to-digital converter subsystem including 12-bit quantizer, sample-and-hold amplifier, and internal reference. The CLC949 has been optimized for low power operation with high dynamic range. The CLC949 has a unique feature which allows the user to adjust internal bias levels in the converter which results in a trade-off between power dissipation and maximum conversion rate. With bias set for 220mW power dissipation the converter operates at 20MSPS. Under these conditions, dynamic performance with a 9.9MHz analog input is typically 68dB SNR and 72dBc SFDR. When bias is set for only 65mW power dissipation the converter maintains excellent performance at 5MSPS. With a 2.4MHz analog input signal the SNR is 70dB and SFDR is 78dBc. This excellent dynamic performance in the frequency domain without high power requirements make the part a strong performer for communications and radar applications. The low input noise of the CLC949, its 0.5LSB differential linearity error specification, fast settling, and low power dissipation also lead to excellent performance in imaging systems. All parts are thoroughly tested to insure that guaranteed specifications are met. ■ The CLC949 incorporates an input sample-and-hold amplifier followed by a quantizer which uses a pipelined architecture to minimize comparator count and the associated power dissipation penalty. An on-board voltage reference is provided. Analog input signals, conversion clock, and a single supply are all that are required for CLC949 operation. ■ For applications requiring high temperature operation and very low distortion with high frequency input signals, use of an external sample-and-hold amplifier may enhance performance by reducing the slew rates that the CLC949 sees during its sampling period (just after the falling edge of CLK). The CLC949 is fabricated in a 0.9µm CMOS technology. The CLC949ACQ is specified over the commercial temperature range of 0°C to +70°C and the CLC949AJQ is specified over the industrial range of -40°C to +85°C. Both are packaged in a 44-pin Plastic Leaded Chip Carrier (PLCC). © 1996 National Semiconductor Corporation Printed in the U.S.A. ■ ■ Applications ■ ■ ■ ■ ■ ■ ■ CCD imaging IR imaging FLIR processing Medical imaging High definition video Instrumentation Radar processing Digital communications SFDR (dBc) SNR (dB), SFDR (dBc) Note that the reason for this degradation is the reduced ability of the CLC949 to handle high slew rates at high temperatures. In applications such as CCD imaging systems, where the slew rate at the A/D sampling instant is very low, this degradation will not be nearly so pronounced. ■ Power Dissipation vs. Conversion Rate 200 150 Power (mW) The CLC949 exhibits very stable performance over the commercial and industrial temperature ranges. Most parameters shift very little as the ambient temperature changes from -40°C to 85°C. An exception to this rule is the dynamic performance of the converter. As the temperature is increased, the distortion increases, especially at higher input frequencies. This can be seen in the plot on page 3. For input frequencies below 7MHz, there is relatively little variation in distortion as the temperature is changed, but at higher input frequencies, it is apparent that the performance degrades as the temperature is increased. ■ Very low/programmable power 0.07W @ 5MSPS 0.22W @ 20MSPS 0.40W @ 30MSPS Single supply operation (+5V) 0.5 LSB differential linearity error Wide dynamic range 72dBc spurious-free dynamic range 68dB signal-to-noise ratio No missing codes Comlinear CLC949 Very Low-Power, 12-Bit, 20MSPS Monolithic Converter August 1996 100 50 0 0 5 10 15 20 Sample Rate (MSPS) http://www.national.com CLC949 Electrical Characteristics (+VDD = + 5V, Medium Bias (200µA): unless specified) PARAMETERS Case Temperature CONDITIONS DYNAMIC CHARACTERISTICS overvoltage recovery VIN = 1.5FS effective aperture delay aperture jitter slew rate settling time NOISE and DISTORTION (20MSPS) Signal-to-Noise Ratio (no harmonics) 4.985MHz; FS 9.663MHz; FS Spurious-Free Dynamic Range 4.985MHz; FS -1dB 9.663MHz; FS -1dB Intermodulation Distortion f1 = 5.58MHz @ FS -7dB; f2 = 5.70MHz @ FS -7dB 3dB bandwidth (full power) TYP MIN/MAX RATINGS +25˚C 0 to 70˚C -40 to 85˚C UNITS SYMBOL 15 3.0 7.0 400 12 25 6.2 15 25 6.2 15 25 6.2 15 ns ns ps(rms) V/µS ns OR TA AJ SR ST 68 68 66 66 66 66 66 66 dB dB SNR2 SNR3 72 72 63 58 55 dBc dBc SFDR2 SFDR3 dBc MHz IMD BW -70 100 NOISE and DISTORTION (5MSPS, low bias) Signal-to-Noise Ratio (no harmonics) 2.4MHz; FS Spurious-Free Dynamic Range 2.4MHz; FS -1dB 70 68 68 67 dB SNR1 78 66 66 64 dBc SFDR1 NOISE and DISTORTION (25.6MSPS, high bias) Signal-to-Noise Ratio (no harmonics) 9.894MHz; FS Spurious-Free Dynamic Range 9.894MHz; FS-1dB 67 63 63 63 dB SNR4 67 59 53 48 dBc SFDR4 0.5 1.2 60 0 5.0 15 1.0 1.0 3.5 1.0 3.5 1.0 3.5 0 25 0 25 0 25 5.0 5.0 5.0 LSB LSB dB codes mV µV/°C %FS DNL INL CMRR MC VIO DVIO GE dB dB PSRA PSRD 3.24-3.26 1.24-1.26 1.98-2.02 V V V VREFP VREFN VDIFF VCM VDM IBN CIN DC ACCURACY and PERFORMANCE differential non-linearity integral non-linearity common mode rejection ratio missing codes mid-scale offset temperature coefficient gain error power supply rejection Vdda Vddd dc; FS dc; FS dc dc dc 55 50 VOLTAGE REFERENCE CHARACTERISTICS positive reference voltage (internal) negative reference voltage (internal) differential reference voltage (Vrefp - Vrefn) 3.25 1.25 2.0 ANALOG INPUT PERFORMANCE common mode range differential range analog input bias current analog input capacitance 2-3 ±2 ±0.1 5.0 ±1.0 10 ±1.0 10 ±1.0 10 V V µA pF logic LOW logic HIGH logic LOW logic HIGH ±0.1 ±0.1 1 4.0 ±1.0 ±1.0 1 4.0 ±1.0 ±1.0 1 4.0 ±1.0 ±1.0 V V µA µA VIL VIH IIL IIH logic LOW logic HIGH 0.25 4.8 0.5 4.5 0.5 4.5 0.5 4.5 V V VOL VOH 30 10 7.0 6.5 30 10 4.5 6.5 30 10 4.5 6.5 30 10 4.5 6.5 MSPS KSPS ns clocks CR CRM THLD 44 220 65 400 60 300 60 300 60 300 mA mW mW mW IDD PDM PDL PDH DIGITAL INPUTS CMOS input voltage CMOS input current DIGITAL OUTPUTS CMOS output voltage TIMING maximum conversion rate minimum conversion rate data hold time pipeline delay POWER REQUIREMENTS supply current (+Vdd) power dissipation power dissipation (low bias) power dissipation (high bias) 20MSPS 5MSPS 30MSPS 3.24-3.26 1.24-1.26 1.98-2.02 3.24-3.26 1.24-1.26 1.98-2.02 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. http://www.national.com 2 CLC949 Typical Performance Characteristics (+VDD = + 5V, Med Bias, Fs = 20MSPS: unless specified) Output Spectrum 9MHz -20 -20 -20 -40 -60 -80 Output Level (dBFS) 0 -40 -60 -80 -100 -100 0 2 6 4 8 2 8 10 0 SNR 40 20 60 SFDR SNR 40 20 -20 0 -10 SFDR SNR 40 20 -40 -20 -30 0 -10 -50 10 Medium Bias 70 SFDR (dBc) SNR (dB) High Bias SNR (dB) Low Bias 50 40 50 Medium Bias Low Bias 60 50 Fin = 5MHz FS = 20MHz Fin = 5MHz 30 0 40 0.1 100M 1.0 100 10 0.1 1.0 Sample Rate (MSPS) Input Frequency (MHz) Two Tone Intermodulation Distortion 100 10 Sample Rate (MSPS) Integral Non-Linearity 0 10 High Bias 60 60 0 -10 80 SFDR (dBc) 70 10M -20 -30 SFDR vs. Sample Rate vs. Bias 70 1M -40 Input Amplitude (dBFS) SNR vs. Sample Rate vs. Bias SNR & SFDR vs. Input Frequency 100k 60 Input Amplitude (dBFS) Input Amplitude (dBFS) 80 10 0 -50 10 8 SNR & SFDR vs. Input Amplitude 9MHz 0 0 6 4 80 SNR (dB) & SFDR (dBc) SFDR -30 2 Frequency (MHz) 80 SNR (dB) & SFDR (dBc) SNR (dB) & SFDR (dBc) 6 4 SNR & SFDR vs. Input Amplitude 5MHz SNR & SFDR vs. Input Amplitude 1MHz -40 -80 Frequency (MHz) 80 -50 -60 -120 0 10 Frequency (MHz) 60 -40 -100 -120 -120 SNR (dB), SFDR (dBc) Output Spectrum 15MHz 0 Output Level (dBFS) Output Level (dBFS) Output Spectrum 1MHz 0 Differential Non-Linearity 2.5 1.5 1 1.5 -60 -80 1 DNL (LSBs) -40 INL (LSBs) Output Level (dBFS) 2 -20 0.5 0 -0.5 -1 -1.5 -100 0.5 0 -0.5 -1 -2 -2.5 -120 0 2 6 4 8 -1.5 0 10 Frequency (MHz) 1000 2000 3000 4000 0 3000 2000 4000 Output Code SFDR vs. Input Frequency Pulse Settling Response 4000 I/O Timing (Convert CLK & Bit Skew) ) 80 76 2000 1000 ( -20°C 300 0°C 72 20°C 200 68 60°C 100 80°C 60 0 50 100 Time (ns) 150 200 Output Data Convert 40°C 64 0 400 p 3000 SFDR (dBc) ADC Output Code 1000 Output Code 0 1 10 Input Frequency (MHz) 3 100 0 4 8 12 16 20 Time (ns) http://www.national.com Recommended Operating Conditions supply voltage (VDD) differential voltage between any two GND’s analog input voltage range (full scale) digital input voltage range operating temperature range clock pulse-width high (Cpwh) Absolute Maximum Ratings* -0.5V to +7V supply voltage (VDD) differential voltage between any two GND’s 200mV analog input voltage range -0.5V to +VDD digital input voltage range -0.5V to +VDD output short circuit duration (one pin to gnd) infinite junction temperature +175°C storage temperature range -65°C to +150°C lead solder duration (+300°C) 10 sec +5V ± 5% <10mV 1.25 – 3.25V 0 to VDD 0°C to 70°C > 25ns *NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. will all be tied together. For more detailed discussion, please refer to the paragraph on power and grounds in the applications section of the databook. BC1 CLK NC VDDD VDDD VDDD VDDA VDDA VDDA VREFPO VREFNO Pinout & Pin Description and Usage 6 5 4 3 2 1 44 43 42 41 40 VREFMO 7 39 BCO 38 D12(LSB) TOP VIEW VREFP 8 VREFN 9 Clock (CLK) The CLK accepts a CMOS clock input. Samples are taken on the falling edges of the CLK and data emerges 6 1/2 clock cycles later, on to the rising edge of the CLK. 37 D11 36 D10 VREFPC 10 VREFNC 11 35 D9 44-Pin PLCC NC 12 34 D8 BIASC 13 33 D7 32 D6 GNDA 14 VINP 15 Output Data (D1-D12, MSBINV, OE\) The data emerges from the CLC949 as CMOS level digital data on D1(MSB) through D12(LSB). The outputs can be put into a high impedance state by bringing OE\ high. There is an internal pulldown resistor so that if this input is left open, the output data is enabled. MSBINV will invert the MSB of the output data. With MSBINV in the high state, the output data is two’s complement, when low, the output data format is offset binary. An internal pulldown resistor makes the output default to offset binary if MSBINV is left open. 31 D5 30 D4 VINN 16 GNDA 17 29 D3 D2 D1(MSB) OE\ MSBINV GNDD GNDD GNDD GNDA GNDA GNDA GNDA 18 19 20 21 22 23 24 25 26 27 28 References (VREFN, VREFP, VREFNO, VREFPO, VREFNC, VREFPC, VREFMO) To use the internal references, connect VREFPO to VREFP and VREFNO to VREFN. The nominal value for VREFPO is 3.25V and for VREFNO is 1.25V. VREFPC and VREFNC are internal reference points which should be bypassed to GND with a 0.1µF capacitor. VREFMO is an output voltage that is equal to the mid point of the reference range and can be used to apply the appropriate offset to the analog inputs. For a more detailed discussion on references, see the paragraph on references in the applications section of this datasheet. Bias Control (BCO, BC1, BIASC) The DC bias current of the CLC949 is controlled by three pins: BCO, BC1, and BIASC. BC0 and BC1 are digital CMOS inputs and set the bias current in accordance with the truth table below: Analog Input (VINP, VINN) The analog input to the CLC949 is a differential signal applied to VINP and VINN. For more detail on driving the inputs, see the paragraphs in the applications section of this datasheet. Power Supplies and Grounds (VDDA, VDDD, GNDA, GNDD) The power and ground pins of the CLC949 are split into those that supply the analog portions of the integrated circuit (VDDA, GNDA) and the digital portions of the chip (VDDD, GNDD). If your system uses separate power and ground planes, then performance can be improved by making use of the appropriate pins. In many systems, the power pins will all be tied together and the GND pins http://www.national.com BC0 BC1 Bias Current PD@10MSPS 0 0 Default: Med Bias (200µA) 200mW 1 0 Analog Mode Variable 0 1 High Bias (400µA) 350mW 1 1 Low Bias (50µA) 75mW In the analog mode, the user provides a bias current through the BIASC pin of the CLC949. As the bias current is increased, the power dissipation of the CLC949 is increased and the part becomes capable of increased conversion rates. NC No connection - leave these pins open. 4 CLC949 OPERATION Application In a high speed data acquisition system, the overall performance is often determined by the A/D converter and its surrounding circuitry. You should pay special attention to the data converter and its support circuitry if you want to obtain the best possible performance. The information on these pages is intended to help you design the circuitry surrounding the CLC949 in such a way as to achieve superior results. Additional information is available in the form of Comlinear applications notes. Especially useful are AD-01 and AD-02. Sinusoisal Clock Input 1k Sample -3 Valid Sample -2 Valid Sample -1 Valid 10k 50Ω 4 2.2k 1 0.1µF 5 To CLC949 Clock 74AC04 10k 0.1µF Driving the Differential Input The CLC949 has a differential input with a common mode voltage of 2.25V. Since not all applications have a signal preconditioned in this manner there is often a need to do a single-ended-to-differential conversion and to add offset. In systems which do not need to be DC coupled, the best method for doing this is with an RF transformer such as the Minicircuits TMO1-1T. This is an RF transformer with a center tapped secondary which will operate over a frequency range of 50kHz to 200MHz. You can offset the input and split the phases simply by connecting the center tap to the mid scale reference output (VREFMO) as shown in Figure 3. Sample 5 CLK Output Data 8 In addition to the circuitry generating the clock, the layout of the clock distribution network can affect the overall performance of the converter. To obtain the best possible performance, a clock driver with very low output impedance and fast edge rates such as the 74AC04, should be placed as close as possible to the CLC949 clock input pin. Additional length in the circuit trace for the clock will cause an increase in the jitter seen by the converter. On the CLC949 evaluation board, the E949PCASM, there is less than 1/16th of an inch between the 74AC04 that is driving the clock input and the input to the CLC949. If the system has several CLC949s, and jitter is liable to generate problems, then use a separate clock driver for each CLC949. Each driver should be placed as close to the converter that it is driving as is practicable. Sample 7 Sample 3 3 Here the CLC006 cable driver is used as a comparator to generate a high speed clock. The CLC006 has less than 2ps of jitter and has rise and fall times less than 1ns. The CLC006 output is then buffered by a 74AC04 which maintains fast edge rates and provides CMOS levels for the CLC949. If there is excessive jitter in the CLK, then the digitized signal will exhibit an excessive amount of noise, especially for high frequency inputs. For a more detailed description of this phenomenon, please read the Comlinear Application Note AD-03. Sample 6 Sample 1 6 50Ω + Figure 2: Clock Generation Effective Aperture Delay Sample 2 Sample 4 9 10k CLC006 1k Timing and CLK Generation The falling edge of the CLK pulse causes the input sample-and-hold amplifier to transition into the hold mode. The sample is taken approximately 3ns after this falling edge. The digitized data is presented to the output latches 6 1/2 clock cycles later and is held until after the next rising edge of CLK. This timing is shown in the timing diagram, Figure 1. Sample 0 0.1µF +5V Circuit Description The CLC949 ADC consists of an input Sample-and-Hold Amplifier (SHA) followed by a pipelined quantizer. Internal reference sources and output data latches complete the major functions required of an A/D converter. Digital error correction in the quantizer helps to provide accurate conversions of high speed dynamic signals. The speed of the analog circuitry is determined in part by the internal bias currents applied. The CLC949 allows you to make this important tradeoff between power and performance through settings on two digital control pins and for fine adjustments through the use of an external resistor. Analog Input +5V +5V 2.2k Sample 0 Valid Output Hold Time Figure 1: Timing Diagram The CLC949 is designed to operate with a CMOS clock signal. To obtain the lowest possible noise when digitizing a high frequency input, more care must be taken in the generation of this clock than is usually accorded to CMOS Clocks. To minimize aperture jitter induced errors, the CLK needs to have as low a jitter as possible and as fast an edge rate as possible. To obtain a very low jitter clock from a sinusoidal source, the circuit shown in Figure 2 is recommended. This set up can be realized on the CLC949 evaluation board by enabling option 1. See E949PCASM data sheet for details. A transformer coupled input will allow the CLC949 to exhibit the best possible distortion performance for high frequency input signals. 5 http://www.national.com VIN Reference Generation The CLC949 has internally generated reference voltages. To use these references, you must externally connect the reference inputs by shorting VREFPO to VREFP and VREFNO to VREFN. During the conversion cycle, the impedance on these four pins varies dynamically. To maintain stable biases on these pins you must bypass them with 0.1µF to GND. If you want to provide an external reference, then you have to be careful to provide low output impedance drivers to the VREFP and VREFN pins. Bypass capacitors on all reference pins are recommended for best performance. VINP 15pF CLC949 VREFMO 50Ω VINN TM01-1T 15pF Figure 3: Transformer Coupled Input Since the transformer response does not extend to DC it is not an effective solution for applications which require DC coupled inputs. To drive the input of the CLC949, and retain DC information, an amplifier configuration is required. Comlinear suggests the use of the circuit shown in Figure 4. This circuit is used on the E949PCASM. Bias Control One of the unique features of the CLC949 is that it allows you to set the internal bias current of the device. When designing an A/D converter a tradeoff is made between the amount of power dissipated and the performance. The CLC949 allows you to make this tradeoff yourself. The bias current is controlled by the pins BC0 and BC1. These two pins are digital input pins from which one of three discrete bias points may be selected (see truth table on page 4 of this datasheet) or an external bias may be provided through the analog bias control pin BIASC. If BC0 and BC1 are left open, they will drift low and provide the default bias condition which results in 220mW of dissipation at 20MHz sampling rate. The actual power dissipated by the device is a function of both the bias condition and the sample rate. The relationship between power and speed is shown for the three discrete bias points in Figure 5. 1k CLC428 + U5A 1.25k 1k +5V CLC428 + U5B 500Ω 500Ω 500Ω VIN R29 400Ω +5V R3 400Ω CLC409 R30 + 50Ω R7 400Ω R10 50Ω +5V U7 R8 50Ω + R2 400Ω CLC409 - U6 VREFMO R27 50Ω VINP 15pF CLC949 R26 50Ω Power Dissipation vs. Sample Rate VINN 15pF Power Dissipation (mW) 400Ω Figure 4: Amplifier Coupled Input In this circuit U7 buffers the analog input with a gain of +1, and U6 buffers the input with a gain of -1. The circuit has been designed so that U6 and U7 have the same loop gain, thereby offering the best possible match of their AC characteristics. U5 is used to generate the required offset voltages which are summed into the input signal via U6 and U7. The CLC409 was selected for U6 and U7 due to its current feedback topology which allows for very low distortion even at high frequencies, and its excellent phase linearity. Phase match between U6 and U7 is critical for good pulse response. To generate the D.C. offsets, the CLC428 dual Op-amp was selected. The CLC428 is a voltage-feedback op amp with very good DC characteristics, and the large bandwidth makes the output impedance low over a wide range of frequencies, allowing good AC performance. High Bias 300 200 Medium Bias 100 Low Bias 0 100k 1M 10M 40M Sample Rate (Hz) Figure 5: Power Dissipation vs. Sample Rate As the bias is turned up, the ability of the CLC949 to handle high frequency inputs and the power dissipation of the CLC949 increases. To use the BIASC pin, attach a resistor from the pin to VDDA. The current drawn by this resistor is mirrored in the device to set the internal bias currents. A smaller value resistor will result in higher bias currents and higher performance.Beyond a certain point, additional improvement is not seen, although power continues to increase. For this reason, it is recommended that bias setting resistors of less than 10K not be used. To generate the graph in Figure 6 a CLC949 was set to sample a signal 1dB below full scale Regardless of how the input is driven, a small capacitor (15pF) should be added from the VINP and VINN terminals to GND. This will help to reduce the current transients that are generated by the CLC949 inputs during sampling. http://www.national.com 400 6 with a frequency of 1/2 the sample rate. The bias current was then turned up until the SNR was better than 65dB and the SFDR exceeded 72dB. The axis on the left shows the power that was dissipated by the device as a function of speed, whereas the other curve uses the axis on the right to show the resistor value required to obtain this bias. the McKenzie #PLCC-44P-T-SMT socket which has low parasitic impedances. The traces from the clock source to the CLC949 should be as short as possible, if forced to put the clock driver more than a couple of centimeters away from the CLC949, then add a buffer for the clock right next to the CLC949. There is an evaluation board available for the CLC949 (E949PCASM) This board can be used to quickly evaluate the performance of the CLC949 data converter. Use of this evaluation board as a model for your PCB layout is recommended. The schematic for this evaluation board is shown in Figure 8 on the following page. The board layout for the E949PCASM is shown in the E949PCASM datasheet. Power Dissipation & Programming Resistor vs. Sample Rate 200 50 40 Resistor 100 30 Rp (kΩ) Power (mW) 150 Power 50 Power Supplies, Grounding and Bypassing To obtain the best possible performance from high speed devices, you must pay close attention to power supplies, bypassing and grounding. This applies not only to the A/D converter itself but to the entire system. 20 0 0 0 5 15 10 20 Sample Rate (MSPS) The recommended supply decoupling scheme for the CLC949 includes: Figure 6: Power Dissipation & Programming Resistor vs. Sample Rate • One 0.01 to 0.033µF capacitor between each power pin and GND. Dynamic Power Down In systems where you do not use the A/D converter continually, and low power consumption is a key requirement, the power to the CLC949 can be turned down while it is not being used. This is done through the use of the BIASC pin, and a programming resistor to the power supply. When the potential on this resistor is brought low, the part goes into a sleep mode which saves power. This can be accomplished by connecting the bias setting resistor to a CMOS gate as shown in Figure 7. In sleep mode the CLC949 will draw approximately 8mA, or 40mW on a 5V supply. • One 6.8 to 10µF capacitor per board, placed no more than a few inches from the A/D connected between VDD and GND. • One 0.1µF capacitor from each of the reference inputs (VREFP, VREFN, VREFPC, VREFNC) to GND. • If the board has supplies that include excessive digital switching noise, then ferrite beads in series with the power feed to the A/D should also be included. • Proper bypassing of all other integrated circuits on the board, especially digital logic I.C.s. Package Thermal Resistance CLC949 Package BIASC BC0 BC1 44-pin PLCC Sleep Rp* 10k CMOS Inverter qJC qJA 10°C/W 35°C/W Ordering Information VDD *See Figure 6 above. Model CLC949ACQ CLC949AJQ Figure 7: Dynamic Power Savings PCB Layout The keys to a successful CLC949 layout are a substantial low-impedance ground plane, short connections in and out of the data converter, and proper power supply decoupling. The use of a socket for the final design is not recommended but if one must be used during debug or prototyping, then Comlinear recommends Temperature Range Description 0˚C to +70˚C -40˚C to +85˚C 44-pin PLCC 44-pin PLCC Power Requirements Vcc = +5V, 5MSPS, Low Bias Vcc = +5V, 20MSPS, Med Bias Vcc = +5V, 30MSPS, High Bias 7 Typ Units 65 220 400 mW mW mW http://www.national.com Figure 8: CLC949 Evaluation Board VDDD VDDD VDDA VDDA VDDA VREFNO VREFPO BCO D12(LSB) D9 GNDA VREFNC GNDA D10 GNDD VREFPC GNDD D11 GNDD VREFN VREFMO VREFP NC OE\ CLK CLC949 Eval Board VDDD MSBINV BC1 8 GNDA VINN VINP D3 D4 D5 D6 D8 D7 GNDA GNDA NC D1(MSB) BIASC GNDA D2 http://www.national.com Data Ready D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 This page intentionally left blank. 9 http://www.national.com This page intentionally left blank. http://www.national.com 10 This page intentionally left blank. 11 http://www.national.com Comlinear CLC949 Very Low-Power, 12-Bit, 20MSPS Monolithic Converter Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 13th Floor, Straight Block Ocean Centre, 5 Canton Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 12 Lit #150949-004