Renesas HD64338101 Renesas 8-bit single-chip microcomputer h8 family / h8/300l super low power sery Datasheet

REJ09B0024-0600
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
8
H8/3802, H8/38004,
H8/38002S, H8/38104 Group
Hardware Manual
Renesas 8-Bit Single-Chip Microcomputer
H8 Family / H8/300L Super Low Power Series
H8/3802 Group
H8/38004 Group
H8/3802
H8/3801
H8/3800
H8/38004
H8/38003
H8/38002
H8/38001
H8/38000
H8/38002S Group
H8/38104 Group
Rev. 6.00
Revision Date: Mar 15, 2005
H8/38002S
H8/38001S
H8/38000S
H8/38104
H8/38103
H8/38102
H8/38101
H8/38100
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 6.00 Mar 15, 2005 page ii of l
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 6.00 Mar 15, 2005 page iii of l
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 6.00 Mar 15, 2005 page iv of l
Preface
The H8/3802 Group, H8/38004 Group, and H8/38104 Group are single-chip microcomputers
made up of the high-speed H8/300L CPU employing Renesas technology’s original architecture as
their cores, and the peripheral functions required to configure a system. The H8/300L CPU has an
instruction set that is compatible with the H8/300 CPU. Below is a table listing the product
specifications for each group.
H8/3802 Group
H8/38004 Group
Item
ZTAT
Memory
Timers
Mask ROM Flash ROM Mask ROM Mask ROM Flash ROM Mask ROM
ROM
16 k
8 k to 16 k
16 k/32 k
32 k
8 k to 16 k
16 k/32 k
8 k to 32 k
1k
512 or 1 k
1k
1k
512 k
1k
512 or 1 k
16 MHz
16 MHz
—
16 MHz
—
20 MHz
20 MHz
10 MHz
10 MHz
—
16 MHz
—
20 MHz
20 MHz
4 MHz
4 MHz
—
—
—
—
—
—
—
10 MHz
—
10 MHz
—
—
1.8 to 3.6 V
—
—
4 MHz (2.2 V
or more)
—
4 MHz
—
—
9
Input
9
9
9
9
9
9
Output
6
6
6
5
6
5
5
I/O
39
39
39
39
39
39
39
Clock (timer A)
1
1
1
1
1
1
1
Compare (timer F)
1
1
1
1
1
1
1
AEC
1
1
1
1
1
1
1
WDT
1
WDT (discrete)
SCI
1
1
UART/Clock
frequency
A-D (resolution × input
channels)
LCD
H8/38104 Group
RAM
Operating 4.5 to 5.5 V
voltage
2.7 to 5.5 V
and
operating 1.8 to 5.5 V
frequency
2.7 to 3.6 V
I/O ports
H8/38002S
Group
1 ch
1 ch
1 ch
1 ch
1 ch
1
1
1 ch
1 ch
10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch
seg
25
com
External interrupt
(internal wakeup)
25
25
25
25
25
25
4
4
4
4
4
4
4
11(8)
11(8)
11(8)
11(8)
11(8)
11(8)
11(8)
POR (power-on reset)
—
—
—
—
—
1
1
LVD
—
—
—
—
—
1
1
FP-64A
FP-64A
FP-64A
FP-64A
FP-64A
FP-64A
FP-64A
FP-64E
FP-64E
FP-64E
FP-64E
FP-64K*
FP-64E
FP-64E
DP-64S
DP-64S
Package
die
Operating temperature
die
Standard specifications: –20 to 75°C, WTR: –40 to 85°C
Note: * Under development.
Rev. 6.00 Mar 15, 2005 page v of l
Target Users: This manual was written for users who will be using the H8/3802 Group,
H8/38004 Group, H8/38002S Group, and H8/38104 Group in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the H8/3802 Group, H8/38004 Group, H8/38002S Group, and
H8/38104 Group to the target users.
Refer to the H8/300L Series Programming Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300L Series Programming Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 14,
List of Registers.
Example:
Bit order:
The MSB is on the left and the LSB is on the right.
Notes:
The following limitations apply to H8/38004, H8/38002, H8/38104, and H8/38102 programming
and debugging when the on-chip emulator is used.
1. Pin P95 is not available because it is used exclusively by the on-chip emulator.
2. Pins P33, P34, and P35 are unavailable for use. In order to use these pins additional hardware
must be mounted on the user board.
3. The address range H'7000 to H'7FFF is used by the on-chip emulator and is unavailable to the
user.
4. The address range H'F780 to H'FB7F must not be accessed under any circumstances.
5. When the on-chip emulator is being used, pin P95 is I/O, pins P33 and P34 are input, and pin
P35 is output.
6. When using the on-chip emulator, pins OSC1 and OSC2 should be connected to an oscillator,
or an external clock should be supplied to pin OSC1, even if the on-chip oscillator of the
H8/38104 Group is selected.
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/eng/
Rev. 6.00 Mar 15, 2005 page vi of l
H8/3802 Group, H8/38004 Group, H8/38002S Group, H8/38104 Group manuals:
Document Title
Document No.
H8/3802 Group, H8/38004 Group, H8/38002S Group, H8/38104 Group
Hardware Manual
This manual
H8/300L Series Programming Manual
ADE-602-040
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058-0100H
(ADE-702-247)
H8S, H8/300 Series Simulator/Debugger User's Manual
ADE-702-282
H8S, H8/300 Series High-performance Embedded Workshop, Highperformance Debugging Interface Tutorial
ADE-702-231
High-performance Embedded Workshop User's Manual
ADE-702-201
Application notes:
Document Title
Single Power Supply F-ZTAT
Document No.
TM
On-Board Programming
ADE-502-055
Rev. 6.00 Mar 15, 2005 page vii of l
Rev. 6.00 Mar 15, 2005 page viii of l
Main Revisions and Additions in this Edition
Item
Page
All
Preface
Revisions (See Manual for Details)
H8/38002S added
v
Table amended
H8/3802 Group
H8/38004 Group
Item
ZTAT
Memory
Timers
Mask ROM Flash ROM Mask ROM Mask ROM Flash ROM Mask ROM
16 k
8 k to 16 k
16 k/32 k
32 k
8 k to 16 k
16 k/32 k
8 k to 32 k
RAM
1k
512 or 1 k
1k
1k
512 k
1k
512 or 1 k
16 MHz
16 MHz
—
16 MHz
—
20 MHz
20 MHz
10 MHz
10 MHz
—
16 MHz
—
20 MHz
20 MHz
4 MHz
4 MHz
—
—
—
—
—
—
—
10 MHz
—
10 MHz
—
—
1.8 to 3.6 V
—
—
4 MHz (2.2 V
or more)
—
4 MHz
—
—
Input
9
9
9
9
9
9
9
Output
6
6
6
5
6
5
5
I/O
39
39
39
39
39
39
39
Clock (timer A)
1
1
1
1
1
1
1
Compare (timer F)
1
1
1
1
1
1
1
AEC
1
1
1
1
1
1
1
WDT
1
WDT (discrete)
SCI
UART/Clock
frequency
A-D (resolution × input
input channels)
LCD
H8/38104 Group
ROM
Operating 4.5 to 5.5 V
voltage
2.7 to 5.5 V
and
operating 1.8 to 5.5 V
frequency
2.7 to 3.6 V
I/O ports
H8/38002S
Group
1
1
1 ch
1 ch
1 ch
1 ch
1 ch
1
1
1 ch
1 ch
10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch 10 bit × 4 ch
seg
25
25
25
25
25
25
com
4
4
4
4
4
4
4
11(8)
11(8)
11(8)
11(8)
11(8)
11(8)
11(8)
1
External interrupt
(internal wakeup)
25
POR power-on ( reset)
—
—
—
—
—
1
LVD
—
—
—
—
—
1
1
FP-64A
FP-64A
FP-64A
FP-64A
FP-64A
FP-64A
FP-64A
FP-64E
FP-64E
FP-64E
FP-64E
FP-64K*
FP-64E
FP-64E
DP-64S
DP-64S
Package
die
Operating temperature
die
Standard specifications: –20 to 75 C, WTR: –40 to 85 C
Note: * Under development.
Rev. 6.00 Mar 15, 2005 page ix of l
Item
Page
Revisions (See Manual for Details)
1.1 Features
1 to 3
Description amended
• Various peripheral functions
Watchdog timer (WDT) (H8/38004, H8/38002S Group and
H8/38104 Group only)
• On-chip memory
Product Classification
Mask ROM version
Model
ROM
RAM
H8/38002S
HD64338002S
16 kbytes
512 bytes
H8/38001S
HD64338001S
12 kbytes
512 bytes
H8/38000S
HD64338000S
8 kbytes
512 bytes
H8/38104
HD64338104
32 kbytes
1 kbyte
H8/38103
HD64338103
24 kbytes
1 kbyte
H8/38102
HD64338102
16 kbytes
1 kbyte
H8/38101
HD64338101
12 kbytes
512 bytes
H8/38100
HD64338100
8 kbytes
512 bytes
• Compact package
Package
Code
Body Size
Pin Pitch
QFP-64
FP-64A
14.0 × 14.0 mm
0.8 mm
LQFP-64
FP-64E
LQFP-64
FP-64K*
DP-64S
DP-64S
17.0 × 57.6 mm
Die


10.0 × 10.0 mm
10.0 × 10.0 mm
0.5 mm
0.5 mm
1.0 mm

Note added
Note: * Under development. The package dimensions of the
FP-64K and FP-64E differ. For details, see appendix E,
Package Dimensions.
Rev. 6.00 Mar 15, 2005 page x of l
Item
Page
Revisions (See Manual for Details)
1.2 Internal Block
Diagram
4
Figure amended
OSC1
OSC2
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Port 3
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Port 4
System clock oscillator
Vss
Vss = AVss
Vcc
RES
TEST
H8/300L
CPU
Subclock oscillator
RAM
Port A
x1
x2
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port 5
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
Timer A
Port 8
Asynchronous
event counter
(AEC)
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
10-bit PWM1
Timer F
AVcc
RAM
LCD
controller/driver
Port B
LCD
power
supply
10-bit PWM2
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
P95
P94
P93
P92
P91/PWM2
P90/PWM1
Port 7
ROM
Port 9
IRQAEC
Port 6
Figure 1.1 Internal
Block Diagram of
H8/3802 Group
V1
V2
V3
PB3/AN3/IRQ1
PB2/AN2
PB1/AN1
PB0/AN0
10-bit A/D converter
Rev. 6.00 Mar 15, 2005 page xi of l
Item
Page
Revisions (See Manual for Details)
1.2 Internal Block
Diagram
5
Figure amended
OSC1
OSC2
Port 3
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Port 4
System clock oscillator
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
RAM
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
IRQAEC
Timer A
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
10-bit PWM1
Timer F
SCI3
LCD
controller/driver
AVcc
10-bit A/D converter
Port B
Port 6
WDT
LCD
power
supply
10-bit PWM2
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
P95
P94
P93
P92
P91/PWM2
P90/PWM1
Port 8
Asynchronous
event counter
(AEC)
Port 9
ROM
Port 7
Port 5
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
Rev. 6.00 Mar 15, 2005 page xii of l
Vss
Vss = AVss
Vcc
RES
TEST
H8/300L
CPU
Subclock oscillator
Port A
x1
x2
Figure 1.2 Internal
Block Diagram of
H8/38004 Group
V1
V2
V3
PB3/AN3/IRQ1
PB2/AN2
PB1/AN1
PB0/AN0
Item
Page
Revisions (See Manual for Details)
1.2 Internal Block
Diagram
6
Figure amended
OSC1
OSC2
Port 3
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Port 4
System clock oscillator
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
1.4 Pin Functions
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port 9
P95
P93/Vref
P92
P91/PWM2
P90/PWM1
Port 8
P80/SEG25
Port 7
Power-on reset
and low-voltage
detection circuit
Timer A
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Port 5
10-bit PWM1
Timer F
LCD
power
supply
Port 6
WDT
LCD
controller/driver
Port B
SCI3
AVcc
Figure 1.4 Pin
Arrangement of
H8/3802, H8/38004 and
H8/38002S Group (FP64A, FP-64E, FP-64K)
Asynchronous
event counter
(AEC)
ROM
10-bit PWM2
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
7
RAM
IRQAEC
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
1.3 Pin Arrangement
CVcc
Vss
Vss = AVss
Vcc
RES
TEST
H8/300L
CPU
Subclock oscillator
Port A
x1
x2
Figure 1.3 Internal
Block Diagram of
H8/38104 Group
V1
V2
V3
PB3/AN3/IRQ1
PB2/AN2
PB1/AN1/extU
PB0/AN0/extD
10-bit A/D converter
Title and figure amended
FP-64A, FP-64E, FP-64K (Top view)
19 to 22
Table amended
Pin No.
Table 1.4 Pin
Functions
Type
Symbol
FP-64A,
FP-64E,
FP-64K
I/O
Functions
Clock pins
X1
2
10
2
2
Input
X2
3
11
3
3
Output
These pins connect to a 32.768or 38.4-kHz*5 crystal resonator
for subclocks.
DP-64S
Pad
Pad
No.*1*3 No.*2
See section 4, Clock Pulse
Generators, for a typical
connection.
Note added
Note: 5. Does not apply to H8/38104 Group
Rev. 6.00 Mar 15, 2005 page xiii of l
Item
Page
Revisions (See Manual for Details)
2.2 Address Space
and Memory Map
29
Notes amended
Note 1. This area is unavailable to the user.
Figure 2.1(6)
H8/38002, H8/38102
Memory Map
Figure 2.1(7)
H8/38002S Memory
Map
30
Newly added
Figure 2.1(8)
31
H8/38001, H8/38001S,
H8/38101 Memory Map
Title amended
32
Figure 2.1(9)
H8/38000, H8/38000S,
H8/38100 Memory Map
Title amended
3.2.4 Interrupt
Request Register 1
(IRR1)
Table amended
80
Bit
Bit Name
Initial
Value
R/W
Description
7
IRRTA
0
R/W *
Timer A Interrupt Request Flag
[Setting condition]
When the timer A counter value overflows
[Clearing condition]
When IRRTA = 1, it is cleared by writing 0
3.5.3 Interrupt
Request Flag Clearing
Method
89, 90
Replaced
3.5.4 Notes on
Rewriting Port Mode
Registers
90 to 92
Replaced
4.1 Features
93
Description amended
Figure 4.1 shows a block diagram of the clock pulse generators
of the H8/3802, H8/38004 and H8/38002S Group.
Figure 4.1 Block
Diagram of Clock Pulse
Generators (H8/3802,
H8/38004, H8/38002S
Group)
Title amended
Rev. 6.00 Mar 15, 2005 page xiv of l
Item
Page
Revisions (See Manual for Details)
4.3 System Clock
Generator
96
Figure amended
OSC2
Figure 4.3 Block
Diagram of System
Clock Generator
LPM
OSC1
4.3.1 Connecting
Crystal Resonator
Figure 4.4(2) Typical
Connection to Crystal
Resonator (H8/38004,
H8/38002S, H8/38104
Group)
Table 4.1 Crystal
Resonator Parameters
Description amended
Figure 4.4(1) shows a typical method of connecting a crystal
oscillator to the H8/3802 Group, and figure 4.4(2) shows a
typical method of connecting a crystal oscillator to the
H8/38004, H8/38104 and H8/38002S Group.
97
Title amended
Table amended
Frequency (MHz)
RS (max)
C0 (max)
4.10
4.193
100
7 pF
Rev. 6.00 Mar 15, 2005 page xv of l
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Page
Revisions (See Manual for Details)
4.3.2 Connecting
Ceramic Resonator
98
Description amended
Figure 4.6(1) shows a typical method of connecting a ceramic
oscillator to the H8/3802 Group, and figure 4.6(2) shows a
typical method of connecting a crystal oscillator to the
H8/38004, H8/38002S and H8/38104 Group.
Title amended
Figure 4.6(2) Typical
Connection to Ceramic
Resonator (H8/38004,
H8/38002S, H8/38104
Group)
Figure amended
Frequency
Manufacturer
Prodoct Name
C1, C2
Recommendation
Value
2.0 MHz
Murata Manufacturing Co., CSTCC2M00G53-B0
Ltd.
CSTCC2M00G56-B0
15 pF ±20%
10.0 MHz
CSTLS10M0G53-B0
15 pF ±20%
CSTLS10M0G56-B0
47 pF ±20%
16.0 MHz*1
CSTLS16M0X53-B0
15 pF ±20%
20.0 MHz*2
CSTLS20M0X53-B0
15 pF ±20%
47 pF ±20%
Rf = 1 MΩ ±20%
Notes: Consult with the crystal resonator manufacturer
to determine the circuit constants.
1. This does not apply to the H8/38004 and H8/38002S Group.
2. H8/38104 Group only.
4.4.1 Connecting
32.768-kHz/38.4-kHz
Crystal Resonator
100
Figure amended
C1 = C2 = 6 to 12.5 pF (typ.)
Figure 4.9 Typical
Connection to 32.768kHz/38.4-kHz Crystal
Resonator
Figure 4.10 Equivalent 101
Circuit of 32.768kHz/38.4-kHz Crystal
Resonator
Figure amended
CO = 0.8 pF (typ.)
RS = 14 kΩ (typ.)
fW = 32.768 kHz/38.4 kHz
4.6.3 Definition of
106, 107 Description amended
Oscillation Stabilization
Meanwhile, once the system clock has halted, a standby time
Standby Time
is necessary in order for the CPU and peripheral
functions to operate normally.
Oscillation stabilization standby time = oscillation stabilization
time + standby time
1
= trc + (8 to 16,384 states) * ................. (1)
(to 131,072 states) *2
Notes: 1. H8/3802 Group, H8/38004 and H8/38002S Group
2. H8/38104 Group
Rev. 6.00 Mar 15, 2005 page xvi of l
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Page
4.6.4 Notes on Use of 107
Resonator
Revisions (See Manual for Details)
Description amended
resonator characteristics,
Depending on the individual
the oscillation waveform amplitude may not be sufficiently large
immediately after the oscillation stabilization standby time,
making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential.
Note: * This figure applies to the H8/3802, H8/38004 and
H8/38002S Groups. The number of states on the
H8/38104 Group is 8,192 or more.
5.1.1 System Control
Register 1 (SYSCR1)
111
Title amended
117
Note amended
Table 5.1(1) Operating
Frequency and Waiting
Time (H8/3802 Group,
H8/38004 Group,
H8/38002S Group)
5.2 Mode Transitions
and States of LSI
Figure 5.1 Mode
Transition Diagram
120
Table 5.3 Internal
State in Each Operating
Mode
Note: A transition between different modes cannot be made to
occur simply because an interrupt request is generated.
Make sure that interrupts are enabled.
Notes amended
Notes: 8. On the H8/38104 Group, operates when φw/32 is
selected as the internal clock or the on-chip oscillator
is selected; otherwise stops and stands by. On the
H8/38004, H8/38002S Group, operates when φw/32
is selected as the internal clock; otherwise stops and
stands by.
9. On the H8/38104 Group, operates when φw/32 is
selected as the internal clock or the on-chip oscillator
is selected; otherwise stops and stands by. On the
H8/38004, H8/38002S Group, stops and stands by.
10. On the H8/38104 Group, operates only when the onchip oscillator is selected; other-wise stops and
stands by. On the H8/38004, H8/38002S Group,
stops and stands by.
Rev. 6.00 Mar 15, 2005 page xvii of l
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Section 6 ROM
131
Description amended
The H8/3802 has 16 kbytes of the on-chip mask ROM, the
H8/3801 has 12 kbytes, and the H8/3800 has 8 kbytes. The
H8/38004 and H8/38104 have 32 kbytes of the on-chip mask
ROM, the H8/38003 and H8/38103 have 24 kbytes, the
H8/38002, H8/38002S and H8/38102 have 16 kbytes, the
H8/38001, H8/38001S and H8/38101 have 12 kbytes, and the
H8/38000, H8/38000S and H8/38100 have 8 kbytes. The ROM
is connected to the CPU by a 16-bit data bus, allowing highspeed two-state access for both byte data and word data.
6.7.1 Boot Mode
151
Table 6.7 Oscillation
Frequencies for which
Automatic Adjustment
of LSI Bit Rate is
Possible (fOSC)
Section 7 RAM
175
Table amended
Product Group
Host Bit Rate
H8/38104F Group
19,200 bps
Oscillation Frequency Range of LSI (fOSC)
16 to 20 MHz
9,600 bps
8 to 20 MHz
4,800 bps
4 to 20 MHz
2,400 bps
2 to 20 MHz
1,200 bps
2 to 20 MHz
Table amended
Product Classification
Mask ROM version
Section 8 I/O Ports
178
Table 8.1 Port
Functions
RAM Size
RAM Address
H8/38002S
512 bytes
H'FD80 to H'FF7F
H8/38001S
512 bytes
H'FD80 to H'FF7F
H8/38000S
512 bytes
H'FD80 to H'FF7F
Notes amended
Notes: 2. Implemented on H8/3802 Group only. Standard highvoltage port on H8/38104 Group, H8/38002S Group
and H8/38004 Group.
4. Implemented on H8/3802 Group only. Input port on
H8/38004 Group, H8/38002S Group and H8/38104
Group.
8.1.5 Port Mode
Register 2 (PMR2)
183
Table amended
Bit
Bit Name
Initial
Value
R/W
Description
2
WDCKS
0
R/W
Watchdog Timer Source Clock Select
This bit selects the input clock for the watchdog timer.
Note that this bit is implemented differently on the
H8/38004, H8/38002S Group and on H8/38104 Group.
H8/38004, H8/38002S Group:
0: /8,192
1: w/32
H8/38104 Group: 0: Clock specified by timer mode
register W (TMW)
1: w/32
Note: This bit is reserved and only 0 can be written in
the H8/3802 Group.
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8.2.3 Serial Port
Control Register
(SPCR)
188
Table amended
Bit
Description
3
TXD32 Pin Output Data Inversion Switch
This bit selects whether or not the logic level of the
TXD32 pin output data is inverted.
0: TXD32 output data is not inverted
1: TXD32 output data is inverted
2
RXD32 Pin Input Data Inversion Switch
This bit selects whether or not the logic level of the
RXD32 pin input data is inverted.
0: RXD32 input data is not inverted
1: RXD32 input data is inverted
8.7 Port 9
202
Description amended
Port 9 is a dedicated current port for NMOS output that also
functions as a PWM output pin.
8.7.2 Port Mode
Register 9 (PMR9)
204
Table amended
Bit
Bit Name
Initial
Value
R/W
Description
3
PIOFF
0
R/W
P92 to P90 Step-Up Circuit Control
This bit turns on and off the P92 to P90 step-up circuit.
0: Step-up circuit of large-current port is turned on
1: Step-up circuit of large-current port is turned off
Note: This bit is valid in the H8/3802 Group only. It
functions as a readable/writable reserved bit in
versions other than the H8/3802 Group.
8.7.3 Pin Functions
205
• P93/Vref
Description amended
As shown below, switching is performed based on the setting of
VREFSEL in LVDSR. Note that this function is implemented on
the H8/38104 Group only. The Vref pin is the input pin for the
LVD’s external reference voltage.
VREFSEL
Pin Function
8.9.2 Port Mode
Register B (PMRB)
209
0
1
P93 output pin
Vref input pin
Note deleted
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Page
Revisions (See Manual for Details)
9.1 Overview
213
Description amended
The H8/3802 Group provides three timers: timer A, timer F, and
asynchronous event counter. The H8/38004 Group, H8/38002S
Group and H8/38104 Group provide four timers: timer A, timer
F, asynchronous event counter, and watchdog timer.
Table 9.1 Timer
Functions
214
Table and note amended
Name
Functions
Watchdog
timer*
•
Internal Clock
φ/8192, φW /32
Generates a reset
signal by overflow of
8-bit counter
φ/64 to φ/8192
φw/32
On-chip
oscillator
Event Input Waveform
Pin
Output Pin
−
−
Remarks
H8/38004,
H8/38002S
Group
H8/38104
Group
Note: * The watchdog timer functions differently on the
H8/38004, H8/38002S and H8/38104 Group. See
section 9.5, Watchdog Timer, for details.
9.2.3 Operation
218
Description amended
Clock Time Base Operation: When bit TMA3 in TMA is set to 1,
the timer A functions as a clock-timer base by counting clock
signals output by prescaler W.
The overflow period
of timer A is set by bits TMA1 and TMA0 in TMA. A choice of
four periods is available. In clock time base operation (TMA3 =
1), setting bit TMA2 to 1 clears both TCA and prescaler W to
H'00.
9.3.4 CPU Interface
225
Description amended
When performing TCF read/write access or OCRF write access
in 16-bit mode, data will not be transferred correctly if only the
upper byte or only the lower byte is accessed. Access must be
performed for all 16 bits (using two consecutive byte-size MOV
instructions), and the upper byte must be accessed before the
lower byte.
9.3.5 Operation
Timer F Operation
• Operation in 16-bit
timer mode
228
Description amended
When CKSH2 is cleared to 0 in timer control register F (TCRF),
timer F operates as a 16-bit timer.
The timer F operating clock can be selected from three internal
clocks output by prescaler S by means of bits CKSL2 to CKSL0
in TCRF.
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Revisions (See Manual for Details)
9.4.6 Usage Notes
248, 249 Description amended
2. The maximum clock frequency that may be input to the
AEVH and AEVL pins is 16 MHz*1. Furthermore, the clock
high width and low width should be half or more the OSC
clock cycle time. The duty ratio does not matter as long as
the high width and low width satisfy the minimum
requirement.
Maximum Clock
Frequency Input to
AEVH/AEVL Pin
Mode
Watch, subactive, subsleep, standby
(φW/2) 1000 kHz
φW = 32.768 kHz or 38.4 kHz*
(φW/4) 500 kHz
2
(φW/8) 250 kHz
Notes: 1. Up to 10 MHz in the H8/38004, H8/38002S Group.
2. Does not apply to H8/38104 Group.
9.5 Watchdog Timer
250
Description amended
However, as shown in watchdog timer block diagrams figure
9.12 (1) and figure 9.12 (2), the implementation differs in the
H8/38004, H8/38002S Group and the H8/38104 Group.
9.5.1 Features
Description amended
• Selectable from two counter input clocks (H8/38004,
H8/38002S Group).
Figure 9.12(1) Block
Diagram of Watchdog
Timer (H8/38004,
H8/38002S Group)
9.5.2 Register
Descriptions
Title amended
253
Notes: 2.Initial value 0 on H8/38004, H8/38002S Group and 1
on H8/38104 Group.
Timer Control/Status
Register W (TCSRW)
9.5.3 Operation
Notes amended
3.On reset, cleared to 0 on H8/38004, H8/38002S Group
and set to 1 on H8/38104 Group.
254
Description amended
The input clock is selected by the WDCKS bit in the port mode
register 2 (PMR2)*: On the H8/38004, H8/38002S Group,
φ/8192 is selected when the WDCKS bit is cleared to 0, and
φw/32 when set to 1.
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9.5.4 Operating States 256
of Watchdog Timer
Description amended
Table 9.8(1) Operating
States of Watchdog
Timer (H8/38004,
H8/38002S Group)
Title amended
10.3.8 Bit Rate
Register (BRR)
269
Tables 9.8(1) and 9.8(2) summarize the operating states of the
watchdog timer for the H8/38004, H8/38002S Group and
H8/38104 Group, respectively.
Description amended
The values are shown in table 10.5
N=
Table 10.2 Examples
of BRR Settings for
Various Bit Rates
(Asynchronous Mode)
(2)
271
B:
N:
φ:
n:
–1
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (Hz)
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.3.)
Table amended
φ
10 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
110
3
43
0.88
150
3
32
–1.36
200
3
23
1.73
250
3
19
–2.34
300
3
15
1.73
600
3
7
1.73
1200
3
3
1.73
2400
3
1
1.73
4800
3
0
1.73
9600
2
1
1.73
19200
2
0
1.73
31250
0
9
0
38400
0
7
1.73
Rev. 6.00 Mar 15, 2005 page xxii of l
32 • 2 2n • B
.
B (bit rate obtained from n, N, φ ) – R (bit rate in left-hand column in table 10.2)
R (bit rate in left-hand column in table 10.2)
Error (%) =
Legend:
φ
• 100
Item
Page
Revisions (See Manual for Details)
10.3.8 Bit Rate
Register (BRR)
272
Table amended
Table 10.4 Maximum
Bit Rate for Each
Frequency
(Asynchronous Mode)
Table 10.5 BRR
273
Settings for Various Bit
Rates (Clocked
Synchronous Mode) (2)
Setting
OSC (MHz)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
0.0384*
0.0192
600
0
0
2
1
31250
0
0
2.4576
1.2288
38400
0
0
4
2
62500
0
0
10
5
156250
0
0
16
8
250000
0
0
20
10
312500
0
0
Table amended
φ
10 MHz
Bit Rate
(bit/s)
n
N
Error (%)
200
0
12499
0
250
2
624
0
300
0
8332
0
500
0
4999
0
1k
0
2499
0
2.5k
0
999
0
5k
0
499
0
10k
0
249
0
25k
0
99
0
50k
0
49
0
100k
0
24
0
250k
0
9
0
500k
0
4
0
1M
—
—
—
Note added
Note:
The value set in BRR is given by the following formula:
N=
B:
N:
φ:
n:
φ
8 • 22n • B
–1
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (Hz)
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.6.)
Rev. 6.00 Mar 15, 2005 page xxiii of l
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10.3.9 Serial Port
Control Register
(SPCR)
274
Table amended
Bit
Description
3
TXD32 Pin Output Data Inversion Switch
This bit selects whether or not the logic level of the
TXD32 pin output data is inverted.
0: TXD32 output data is not inverted
1: TXD32 output data is inverted
2
RXD32 Pin Input Data Inversion Switch
This bit selects whether or not the logic level of the
RXD32 pin input data is inverted.
0: RXD32 input data is not inverted
1: RXD32 input data is inverted
10.5.4 Serial Data
Reception (Clocked
Synchronous Mode)
291
Figure amended
Serial
clock
Serial
data
Figure 10.12 Example
of SCI3 Reception
Operation in Clocked
Synchronous Mode
Bit 7
Bit 0
Bit 7
Bit 0
1 frame
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
RXI interrupt
request
generated
User
processing
10.7 Interrupts
301
Table 10.11 SCI3
Interrupt Requests
RDRF flag
cleared
to 0
RXI interrupt request generated
RDR data read
RDR data has
not been read
(RDRF = 1)
ERI interrupt request
generated by
overrun error
Overrun error
processing
Table and description amended
Interrupt Requests
Abbreviation
Interrupt Sources
Receive Data Full
RXI
Setting RDRF in SSR
Enable Bit
RIE
Transmit Data Empty
TXI
Setting TDRE in SSR
TIE
Transmission End
TEI
Setting TEND in SSR
TEIE
Receive Error
ERI
Setting OER, FER, or PER in SSR
RIE
Each interrupt request can be enabled or disabled by means of
bits TIE, RIE and TEIE in SCR3.
Table 10.12
Transmit/Receive
Interrupts
302
10.8.10 Oscillator Use 307
with Serial
Communication
Interface 3 in
Asynchronous Mode
(H8/38104 Group Only)
Table amended
Flag and Enable Bit
Title and description amended
When implementing serial communication interface 3 in
asynchronous mode on the H8/38104 Group, the system clock
oscillator must be used. The on-chip oscillator should not be
used in this case.
Rev. 6.00 Mar 15, 2005 page xxiv of l
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Section 11 10-Bit
PWM
309
Description amended
Figure 11.1(1) shows a block diagram of the 10-bit PWM of the
H8/3802 Group, H8/38004 Group and H8/38002S Group.
11.1 Features
Description amended
• On the H8/38104 Group it is possible to select between two
types of PWM output: pulse-division 10-bit PWM and event
counter PWM (PWM incorporating AEC). (The H8/3802
Group, H8/38004 Group and H8/38002S Group can only
produce 10-bit PWM output.) Refer to section 9.4,
Asynchronous Event Counter, for information on event counter
PWM.
310
Figure 11.1(1) Block
Diagram of 10-Bit PWM
Title amended
(H8/3802 Group,
H8/38004 Group,
H8/38002S Group)
11.2 Input/Output Pins 311
Note amended
Table 11.1 Pin
Configuration
Note: * The event counter PWM output pin is valid on the
H8/38104 Group only.
11.3.1 PWM Control
Register (PWCR)
312
11.4.1 Operation
315
Description amended
On the H8/3802 Group, H8/38004 Group and H8/38002S
Group, PWCR selects the conversion period.
Description amended
1. Set the PWM2 and/or PWM1 bits in port mode register 9
(PMR9) to 1 to set the P91/PWM2 pin or P90/PWM1 pin, or
both, to function as PWM output pins.
12.1 Features
317
Description amended
• Conversion time: at least 12.4 µs per channel (φ = 5 MHz
operation)/6.2 µs (φ = 10 MHz operation)*
12.7.1 Permissible
Signal Source
Impedance
327
12.7.3 Additional
Usage Notes
328
Description amended
As a countermeasure, a large capacitance can be provided
externally to the analog input pin. This will cause the actual
input resistance to comprise only the internal input resistance of
10 kΩ, allowing the signal source impedance to be ignored. This
countermeasure has the disadvantage of creating a low-pass
filter from the signal source impedance and capacitance, with
the result that it may not be possible to follow analog signals
having a large differential coefficient (e.g., 5 mV/µs or greater)
(see figure 12.7). …
Title amended
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Revisions (See Manual for Details)
13.1 Features
329
Description amended
• On-chip power supply split-resistance
Removal of split-resistance can be controlled in software. Note
that this capability is implemented in the H8/38104 Group
only.
Figure 13.1(1) Block
Diagram of LCD
Controller/Driver
(H8/3802 Group,
H8/38004 Group,
H8/38002S Group)
330
Title amended
13.3.3 LCD Control
Register 2 (LCR2)
338
Note amended
17.1 Absolute
Maximum Ratings of
H8/3802 Group (ZTAT
Version, Mask ROM
Version)
377
Title amended
17.2 Electrical
Characteristics of
H8/3802 Group (ZTAT
Version, Mask ROM
Version)
378
Title amended
394
17.3 Absolute
Maximum Ratings of
H8/38004 Group
(F-ZTAT Version, Mask
ROM Version),
H8/38002S Group
(Mask ROM Version)
Title amended
395
17.4 Electrical
Characteristics of
H8/38004 Group
(F-ZTAT Version, Mask
ROM Version),
H8/38002S Group
(Mask ROM Version)
Title amended
Note: * Applies to H8/38104 Group only. On the H8/3802
Group, H8/38004 Group or H8/38002S Group, these
bits are reserved like bit 4.
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17.4.1 Power Supply
Voltage and Operating
Ranges
395
Figure amended
10.0
fosc(MHz)
Power Supply Voltage
and Oscillation
Frequency Range (FZTAT Version)
4.0
2.0
2.2
2.7
3.6
Vcc (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
4 MHz specification
10 MHz specification
17.5 Absolute
416
Maximum Ratings of
H8/38104 Group
(F-ZTAT Version, Mask
ROM Version)
Title amended
17.6 Electrical
417
Characteristics of
H8/38104 Group
(F-ZTAT Version, Mask
ROM Version)
Title amended
17.6.1 Power Supply
Voltage and Operating
Ranges
Figure amended
20.0
fosc (MHz)
Power Supply Voltage
and Oscillation
Frequency Range
(System Clock
Oscillator Selected)
2.0
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Rev. 6.00 Mar 15, 2005 page xxvii of l
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Revisions (See Manual for Details)
17.6.1 Power Supply
Voltage and Operating
Ranges
418
Figure amended
10.0
φ (MHz)
Power Supply Voltage
and Operating
Frequency Range
(System Clock
Oscillator Selected)
1.0
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
φ (kHz)
1250
15.625
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
420
Figure amended
10.0
φ (MHz)
Analog Power Supply
Voltage and A/D
Converter Operating
Range (System Clock
Oscillator Selected)
1.0
2.7
5.5
AVCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Rev. 6.00 Mar 15, 2005 page xxviii of l
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Revisions (See Manual for Details)
17.6.2 DC
Characteristics
424
Table amended
Values
Item
Table 17.15 DC
Characteristics (4)
Symbol
Active
IOPE1
mode
current
consumption
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
VCC
Active (high-speed)
mode
VCC = 5 V,
fOSC = 2 MHz
—
0.8
—
mA
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
1.5
*2 *3 *4
—
Approx.
max. value
= 1.1 •
Typ.
Table 17.15 DC
Characteristics (5)
428
Table amended
Values
Item
Symbol
Allowable IOL
output low
current
(per pin)
17.6.3 AC
Characteristics
430
Table 17.16 Control
Signal Timing
431
Table 17.17 Serial
Interface (SCI3) Timing
17.6.4 A/D Converter
Characteristics
432
17.6.9 Watchdog
Timer Characteristics
Table 17.27 Watchdog
Timer Characteristics
Test Condition
Typ
Max
Unit
Port 9
VCC = 4.0 V to 5.5 V —
—
15.0
mA
Other than above
—
5.0
—
Values
Item
Symbol
Applicable
Pins
System clock
oscillation
frequency
fOSC
OSC1, OSC2
OSC clock (
cycle time
tOSC
OSC)
Test Condition
Min
On-chip oscillator
selected
OSC1, OSC2
On-chip oscillator
selected
Notes
Typ
Max
Unit
MHz
2.0
—
20.0
0.7
—
2.0
50.0
—
500
500
—
1429
Reference
Figure
*2
ns
Figure 17.1
External clock high tCPH
width
OSC1
20
—
—
ns
Figure 17.1
External clock low
width
tCPL
OSC1
20
—
—
ns
Figure 17.1
External clock rise
time
tCPr
OSC1
—
—
5
ns
Figure 17.1
External clock fall
time
tCPf
OSC1
—
—
5
ns
Figure 17.1
Table amended
Test
Condition
Values
Min
Typ Max Unit
Reference
Figure
tRXS
150.0
—
—
ns
Figure 17.5
tRXH
150.0
—
—
ns
Figure 17.5
Item
Symbol
Receive data setup time
(clocked synchronous)
Receive data hold time
(clocked synchronous)
Table amended
Symbol
Applicable Test
Pins
Condition
Conversion time
440
Min
Table amended
Item
Table 17.18 A/D
Converter
Characteristics
Applicable Pins
Values
Min
Typ
Max
Unit
6.2
—
124
µs
Reference
Figure
Table amended
Item
Symbol
On-chip oscillator
overflow time
tOVF
Applicable
Pins
Rated Values
Test
Condition
Min
Typ
Max
Unit
Note
VCC = 5 V
0.2
0.4
—
s
*
Rev. 6.00 Mar 15, 2005 page xxix of l
Item
Page
Revisions (See Manual for Details)
A.1 Instruction List
455
Notes amended
Table A.1 Instruction
Set
B.7 Port 9 Block
Diagrams
(4) The number of states required for execution is 4n + 9 (n =
value of R4L). In the H8/38004 Group, H8/38002S Group
and H8/38104 Group, the number of states required for
execution is 4n + 8.
478
Newly added
481
Newly added
Figure B.9(c) Port B
Block Diagram (Pin
PB1, H8/38104 Group
Only)
482
Newly added
Appendix D Product
Code Lineup
487
Newly added
Appendix E Package
Dimensions
490
Description amended
Figure E.3 Package
Dimensions (FP-64K)
492
Figure B.7(c) Port 9
Block Diagram (Pin
P93, H8/38104 Group
Only)
B.9 Port B Block
Diagrams
Figure B.9(b) Port B
Block Diagram (Pin
PB0, H8/38104 Group
Only)
Table D.3 Product
Code Lineup of
H8/38002S Group
The package dimensions are shown in figure E.1 (FP-64A),
figure E.2 (FP-64E), figure E.3 (FP-64K), and figure E.4 (DP64S).
Newly added
Rev. 6.00 Mar 15, 2005 page xxx of l
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
1.4
1
Features............................................................................................................................. 1
Internal Block Diagram..................................................................................................... 4
Pin Arrangement ............................................................................................................... 7
Pin Functions .................................................................................................................... 19
Section 2 CPU ...................................................................................................................... 23
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Features.............................................................................................................................
Address Space and Memory Map .....................................................................................
Register Configuration......................................................................................................
2.3.1 General Registers.................................................................................................
2.3.2 Program Counter (PC) .........................................................................................
2.3.3 Condition Code Register (CCR) ..........................................................................
2.3.4 Initial Register Values .........................................................................................
Data Formats.....................................................................................................................
2.4.1 General Register Data Formats............................................................................
2.4.2 Memory Data Formats .........................................................................................
Instruction Set...................................................................................................................
2.5.1 Data Transfer Instructions ...................................................................................
2.5.2 Arithmetic Operations Instructions......................................................................
2.5.3 Logic Operations Instructions..............................................................................
2.5.4 Shift Instructions..................................................................................................
2.5.5 Bit Manipulation Instructions ..............................................................................
2.5.6 Branch Instructions..............................................................................................
2.5.7 System Control Instructions.................................................................................
2.5.8 Block Data Transfer Instructions .........................................................................
Addressing Modes and Effective Address ........................................................................
2.6.1 Addressing Modes ...............................................................................................
2.6.2 Effective Address Calculation .............................................................................
Basic Bus Cycle ................................................................................................................
2.7.1 Access to On-Chip Memory (RAM, ROM).........................................................
2.7.2 On-Chip Peripheral Modules ...............................................................................
CPU States ........................................................................................................................
Usage Notes ......................................................................................................................
2.9.1 Notes on Data Access to Empty Areas ................................................................
2.9.2 Access to Internal I/O Registers ..........................................................................
2.9.3 EEPMOV Instruction...........................................................................................
2.9.4 Bit Manipulation Instructions ..............................................................................
23
24
33
34
34
35
36
36
36
38
39
41
43
44
44
46
49
51
52
53
53
56
60
60
61
63
64
64
64
65
65
Rev. 6.00 Mar 15, 2005 page xxxi of l
Section 3 Exception Handling ......................................................................................... 73
3.1
3.2
3.3
3.4
3.5
Exception Sources and Vector Address ............................................................................
Register Descriptions........................................................................................................
3.2.1 Interrupt Edge Select Register (IEGR) ................................................................
3.2.2 Interrupt Enable Register 1 (IENR1) ...................................................................
3.2.3 Interrupt Enable Register 2 (IENR2) ...................................................................
3.2.4 Interrupt Request Register 1 (IRR1) ....................................................................
3.2.5 Interrupt Request Register 2 (IRR2) ....................................................................
3.2.6 Wakeup Interrupt Request Register (IWPR) .......................................................
3.2.7 Wakeup Edge Select Register (WEGR) ..............................................................
Reset Exception Handling.................................................................................................
Interrupt Exception Handling ...........................................................................................
3.4.1 External Interrupts ...............................................................................................
3.4.2 Internal Interrupts ................................................................................................
3.4.3 Interrupt Handling Sequence ...............................................................................
3.4.4 Interrupt Response Time......................................................................................
Usage Notes ......................................................................................................................
3.5.1 Interrupts after Reset............................................................................................
3.5.2 Notes on Stack Area Use .....................................................................................
3.5.3 Interrupt Request Flag Clearing Method .............................................................
3.5.4 Notes on Rewriting Port Mode Registers ............................................................
75
77
77
78
79
80
81
82
83
83
84
84
85
86
87
89
89
89
89
90
Section 4 Clock Pulse Generators................................................................................... 93
4.1
4.2
4.3
4.4
4.5
4.6
Features.............................................................................................................................
Register Description .........................................................................................................
System Clock Generator ...................................................................................................
4.3.1 Connecting Crystal Resonator .............................................................................
4.3.2 Connecting Ceramic Resonator ...........................................................................
4.3.3 External Clock Input Method ..............................................................................
4.3.4 On-Chip Oscillator Selection Method (H8/38104 Group Only)..........................
Subclock Generator ..........................................................................................................
4.4.1 Connecting 32.768-kHz/38.4-kHz Crystal Resonator .........................................
4.4.2 Pin Connection when Not Using Subclock..........................................................
4.4.3 External Clock Input............................................................................................
Prescalers ..........................................................................................................................
4.5.1 Prescaler S ...........................................................................................................
4.5.2 Prescaler W..........................................................................................................
Usage Notes ......................................................................................................................
4.6.1 Note on Resonators..............................................................................................
4.6.2 Notes on Board Design ........................................................................................
4.6.3 Definition of Oscillation Stabilization Standby Time..........................................
4.6.4 Notes on Use of Resonator ..................................................................................
Rev. 6.00 Mar 15, 2005 page xxxii of l
93
95
96
96
98
99
99
100
100
101
101
102
102
102
102
102
104
105
107
4.6.5
Notes on H8/38104 Group................................................................................... 108
Section 5 Power-Down Modes ........................................................................................ 109
5.1
5.2
5.3
5.4
5.5
Register Descriptions........................................................................................................
5.1.1 System Control Register 1 (SYSCR1) .................................................................
5.1.2 System Control Register 2 (SYSCR2) .................................................................
5.1.3 Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2) ..................................
Mode Transitions and States of LSI..................................................................................
5.2.1 Sleep Mode ..........................................................................................................
5.2.2 Standby Mode......................................................................................................
5.2.3 Watch Mode.........................................................................................................
5.2.4 Subsleep Mode.....................................................................................................
5.2.5 Subactive Mode ...................................................................................................
5.2.6 Active (Medium-Speed) Mode ............................................................................
Direct Transition ...............................................................................................................
5.3.1 Direct Transition from Active (High-Speed) Mode to Active
(Medium-Speed) Mode........................................................................................
5.3.2 Direct Transition from Active (Medium-Speed) Mode to Active
(High-Speed) Mode .............................................................................................
5.3.3 Direct Transition from Subactive Mode to Active (High-Speed) Mode..............
5.3.4 Direct Transition from Subactive Mode to Active (Medium-Speed) Mode ........
5.3.5 Notes on External Input Signal Changes before/after Direct Transition..............
Module Standby Function.................................................................................................
Usage Notes ......................................................................................................................
5.5.1 Standby Mode Transition and Pin States .............................................................
5.5.2 Notes on External Input Signal Changes before/after Standby Mode..................
110
110
113
114
116
120
121
121
122
122
123
124
125
126
126
127
127
128
128
128
128
Section 6 ROM..................................................................................................................... 131
6.1
6.2
6.3
6.4
6.5
6.6
Block Diagram..................................................................................................................
H8/3802 PROM Mode......................................................................................................
6.2.1 Setting to PROM Mode .......................................................................................
6.2.2 Socket Adapter Pin Arrangement and Memory Map...........................................
H8/3802 Programming......................................................................................................
6.3.1 Writing and Verifying..........................................................................................
6.3.2 Programming Precautions....................................................................................
Reliability of Programmed Data .......................................................................................
Overview of Flash Memory ..............................................................................................
6.5.1 Features................................................................................................................
6.5.2 Block Diagram.....................................................................................................
6.5.3 Block Configuration ............................................................................................
Register Descriptions........................................................................................................
6.6.1 Flash Memory Control Register 1 (FLMCR1).....................................................
131
132
132
132
135
135
139
140
141
141
142
143
144
145
Rev. 6.00 Mar 15, 2005 page xxxiii of l
6.6.2 Flash Memory Control Register 2 (FLMCR2) ....................................................
6.6.3 Erase Block Register (EBR) ................................................................................
6.6.4 Flash Memory Power Control Register (FLPWCR)............................................
6.6.5 Flash Memory Enable Register (FENR)..............................................................
6.7 On-Board Programming Modes........................................................................................
6.7.1 Boot Mode ...........................................................................................................
6.7.2 Programming/Erasing in User Program Mode.....................................................
6.7.3 Notes on On-Board Programming .......................................................................
6.8 Flash Memory Programming/Erasing...............................................................................
6.8.1 Program/Program-Verify.....................................................................................
6.8.2 Erase/Erase-Verify...............................................................................................
6.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................
6.9 Program/Erase Protection .................................................................................................
6.9.1 Hardware Protection ............................................................................................
6.9.2 Software Protection .............................................................................................
6.9.3 Error Protection ...................................................................................................
6.10 Programmer Mode ............................................................................................................
6.10.1 Socket Adapter ....................................................................................................
6.10.2 Programmer Mode Commands............................................................................
6.10.3 Memory Read Mode ............................................................................................
6.10.4 Auto-Program Mode............................................................................................
6.10.5 Auto-Erase Mode.................................................................................................
6.10.6 Status Read Mode ................................................................................................
6.10.7 Status Polling .......................................................................................................
6.10.8 Programmer Mode Transition Time ....................................................................
6.10.9 Notes on Memory Programming .........................................................................
6.11 Power-Down States for Flash Memory.............................................................................
146
146
147
147
148
148
151
152
153
153
157
157
159
159
159
159
160
160
160
164
167
169
170
172
173
173
174
Section 7 RAM..................................................................................................................... 175
7.1
Block Diagram.................................................................................................................. 176
Section 8 I/O Ports .............................................................................................................. 177
8.1
8.2
Port 3.................................................................................................................................
8.1.1 Port Data Register 3 (PDR3) ...............................................................................
8.1.2 Port Control Register 3 (PCR3) ...........................................................................
8.1.3 Port Pull-Up Control Register 3 (PUCR3)...........................................................
8.1.4 Port Mode Register 3 (PMR3) .............................................................................
8.1.5 Port Mode Register 2 (PMR2) .............................................................................
8.1.6 Pin Functions .......................................................................................................
8.1.7 Input Pull-Up MOS..............................................................................................
Port 4.................................................................................................................................
8.2.1 Port Data Register 4 (PDR4) ...............................................................................
Rev. 6.00 Mar 15, 2005 page xxxiv of l
179
180
180
181
182
183
184
185
186
186
8.2.2 Port Control Register 4 (PCR4) ...........................................................................
8.2.3 Serial Port Control Register (SPCR)....................................................................
8.2.4 Pin Functions .......................................................................................................
8.3 Port 5.................................................................................................................................
8.3.1 Port Data Register 5 (PDR5) ...............................................................................
8.3.2 Port Control Register 5 (PCR5) ...........................................................................
8.3.3 Port Pull-Up Control Register 5 (PUCR5)...........................................................
8.3.4 Port Mode Register 5 (PMR5) .............................................................................
8.3.5 Pin Functions .......................................................................................................
8.3.6 Input Pull-Up MOS..............................................................................................
8.4 Port 6.................................................................................................................................
8.4.1 Port Data Register 6 (PDR6) ...............................................................................
8.4.2 Port Control Register 6 (PCR6) ...........................................................................
8.4.3 Port Pull-Up Control Register 6 (PUCR6)...........................................................
8.4.4 Pin Functions .......................................................................................................
8.4.5 Input Pull-Up MOS..............................................................................................
8.5 Port 7.................................................................................................................................
8.5.1 Port Data Register 7 (PDR7) ...............................................................................
8.5.2 Port Control Register 7 (PCR7) ...........................................................................
8.5.3 Pin Functions .......................................................................................................
8.6 Port 8.................................................................................................................................
8.6.1 Port Data Register 8 (PDR8) ...............................................................................
8.6.2 Port Control Register 8 (PCR8) ...........................................................................
8.6.3 Pin Functions .......................................................................................................
8.7 Port 9.................................................................................................................................
8.7.1 Port Data Register 9 (PDR9) ...............................................................................
8.7.2 Port Mode Register 9 (PMR9) .............................................................................
8.7.3 Pin Functions .......................................................................................................
8.8 Port A................................................................................................................................
8.8.1 Port Data Register A (PDRA)..............................................................................
8.8.2 Port Control Register A (PCRA) .........................................................................
8.8.3 Pin Functions .......................................................................................................
8.9 Port B ................................................................................................................................
8.9.1 Port Data Register B (PDRB) ..............................................................................
8.9.2 Port Mode Register B (PMRB)............................................................................
8.9.3 Pin Functions .......................................................................................................
8.10 Usage Notes ......................................................................................................................
8.10.1 How to Handle Unused Pin .................................................................................
187
187
189
190
191
191
192
192
193
194
194
195
195
196
196
197
198
198
199
199
200
201
201
202
202
203
204
204
205
206
206
207
208
209
209
210
211
211
Section 9 Timers .................................................................................................................. 213
9.1
9.2
Overview........................................................................................................................... 213
Timer A............................................................................................................................. 215
Rev. 6.00 Mar 15, 2005 page xxxv of l
9.3
9.4
9.5
9.2.1 Features................................................................................................................
9.2.2 Register Descriptions...........................................................................................
9.2.3 Operation .............................................................................................................
9.2.4 Timer A Operating States ....................................................................................
Timer F .............................................................................................................................
9.3.1 Features................................................................................................................
9.3.2 Input/Output Pins.................................................................................................
9.3.3 Register Descriptions...........................................................................................
9.3.4 CPU Interface ......................................................................................................
9.3.5 Operation .............................................................................................................
9.3.6 Timer F Operating States.....................................................................................
9.3.7 Usage Notes.........................................................................................................
Asynchronous Event Counter (AEC)................................................................................
9.4.1 Features................................................................................................................
9.4.2 Input/Output Pins.................................................................................................
9.4.3 Register Descriptions...........................................................................................
9.4.4 Operation .............................................................................................................
9.4.5 Operating States of Asynchronous Event Counter ..............................................
9.4.6 Usage Notes.........................................................................................................
Watchdog Timer ...............................................................................................................
9.5.1 Features................................................................................................................
9.5.2 Register Descriptions...........................................................................................
9.5.3 Operation .............................................................................................................
9.5.4 Operating States of Watchdog Timer ..................................................................
215
216
218
218
219
219
221
221
225
227
230
230
234
234
236
236
243
248
248
250
250
251
254
256
Section 10 Serial Communication Interface 3 (SCI3) .............................................. 257
10.1 Features............................................................................................................................. 257
10.2 Input/Output Pins.............................................................................................................. 259
10.3 Register Descriptions........................................................................................................ 259
10.3.1 Receive Shift Register (RSR) .............................................................................. 259
10.3.2 Receive Data Register (RDR).............................................................................. 260
10.3.3 Transmit Shift Register (TSR)............................................................................. 260
10.3.4 Transmit Data Register (TDR) ............................................................................ 260
10.3.5 Serial Mode Register (SMR) ............................................................................... 261
10.3.6 Serial Control Register 3 (SCR3) ........................................................................ 264
10.3.7 Serial Status Register (SSR) ................................................................................ 266
10.3.8 Bit Rate Register (BRR) ...................................................................................... 269
10.3.9 Serial Port Control Register (SPCR).................................................................... 274
10.4 Operation in Asynchronous Mode .................................................................................... 275
10.4.1 Clock.................................................................................................................... 276
10.4.2 SCI3 Initialization................................................................................................ 280
10.4.3 Data Transmission ............................................................................................... 281
Rev. 6.00 Mar 15, 2005 page xxxvi of l
10.4.4 Serial Data Reception ..........................................................................................
10.5 Operation in Clocked Synchronous Mode ........................................................................
10.5.1 Clock....................................................................................................................
10.5.2 SCI3 Initialization................................................................................................
10.5.3 Serial Data Transmission .....................................................................................
10.5.4 Serial Data Reception (Clocked Synchronous Mode) .........................................
10.5.5 Simultaneous Serial Data Transmission and Reception.......................................
10.6 Multiprocessor Communication Function ........................................................................
10.6.1 Multiprocessor Serial Data Transmission ............................................................
10.6.2 Multiprocessor Serial Data Reception .................................................................
10.7 Interrupts...........................................................................................................................
10.8 Usage Notes ......................................................................................................................
10.8.1 Break Detection and Processing ..........................................................................
10.8.2 Mark State and Break Sending.............................................................................
10.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ....................................................................
10.8.4 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ............................................................................................
10.8.5 Note on Switching SCK32 Function....................................................................
10.8.6 Relation between Writing to TDR and Bit TDRE ...............................................
10.8.7 Relation between RDR Reading and bit RDRF...................................................
10.8.8 Transmit and Receive Operations when Making State Transition.......................
10.8.9 Setting in Subactive or Subsleep Mode ...............................................................
10.8.10 Oscillator Use with Serial Communications Interface 3
(H8/38104 Group only) .......................................................................................
283
287
287
287
288
291
293
295
297
298
301
303
303
303
304
304
305
306
306
307
307
307
Section 11 10-Bit PWM .................................................................................................... 309
11.1 Features............................................................................................................................. 309
11.2 Input/Output Pins.............................................................................................................. 311
11.3 Register Descriptions........................................................................................................ 312
11.3.1 PWM Control Register (PWCR) ......................................................................... 312
11.3.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 314
11.4 Operation .......................................................................................................................... 315
11.4.1 Operation ............................................................................................................. 315
11.4.2 PWM Operating States ........................................................................................ 316
Section 12 A/D Converter ................................................................................................. 317
12.1 Features............................................................................................................................. 317
12.2 Input/Output Pins.............................................................................................................. 319
12.3 Register Descriptions........................................................................................................ 319
12.3.1 A/D Result Registers H and L (ADRRH and ADRRL)....................................... 319
12.3.2 A/D Mode Register (AMR) ................................................................................. 320
Rev. 6.00 Mar 15, 2005 page xxxvii of l
12.3.3 A/D Start Register (ADSR) .................................................................................
12.4 Operation ..........................................................................................................................
12.4.1 A/D Conversion ...................................................................................................
12.4.2 Operating States of A/D Converter......................................................................
12.5 Example of Use.................................................................................................................
12.6 A/D Conversion Accuracy Definitions .............................................................................
12.7 Usage Notes ......................................................................................................................
12.7.1 Permissible Signal Source Impedance .................................................................
12.7.2 Influences on Absolute Accuracy ........................................................................
12.7.3 Additional Usage Notes.......................................................................................
321
321
321
322
322
325
327
327
327
327
Section 13 LCD Controller/Driver ................................................................................. 329
13.1 Features............................................................................................................................. 329
13.2 Input/Output Pins.............................................................................................................. 332
13.3 Register Descriptions........................................................................................................ 333
13.3.1 LCD Port Control Register (LPCR)..................................................................... 333
13.3.2 LCD Control Register (LCR) .............................................................................. 336
13.3.3 LCD Control Register 2 (LCR2) ......................................................................... 338
13.4 Operation .......................................................................................................................... 339
13.4.1 Settings up to LCD Display ................................................................................. 339
13.4.2 Relationship between LCD RAM and Display.................................................... 341
13.4.3 Operation in Power-Down Modes ....................................................................... 346
13.4.4 Boosting LCD Drive Power Supply..................................................................... 347
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104
Group Only)............................................................................................................................. 349
14.1 Features............................................................................................................................. 349
14.2 Register Descriptions........................................................................................................ 351
14.2.1 Low-Voltage Detection Control Register (LVDCR) ........................................... 351
14.2.2 Low-Voltage Detection Status Register (LVDSR) .............................................. 353
14.2.3 Low-Voltage Detection Counter (LVDCNT) ...................................................... 354
14.3 Operation .......................................................................................................................... 354
14.3.1 Power-On Reset Circuit....................................................................................... 354
14.3.2 Low-Voltage Detection Circuit ........................................................................... 355
Section 15 Power Supply Circuit (H8/38104 Group Only) .................................... 363
15.1 When Using Internal Power Supply Step-Down Circuit .................................................. 363
15.2 When Not Using Internal Power Supply Step-Down Circuit............................................ 364
Section 16 List of Registers.............................................................................................. 365
16.1 Register Addresses (Address Order)................................................................................. 366
16.2 Register Bits ..................................................................................................................... 370
Rev. 6.00 Mar 15, 2005 page xxxviii of l
16.3 Register States in Each Operating Mode .......................................................................... 373
Section 17 Electrical Characteristics ............................................................................. 377
17.1 Absolute Maximum Ratings of H8/3802 Group
(ZTAT Version, Mask ROM Version) .............................................................................
17.2 Electrical Characteristics of H8/3802 Group (ZTAT Version, Mask ROM Version) ......
17.2.1 Power Supply Voltage and Operating Ranges .....................................................
17.2.2 DC Characteristics ...............................................................................................
17.2.3 AC Characteristics ...............................................................................................
17.2.4 A/D Converter Characteristics.............................................................................
17.2.5 LCD Characteristics.............................................................................................
17.3 Absolute Maximum Ratings of H8/38004 Group
(F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version).......
17.4 Electrical Characteristics of H8/38004 Group
(F-ZTAT Version, Mask ROM Version), H8/38002S Group (Mask ROM Version).......
17.4.1 Power Supply Voltage and Operating Ranges .....................................................
17.4.2 DC Characteristics ...............................................................................................
17.4.3 AC Characteristics ...............................................................................................
17.4.4 A/D Converter Characteristics.............................................................................
17.4.5 LCD Characteristics.............................................................................................
17.4.6 Flash Memory Characteristics .............................................................................
17.5 Absolute Maximum Ratings of H8/38104 Group
(F-ZTAT Version, Mask ROM Version) ..........................................................................
17.6 Electrical Characteristics of H8/38104 Group
(F-ZTAT Version, Mask ROM Version) ..........................................................................
17.6.1 Power Supply Voltage and Operating Ranges .....................................................
17.6.2 DC Characteristics ...............................................................................................
17.6.3 AC Characteristics ...............................................................................................
17.6.4 A/D Converter Characteristics.............................................................................
17.6.5 LCD Characteristics.............................................................................................
17.6.6 Flash Memory Characteristics .............................................................................
17.6.7 Power Supply Voltage Detection Circuit Characteristics ....................................
17.6.8 Power-On Reset Circuit Characteristics ..............................................................
17.6.9 Watchdog Timer Characteristics..........................................................................
17.7 Operation Timing..............................................................................................................
17.8 Output Load Condition .....................................................................................................
17.9 Resonator Equivalent Circuit............................................................................................
17.10 Usage Note........................................................................................................................
377
378
378
381
388
391
393
394
395
395
399
406
411
413
414
416
417
417
421
430
432
433
434
436
439
440
440
442
443
444
Appendix A Instruction Set .............................................................................................. 445
A.1
A.2
Instruction List.................................................................................................................. 445
Operation Code Map......................................................................................................... 456
Rev. 6.00 Mar 15, 2005 page xxxix of l
A.3
Number of Execution States ............................................................................................. 458
Appendix B I/O Port Block Diagrams .......................................................................... 465
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
B.9
Port 3 Block Diagrams......................................................................................................
Port 4 Block Diagrams......................................................................................................
Port 5 Block Diagram .......................................................................................................
Port 6 Block Diagram .......................................................................................................
Port 7 Block Diagram .......................................................................................................
Port 8 Block Diagram .......................................................................................................
Port 9 Block Diagrams......................................................................................................
Port A Block Diagram ......................................................................................................
Port B Block Diagrams .....................................................................................................
465
469
473
474
475
476
477
479
480
Appendix C Port States in Each Operating State ....................................................... 483
Appendix D Product Code Lineup ................................................................................. 484
Appendix E Package Dimensions................................................................................... 490
Appendix F Chip Form Specifications .......................................................................... 494
Appendix G Bonding Pad Form...................................................................................... 496
Appendix H Chip Tray Specifications .......................................................................... 497
Index
............................................................................................................................. 501
Rev. 6.00 Mar 15, 2005 page xl of l
Figures
Section 1 Overview
Figure 1.1
Internal Block Diagram of H8/3802 Group ....................................................... 4
Figure 1.2
Internal Block Diagram of H8/38004 Group ..................................................... 5
Figure 1.3
Internal Block Diagram of H8/38104 Group ..................................................... 6
Figure 1.4
Pin Arrangement of H8/3802 and H8/38004 Group (FP-64A, FP-64E)............ 7
Figure 1.5
Pin Arrangement of H8/3802 Group (DP-64S) ................................................. 8
Figure 1.6
Pin Arrangement of H8/38104 Group (FP-64A, FP-64E) ................................. 9
Figure 1.7
Pad Arrangement of HCD6433802, HCD6433801, and HCD6433800
(Top View)......................................................................................................... 10
Figure 1.8
Pad Arrangement of HCD64338004, HCD64338003, HCD64338002,
HCD64338001, and HCD64338000 (Top View) .............................................. 13
Figure 1.9
Pad Arrangement of HCD64F38004 and HCD64F38002 (Top View).............. 16
Section 2 CPU
Figure 2.1(1) H8/3802 Memory Map ......................................................................................
Figure 2.1(2) H8/3801 Memory Map ......................................................................................
Figure 2.1(3) H8/3800 Memory Map ......................................................................................
Figure 2.1(4) H8/38004, H8/38104 Memory Map ..................................................................
Figure 2.1(5) H8/38003, H8/38103 Memory Map ..................................................................
Figure 2.1(6) H8/38002, H8/38102 Memory Map ..................................................................
Figure 2.1(7) H8/38001, H8/38101 Memory Map ..................................................................
Figure 2.1(8) H8/38000, H8/38100 Memory Map ..................................................................
Figure 2.2
CPU Registers....................................................................................................
Figure 2.3
Stack Pointer......................................................................................................
Figure 2.4
General Register Data Formats..........................................................................
Figure 2.5
Memory Data Formats .......................................................................................
Figure 2.6
Instruction Formats of Data Transfer Instructions .............................................
Figure 2.7
Instruction Formats of Arithmetic, Logic, and Shift Instructions ......................
Figure 2.8
Instruction Formats of Bit Manipulation Instructions........................................
Figure 2.9
Instruction Formats of Branch Instructions .......................................................
Figure 2.10
Instruction Formats of System Control Instructions ..........................................
Figure 2.11
Instruction Format of Block Data Transfer Instructions ....................................
Figure 2.12
On-Chip Memory Access Cycle ........................................................................
Figure 2.13
On-Chip Peripheral Module Access Cycle (2-State Access) .............................
Figure 2.14
On-Chip Peripheral Module Access Cycle (3-State Access) .............................
Figure 2.15
CPU Operation States ........................................................................................
Figure 2.16
State Transitions ................................................................................................
Figure 2.17
Example of Timer Configuration with Two Registers Allocated to Same
Address ..............................................................................................................
24
25
26
27
28
29
30
31
32
33
36
37
41
44
47
49
50
51
58
59
60
61
62
63
Rev. 6.00 Mar 15, 2005 page xli of l
Section 3 Exception Handling
Figure 3.1
Reset Sequence ..................................................................................................
Figure 3.2
Stack Status after Exception Handling...............................................................
Figure 3.3
Interrupt Sequence .............................................................................................
Figure 3.4
Port Mode Register Setting and Interrupt Request Flag Clearing Procedure.....
79
81
82
85
Section 4 Clock Pulse Generators
Figure 4.1
Block Diagram of Clock Pulse Generators (H8/3802, H8/38004 Group) .........
Figure 4.2
Block Diagram of Clock Pulse Generators (H8/38104 Group) .........................
Figure 4.3
Block Diagram of System Clock Generator ......................................................
Figure 4.4(1) Typical Connection to Crystal Resonator (H8/3802 Group) .............................
Figure 4.4(2) Typical Connection to Crystal Resonator (H8/38004, H8/38104 Group)..........
Figure 4.5
Equivalent Circuit of Crystal Resonator ............................................................
Figure 4.6(1) Typical Connection to Ceramic Resonator (H8/3802 Group) ...........................
Figure 4.6(2) Typical Connection to Ceramic Resonator (H8/38004, H8/38104 Group)........
Figure 4.7
Example of External Clock Input ......................................................................
Figure 4.8
Block Diagram of Subclock Generator..............................................................
Figure 4.9
Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator ......................
Figure 4.10
Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator ........................
Figure 4.11
Pin Connection when Not Using Subclock........................................................
Figure 4.12
Pin Connection when Inputting External Clock.................................................
Figure 4.13
Example of Crystal and Ceramic Resonator Arrangement ................................
Figure 4.14
Negative Resistor Measurement and Proposed Changes in Circuit...................
Figure 4.15
Example of Incorrect Board Design ..................................................................
Figure 4.16
Oscillation Stabilization Standby Time .............................................................
87
88
90
90
91
91
91
92
92
93
93
94
94
94
96
97
97
98
Section 5 Power-Down Modes
Figure 5.1
Mode Transition Diagram.................................................................................. 107
Figure 5.2
Standby Mode Transition and Pin States ........................................................... 117
Figure 5.3
External Input Signal Capture when Signal Changes before/after
Standby Mode or Watch Mode.......................................................................... 118
Section 6 ROM
Figure 6.1
Block Diagram of ROM (H8/3802)...................................................................
Figure 6.2
Socket Adapter Pin Correspondence (with HN27C101) ...................................
Figure 6.3
H8/3802 Memory Map in PROM Mode............................................................
Figure 6.4
High-Speed, High-Reliability Programming Flowchart ....................................
Figure 6.5
PROM Write/Verify Timing..............................................................................
Figure 6.6
Recommended Screening Procedure .................................................................
Figure 6.7
Block Diagram of Flash Memory ......................................................................
Figure 6.8(1) Block Configuration of 32-kbyte Flash Memory...............................................
Figure 6.8(2) Block Configuration of 16-kbyte Flash Memory...............................................
Rev. 6.00 Mar 15, 2005 page xlii of l
119
121
122
124
127
128
130
131
132
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12(1)
Figure 6.12(2)
Figure 6.13
Figure 6.14
Figure 6.15
Figure 6.16
Figure 6.17
Figure 6.18
Figure 6.19
Figure 6.20
Programming/Erasing Flowchart Example in User Program Mode ..................
Program/Program-Verify Flowchart..................................................................
Erase/Erase-Verify Flowchart............................................................................
Socket Adapter Pin Correspondence Diagram (H8/38004F, H8/38002F).........
Socket Adapter Pin Correspondence Diagram (H8/38104F, H8/38102F).........
Timing Waveforms for Memory Read after Command Write...........................
Timing Waveforms in Transition from Memory Read Mode to
Another Mode....................................................................................................
Timing Waveforms in CE and OE Enable State Read.......................................
Timing Waveforms in CE and OE Clock System Read ....................................
Timing Waveforms in Auto-Program Mode......................................................
Timing Waveforms in Auto-Erase Mode...........................................................
Timing Waveforms in Status Read Mode..........................................................
Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence ...............................................................................
140
142
145
148
149
150
151
152
152
154
155
156
158
Section 7 RAM
Figure 7.1
Block Diagram of RAM (H8/3802)................................................................... 162
Section 8 I/O Ports
Figure 8.1
Port 3 Pin Configuration ....................................................................................
Figure 8.2
Port 4 Pin Configuration ....................................................................................
Figure 8.3
Input/Output Data Inversion Function ...............................................................
Figure 8.4
Port 5 Pin Configuration ....................................................................................
Figure 8.5
Port 6 Pin Configuration ....................................................................................
Figure 8.6
Port 7 Pin Configuration ....................................................................................
Figure 8.7
Port 8 Pin Configuration ....................................................................................
Figure 8.8
Port 9 Pin Configuration ....................................................................................
Figure 8.9
Port A Pin Configuration ...................................................................................
Figure 8.10
Port B Pin Configuration ...................................................................................
165
172
173
176
180
184
186
188
190
192
Section 9 Timers
Figure 9.1
Block Diagram of Timer A................................................................................ 200
Figure 9.2
Block Diagram of Timer F................................................................................. 204
Figure 9.3
Write Access to TCF (CPU → TCF) ................................................................. 210
Figure 9.4
Read Access to TCF (TCF → CPU).................................................................. 211
Figure 9.5
TMOFH/TMOFL Output Timing ...................................................................... 213
Figure 9.6
Clear Interrupt Request Flag when Interrupt Source Generation Signal is
Valid .................................................................................................................. 217
Figure 9.7
Block Diagram of Asynchronous Event Counter............................................... 219
Figure 9.8
Example of Software Processing when Using ECH and ECL as
16-Bit Event Counter ......................................................................................... 228
Rev. 6.00 Mar 15, 2005 page xliii of l
Figure 9.9
Example of Software Processing when Using ECH and ECL as
8-Bit Event Counters .........................................................................................
Figure 9.10
Event Counter Operation Waveform .................................................................
Figure 9.11
Example of Clock Control Operation ................................................................
Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004 Group)....................................
Figure 9.12(2) Block Diagram of Watchdog Timer (H8/38104 Group)....................................
Figure 9.13
Example of Watchdog Timer Operation............................................................
Section 10 Serial Communication Interface 3 (SCI3)
Figure 10.1
Block Diagram of SCI3 .....................................................................................
Figure 10.2
Data Format in Asynchronous Communication.................................................
Figure 10.3
Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) .......
Figure 10.4
Sample SCI3 Initialization Flowchart................................................................
Figure 10.5
Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)......................................................................
Figure 10.6
Sample Serial Transmission Flowchart (Asynchronous Mode).........................
Figure 10.7
Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)......................................................................
Figure 10.8
Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)................
Figure 10.8
Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)................
Figure 10.9
Data Format in Clocked Synchronous Communication.....................................
Figure 10.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode..
Figure 10.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode).............
Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode ...........
Figure 10.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)..................
Figure 10.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode) ...........................................................................
Figure 10.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H’AA to Receiving Station A) ......................................
Figure 10.16 Sample Multiprocessor Serial Transmission Flowchart ....................................
Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (1) ....................................
Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (2) ....................................
Figure 10.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ..........................
Figure 10.19(a) RDRF Setting and RXI Interrupt .......................................................................
Figure 10.19(b) TDRE Setting and TXI Interrupt .......................................................................
Figure 10.19(c) TEND Setting and TEI Interrupt .......................................................................
Figure 10.20 Receive Data Sampling Timing in Asynchronous Mode...................................
Figure 10.21 Relation between RDR Read Timing and Data .................................................
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230
231
234
235
238
242
256
257
261
262
263
265
266
267
268
269
270
271
272
273
275
276
277
278
279
281
282
282
284
285
Section 11 10-Bit PWM
Figure 11.1(1) Block Diagram of 10-Bit PWM (H8/3802 Group, H8/38004 Group) ............... 287
Figure 11.1(2) Block Diagram of 10-Bit PWM (H8/38104 Group) .......................................... 288
Figure 11.2
Waveform Output by 10-Bit PWM.................................................................... 291
Section 12 A/D Converter
Figure 12.1
Block Diagram of A/D Converter......................................................................
Figure 12.2
Example of A/D Conversion Operation.............................................................
Figure 12.3
Flowchart of Procedure for Using A/D Converter (Polling by Software)..........
Figure 12.4
Flowchart of Procedure for Using A/D Converter (Interrupts Used).................
Figure 12.5
A/D Conversion Accuracy Definitions (1) ........................................................
Figure 12.6
A/D Conversion Accuracy Definitions (2) ........................................................
Figure 12.7
Example of Analog Input Circuit.......................................................................
294
299
300
300
301
302
303
Section 13 LCD Controller/Driver
Figure 13.1(1) Block Diagram of LCD Controller/Driver
(H8/3802 Group, H8/38004 Group) ..................................................................
Figure 13.1(2) Block Diagram of LCD Controller/Driver (H8/38104 Group) ..........................
Figure 13.2
Handling of LCD Drive Power Supply when Using 1/2 Duty...........................
Figure 13.3
LCD RAM Map (1/4 Duty) ...............................................................................
Figure 13.4
LCD RAM Map (1/3 Duty) ...............................................................................
Figure 13.5
LCD RAM Map (1/2 Duty) ...............................................................................
Figure 13.6
LCD RAM Map (Static Mode) ..........................................................................
Figure 13.7
Output Waveforms for Each Duty Cycle (A Waveform) ..................................
Figure 13.8
Output Waveforms for Each Duty Cycle (B Waveform)...................................
Figure 13.9
Connection of External Split-Resistance ...........................................................
306
307
314
315
316
316
317
318
319
321
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Figure 14.1
Block Diagram of Power-On Reset Circuit and Low-Voltage Detection
Circuit ................................................................................................................ 324
Figure 14.2
Operational Timing of Power-On Reset Circuit ................................................ 328
Figure 14.3
Operational Timing of LVDR Circuit................................................................ 329
Figure 14.4
Operational Timing of LVDI Circuit ................................................................. 330
Figure 14.5
Operational Timing of Low-Voltage Detection Interrupt Circuit
(Using Pins Vref, extD, and extU)..................................................................... 331
Figure 14.6
LVD Function Usage Example Employing Pins Vref, extD, and extU ............. 332
Figure 14.7
Timing for Operation/Release of Low-Voltage Detection Circuit..................... 334
Section 15 Power Supply Circuit (H8/38104 Group Only)
Figure 15.1
Power Supply Connection when Internal Step-Down Circuit is Used............... 335
Figure 15.2
Power Supply Connection when Internal Step-Down Circuit is Not Used........ 336
Rev. 6.00 Mar 15, 2005 page xlv of l
Section 17 Electrical Characteristics
Figure 17.1
Clock Input Timing............................................................................................
RES Low Width Timing ....................................................................................
Figure 17.2
Figure 17.3
Input Timing ......................................................................................................
Figure 17.4
SCK3 Input Clock Timing.................................................................................
Figure 17.5
SCI3 Input/Output Timing in Clocked Synchronous Mode ..............................
Figure 17.6
Output Load Circuit...........................................................................................
Figure 17.7
Resonator Equivalent Circuit.............................................................................
Figure 17.8
Resonator Equivalent Circuit.............................................................................
Appendices
Figure B.1(a)
Figure B.1(b)
Figure B.1(c)
Figure B.1(d)
Figure B.2(a)
Figure B.2(b)
Figure B.2(c)
Figure B.2(d)
Figure B.3
Figure B.4
Figure B.5
Figure B.6
Figure B.7(a)
Figure B.7(b)
Figure B.8
Figure B.9
Figure E.1
Figure E.2
Figure E.3
Figure F.1
Figure F.2
Figure F.3
Figure G.1
Figure H.1
Figure H.2
Figure H.3
Port 3 Block Diagram (Pins P37 and P36).........................................................
Port 3 Block Diagram (Pin P35) ........................................................................
Port 3 Block Diagram (Pins P34 and P33).........................................................
Port 3 Block Diagram (Pins P32 and P31).........................................................
Port 4 Block Diagram (Pin P43) ........................................................................
Port 4 Block Diagram (Pin P42) ........................................................................
Port 4 Block Diagram (Pin P41) ........................................................................
Port 4 Block Diagram (Pin P40) ........................................................................
Port 5 Block Diagram ........................................................................................
Port 6 Block Diagram ........................................................................................
Port 7 Block Diagram ........................................................................................
Port 8 Block Diagram (Pin P80) ........................................................................
Port 9 Block Diagram (Pins P91 and P90).........................................................
Port 9 Block Diagram (Pins P95 to P92) ...........................................................
Port A Block Diagram .......................................................................................
Port B Block Diagram........................................................................................
Package Dimensions (FP-64A)..........................................................................
Package Dimensions (FP-64E) ..........................................................................
Package Dimensions (DP-64S)..........................................................................
Cross-Sectional View of Chip
(HCD6433802, HCD6433801, and HCD6433800)...........................................
Cross-Sectional View of Chip (HCD64338004, HCD64338003,
HCD64338002, HCD64338001, and HCD64338000) ......................................
Cross-Sectional View of Chip (HCD64F38004 and HCD64F38002) ...............
Bonding Pad Form (HCD6433802, HCD6433801, HCD6433800,
HCD64338004, HCD64338003, HCD64338002, HCD64338001,
HCD64338000, HCD64F38004, and HCD64F38002)......................................
Chip Tray Specifications (HCD6433802, HCD6433801, and HCD6433800) ..
Chip Tray Specifications (HCD64338004, HCD64338003, HCD64338002,
HCD64338001, and HCD64338000).................................................................
Chip Tray Specifications (HCD64F38004 and HCD64F38002) .......................
Rev. 6.00 Mar 15, 2005 page xlvi of l
408
408
408
409
409
409
410
410
433
434
434
435
435
436
437
438
439
440
441
442
442
443
443
444
451
452
453
454
454
455
456
457
458
459
Tables
Section 1 Overview
Table 1.1
Pad Coordinate of HCD6433802, HCD6433801, and HCD6433800 ....................
Table 1.2
Pad Coordinate of HCD64338004, HCD64338003, HCD64338002,
HCD64338001, and HCD64338000 ......................................................................
Table 1.3
Pad Coordinate of HCD64F38004 and HCD64F38002 .........................................
Table 1.4
Pin Functions..........................................................................................................
Section 2 CPU
Table 2.1
Instruction Set ........................................................................................................
Table 2.2
Operation Notation.................................................................................................
Table 2.3
Data Transfer Instructions......................................................................................
Table 2.4
Arithmetic Operations Instructions ........................................................................
Table 2.5
Logic Operations Instructions ................................................................................
Table 2.6
Shift Instructions ....................................................................................................
Table 2.7
Bit Manipulation Instructions (1)...........................................................................
Table 2.7
Bit Manipulation Instructions (2)...........................................................................
Table 2.8
Branch Instructions ................................................................................................
Table 2.9
System Control Instructions ...................................................................................
Table 2.10 Block Data Transfer Instructions ...........................................................................
Table 2.11 Addressing Modes..................................................................................................
Table 2.12 Effective Address Calculation................................................................................
Table 2.13 Registers with Shared Addresses ...........................................................................
Table 2.14 Registers with Write-Only Bits ..............................................................................
11
14
17
19
38
39
40
42
43
43
45
46
48
50
51
52
55
68
68
Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address ................................................................. 71
Table 3.2
Interrupt Wait States .............................................................................................. 81
Table 3.3
Conditions under which Interrupt Request Flag is Set to 1.................................... 83
Section 4 Clock Pulse Generators
Table 4.1
Crystal Resonator Parameters ................................................................................ 91
Table 4.2
System Clock Oscillator and On-Chip Oscillator Selection Methods.................... 93
Section 5 Power-Down Modes
Table 5.1(1) Operating Frequency and Waiting Time (H8/3802 Group, H8/38004 Group) ......
Table 5.1(2) Operating Frequency and Waiting Time (H8/38104 Group) .................................
Table 5.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling .......
Table 5.3
Internal State in Each Operating Mode ..................................................................
103
103
108
109
Rev. 6.00 Mar 15, 2005 page xlvii of l
Section 6 ROM
Table 6.1
Setting to PROM Mode..........................................................................................
Table 6.2
Mode Selection in PROM Mode (H8/3802) ..........................................................
Table 6.3
DC Characteristics .................................................................................................
Table 6.4
AC Characteristics .................................................................................................
Table 6.5
Setting Programming Modes..................................................................................
Table 6.6
Boot Mode Operation.............................................................................................
Table 6.7
Oscillation Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible (fOSC) ........................................................................................................
Table 6.8
Reprogram Data Computation Table .....................................................................
Table 6.9
Additional-Program Data Computation Table .......................................................
Table 6.10 Programming Time ................................................................................................
Table 6.11 Command Sequence in Programmer Mode............................................................
Table 6.12 AC Characteristics in Transition to Memory Read Mode......................................
Table 6.13 AC Characteristics in Transition from Memory Read Mode to Another Mode.....
Table 6.14 AC Characteristics in Memory Read Mode ...........................................................
Table 6.15 AC Characteristics in Auto-Program Mode ...........................................................
Table 6.16 AC Characteristics in Auto-Erase Mode................................................................
Table 6.17 AC Characteristics in Status Read Mode ...............................................................
Table 6.18 Return Codes in Status Read Mode........................................................................
Table 6.19 Status Polling Output .............................................................................................
Table 6.20 Stipulated Transition Times to Command Wait State............................................
Table 6.21 Flash Memory Operating States.............................................................................
120
123
125
126
136
138
139
143
143
143
147
150
151
151
153
155
156
157
157
158
159
Section 8 I/O Ports
Table 8.1
Port Functions ........................................................................................................ 163
Section 9 Timers
Table 9.1
Timer Functions .....................................................................................................
Table 9.2
Timer A Operating States.......................................................................................
Table 9.3
Pin Configuration...................................................................................................
Table 9.4
Timer F Operating States .......................................................................................
Table 9.5
Pin Configuration...................................................................................................
Table 9.6
Examples of Event Counter PWM Operation ........................................................
Table 9.7
Operating States of Asynchronous Event Counter.................................................
Table 9.8(1) Operating States of Watchdog Timer (H8/38004 Group) ......................................
Table 9.8(2) Operating States of Watchdog Timer (H8/38104 Group) ......................................
198
202
204
214
220
231
232
239
239
Section 10 Serial Communication Interface 3 (SCI3)
Table 10.1 Pin Configuration................................................................................................... 243
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ....... 251
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ....... 252
Rev. 6.00 Mar 15, 2005 page xlviii of l
Table 10.3
Table 10.4
Table 10.5
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.10
Table 10.11
Table 10.12
Relation between n and Clock................................................................................
Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) ................
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) ................
Relation between n and Clock................................................................................
Data Transfer Formats (Asynchronous Mode).......................................................
SMR Settings and Corresponding Data Transfer Formats .....................................
SMR and SCR3 Settings and Clock Source Selection ...........................................
SSR Status Flags and Receive Data Handling .......................................................
SCI3 Interrupt Requests .........................................................................................
Transmit/Receive Interrupts...................................................................................
252
253
253
254
255
258
259
260
265
280
281
Section 11 10-Bit PWM
Table 11.1 Pin Configuration................................................................................................... 288
Table 11.2 PWM Operating States........................................................................................... 292
Section 12 A/D Converter
Table 12.1 Pin Configuration................................................................................................... 295
Table 12.2 Operating States of A/D Converter ........................................................................ 297
Section 13 LCD Controller/Driver
Table 13.1 Pin Configuration...................................................................................................
Table 13.2 Duty Cycle and Common Function Selection ........................................................
Table 13.3 Segment Driver Selection ......................................................................................
Table 13.4 Frame Frequency Selection....................................................................................
Table 13.5 Output Levels .........................................................................................................
Table 13.6 Power-Down Modes and Display Operation..........................................................
308
310
310
312
320
321
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Table 14.1 LVDCR Settings and Select Functions .................................................................. 326
Section 17 Electrical Characteristics
Table 17.1 Absolute Maximum Ratings...................................................................................
Table 17.2 DC Characteristics (1)............................................................................................
Table 17.2 DC Characteristics (2)............................................................................................
Table 17.2 DC Characteristics (3)............................................................................................
Table 17.2 DC Characteristics (4)............................................................................................
Table 17.2 DC Characteristics (5)............................................................................................
Table 17.2 DC Characteristics (6)............................................................................................
Table 17.3 Control Signal Timing............................................................................................
Table 17.4 Serial Interface (SCI3) Timing...............................................................................
Table 17.5 A/D Converter Characteristics ...............................................................................
347
351
352
353
354
355
356
358
360
360
Rev. 6.00 Mar 15, 2005 page xlix of l
Table 17.6
Table 17.7
Table 17.8
Table 17.9
Table 17.10
Table 17.11
Table 17.12
Table 17.13
Table 17.14
Table 17.15
Table 17.15
Table 17.15
Table 17.15
Table 17.15
Table 17.16
Table 17.17
Table 17.18
Table 17.19
Table 17.20
Table 17.21
Table 17.22
Table 17.23
Table 17.24
Table 17.25
Table 17.26
Table 17.27
LCD Characteristics...............................................................................................
Absolute Maximum Ratings ..................................................................................
DC Characteristics .................................................................................................
Control Signal Timing............................................................................................
Serial Interface (SCI3) Timing...............................................................................
A/D Converter Characteristics ...............................................................................
LCD Characteristics...............................................................................................
Flash Memory Characteristics................................................................................
Absolute Maximum Ratings ..................................................................................
DC Characteristics (1)............................................................................................
DC Characteristics (2)............................................................................................
DC Characteristics (3)............................................................................................
DC Characteristics (4)............................................................................................
DC Characteristics (5)............................................................................................
Control Signal Timing............................................................................................
Serial Interface (SCI3) Timing...............................................................................
A/D Converter Characteristics ...............................................................................
LCD Characteristics...............................................................................................
Flash Memory Characteristics................................................................................
Power Supply Voltage Detection Circuit Characteristics (1).................................
Power Supply Voltage Detection Circuit Characteristics (2).................................
Power Supply Voltage Detection Circuit Characteristics (3).................................
Power Supply Voltage Detection Circuit Characteristics (4).................................
Power Supply Voltage Detection Circuit Characteristics (5).................................
Power-On Reset Circuit Characteristics.................................................................
Watchdog Timer Characteristics............................................................................
362
363
368
375
378
379
381
382
384
389
390
391
392
393
398
399
400
401
402
404
404
405
406
407
407
408
Appendices
Table A.1
Table A.2
Table A.3
Table A.4
Table C.1
Table D.1
Table D.2
Table D.3
Instruction Set ........................................................................................................
Operation Code Map..............................................................................................
Number of States Required for Execution .............................................................
Number of Cycles in Each Instruction ...................................................................
Port States ..............................................................................................................
Product Code Lineup of H8/3802 Group ...............................................................
Product Code Lineup of H8/38004 Group .............................................................
Product Code Lineup of H8/38104 Group .............................................................
415
425
427
427
445
446
447
449
Rev. 6.00 Mar 15, 2005 page l of l
Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8/300L central processing unit
Complete instruction set compatibility with H8/300 CPU
Sixteen 8-bit general registers (Can be used as eight 16-bit general registers)
55 basic instructions
• Various peripheral functions
Timer A (can be used as a time base for a clock)
Timer F (16-bit timer)
Asynchronous event counter (16-bit timer)
Watchdog timer (WDT) (H8/38004, H8/38002S Group and H8/38104 Group only)
SCI3 (Asynchronous or clocked synchronous serial communication interface)
10-bit PWM
10-bit A/D converter
LCD controller/driver
Power-on reset and low-voltage detect circuits (H8/38104 Group only)
Rev. 6.00 Mar 15, 2005 page 1 of 502
REJ09B0024-0600
Section 1 Overview
• On-chip memory
Product Classification
Model
ROM
RAM
H8/38004
HD64F38004
32 kbytes
1 kbyte
H8/38002
HD64F38002
16 kbytes
1 kbyte
H8/38104
HD64F38104
32 kbytes
1 kbyte
H8/38102
HD64F38102
16 kbytes
1 kbyte
PROM version
(ZTATTM version*2)
H8/3802
HD6473802
16 kbytes
1 kbyte
Mask ROM version
H8/3802
HD6433802
16 kbytes
1 kbyte
H8/3801
HD6433801
12 kbytes
512 bytes
Flash memory version
(F-ZTATTM version*1)
H8/3800
HD6433800
8 kbytes
512 bytes
H8/38004
HD64338004
32 kbytes
1 kbyte
H8/38003
HD64338003
24 kbytes
1 kbyte
H8/38002
HD64338002
16 kbytes
1 kbyte
H8/38001
HD64338001
12 kbytes
512 bytes
H8/38000
HD64338000
8 kbytes
512 bytes
H8/38002S
HD64338002S
16 kbytes
512 bytes
H8/38001S
HD64338001S
12 kbytes
512 bytes
H8/38000S
HD64338000S
8 kbytes
512 bytes
H8/38104
HD64338104
32 kbytes
1 kbyte
H8/38103
HD64338103
24 kbytes
1 kbyte
H8/38102
HD64338102
16 kbytes
1 kbyte
H8/38101
HD64338101
12 kbytes
512 bytes
H8/38100
HD64338100
8 kbytes
512 bytes
Notes: 1. F-ZTAT is a trademark of Renesas Technology Corp.
2. ZTAT is a trademark of Renesas Technology Corp.
• General I/O ports
I/O pins: 39 I/O pins
Input-only pins: 5 input pins
Output-only pins: 6 output pins (5 pins on H8/38104 Group)
• Supports various power-down modes
Rev. 6.00 Mar 15, 2005 page 2 of 502
REJ09B0024-0600
Section 1 Overview
• Compact package
Package
Code
Body Size
Pin Pitch
QFP-64
FP-64A
14.0 × 14.0 mm
0.8 mm
LQFP-64
FP-64E
LQFP-64
FP-64K*
DP-64S
DP-64S
17.0 × 57.6 mm
1.0 mm
Die



10.0 × 10.0 mm
10.0 × 10.0 mm
0.5 mm
0.5 mm
The DP-64S package is only for the H8/3802 Group.
The chip is not supported by the H8/38104 Group.
Note: * Under development. The package dimensions of the FP-64K and FP-64E differ. For details,
see appendix E, Package Dimensions.
Rev. 6.00 Mar 15, 2005 page 3 of 502
REJ09B0024-0600
Section 1 Overview
Internal Block Diagram
OSC1
OSC2
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Port 3
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Port 4
System clock oscillator
Vss
Vss = AVss
Vcc
RES
TEST
H8/300L
CPU
Subclock oscillator
RAM
Port A
x1
x2
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port 8
Port 5
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
Timer A
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
10-bit PWM1
Timer F
Port 6
LCD
power
supply
10-bit PWM2
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
RAM
AVcc
LCD
controller/driver
P95
P94
P93
P92
P91/PWM2
P90/PWM1
Port 7
Asynchronous
event counter
(AEC)
Port 9
IRQAEC
ROM
Port B
1.2
V1
V2
V3
PB3/AN3/IRQ1
PB2/AN2
PB1/AN1
PB0/AN0
10-bit A/D converter
Large-current (25 mA/pin) high-voltage open-drain pin (7 V)
Large-current (10 mA/pin) high-voltage open-drain pin (7 V)
High-voltage (7 V) input pin
Figure 1.1 Internal Block Diagram of H8/3802 Group
Rev. 6.00 Mar 15, 2005 page 4 of 502
REJ09B0024-0600
Section 1 Overview
OSC1
OSC2
Port 3
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Port 4
System clock oscillator
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Vss
Vss = AVss
Vcc
RES
TEST
H8/300L
CPU
Subclock oscillator
RAM
Port A
x1
x2
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
IRQAEC
Timer A
Port 9
Port 8
Asynchronous
event counter
(AEC)
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
10-bit PWM1
Timer F
SCI3
LCD
controller/driver
AVcc
Port B
Port 6
WDT
LCD
power
supply
10-bit PWM2
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
P95
P94
P93
P92
P91/PWM2
P90/PWM1
Port 7
Port 5
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
ROM
V1
V2
V3
PB3/AN3/IRQ1
PB2/AN2
PB1/AN1
PB0/AN0
10-bit A/D converter
Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because
they are used exclusively by the on-chip emulator.
Figure 1.2 Internal Block Diagram of H8/38004 Group
Rev. 6.00 Mar 15, 2005 page 5 of 502
REJ09B0024-0600
Section 1 Overview
OSC1
OSC2
System clock oscillator
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
CVcc
Vss
Vss = AVss
Vcc
RES
TEST
H8/300L
CPU
Subclock oscillator
RAM
Port A
x1
x2
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port 9
Port 5
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
Timer A
Power-on reset
and low-voltage
detection circuit
P95
P93/Vref
P92
P91/PWM2
P90/PWM1
Port 8
Port 4
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
Asynchronous
event counter
(AEC)
P80/SEG25
Port 7
Port 3
IRQAEC
ROM
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
10-bit PWM1
Timer F
Port 6
WDT
SCI3
LCD
controller/driver
AVcc
Port B
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
LCD
power
supply
10-bit PWM2
V1
V2
V3
PB3/AN3/IRQ1
PB2/AN2
PB1/AN1/extU
PB0/AN0/extD
10-bit A/D converter
: Large current (15 mA) pin
Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because
they are used exclusively by the on-chip emulator.
Figure 1.3 Internal Block Diagram of H8/38104 Group
Rev. 6.00 Mar 15, 2005 page 6 of 502
REJ09B0024-0600
Section 1 Overview
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Pin Arrangement
P90/PWM1
49
32
P70/SEG17
P91/PWM2
50
31
P71/SEG18
P92
51
30
P72/SEG19
P93
52
29
P73/SEG20
P94
53
28
P74/SEG21
P95
54
27
P75/SEG22
Vss
55
26
P76/SEG23
IRQAEC
56
25
P77/SEG24
P40/SCK32
57
24
P80/SEG25
P41/RXD32
58
23
PA0/COM1
P42/TXD32
59
22
PA1/COM2
P43/IRQ0
60
21
PA2/COM3
AVcc
61
20
PA3/COM4
PB0/AN0
62
19
V3
PB1/AN1
63
18
V2
PB2/AN2
64
17
V1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X1
X2
Vss=AVss
OSC2
OSC1
TEST
RES
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Vcc
FP-64A, FP-64E, FP-64K
(Top view)
PB3/IRQ1/AN3
1.3
Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because
they are used exclusively by the on-chip emulator.
Figure 1.4 Pin Arrangement of H8/3802, H8/38004 and H8/38002S Group
(FP-64A, FP-64E, FP-64K)
Rev. 6.00 Mar 15, 2005 page 7 of 502
REJ09B0024-0600
Section 1 Overview
P40/SCK32
1
64
IRQAEC
P41/RXD32
2
63
Vss
P42/TXD32
3
62
P95
4
61
P94
AVcc
5
60
P93
PB0/AN0
6
59
P92
PB1/AN1
7
58
P91/PWM2
PB2/AN2
8
57
P90/PWM1
/AN3
9
56
P50/
/SEG1
X1
10
55
P51/
/SEG2
X2
11
54
P52/
/SEG3
VSS=AVSS
12
53
P53/
/SEG4
OSC2
13
52
P54/
/SEG5
OSC1
14
51
P55/
/SEG6
TEST
15
50
P56/
/SEG7
49
P57/
/SEG8
48
P60/SEG9
P43/
PB3/
16
DP-64S
(Top view)
P31/TMOFL
17
P32/TMOFH
18
47
P61/SEG10
P33
19
46
P62/SEG11
P34
20
45
P63/SEG12
P35
21
44
P64/SEG13
P36/AEVH
22
43
P65/SEG14
P37/AEVL
23
42
P66/SEG15
Vcc
24
41
P67/SEG16
V1
25
40
P70/SEG17
V2
26
39
P71/SEG18
V3
27
38
P72/SEG19
PA3/COM4
28
37
P73/SEG20
PA2/COM3
29
36
P74/SEG21
PA1/COM2
30
35
P75/SEG22
PA0/COM1
31
34
P76/SEG23
P80/SEG25
32
33
P77/SEG24
Figure 1.5 Pin Arrangement of H8/3802 Group (DP-64S)
Rev. 6.00 Mar 15, 2005 page 8 of 502
REJ09B0024-0600
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P60/SEG9
P61/SEG10
P62/SEG11
P63/SEG12
P64/SEG13
P65/SEG14
P66/SEG15
P67/SEG16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Section 1 Overview
P90/PWM1
49
32
P70/SEG17
P91/PWM2
50
31
P71/SEG18
P92
51
30
P72/SEG19
P93/Vref
52
29
P73/SEG20
CVcc
53
28
P74/SEG21
P95
54
27
P75/SEG22
Vss
55
26
P76/SEG23
IRQAEC
56
25
P77/SEG24
P40/SCK32
57
24
P80/SEG25
P41/RXD32
58
23
PA0/COM1
P42/TXD32
59
22
PA1/COM2
P43/IRQ0
60
21
PA2/COM3
AVcc
61
20
PA3/COM4
PB0/AN0/extD
62
19
V3
PB1/AN1/extU
63
18
V2
PB2/AN2
64
17
V1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PB3/IRQ1/AN3
X1
X2
Vss=AVss
OSC2
OSC1
TEST
RES
P31/TMOFL
P32/TMOFH
P33
P34
P35
P36/AEVH
P37/AEVL
Vcc
FP-64A, FP-64E
(Top view)
Note: When the on-chip emulator is used, pins P95, P33, P34, and P35 are unavailable to the user because
they are used exclusively by the on-chip emulator.
Figure 1.6 Pin Arrangement of H8/38104 Group (FP-64A, FP-64E)
Rev. 6.00 Mar 15, 2005 page 9 of 502
REJ09B0024-0600
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Section 1 Overview
Model
name
1
49
2
48
3
47
4
46
5
6
Y
7
45
8
44
43
9
10
42
X
(0, 0)
11
41
12
40
13
39
14
38
37
15
36
16
35
17
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
34
Chip size: 3.60 mm × 3.73 mm
Voltage level on the back of the chip: GND
Figure 1.7 Pad Arrangement of HCD6433802, HCD6433801, and HCD6433800 (Top View)
Rev. 6.00 Mar 15, 2005 page 10 of 502
REJ09B0024-0600
Section 1 Overview
Table 1.1
Pad Coordinate of HCD6433802, HCD6433801, and HCD6433800
Coordinate
Pad
No.
Pad Name
X (µ
µm)
1
PB3/IRQ1/AN3
2
Coordinate
Y (µ
µm)
Pad
No.
Pad Name
X (µ
µm)
Y (µ
µm)
-1677
1495
32
P71/SEG18
1400
-1742
X1
-1677
1084
33
P70/SEG17
1578
-1742
3
X2
-1677
943
34
P67/SEG16
1677
-1401
4
AVss
-1677
765
35
P66/SEG15
1677
-1190
5
Vss
-1677
619
36
P65/SEG14
1677
-950
6
OSC2
-1677
488
37
P64/SEG13
1677
-801
7
OSC1
-1677
356
38
P63/SEG12
1677
-608
8
TEST
-1677
225
39
P62/SEG11
1677
-459
9
RES
-1677
94
40
P61/SEG10
1677
-310
10
P31/TMOFL
-1677
-40
41
P60/SEG9
1677
-160
11
P32/TMOFH
-1677
-176
42
P57/WKP7/SEG8
1677
-11
12
P33
-1677
-313
43
P56/WKP6/SEG7
1677
121
13
P34
-1677
-450
44
P55/WKP5/SEG6
1677
252
14
P35
-1677
-587
45
P54/WKP4/SEG5
1677
383
15
P36/AEVH
-1677
-943
46
P53/WKP3/SEG4
1677
801
16
P37/AEVL
-1677
-1083
47
P52/WKP2/SEG3
1677
950
17
Vcc
-1677
-1404
48
P51/WKP1/SEG2
1677
1190
18
V1
-1578
-1742
49
P50/WKP0/SEG1
1677
1402
19
V2
-1339
-1742
50
P90/PWM1
1578
1742
20
V3
-1193
-1742
51
P91/PWM2
1411
1742
21
PA3/COM4
-1049
-1742
52
P92
1193
1742
22
PA2/COM3
-850
-1742
53
P93
1051
1742
23
PA1/COM2
-400
-1742
54
P94
850
1742
24
PA0/COM1
-200
-1742
55
P95
650
1742
25
P80/SEG25
0
-1742
56
Vss
400
1742
26
P77/SEG24
320
-1742
57
IRQAEC
200
1742
27
P76/SEG23
451
-1742
58
P40/SCK32
-298
1742
28
P75/SEG22
583
-1742
59
P41/RXD32
-435
1742
29
P74/SEG21
850
-1742
60
P42/TXD32
-572
1742
30
P73/SEG20
1051
-1742
61
P43/IRQ0
-752
1742
31
P72/SEG19
1193
-1742
62
AVcc
-1036
1742
Rev. 6.00 Mar 15, 2005 page 11 of 502
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Section 1 Overview
Coordinate
Pad
No.
Pad Name
X (µ
µm)
63
PB0/AN0
64
PB1/AN1
Coordinate
Y (µ
µm)
Pad
No.
Pad Name
X (µ
µm)
Y (µ
µm)
-1170
1742
65
PB2/AN2
-1578
1742
-1400
1742
Note: The power supply (Vss) pads in pad numbers 4, 5, and 56 must not be open but connected.
The TEST pad in pad number 8 must be connected to the Vss voltage level. If not, this LSI
does not operate correctly. The coordinate values indicate center positions of pads and the
accuracy is ±5 µm. The home-point position is center of the chip and the center is located at
half the distance between the upper and lower pads and left and right pads.
Rev. 6.00 Mar 15, 2005 page 12 of 502
REJ09B0024-0600
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Section 1 Overview
1
48
47
2
46
3
45
4
44
5
43
Y
42
6
41
7
8
(0, 0)
9
40
X
10
39
11
12
38
13
14
37
36
15
35
16
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Model name
Chip size: 2.73 mm × 3.27 mm
Voltage level on the back of the chip: GND
: NC pad
Figure 1.8 Pad Arrangement of HCD64338004, HCD64338003, HCD64338002,
HCD64338001, and HCD64338000 (Top View)
Rev. 6.00 Mar 15, 2005 page 13 of 502
REJ09B0024-0600
Section 1 Overview
Table 1.2
Pad Coordinate of HCD64338004, HCD64338003, HCD64338002,
HCD64338001, and HCD64338000
Coordinate
Pad
No.
Pad Name
X (µ
µm)
1
PB3/IRQ1/AN3
2
Coordinate
Y (µ
µm)
Pad
No.
Pad Name
X (µ
µm)
Y (µ
µm)
-1224
1214
30
P72/SEG19
667
-1484
X1
-1224
957
31
P71/SEG18
790
-1484
3
X2
-1224
786
32
P70/SEG17
913
-1484
4
Vss = AVss
-1224
596
33
P67/SEG16
1215
-1194
5
OSC2
-1224
406
34
P66/SEG15
1215
-1080
6
OSC1
-1224
234
35
P65/SEG14
1215
-909
7
TEST
-1224
120
36
P64/SEG13
1215
-738
8
RES
-1224
6
37
P63/SEG12
1215
-566
9
P31/TMOFL
-1224
-108
38
P62/SEG11
1215
-395
10
P32/TMOFH
-1224
-222
39
P61/SEG10
1215
-224
11
P33
-1224
-336
40
P60/SEG9
1215
-52
12
P34
-1224
-450
41
P57/WKP7/SEG8
1215
119
13
P35
-1224
-564
42
P56/WKP6/SEG7
1215
233
14
P36/AEVH
-1224
-678
43
P55/WKP5/SEG6
1215
404
15
P37/AEVL
-1224
-849
44
P54/WKP4/SEG5
1215
576
16
Vcc
-1224
-1142
45
P53/WKP3/SEG4
1215
747
17
V1
-922
-1484
46
P52/WKP2/SEG3
1215
919
18
V2
-799
-1484
47
P51/WKP1/SEG2
1215
1090
19
V3
-676
-1484
48
P50/WKP0/SEG1
1215
1206
20
PA3/COM4
-553
-1484
49
P90/PWM1
913
1494
21
PA2/COM3
-430
-1484
50
P91/PWM2
790
1494
22
PA1/COM2
-307
-1484
51
P92
667
1494
23
PA0/COM1
-185
-1484
52
P93
544
1494
24
P80/SEG25
-62
-1484
53
P94
421
1494
25
P77/SEG24
53
-1484
54
P95
299
1494
26
P76/SEG23
176
-1484
55
Vss
176
1494
27
P75/SEG22
299
-1484
56
IRQAEC
37
1494
28
P74/SEG21
421
-1484
57
P40/SCK32
-77
1494
29
P73/SEG20
544
-1484
58
P41/RXD32
-200
1494
Rev. 6.00 Mar 15, 2005 page 14 of 502
REJ09B0024-0600
Section 1 Overview
Coordinate
Pad
No.
Pad Name
X (µ
µm)
59
P42/TXD32
60
61
Coordinate
Y (µ
µm)
Pad
No.
Pad Name
X (µ
µm)
Y (µ
µm)
-323
1494
62
PB0/AN0
-692
1494
P43/IRQ0
-446
1494
63
PB1/AN1
-815
1494
AVcc
-569
1494
64
PB2/AN2
-937
1494
Note: The power supply (Vss) pads in pad numbers 4 and 55 must not be open but connected.
The TEST pad in pad number 7 must be connected to the Vss voltage level. If not, this LSI
does not operate correctly. The coordinate values indicate center positions of pads and the
accuracy is ±5 µm. The home-point position is center of the chip and the center is located at
half the distance between the upper and lower pads and left and right pads.
Rev. 6.00 Mar 15, 2005 page 15 of 502
REJ09B0024-0600
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
Section 1 Overview
Model
name
1
49
48
2
47
3
4
5
6
7
46
45
Y
44
43
8
42
9
X
(0, 0)
10
41
40
11
39
12
38
13
14
37
15
36
35
16
34
Product Model Name Model Name on Chip
HCD64F38004
HD64F38004
HCD64F38004C4
HD64F38004-4
HCD64F38002
HD64F38004
HCD64F38002C4
HD64F38004-4
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Chip size: 4.09 mm × 3.82 mm
Voltage level on the back of the chip: GND
: NC pad
Figure 1.9 Pad Arrangement of HCD64F38004 and HCD64F38002 (Top View)
Rev. 6.00 Mar 15, 2005 page 16 of 502
REJ09B0024-0600
Section 1 Overview
Table 1.3
Pad Coordinate of HCD64F38004 and HCD64F38002
Coordinate
Pad
No.
Pad Name
X (µ
µm)
1
PB3/IRQ1/AN3
2
Coordinate
Y (µ
µm)
Pad
No.
Pad Name
X (µ
µm)
Y (µ
µm)
-1915
1490
32
P71/SEG18
1411
-1779
X1
-1915
1182
33
P70/SEG17
1628
-1779
3
X2
-1915
1022
34
P67/SEG16
1914
-1496
4
Vss
-1915
926
35
P66/SEG15
1914
-1297
5
Vss = AVss
-1915
786
36
P65/SEG14
1914
-1098
6
OSC2
-1915
648
37
P64/SEG13
1914
-899
7
OSC1
-1915
495
38
P63/SEG12
1914
-700
8
TEST
-1915
295
39
P62/SEG11
1914
-500
9
RES
-1915
96
40
P61/SEG10
1914
-302
10
P31/TMOFL
-1915
-103
41
P60/SEG9
1914
-103
11
P32/TMOFH
-1915
-302
42
P57/WKP7/SEG8
1914
96
12
P33
-1915
-486
43
P56/WKP6/SEG7
1914
295
13
P34
-1915
-657
44
P55/WKP5/SEG6
1914
495
14
P35
-1915
-750
45
P54/WKP4/SEG5
1914
694
15
P36/AEVH
-1915
-989
46
P53/WKP3/SEG4
1914
893
16
P37/AEVL
-1915
-1247
47
P52/WKP2/SEG3
1914
1092
17
Vcc
-1915
-1438
48
P51/WKP1/SEG2
1914
1291
18
V1
-1623
-1779
49
P50/WKP0/SEG1
1914
1490
19
V2
-1406
-1779
50
P90/PWM1
1628
1779
20
V3
-1189
-1779
51
P91/PWM2
1368
1779
21
PA3/COM4
-973
-1779
52
P92
1113
1779
22
PA2/COM3
-756
-1779
53
P93
976
1779
23
PA1/COM2
-539
-1779
54
P94
759
1779
24
PA0/COM1
-323
-1779
55
P95
542
1779
25
P80/SEG25
-106
-1779
56
Vss
324
1779
26
P77/SEG24
111
-1779
57
IRQAEC
96
1779
27
P76/SEG23
328
-1779
58
P40/SCK32
-109
1779
28
P75/SEG22
544
-1779
59
P41/RXD32
-327
1779
29
P74/SEG21
761
-1779
60
P42/TXD32
-545
1779
30
P73/SEG20
978
-1779
61
P43/IRQ0
-762
1779
31
P72/SEG19
1194
-1779
62
AVcc
-980
1779
Rev. 6.00 Mar 15, 2005 page 17 of 502
REJ09B0024-0600
Section 1 Overview
Coordinate
Pad
No.
Pad Name
X (µ
µm)
63
PB0/AN0
64
PB1/AN1
Coordinate
Y (µ
µm)
Pad
No.
Pad Name
X (µ
µm)
Y (µ
µm)
-1198
1779
65
PB2/AN2
-1613
1779
-1414
1779
Note: The power supply (Vss) pads in pad numbers 4, 5, and 56 must not be open but connected.
The TEST pad in pad number 8 must be connected to the Vss voltage level. If not, this LSI
does not operate correctly. The coordinate values indicate center positions of pads and the
accuracy is ±5 µm. The home-point position is center of the chip and the center is located at
half the distance between the upper and lower pads and left and right pads.
Rev. 6.00 Mar 15, 2005 page 18 of 502
REJ09B0024-0600
Section 1 Overview
1.4
Pin Functions
Table 1.4
Pin Functions
Pin No.
Type
Symbol
FP-64A,
FP-64E,
FP-64K
Power
source pins
VCC
16
17
16
Input
Power supply pin. Connect this
pin to the system power supply.
VSS
4 (= AVSS) 12 (= AVSS) 4
55
63
5
56
4
55
Input
Ground pin. Connect this pin to
the system power supply (0V).
AVCC
61
5
62
61
Input
Analog power supply pin for the
A/D converter. When the A/D
converter is not used, connect
this pin to the system power
supply.
AVSS
4 (= VSS)
12 (= VSS)
4
5
4
Input
Ground pin for the A/D
converter. Connect this pin to
the system power supply (0 V).
V1
V2
V3
17
18
19
25
26
27
18
19
20
17
18
19
Input
Power supply pin for the LCD
controller/driver.
CVCC*4
53
—
—
—
Input
This is the internal step-down
power supply pin. To ensure
stability, a capacitor with a rating
of about 0.1 µF should be
connected between this pin and
the VSS pin.
OSC1
6
14
7
6
Input
OSC2
5
13
6
5
Output
These pins connect to a crystal
or ceramic resonator for system
clocks, or can be used to input
an external clock.
Clock pins
DP-64S
Pad
Pad
No.*1*3 No.*2
I/O
Functions
24
See section 4, Clock Pulse
Generators, for a typical
connection.
X1
2
10
2
2
Input
X2
3
11
3
3
Output
These pins connect to a 32.7685
or 38.4-kHz* crystal resonator
for subclocks.
See section 4, Clock Pulse
Generators, for a typical
connection.
Rev. 6.00 Mar 15, 2005 page 19 of 502
REJ09B0024-0600
Section 1 Overview
Pin No.
Type
System
control
Interrupt
pins
Symbol
FP-64A,
FP-64E,
FP-64K
DP-64S
Pad
Pad
1 3
2
No.* * No.*
I/O
Functions
RES
8
16
9
8
Input
Reset pin. When this driven low,
the chip is reset.
TEST
7
15
8
7
Input
Test pin. Connect this pin to Vss.
Users cannot use this pin.
60
4
61
60
Input
1
9
1
1
External interrupt request input
pins. Can select the rising or
falling edge.
56
64
57
56
Input
Asynchronous event counter
interrupt input pin. Enables
asynchronous event input.
IRQ0
IRQ1
IRQAEC
On the H8/38104 Group, this
must be fixed at VCC or GND
because the oscillator is
selected by the input level during
resets. Refer to section 4, Clock
Pulse Generators, for
information on the selection
method.
WKP7 to
WKP0
41 to 48
49 to 56
42 to 49 41 to 48 Input
Wakeup interrupt request input
pins. Can select the rising or
falling edge.
AEVL
AEVH
15
14
23
22
16
15
15
14
Input
This is an event input pin for
input to the asynchronous event
counter.
TMOFL
9
17
10
9
Output
This is an output pin for
waveforms generated by the
timer FL output compare
function.
TMOFH
10
18
11
10
Output
This is an output pin for
waveforms generated by the
timer FH output compare
function.
10-bit PWM PWM1
49
57
50
49
Output
PWM2
50
58
51
50
These are output pins for
waveforms generated by the
channel 1 and 2 10-bit PWMs.
Timer
Rev. 6.00 Mar 15, 2005 page 20 of 502
REJ09B0024-0600
Section 1 Overview
Pin No.
FP-64A,
FP-64E,
FP-64K
DP-64S
Pad
Pad
1 3
2
No.* * No.*
I/O
Functions
Type
Symbol
I/O ports
P37 to
P31
15 to 9
23 to 17
16 to 10 15 to 9
I/O
7-bit I/O port. Input or output can
be designated for each bit by
means of the port control
register 3 (PCR3). When the onchip emulator is used, pins P33,
P34, and P35 are unavailable to
the user because they are used
exclusively by the on-chip
emulator.
P43
60
4
61
Input
1-bit input port.
P42 to
P40
59 to 57
3 to 1
60 to 58 59 to 57 I/O
3-bit I/O port. Input or output can
be designated for each bit by
means of the port control
register 4 (PCR4).
P57 to
P50
41 to 48
49 to 56
42 to 49 41 to 48 I/O
8-bit I/O port. Input or output can
be designated for each bit by
means of the port control
register 5 (PCR5).
P67 to
P60
33 to 40
41 to 48
34 to 41 33 to 40 I/O
8-bit I/O port. Input or output can
be designated for each bit by
means of the port control
register 6 (PCR6).
P77 to
P70
25 to 32
33 to 40
26 to 33 25 to 32 I/O
8-bit I/O port. Input or output can
be designated for each bit by
means of the port control
register 7 (PCR7).
P80
24
32
25
1-bit I/O port. Input or output can
be designated for each bit by
means of the port control
register 8 (PCR8).
60
24
I/O
Rev. 6.00 Mar 15, 2005 page 21 of 502
REJ09B0024-0600
Section 1 Overview
Pin No.
Type
Symbol
I/O ports
P95 to
P90
FP-64A,
FP-64E,
FP-64K
DP-64S
Pad
Pad
1 3
2
No.* * No.*
54 to 49
62 to 57
55 to 50 54 to 49 Output
I/O
Functions
6-bit output port. When the onchip emulator is used, pin P95 is
unavailable to the user because
it is used exclusively by the onchip emulator. In the F-ZTAT
version, pin P95 should not be
open but pulled up to go high in
user mode.
Note that the H8/38104 Group is
not equipped with a pin 94.
PA3 to
PA0
20 to 23
28 to 31
21 to 24 20 to 23 I/O
4-bit I/O port. Input or output can
be designated for each bit by
means of the port control
register A (PCRA).
PB3 to
PB0
1,
64 to 62
9 to 6
1,
1,
Input
65 to 63 64 to 62
4-bit input port.
RXD32
58
2
59
58
Input
Receive data input pin.
Serial communication
interface
(SCI)
TXD32
59
3
60
59
Output
Transmit data output pin.
SCK32
57
1
58
57
I/O
Clock I/O pin.
A/D
converter
AN3 to
AN0
1,
64 to 62
9 to 6
1,
1,
Input
65 to 63 64 to 62
Analog data input pins.
LCD
controller/
driver
COM4 to 20 to 23
COM1
28 to 31
21 to 24 20 to 23 Output
LCD common output pins.
SEG25 to 24 to 48
SEG1
32 to 56
25 to 49 24 to 48 Output
LCD segment output pins.
52
—
—
—
Input
Reference voltage input pin.
62
—
—
—
Input
Power supply drop detection
voltage input pin.
63
—
—
—
Input
Power supply rise detection
voltage input pin.
Low-voltage Vref
detection
extD
circuit
4
(LVD) *
extU
Notes: 1. Pad number for HCD6433802, HCD6433801, and HCD6433800
2. Pad number for HCD64338004, HCD64338003, HCD64338002, HCD64338001, and
HCD64338000
3. Pad number for HCD64F38004 and HCD64F38002
4. H8/38104 Group only
5. Does not apply to H8/38104 Group
Rev. 6.00 Mar 15, 2005 page 22 of 502
REJ09B0024-0600
Section 2 CPU
Section 2 CPU
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1
Features
• General-register architecture
 Sixteen 8-bit general registers, also usable as eight 16-bit registers
• Fifty-five basic instructions
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct [Rn]
 Register indirect [@Rn]
 Register indirect with displacement [@(d:16,Rn)]
 Register indirect with post-increment or pre-decrement [@Rn+ or @–Rn]
 Absolute address [@aa:8 or @aa:16]
 Immediate [#xx:8 or #xx:16]
 Program-counter relative [@(d:8,PC)]
 Memory indirect [@@aa:8]
• 64-kbyte address space
• High-speed operation
 All frequently-used instructions execute in two to four states
 8/16-bit register-register add/subtract : 0.25 µs*
 8 × 8-bit multiply : 1.75 µs*
 16 ÷ 8-bit divide : 1.75 µs*
Note: * These values are at φ = 8 MHz.
• Power-down state
 Transition to power-down state by SLEEP instruction
CPU30L0A_000020020900
Rev. 6.00 Mar 15, 2005 page 23 of 502
REJ09B0024-0600
Section 2 CPU
2.2
Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area.
Figures 2.1 show the memory map.
(PROM and Mask ROM versions)
H'0000
Interrupt vector area
H'0029
H'002A
On-chip ROM
(16 kbytes)
H'3FFF
Not used
H'F740
LCD RAM
(13 bytes)
H'F74C
Not used
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
Internal I/O register
(128 bytes)
H'FFFF
Figure 2.1(1) H8/3802 Memory Map
Rev. 6.00 Mar 15, 2005 page 24 of 502
REJ09B0024-0600
Section 2 CPU
(Mask ROM version)
H'0000
Interrupt vector area
H'0029
H'002A
On-chip ROM
(12 kbytes)
H'2FFF
Not used
H'F740
H'F74C
LCD RAM
(13 bytes)
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
(128 bytes)
H'FFFF
Figure 2.1(2) H8/3801 Memory Map
Rev. 6.00 Mar 15, 2005 page 25 of 502
REJ09B0024-0600
Section 2 CPU
(Mask ROM version)
H'0000
Interrupt vector area
H'0029
H'002A
On-chip ROM
(8 kbytes)
H'1FFF
Not used
H'F740
H'F74C
LCD RAM
(13 bytes)
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
(128 bytes)
H'FFFF
Figure 2.1(3) H8/3800 Memory Map
Rev. 6.00 Mar 15, 2005 page 26 of 502
REJ09B0024-0600
Section 2 CPU
(Flash memory version)
H'0000
(Mask ROM version)
H'0000
Interrupt vector area
Interrupt vector area
H'0029
H'0029
H'002A
H'002A
On-chip ROM
On-chip ROM
(32 kbytes)
(32 kbytes)
H'7000
Firmware for on-chip emulator*1
H'7FFF
H'7FFF
Not used
H'F020
H'F02B
Internal I/O register
Not used
Not used
H'F740
H'F740
LCD RAM
LCD RAM
(13 bytes)
(13 bytes)
H'F74C
H'F780
H'FB7F
H'FB80
H'FF7F
H'F74C
Not used
Work area for
flash memory reprogramming*2
(1 kbyte)
On-chip RAM
(2 kbytes)
User area
(1 kbyte)
H'FF80
Not used
H'FB80
On-chip RAM
H'FF7F
(1 kbyte)
H'FF80
Internal I/O register
Internal I/O register
(128 bytes)
H'FFFF
(128 bytes)
H'FFFF
Note: 1. When the on-chip emulator is used, this area is unavailable to the user.
2. When flash memory is programmed, this area is used by the programming control program.
When the on-chip emulator is used, this area is unavailable to the user.
Figure 2.1(4) H8/38004, H8/38104 Memory Map
Rev. 6.00 Mar 15, 2005 page 27 of 502
REJ09B0024-0600
Section 2 CPU
(Mask ROM version)
H'0000
Interrupt vector area
H'0029
H'002A
On-chip ROM
(24 kbytes)
H'5FFF
Not used
H'F740
LCD RAM
(13 bytes)
H'F74C
Not used
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
Internal I/O register
(128 bytes)
H'FFFF
Figure 2.1(5) H8/38003, H8/38103 Memory Map
Rev. 6.00 Mar 15, 2005 page 28 of 502
REJ09B0024-0600
Section 2 CPU
(Flash memory version)
H'0000
(Mask ROM version)
H'0000
Interrupt vector area
Interrupt vector area
H'0029
H'0029
H'002A
H'002A
On-chip ROM
On-chip ROM
(16 kbytes)
(16 kbytes)
H'3FFF
H'3FFF
Not used
H'7000
Firmware for on-chip emulator*1
H'7FFF
Not used
Not used
H'F020
H'F02B
Internal I/O register
Not used
H'F740
H'F740
LCD RAM
LCD RAM
(13 bytes)
(13 bytes)
H'F74C
H'F74C
Not used
H'F780
H'FB7F
H'FB80
H'FF7F
Work area for flash memory
reprogramming*2
(1 kbyte)
On-chip RAM
(2 kbytes)
User area
(1 kbyte)
Not used
H'FB80
H'FF7F
(1 kbyte)
H'FF80
H'FF80
Internal I/O register
Internal I/O register
(128 bytes)
H'FFFF
On-chip RAM
(128 bytes)
H'FFFF
Notes: 1. This area is unavailable to the user.
2. When flash memory is programmed, this area is used by the programming control program.
When the on-chip emulator is used, this area is unavailable to the user.
Figure 2.1(6) H8/38002, H8/38102 Memory Map
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Section 2 CPU
(Mask ROM version)
H'0000
Interrupt vector area
H'0029
H'002A
On-chip ROM
(16 kbytes)
H'3FFF
Not used
H'F740
LCD RAM
(13 bytes)
H'F74C
Not used
H'FD80
H'FF7F
On-chip RAM
(512 byte)
H'FF80
Internal I/O register
(128 bytes)
H'FFFF
Figure 2.1(7) H8/38002S Memory Map
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Section 2 CPU
(Mask ROM version)
H'0000
Interrupt vector area
H'0029
H'002A
On-chip ROM
(12 kbytes)
H'2FFF
Not used
H'F740
LCD RAM
H'F74C
(13 bytes)
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
(128 bytes)
Figure 2.1(8) H8/38001, H8/38001S, H8/38101 Memory Map
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(Mask ROM version)
H'0000
Interrupt vector area
H'0029
H'002A
On-chip ROM
(8 kbytes)
H'1FFF
Not used
H'F740
H'F74C
LCD RAM
(13 bytes)
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
(128 bytes)
Figure 2.1(9) H8/38000, H8/38000S, H8/38100 Memory Map
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2.3
Register Configuration
Figure 2.2 shows the internal register configuration of the H8/300L CPU. There are two groups of
registers: the general registers and control registers.
General registers (Rn)
7
0
7
0
R0H
R0L
R1H
R1L
R2H
R2L
R3H
R3L
R4H
R4L
R5H
R5L
R6H
R6L
(SP)
R7H
R7L
Control register (CR)
15
0
PC
CCR
7
6
5
4
3
2
1
0
I
U
H
U
N
Z
V
C
Legend:
SP:
PC:
CCR:
I:
U:
H:
N:
Z:
V:
C:
Stack pointer
Program counter
Condition code register
Interrupt mask bit
User bit
Half-carry flag
Negative flag
Zero flag
Overflow flag
Carry flag
Figure 2.2 CPU Registers
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2.3.1
General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the upper bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception handling and
subroutine calls. When it functions as the stack pointer, as indicated in figure 2.3, SP (R7) points
to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2.3 Stack Pointer
2.3.2
Program Counter (PC)
This 16-bit counter indicates the address of the next instruction the CPU will execute. All
instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored
(always regarded as 0).
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2.3.3
Condition Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I),
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Bit
Bit Name
Initial
Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts when set to 1. The I bit is set to 1 at
the start of an exception-handling sequence.
6
U
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5
H
Undefined R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, or CMP.W
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and cleared to 0 otherwise.
4
U
Undefined R/W
User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3
N
Undefined R/W
Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2
Z
Undefined R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
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Bit
Bit Name
Initial
Value
0
C
Undefined R/W
R/W
Description
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
Some instructions leave flag bits unchanged.
For the action of each instruction on the flag bits, refer to H8/300L Series Programming Manual.
2.3.4
Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the initial value of the stack pointer (R7) is undefined.
The stack pointer should be initialized by software, by the first instruction executed after a reset.
2.4
Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data. Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0,
1, 2, ..., 7).
All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. The
MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and DIVXU (16
bits ÷ 8 bits) instructions operate on word data.
The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
2.4.1
General Register Data Formats
Figure 2.4 shows the data formats in general registers.
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Data Type
Register No.
Data Format
7
1-bit data
RnH
1-bit data
RnL
Byte data
RnH
Byte data
RnL
Word data
Rn
4-bit BCD data
RnH
4-bit BCD data
RnL
0
7
6
5
4
3
2
1
Don't care
0
7
Don't care
0
7
7
0
MSB
LSB
Don't care
6
5
4
3
2
1
0
Don't care
7
0
MSB
LSB
15
0
MSB
LSB
7
4
Upper digit
3
0
Lower digit
Don't care
7
Don't care
4
Upper digit
3
0
Lower digit
Legend:
RnH: Upper byte of general register
RnL:
Lower byte of general register
MSB: Most significant bit
LSB:
Least significant bit
Figure 2.4 General Register Data Formats
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2.4.2
Memory Data Formats
Figure 2.5 indicates the data formats in memory. The H8/300L CPU can access word data stored
in memory (MOV.W instruction), but the word data must always begin at an even address. If word
data starting at an odd address is accessed, the least significant bit of the address is regarded as 0,
and the word data starting at the preceding address is accessed. The same applies to instruction
codes.
Data Type
Address
Data Format
7
1-bit data
Address n
7
Byte data
Address n
MSB
0
6
5
4
3
2
1
0
LSB
Even address MSB
Upper 8 bits
Odd address
Lower 8 bits
Word data
Even address MSB
Byte data (CCR) on stack
Odd address
MSB
LSB
CCR
LSB
CCR*
LSB
Even address MSB
Word data on stack
Odd address
LSB
Note: * Ignored on return
Legend:
CCR: Condition code register
Figure 2.5 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to
make a complete word. When they are restored, the lower byte is ignored.
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2.5
Instruction Set
The H8/300L CPU can use a total of 55 instructions, which are grouped by function in table 2.1.
Table 2.1
Instruction Set
Function
Instructions
*1
Number
*1
Data transfer
MOV, PUSH , POP
1
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA,
DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
AND, OR, XOR, NOT
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR
8
Bit manipulation
14
Branch
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR,
BXOR, BIXOR, BLD, BILD, BST, BIST
Bcc*2, JMP, BSR, JSR, RTS
5
System control
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
8
Block data transfer
EEPMOV
1
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine
language.
2. Bcc is the general name for conditional branch instructions.
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
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Table 2.2
Operation Notation
Symbol
Description
Rd
General register (destination)
Rs
General register (source)
Rn
General register
(EAd), <Ead>
Destination operand
(EAs), <Eas>
Source operand
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical XOR
→
Move
¬
NOT (logical complement)
:3/:8/:16
3-, 8-, or 16-bit length
( ), < >
Contents of operand indicated by effective address
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Section 2 CPU
2.5.1
Data Transfer Instructions
Table 2.3 describes the data transfer instructions.
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for word data. The @aa:8 addressing
mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.
POP
W
@SP+ → Rn
Pops a general register from the stack. Equivalent to MOV.W@SP+, Rn.
PUSH
W
Rn → @–SP
Pushes a general register onto the stack. Equivalent to MOV.W Rn, @–
SP.
Note:
*
Refers to the operand size.
B: Byte
W: Word
For details on data access, see section 2.9.1, Notes on Data Access to Empty Areas and section
2.9.2, Access to Internal I/O Registers.
Figure 2.6 shows the instruction formats of data transfer instructions.
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Section 2 CPU
15
8
7
0
op
rm
15
8
8
MOV
Rm
7
Rn
0
op
15
rn
rm
rn
rm
rn
rm
rn
@Rm
7
Rn
0
op
@(d: 16, Rm)
Rn
disp
15
8
7
0
op
15
8
op
Rn
7
@aa:8
abs
8
Rn,
@−Rm
0
rn
15
@Rm +
7
Rn
0
op
rn
@aa:16
Rn
abs
15
8
op
7
0
rn
15
#xx:8
IMM
8
7
Rn
0
op
rn
#xx:16
Rn
IMM
15
8
op
7
0
1
1
1
rn
POP, PUSH
@SP+
Rn
Rn,
@-SP
Legend:
op:
Operation field
rm, rn: Register field
disp:
Displacement
abs:
Absolute address
IMM:
Immediate data
Figure 2.6 Instruction Formats of Data Transfer Instructions
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Section 2 CPU
2.5.2
Arithmetic Operations Instructions
Table 2.4 describes the arithmetic operations instructions.
Table 2.4
Arithmetic Operations Instructions
Instruction
Size*
Function
ADD
SUB
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data can
be added or subtracted only when both words are in general registers.
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or addition or subtraction with carry on immediate data and
data in a general register.
INC
DEC
B
Rd ± 1 → Rd
Increments or decrements a general register by 1.
ADDS
SUBS
W
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts 1 or 2 to or from a general register.
DAA
DAS
B
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
DIVXU
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder.
CMP
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result. Word
data can be compared only between two general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register.
Note:
*
Refers to the operand size.
B: Byte
W: Word
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Section 2 CPU
2.5.3
Logic Operations Instructions
Table 2.5 describes the logic operations instructions.
Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B
¬ (Rd) → (Rd)
Obtains the one's complement (logical complement) of general register
contents.
Note:
*
2.5.4
Refers to the operand size.
B: Byte
Shift Instructions
Table 2.6 describes the shift instructions.
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B
Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B
Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note:
*
Refers to the operand size.
B: Byte
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Section 2 CPU
Figure 2.7 shows the instruction formats of arithmetic, logic, and shift instructions.
15
8
7
op
0
rm
15
8
7
0
op
15
8
7
0
rm
8
op
8
0
8
0
0
AND, OR, XOR (#xx:8)
IMM
8
op
AND, OR, XOR (Rm)
rn
7
rn
15
ADD, ADDX, SUBX,
CMP (#xx:8)
7
rm
15
MULXU, DIVXU
IMM
op
op
rn
7
rn
15
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
rn
op
15
ADD, SUB, CMP,
ADDX, SUBX (Rm)
rn
7
0
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
Legend:
op:
Operation field
rm, rn: Register field
IMM:
Immediate data
Figure 2.7 Instruction Formats of Arithmetic, Logic, and Shift Instructions
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Section 2 CPU
2.5.5
Bit Manipulation Instructions
Table 2.7 describes the bit manipulation instructions.
Table 2.7
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Refers to the operand size.
B: Byte
For details on the bit manipulation instructions, see section 2.9.4, Bit Manipulation Instructions.
Figure 2.8 shows the instruction formats of bit manipulation instructions.
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BSET, BCLR, BNOT, BTST
15
8
7
op
15
IMM
8
0
rm
8
rn
7
IMM
op
8
Operand
: Register direct (Rn)
Bit No.
: Immediate (#xx:3)
Operand
: Register direct (Rn)
Bit No.
: Register direct (Rm)
0
rn
op
15
rn
7
op
15
0
0
0
0
0
Operand
: Register indirect (@Rn)
0
0
0
0
Bit No.
: Immediate (#xx:3)
7
0
op
rn
0
0
0
0
Operand
: Register indirect (@Rn)
op
rm
0
0
0
0
Bit No.
: Register direct (Rm)
Operand
: Absolute address (@aa:8)
Bit No.
: Immediate (#xx:3)
Operand
: Absolute address (@aa:8)
Bit No.
: Register direct (Rm)
15
8
7
0
abs
op
IMM
op
15
8
0
0
0
7
0
0
abs
op
rm
op
0
0
0
0
BAND, BOR, BXOR, BLD, BST
15
8
7
rn
IMM
op
15
0
8
7
IMM
op
15
8
: Immediate (#xx:3)
0
0
0
0
Operand
: Register indirect (@Rn)
0
0
0
0
Bit No.
: Immediate (#xx:3)
Operand
: Absolute address (@aa:8)
Bit No.
: Immediate (#xx:3)
7
0
abs
op
IMM
op
: Register direct (Rn)
Bit No.
0
rn
op
Operand
0
0
0
0
BIAND, BIOR, BIXOR, BILD, BIST
15
8
7
IMM
op
15
0
8
rn
7
IMM
op
15
8
: Immediate (#xx:3)
0
0
0
0
Operand
: Register indirect (@Rn)
0
0
0
0
Bit No.
: Immediate (#xx:3)
Operand
: Absolute address (@aa:8)
Bit No.
: Immediate (#xx:3)
7
0
abs
op
op
: Register direct (Rn)
Bit No.
0
rn
op
Operand
IMM
0
0
0
0
Legend:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM:
Immediate data
Figure 2.8 Instruction Formats of Bit Manipulation Instructions
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Section 2 CPU
2.5.6
Branch Instructions
Table 2.8 describes the branch instructions.
Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc
—
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear
(high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine.
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Figure 2.9 shows the instruction formats of branch instructions.
15
8
op
7
0
cc
15
disp
8
7
op
15
Bcc
0
rm
8
0
0
0
7
0
JMP (@Rm)
0
op
JMP (@aa:16)
abs
15
8
7
0
op
JMP (@@aa:8)
abs
15
8
7
0
op
BSR
disp
15
8
7
op
15
0
rm
8
0
7
0
0
0
JSR (@Rm)
0
op
JSR (@aa:16)
abs
15
8
7
op
15
0
JSR (@@aa:8)
abs
8
7
op
0
RTS
Legend:
op: Operation field
cc:
Condition field
rm:
Register field
disp: Displacement
abs: Absolute address
Figure 2.9 Instruction Formats of Branch Instructions
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2.5.7
System Control Instructions
Table 2.9 describes the system control instructions.
Table 2.9
System Control Instructions
Instruction
Size*
Function
RTE
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition from active mode to power-down mode. See section
5, Power-Down Modes, for details.
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to CCR.
STC
B
ANDC
B
CCR → Rd
Copies CCR to a specified general register.
CCR ∧ #IMM → CCR
Logically ANDs CCR with immediate data.
ORC
B
CCR ∨ #IMM → CCR
Logically ORs CCR with immediate data.
XORC
B
CCR ⊕ #IMM → CCR
Logically XORs CCR with immediate data.
NOP
Note:
—
*
PC + 2 → PC
Only increments the program counter.
Refers to the operand size.
B: Byte
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Figure 2.10 shows the instruction formats of system control instructions.
15
8
7
0
RTE, SLEEP, NOP
op
15
8
7
0
op
LDC, STC (Rn)
rn
15
8
7
op
0
IMM
ANDC, ORC,
XORC, LDC (#xx:8)
Legend:
op:
Operation field
rn:
Register field
IMM: Immediate data
Figure 2.10 Instruction Formats of System Control Instructions
2.5.8
Block Data Transfer Instructions
Table 2.10 describes the block data transfer instructions.
Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV
—
If R4L ≠ 0 then
repeat
@R5+ → @R6+
R4L – 1 → R4L
until
R4L = 0
else next;
Block data transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by R5
to locations starting at the address indicated by R6. After the transfer,
the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, EEPMOV
Instruction, for details.
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Figure 2.11 shows the instruction formats of block data transfer instructions.
15
8
7
0
op
op
Legend:
op: Operation field
Figure 2.11 Instruction Format of Block Data Transfer Instructions
2.6
Addressing Modes and Effective Address
2.6.1
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16,Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
5
Absolute address
@aa:8/@aa:16
6
Immediate
#xx:8/#xx:16
7
Program-counter relative
@(d:8,PC)
8
Memory indirect
@@aa:8
Register Direct—Rn
The register field of the instruction specifies an 8- or 16-bit general register containing the
operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
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Register Indirect—@Rn
The register field of the instruction specifies a 16-bit general register containing the address of the
operand in memory.
Register Indirect with Displacement—@(d:16, Rn)
The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the
contents of the specified general register (16 bits) to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.
Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @-Rn
• Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address of
the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented by
1 or 2 to obtain the address of the operand in memory. The register retains the decremented
value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original
contents of the register must be even.
Absolute Address—@aa:8/@aa:16
The instruction specifies the absolute address of the operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR
instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
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Immediate—#xx:8/#xx:16
The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16)
in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit
manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
Program-Counter Relative—@(d:8, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the
instruction code is sign-extended to 16 bits and added to the program counter contents to generate
a branch destination address. The possible branching range is –126 to +128 bytes (–63 to +64
words) from the current address. The displacement should be an even number.
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The second byte of the instruction code
specifies an 8-bit absolute address. The word located at this address contains the branch
destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the
address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower
end of the address area is also used as a vector area. See section 3.1, Exception Sources and
Vector Address, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See section 2.4.2, Memory Data Formats, for further
information.
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2.6.2
Effective Address Calculation
Table 2.12 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST
instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position
in the operand.
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4
3
2
1
No.
op
op
7
7
6
rm
rm
op
disp
7
6
rm
4
4
4
3
3
3
rn
0
0
0
op
7
6
rm
4
3
15
op
7
6
rm
4
3
Register indirect with pre-decrement @-Rn
15
0
0
Register indirect with post-increment or pre-decrement
Register indirect with post-increment @Rn+
15
Register indirect with displacement
@(d:16, Rn)
15
Register indirect @Rn
15
8
Addressing Mode and Instruction Format
Register direct Rn
0
Incremented or decremented by 1 if operand is byte
size, and by 2 if word size
1 or 2
Contents of register indicated by rm (16 bits)
15
0
0
0
1 or 2
Contents of register indicated by rm (16 bits)
15
disp
Contents of register indicated by rm (16 bits)
15
Contents of register indicated by rm (16 bits)
15
Effective Address Calculation Method
rm
0
3
rn
Effective Address (EA)
0
15
15
15
15
0
0
0
0
Operand is contents of registers indicated by rm/rn
3
Section 2 CPU
Table 2.12 Effective Address Calculation
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7
6
5
op
op
IMM
op
8 7
abs
op
8 7
IMM
abs
15
op
8 7
disp
Program-counter relative@ (d: 8, PC)
15
#xx:16
15
#xx:8
Immediate
15
@aa:16
15
Absolute address
@aa:8
0
0
0
0
0
No. Addressing Mode and Instruction Format
PC contents
Sign extension
15
disp
Effective Address Calculation Method
0
H'FF
8 7
15
Operand is 1- or 2-byte immediate data
15
15
Effective Address (EA)
0
0
0
Section 2 CPU
15
op
8
7
abs
Addressing Mode and Instruction Format
Memory indirect@@aa:8
Legend:
rm, rn: Register field
Operation field
op:
disp: Displacement
IMM: Immediate data
Absolute address
abs:
8
No.
0
15
8 7
abs
Memory contents (16 bits)
H'00
Effective Address Calculation Method
0
15
Effective Address (EA)
0
Section 2 CPU
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Section 2 CPU
2.7
Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φSUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.7.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.12 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φ or φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.12 On-Chip Memory Access Cycle
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2.7.2
On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. For details on the data bus width and number of access states of each register, refer to
section 14.1, Register Addresses (Address Order).
Two-State Access to On-Chip Peripheral Modules:
Figure 2.13 shows the operation timing in the case of two-state access to an on-chip peripheral
module.
Bus cycle
T1 state
T2 state
φ or φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (2-State Access)
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Three-State Access to On-Chip Peripheral Modules:
Figure 2.14 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Bus cycle
T1 state
T2 state
T3 state
φ or φ SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.14 On-Chip Peripheral Module Access Cycle (3-State Access)
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2.8
CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state, there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode.
These states are shown in figure 2.15. Figure 2.16 shows the state transitions.
Reset state
The CPU is initialized
Program execution state
Active (high-speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active (medium-speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes successive
program instructions at reduced
speed, synchronized by the subclock
Program halt state
A state in which the CPU
operation is stopped to
conserve power
Sleep (high-speed) mode
Power-down modes
CPU state
Sleep (medium-speed) mode
Standby mode
Watch mode
Subsleep mode
Exception-handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.15 CPU Operation States
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Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
occurs
Program halt state
Interrupt
source
occurs
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.16 State Transitions
2.9
Usage Notes
2.9.1
Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.9.2
Access to Internal I/O Registers
Internal data transfer to or from on-chip peripheral modules other than the on-chip ROM and
RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the
following results will occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Data which is written to lower part of CPU register is not guaranteed.
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Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas.
2.9.3
EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
2.9.4
Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address or when a bit is directly manipulated for a port, because this may
rewrite data of a bit other than the bit to be manipulated.
Bit Manipulation in Two Registers Assigned to Same Address:
Example 1: Timer load register and timer counter
Figure 2.17 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit manipulation instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so the value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
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Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal data bus
Figure 2.17 Example of Timer Configuration with Two Registers
Allocated to Same Address
Example 2: BSET instruction executed designating port 3
P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level
signal at P36. The remaining pins, P35 to P31, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P31 to high-level output.
Prior to executing BSET
P37
P36
P35
P34
P33
P32
P31

Input/output
Input
Input
Output
Output
Output
Output
Output

Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level

PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
BSET instruction executed
BSET
#1,
@PDR3
The BSET instruction is executed for port 3.
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After executing BSET
P37
P36
P35
P34
P33
P32
P31

Input/output
Input
Input
Output
Output
Output
Output
Output

Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
High
level

PCR3
0
0
1
1
1
1
1
1
PDR3
0
1
0
0
0
0
1
1
Description on operation
When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P35 to P31 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a
value of H'81, but the value read by the CPU is H'41.
Next, the CPU sets bit 1 of the read data to 1, changing the PDR3 data to H'43.
Finally, the CPU writes H'43 to PDR3, completing execution of BSET.
As a result of the BSET instruction, bit 1 in PDR3 becomes 1, and P31 outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values. To prevent this problem, store a copy
of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work
area, then write this data to PDR3.
Prior to executing BSET
MOV.B
MOV.B
MOV.B
#81,
R0L,
R0L,
R0L
@RAM0
@PDR3
The PDR3 value (H'81) is written to a work area in
memory (RAM0) as well as to PDR3.
P37
P36
P35
P34
P33
P32
P31

Input/output
Input
Input
Output
Output
Output
Output
Output

Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level

PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
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Section 2 CPU
BSET instruction executed
BSET
#1,
@RAM0
The BSET instruction is executed designating the PDR3
work area (RAM0).
After executing BSET
MOV.B
MOV.B
@RAM0, R0L
R0L, @PDR3
The work area (RAM0) value is written to PDR3.
P37
P36
P35
P34
P33
P32
P31

Input/output
Input
Input
Output
Output
Output
Output
Output

Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
High
level

PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
1
1
RAM0
1
0
0
0
0
0
1
1
Bit Manipulation in Register Containing Write-Only Bit
Example 3: BCLR instruction executed designating PCR3
P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal input at
P36. P35 to P31 are output pins that output low-level signals.
An example of setting the P31 pin as an input pin by the BCLR instruction is shown below. It is
assumed that a high-level signal will be input to this input pin.
Prior to executing BCLR
P37
P36
P35
Input/output
Input
Input
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
PDR3
1
0
0
0
0
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P34
P33
P31

Output
Output

Low
level
Low
level

1
1
1
0
0
1
P32
Section 2 CPU
BCLR instruction executed
BCLR
#1,
@PCR3
The BCLR instruction is executed for PCR3.
After executing BCLR
P37
P36
P35
P34
P33
P32
P31

Input/output
Output
Output
Output
Output
Output
Output
Input

Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
High
level

PCR3
1
1
1
1
1
1
0
1
PDR3
1
0
0
0
0
0
0
1
Description on operation
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 1 in the read data to 0, changing the data to H'FD.
Finally, H'FD is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 1 in PCR3 becomes 0, making P31 an input port. However, bits 7
and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins. To prevent
this problem, store a copy of the PCR3 data in a work area in memory and manipulate data of the
bit in the work area, then write this data to PCR3.
Prior to executing BCLR
MOV.B
MOV.B
MOV.B
#3F,
R0L,
R0L,
R0L
@RAM0
@PCR3
The PCR3 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR3.
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Section 2 CPU
P37
P36
P35
P34
P33
P32
P31

Input/output
Input
Input
Output
Output
Output
Output
Output

Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level

PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
0
0
1
1
1
1
1
1
BCLR instruction executed
BCLR
#1,
@RAM0
The BCLR instructions executed for the PCR3 work area
(RAM0).
After executing BCLR
MOV.B
MOV.B
@RAM0, R0L
R0L, @PCR3
The work area (RAM0) value is written to PCR3.
P37
P36
P35
P34
P33
P32
P31

Input/output
Input
Input
Output
Output
Output
Output
Output

Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
High
level

PCR3
0
0
1
1
1
1
0
1
PDR3
1
0
0
0
0
0
0
1
RAM0
0
0
1
1
1
1
0
1
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Section 2 CPU
Table 2.13 lists the pairs of registers that share identical addresses. Table 2.14 lists the registers
that contain write-only bits.
Table 2.13 Registers with Shared Addresses
Register Name
Abbreviation
Address
Port data register 3*
Port data register 4*
PDR3
H'FFD6
PDR4
H'FFD7
Port data register 5*
PDR5
H'FFD8
Port data register 6*
PDR6
H'FFD9
Port data register 7*
PDR7
H'FFDA
Port data register 8*
PDR8
H'FFDB
Port data register A*
PDRA
H'FFDD
Note:
*
Port data registers have the same addresses as input pins.
Table 2.14 Registers with Write-Only Bits
Register Name
Abbreviation
Address
Port control register 3
PCR3
H'FFE6
Port control register 4
PCR4
H'FFE7
Port control register 5
PCR5
H'FFE8
Port control register 6
PCR6
H'FFE9
Port control register 7
PCR7
H'FFEA
Port control register 8
PCR8
H'FFEB
Port control register A
PCRA
H'FFED
Timer control register F
TCRF
H'FFB6
PWM1 control register
PWCR1
H'FFD0
PWM1 data register U
PWDRU1
H'FFD1
PWM1 data register L
PWDRL1
H'FFD2
PWM2 control register
PWCR2
H'FFCD
PWM2 data register U
PWDRU2
H'FFCE
PWM2 data register L
PWDRL2
H'FFCF
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Section 2 CPU
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Section 3 Exception Handling
Section 3 Exception Handling
Exception handling may be caused by a reset or interrupts.
• Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is
cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and
exception handling starts. Exception handling is the same as exception handling by the RES
pin.
• Interrupts
External interrupts and internal interrupts are masked by the I bit in CCR, and kept masked
while the I bit is set to 1. Exception handling starts when the current instruction or exception
handling ends, if an interrupt request has been issued.
The following notes apply to the HD64F38004.
• Issue
Depending on the circuitry status at power-on, a vector 17 (system reservation) interrupt
request may be generated. If bit I in CCR is cleared to 0, this interrupt will be accepted just
like any other internal interrupt. This can cause processing exceptions to occur, and program
execution will eventually halt since there is no procedure for clearing the interrupt request flag
in question.
• Countermeasure
To prevent the above issue from occurring, it is recommended that the following steps be
added to programs written for the product.
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Section 3 Exception Handling
Reset
Initialize stack pointer
Write H'9E to H'FFC3
Additional
steps
Read H'FFC3
Write H'F1 to H'FFC3
Write H'BF to H'FFFA
Clear I bit in CCR
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User
program
Section 3 Exception Handling
The following is an example in assembler.
.ORG H'0000
.DATA.W
INIT
.ORG H'0100
INIT:
MOV.W #H'FF80:16,SP
MOV.B
MOV.B
MOV.B
MOV.B
MOV.B
MOV.B
MOV.B
ANDC.B
#H'9E:8,R0L
R0L,@H'FFC3:8
@H'FFC3:8,R0L
#H'F1:8,R0L
R0L,@H'FFC3:8
#H'BF:8,R0L
R0L,@H'FFFA:8
#H'7F:8,CCR
; user program
The following is an example in C.
void powerON_Reset(void)
{
// ------------------------------------------------------unsigned char dummy;
*((volatile unsigned char *)0xffc3)= 0x9e;
dummy = *((volatile unsigned char *)0xffc3);
*((volatile unsigned char *)0xffc3)= 0xf1;
*((volatile unsigned char *)0xfffa)= 0xbf;
// ------------------------------------------------------set_imask_ccr(0);
// clear I bit
// user program
}
On the mask ROM version of the product, user programs may be used as is (including the
additional steps described above) or without the additional steps.
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
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Section 3 Exception Handling
Table 3.1
Exception Sources and Vector Address
Relative Module
Exception Sources
Vector
Number
Vector Address
Priority
RES pin
Reset
0
H'0000 to H'0001
High

Reserved for system use
1 to 3
H'0002 to H'0007
IRQ0/Low-voltage detect
interrupt*
4
H'0008 to H'0009
IRQ1
5
H'000A to H'000B
IRQAEC
6
H'000C to H'000D

Reserved for system use
7, 8
H'000E to H'0011
External interrupt
pin
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
9
H'0012 to H'0013

Reserved for system use
10
H'0014 to H'0015
Timer A
Timer A overflow
11
H'0016 to H'0017
Asynchronous
event counter
Asynchronous event counter
overflow
12
H'0018 to H'0019

Reserved for system use
13
H'001A to H'001B
Timer F
Timer FL compare match
Timer FL overflow
14
H'001C to H'001D
Timer FH compare match
Timer FH overflow
15
H'001E to H'001F

Reserved for system use
16, 17
H’0020 to H’0023
SCI3
Transmit end
Transmit data empty
Transmit data full
Receive error
18
H'0024 to H'0025
A/D converter
A/D conversion end
19
H'0026 to H'0027
CPU
Direct transition by execution of 20
SLEEP instruction
H'0028 to H'0029
Watchdog timer
External interrupt
pin/Low-voltage
detect circuit
(LVD)*
Low
Note: * The low-voltage detection circuit and low-voltage detection interrupt are implemented on
the H8/38104 Group only.
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Section 3 Exception Handling
3.2
Register Descriptions
Interrupts are controlled by the following registers.
•
•
•
•
•
•
•
Interrupt edge select register (IEGR)
Interrupt enable register 1 (IENR1)
Interrupt enable register 2 (IENR2)
Interrupt request register 1 (IRR1)
Interrupt request register 2 (IRR2)
Wakeup interrupt request register (IWPR)
Wakeup edge select register (WEGR)
3.2.1
Interrupt Edge Select Register (IEGR)
IEGR selects the direction of an edge that generates interrupt requests of pins and IRQ1 and IRQ0.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 1

Reserved
These bits are always read as 1.
4 to 2


W
Reserved
The write value should always be 0.
1
IEG1
0
R/W
IRQ1 and IRQ0 Edge Select
0
IEG0
0
R/W
0: Falling edge of IRQn pin input is detected
1: Rising edge of IRQn pin input is detected
(n = 1 or 0)
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Section 3 Exception Handling
3.2.2
Interrupt Enable Register 1 (IENR1)
IENR1 enables timers and external pin interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
IENTA
0
R/W
Timer A interrupt enable
Enables or disables timer A overflow interrupt requests.
0: Disables timer A interrupt requests
1: Enables timer A interrupt requests
6


W
Reserved
The write value should always be 0.
5
IENWP
0
R/W
Wakeup Interrupt Enable
Enables or disables WKP7 to WKP0 interrupt requests.
0: Disables WKP7 to WKP0 interrupt requests
1: Enables WKP7 to WKP0 interrupt requests
4, 3


W
Reserved
The write value should always be 0.
2
IENEC2
0
R/W
IRQAEC Interrupt Enable
Enables or disables IRQAEC interrupt requests.
0: Disables IRQAEC interrupt requests
1: Enables IRQAEC interrupt requests
1
IEN1
0
R/W
IRQ1 and IRQ0 Interrupt Enable
0
IEN0
0
R/W
Enables or disables IRQ1 and IRQ0 interrupt requests.
0: Disables IRQn interrupt requests
1: Enables IRQn interrupt requests
(n = 1, 0)
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Section 3 Exception Handling
3.2.3
Interrupt Enable Register 2 (IENR2)
IENR2 enables direct transition, A/D converter, and timer interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
IENDT
0
R/W
Direct Transition Interrupt enable
Enables or disables direct transition interrupt requests.
0: Disables direct transition interrupt requests
1: Enables direct transition interrupt requests
6
IENAD
0
R/W
A/D Converter Interrupt enable
Enables or disables A/D conversion end interrupt
requests.
0: Disables A/D converter interrupt requests
1: Enables A/D converter interrupt requests
5, 4


W
Reserved
The write value should always be 0.
3
IENTFH
0
R/W
Timer FH Interrupt Enable
Enables or disables timer FH compare match or overflow
interrupt requests.
0: Disables timer FH interrupt requests
1: Enables timer FH interrupt requests
2
IENTFL
0
R/W
Timer FL Interrupt Enable
Enables or disables timer FL compare match or overflow
interrupt requests.
0: Disables timer FL interrupt requests
1: Enables timer FL interrupt requests
1


W
Reserved
The write value should always be 0.
0
IENEC
0
R/W
Asynchronous Event Counter Interrupt Enable
Enables or disables asynchronous event counter interrupt
requests.
0: Disables asynchronous event counter interrupt
requests
1: Enables asynchronous event counter interrupt requests
For details on SCI3 interrupt control, refer to section 10.3.6, Serial Control Register 3 (SCR3).
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Section 3 Exception Handling
3.2.4
Interrupt Request Register 1 (IRR1)
IRR1 is a status flag register for timer A, IRQAEC, IRQ1, and IRQ0 interrupt requests. The
corresponding flag is set to 1 when an interrupt request occurs. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit
Bit Name
7
IRRTA
Initial
Value
R/W
Description
0
R/W *
Timer A Interrupt Request Flag
[Setting condition]
When the timer A counter value overflows
[Clearing condition]
When IRRTA = 1, it is cleared by writing 0
6, 4, 3


W
5

1

0
R/W *
Reserved
The write value should always be 0.
Reserved
This bit is always read as 1 and cannot be modified.
2
IRREC2
IRQAEC Interrupt Request Flag
[Setting condition]
When pin IRQAEC is designated for interrupt input and
the designated signal edge is detected
[Clearing condition]
When IRREC2 = 1, it is cleared by writing 0
1
0
IRRl1
IRRl0
0
0
R/W *
R/W *
IRQ1 and IRQ0 Interrupt Request Flag
[Setting condition]
When pin IRQn is designated for interrupt input and the
designated signal edge is detected
(n = 1, 0)
[Clearing condition]
When IRRI1 and IRRI0 = 1, they are cleared by writing 0
Note:
*
Only 0 can be written for flag clearing.
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Section 3 Exception Handling
3.2.5
Interrupt Request Register 2 (IRR2)
IRR2 is a status flag register for direct transition, A/D converter, timer FH, timer FL, and
asynchronous event counter interrupt requests. The corresponding flag is set to 1 when an interrupt
request occurs. The flags are not cleared automatically when an interrupt is accepted. It is
necessary to write 0 to clear each flag.
Bit
Bit Name
Initial
Value
R/W
Description
7
IRRDT
0
R/W *
Direct Transition Interrupt Request Flag
[Setting condition]
When a direct transition is made by executing a SLEEP
instruction while the DTON bit = 1
[Clearing condition]
When IRRDT = 1, it is cleared by writing 0
6
IRRAD
0
R/W *
A/D Converter Interrupt Request Flag
[Setting condition]
When A/D conversion is completed and the ADSF bit is
cleared to 0
[Clearing condition]
When IRRAD = 1, it is cleared by writing 0
5, 4


W
0
R/W *
Reserved
The write value should always be 0.
3
IRRTFH
Timer FH Interrupt Request Flag
[Setting condition]
When TCFH and OCRFH match in 8-bit timer mode, or
when TCF (TCFL, TCFH) and OCRF (OCRFL, OCRFH)
match in 16-bit timer mode
[Clearing condition]
When IRRTFH = 1, it is cleared by writing 0
2
IRRTFL
0
R/W *
Timer FL Interrupt Request Flag
[Setting condition]
When TCFL and OCRFL match in 8-bit timer mode
[Clearing condition]
When IRRTFL = 1, it is cleared by writing 0
1


W
Reserved
The write value should always be 0.
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Section 3 Exception Handling
Bit
Bit Name
0
IRREC
Initial
Value
R/W
Description
0
R/W *
Asynchronous Event Counter Interrupt Request Flag
[Setting condition]
When ECH overflows in 16-bit counter mode, or ECH or
ECL overflows in 8-bit counter mode
[Clearing condition]
When IRREC = 1, it is cleared by writing 0
Note:
*
3.2.6
Only 0 can be written for flag clearing.
Wakeup Interrupt Request Register (IWPR)
IWPR is a status flag register for WKP7 to WKP0 interrupt requests. The flags are not cleared
automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit
Bit Name
7
IWPF7
Initial
Value
R/W
Description
0
R/W *
Wakeup Interrupt Request Flag 7 to 0
[Setting condition]
6
IWPF6
0
R/W *
5
IWPF5
0
4
IWPF4
0
R/W *
R/W *
When pin WKPn is designated for wakeup input and the
designated edge is detected
3
IWPF3
0
(n = 7 to 0)
2
IWPF2
0
R/W *
R/W *
1
IWPF1
0
When IWPFn= 1, it is cleared by writing 0
0
IWPF0
0
R/W *
R/W *
Note:
*
[Clearing condition]
Only 0 can be written for flag clearing.
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Section 3 Exception Handling
3.2.7
Wakeup Edge Select Register (WEGR)
WEGR specifies rising or falling edge sensing for pins WKPn.
Bit
Bit Name
Initial
Value
R/W
7
WKEGS7
0
R/W
6
WKEGS6
0
R/W
5
WKEGS5
0
R/W
4
WKEGS4
0
R/W
3
WKEGS3
0
R/W
2
WKEGS2
0
R/W
1
WKEGS1
0
R/W
0
WKEGS0
0
R/W
3.3
Reset Exception Handling
Description
WKPn Edge Select 7 to 0
Selects WKPn pin input sensing.
0: WKPn pin falling edge is detected
1: WKPn pin rising edge is detected
(n = 7 to 0)
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-on, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1. The reset
exception handling sequence is as follows. However, refer to section 14.3.1, Power-On Reset
Circuit, for information on the reset sequence for the H8/38104 Group, which has a built-in
power-on reset function.
1. Set the I bit in the condition code register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
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Section 3 Exception Handling
3.4
Interrupt Exception Handling
3.4.1
External Interrupts
There are external interrupts, WKP7 to WKP0, IRQ1, IRQ0, and IRQAEC.
WKP7 to WKP0 Interrupts
WKP7 to WKP0 interrupts are requested by input signals to pins WKP7 to WKP0. These
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WKEGS7 to WKEGS0 in
WEGR.
When pins WKP7 to WKP0 are designated for interrupt input in PMR5 and the designated signal
edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bit IENWP in IENR1.
IRQ1 and IRQ0 Interrupts
IRQ1 and IRQ0 interrupts are requested by input signals to pins IRQ1 and IRQ0. These interrupts
are given different vector addresses, and are detected individually by either rising edge sensing or
falling edge sensing, depending on the settings of bits IEG1 and IEG0 in IEGR.
When pins IRQ1 and IRQ0 are designated for interrupt input by PMRB and PMR2 and the
designated signal edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an
interrupt. These interrupts can be masked by setting bits IEN1 and IEN0 in IENR1.
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Section 3 Exception Handling
IRQAEC Interrupt
The IRQAEC interrupt is requested by an input signal to pin IRQAEC. This interrupt is detected
by either rising edge sensing or falling edge sensing, depending on the settings of bits AIEGS1
and AIEGS0 in AEGSR.
When bit IENEC2 in IENR1 is designated for interrupt input and the designated signal edge is
input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
Reset cleared
Initial program
instruction prefetch
Vector fetch Internal
processing
φ
Internal
address bus
(2)
(1)
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
Figure 3.1 Reset Sequence
3.4.2
Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For direct transition interrupt requests generated by execution of a
SLEEP instruction, this function is included in IRR1 and IRR2.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
Rev. 6.00 Mar 15, 2005 page 85 of 502
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Section 3 Exception Handling
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable
bit.
3.4.3
Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the interrupt enable bit is set to 1, an interrupt request signal is sent
to the interrupt controller.
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.
3. Interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
5. Then, the I bit in CCR is set to 1, masking further interrupts. Upon return from interrupt
handling, the values of I bit and other bits in CCR will be restored and returned to the values
prior to the start of interrupt exception handling.
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Notes: 1. When disabling interrupts by clearing bits in the interrupt enable register, or when
clearing bits in the interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
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Section 3 Exception Handling
SP – 4
SP (R7)
CCR
SP – 3
SP + 1
CCR*
SP – 2
SP + 2
PCH
SP – 1
SP + 3
PCL
SP (R7)
SP + 4
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
Legend:
PCH : Upper 8 bits of program counter (PC)
PCL : Lower 8 bits of program counter (PC)
CCR: Condition code register
SP: Stack pointer
Notes: PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
* Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status after Exception Handling
3.4.4
Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 13
15 to 27
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note:
*
Not including EEPMOV instruction.
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REJ09B0024-0600
Figure 3.3 Interrupt Sequence
(2)
(1)
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
Internal data bus
(16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
φ
Interrupt
request signal
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
Section 3 Exception Handling
Section 3 Exception Handling
3.5
3.5.1
Usage Notes
Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests
are disabled immediately after a reset. Since the first instruction of a program is always executed
immediately after the reset state ends, make sure that this instruction initializes the stack pointer
(example: MOV.W #xx: 16, SP).
3.5.2
Notes on Stack Area Use
When word data is accessed, the least significant bit of the address is regarded as 0. Access to the
stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd
address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore
register values.
3.5.3
Interrupt Request Flag Clearing Method
Use the following recommended method for flag clearing in the interrupt request registers (IRR1,
IRR2, and IWPR).
Recommended Method: Perform flag clearing with only one instruction. Either a bit
manipulation instruction or a data transfer instruction in bytes can be used. Two examples of
coding for clearing IRRI1 (bit 1 in IRR1) are shown below:
• BCR #1,@IRR1:8
• MOV.B R1L,@IRR1:8 (Set B′11111101 to R1L in advance)
Malfunction Example: When flag clearing is performed with several instructions, a flag, other
than the intended one, which was set while executing one of those instructions may be accidentally
cleared, and thus cause incorrect operations to occur.
An example of coding for clearing IRRI1 (bit 1 in IRR1), in which IRRI0 is also cleared and the
interrupt becomes invalid is shown below.
MOV.B @IRR1:8,R1L
At this point, IRRI0 is 0.
AND.B #B′11111101,R1L
IRRI0 becomes 1 here.
MOV.B R1L,@IRR1:8
IRRI0 is cleared to 0.
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Section 3 Exception Handling
In the above example, an IRQ0 interrupt occurs while the AND.B instruction is executed. Since
not only the original target IRRI1, but also IRRI0 is cleared to 0, the IRQ0 interrupt becomes
invalid.
3.5.4
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQAEC,
IRQ1, IRQ0, and WKP7 to WKP0, the interrupt request flag may be set to 1.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.
Table 3.3 lists the interrupt request flags which are set to 1 and the conditions.
Table 3.3
Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request Flags
Set to 1
Conditions
IRR1
IRREC2
IRRI1
When the edge designated by AIEGS1 and AIEGS0 in AEGSR is input
while IENEC2 in IENRI is set to 1.
When IRQ1 bit in PMRB is changed from 0 to 1 while pin IRQ1 is low
and IEG1 bit in IEGR = 0.
When IRQ1 bit in PMRB is changed from 1 to 0 while pin IRQ1 is low
and IEG1 bit in IEGR = 1.
IRRI0
When IRQ0 bit in PMR2 is changed from 0 to 1 while pin IRQ0 is low
and IEG0 bit in IEGR = 0.
When IRQ0 bit in PMR2 is changed from 1 to 0 while pin IRQ0 is low
and IEG0 bit in IEGR = 1.
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Section 3 Exception Handling
Interrupt Request Flags
Set to 1
Conditions
IWPR
IWPF7
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low
and WEGR bit WKEGS7 = 0.
When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP7 is low
and WEGR bit WKEGS7 = 1.
IWPF6
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low
and WEGR bit WKEGS6 = 0.
When PMR5 bit WKP6 is changed from 1 to 0 while pin WKP6 is low
and WEGR bit WKEGS6 = 1.
IWPF5
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low
and WEGR bit WKEGS5 = 0.
When PMR5 bit WKP5 is changed from 1 to 0 while pin WKP5 is low
and WEGR bit WKEGS5 = 1.
IWPF4
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low
and WEGR bit WKEGS4 = 0.
When PMR5 bit WKP4 is changed from 1 to 0 while pin WKP4 is low
and WEGR bit WKEGS4 = 1.
IWPF3
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low
and WEGR bit WKEGS3 = 0.
When PMR5 bit WKP3 is changed from 1 to 0 while pin WKP3 is low
and WEGR bit WKEGS3 = 1.
IWPF2
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low
and WEGR bit WKEGS2 = 0.
When PMR5 bit WKP2 is changed from 1 to 0 while pin WKP2 is low
and WEGR bit WKEGS2 = 1.
IWPF1
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low
and WEGR bit WKEGS1 = 0.
When PMR5 bit WKP1 is changed from 1 to 0 while pin WKP1 is low
and WEGR bit WKEGS1 = 1.
IWPF0
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low
and WEGR bit WKEGS0 = 0.
When PMR5 bit WKP0 is changed from 1 to 0 while pin WKP0 is low
and WEGR bit WKEGS0 = 1.
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Section 3 Exception Handling
Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
CCR I bit ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register bit
Execute NOP instruction
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Clear interrupt request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
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Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
4.1
Features
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. In the H8/38104 Group, the system
clock pulse generator includes an on-chip oscillator. The system clock pulse generator consists of
a system clock oscillator and system clock dividers. The subclock pulse generator consists of a
subclock oscillator and a subclock divider.
Figure 4.1 shows a block diagram of the clock pulse generators of the H8/3802, H8/38004 and
H8/38002S Group. Figure 4.2 shows a block diagram of the clock pulse generators of the
H8/38104 Group.
φOSC/2
OSC1
OSC2
System
clock
oscillator
φOSC
(fOSC)
System
clock
divider (1/2)
System
clock
divider
System clock pulse generator
φOSC/16
φOSC/32
φOSC/64
φOSC/128
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
φW
X1
X2
Subclock
oscillator
φW/2
φW
Subclock
(fW)
divider
(1/2, 1/4, 1/8)
φW/4
φSUB
φW/8
φW/2
φW/4
Prescaler W
(5 bits)
Subclock pulse generator
φW/8
to
φW/128
Figure 4.1 Block Diagram of Clock Pulse Generators
(H8/3802, H8/38004, H8/38002S Group)
CPG0201A_000020020900
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Section 4 Clock Pulse Generators
Internal reset signal (other than watchdog timer or low-voltage detect
circuit reset)
C
IRQAEC
OSC1
OSC2
D
Latch
Q
System
clock
oscillator
On-chip
oscillator
φOSC
(fOSC)
φOSC/2
System
clock
divider
(1/2)
System
clock
divider
ROSC
φOSC/16
φOSC/32
φOSC/64
φOSC/128
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
System clock pulse generator
φW
φW/2
X1
X2
Subclock
oscillator
φW
(fW)
Subclock
divider
(1/2, 1/4, 1/8)
φW/4
φW/8
Subclock pulse generator
φSUB
φW/2
φW/4
Prescaler W
(5 bits)
φW/8
to
φW/128
Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38104 Group)
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2, and the
subclock is divided by prescaler W to become a clock signal from φw/128 to φw/8. Both the
system clock and subclock signals are provided to the on-chip peripheral modules.
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Section 4 Clock Pulse Generators
4.2
Register Description
Oscillator Control Register (OSCCR) (H8/38104 Group Only)
OSCCR contains a flag indicating the selection status of the system clock oscillator and on-chip
oscillator, indicates the input level of the IRQAEC pin during resets, and controls whether the
subclock oscillator operates or not.
Bit
Bit Name
Initial
Value
R/W
7
SUBSTP
0
R/W
Description
Subclock oscillator stop control
0: Subclock oscillator operates
1: Subclock oscillator stopped
Note: Bit 7 can be set to 1 only in the active mode (highspeed/medium-speed). Setting bit 7 to 1 in the
subactive mode will cause the LSI to stop
operating.
6

0
R
Reserved
This bit is always read as 0
5 to 3

All 0
R/W
Reserved
These bits are read/write enabled reserved bits.
2
IRQAECF

R
IRQAEC flag
This bit indicates the IRQAEC pin input level set during
resets.
0: IRQAEC pin set to GND during resets
1: IRQAEC pin set to VCC during resets
1
OSCF

R
OSC flag
This bit indicates the oscillator operating with the system
clock pulse generator.
0: System clock oscillator operating (on-chip oscillator
stopped)
1: On-chip oscillator operating (system clock oscillator
stopped)
0

0
R/W
Reserved
Never write 1 to this bit, as it can cause the LSI to
malfunction.
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Section 4 Clock Pulse Generators
4.3
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input. Figure 4.3 shows a block diagram of the system
clock generator.
As shown in figure 4.2, the H8/38104 Group supports selection between a system clock oscillator
and an on-chip oscillator. See section 4.3.4, on-chip oscillator selection method, for information
on selecting the on-chip oscillator.
OSC2
LPM
OSC1
Note: LPM: Power-down mode (standby mode, subactive mode,
subsleep mode, watch mode)
Figure 4.3 Block Diagram of System Clock Generator
4.3.1
Connecting Crystal Resonator
Figure 4.4(1) shows a typical method of connecting a crystal oscillator to the H8/3802 Group, and
figure 4.4(2) shows a typical method of connecting a crystal oscillator to the H8/38004, H8/38104
and H8/38002S Group. Figure 4.5 shows the equivalent circuit of a crystal resonator. A resonator
having the characteristics given in table 4.1 should be used.
C1
Frequency
OSC1
Rf
OSC2
C2
Manufacturer
C1, C2 Recommendation Value
4.19 MHz NIHON DEMPA KOGYO CO., LTD.
12 pF ±20%
C1 = C 2 = 12 pF ±20%
Rf = 1 MΩ ±20%
Note: Consult with the crystal resonator manufacturer
to determine the circuit constants.
Figure 4.4(1) Typical Connection to Crystal Resonator (H8/3802 Group)
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Section 4 Clock Pulse Generators
C1
OSC1
Rf
Frequency
Manufacturer
Prodoct
Name
C1, C2
Recommendation
Value
4.0 MHz
NIHON DEMPA KOGYO CO.,
LTD.
NR-18
12 pF ±20%
C2
OSC2
Rf = 1 MΩ ±20%
Note: Consult with the crystal resonator manufacturer
to determine the circuit constants.
Figure 4.4(2) Typical Connection to Crystal Resonator (H8/38004, H8/38002S, H8/38104
Group)
LS
RS
CS
OSC1
OSC2
C0
Figure 4.5 Equivalent Circuit of Crystal Resonator
Table 4.1
Crystal Resonator Parameters
Frequency (MHz)
4.10
4.193
RS (max)
100 Ω
C0 (max)
7 pF
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Section 4 Clock Pulse Generators
4.3.2
Connecting Ceramic Resonator
Figure 4.6(1) shows a typical method of connecting a ceramic oscillator to the H8/3802 Group,
and figure 4.6(2) shows a typical method of connecting a crystal oscillator to the H8/38004,
H8/38002S and H8/38104 Group.
C1
OSC1
Rf
C2
Frequency
Manufacturer
C1, C2 Recommendation Value
4.0 MHz
Murata Manufacturing Co., Ltd.
30 pF ±10%
OSC2
C1 = C 2 = 30 pF ±10%
Rf = 1 MΩ ±20%
Note: Consult with the ceramic resonator manufacturer
to determine the circuit constants.
Figure 4.6(1) Typical Connection to Ceramic Resonator (H8/3802 Group)
C1
OSC1
Rf
Manufacturer
Frequency
Prodoct Name
C2
OSC2
Ceramic
resonator
C1, C2
Recommendation
Value
2.0 MHz
Murata Manufacturing Co., CSTCC2M00G53-B0
Ltd.
CSTCC2M00G56-B0
15 pF ±20%
10.0 MHz
CSTLS10M0G53-B0
15 pF ±20%
CSTLS10M0G56-B0
47 pF ±20%
16.0 MHz*1
CSTLS16M0X53-B0
15 pF ±20%
20.0 MHz*2
CSTLS20M0X53-B0
15 pF ±20%
47 pF ±20%
Rf = 1 MΩ ±20%
Notes: Consult with the crystal resonator manufacturer
to determine the circuit constants.
1. This does not apply to the H8/38004 and H8/38002S Group.
2. H8/38104 Group only.
Figure 4.6(2) Typical Connection to Ceramic Resonator
(H8/38004, H8/38002S, H8/38104 Group)
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Section 4 Clock Pulse Generators
4.3.3
External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.7 shows a
typical connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1
OSC2
External clock input
Open
Figure 4.7 Example of External Clock Input
4.3.4
On-Chip Oscillator Selection Method (H8/38104 Group Only)
The on-chip oscillator is selected by setting the IRQAEC pin input level during resets*. The
IRQAEC pin input level set during resets must be fixed at VCC or GND, based on the oscillator to
be selected. It is not necessary to connect an oscillator to pins OSC1 and OSC2 if the on-chip
oscillator is selected. In this case, pin OSC1 should be fixed at VCC or GND.
Notes: The system clock oscillator must be selected in order to program or erase flash memory as
part of operations such as on-board programming. Also, when using the on-chip emulator,
an oscillator should be connected, or an external clock input, even if the on-chip oscillator
is selected.
* Other than watchdog timer or low-voltage detect circuit reset.
Table 4.2
System Clock Oscillator and On-Chip Oscillator Selection Methods
IRQAEC pin input level (during resets)
0
1
System clock oscillator
Enabled
Disabled
On-chip oscillator
Disabled
Enabled
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Section 4 Clock Pulse Generators
4.4
Subclock Generator
Figure 4.8 shows a block diagram of the subclock generator. Note that on the H8/38104 Group the
subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR
register. The register setting to disable the subclock oscillator should be made in the active mode.
When restoring operation of the subclock oscillator after it has been disabled using the OSCCR
register, it is necessary to wait for the oscillation stabilization time (typ = 8s) to elapse before
using the subclock.
X2
10 M
X1
Note : Resistance is a reference value.
Figure 4.8 Block Diagram of Subclock Generator
4.4.1
Connecting 32.768-kHz/38.4-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz or 38.4-kHz
crystal resonator, as shown in figure 4.9. Figure 4.10 shows the equivalent circuit of the 32.768kHz or 38.4-kHz crystal resonator. Note that only operation at 32.768 kHz is guaranteed on the
H8/38104 Group.
C1
X1
C2
Frequency
Manufacturer
Product Name
38.4 kHz
Seiko Instruments Inc.
VTC-200
32.768 kHz NIHON DEMPA KOGYO CO., LTD.
MX73P
X2
C1 = C 2 = 6 to 12.5 pF (typ.)
Note: Consult with the crystal resonator manufacturer
to determine the circuit constants.
Figure 4.9 Typical Connection to 32.768-kHz/38.4-kHz Crystal Resonator
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Section 4 Clock Pulse Generators
LS
RS
CS
X1
X2
CO
CO = 0.8 pF (typ.)
RS = 14 kΩ (typ.)
fW = 32.768 kHz/38.4 kHz
Note: Constants are reference values.
Figure 4.10 Equivalent Circuit of 32.768-kHz/38.4-kHz Crystal Resonator
4.4.2
Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure
4.11.
X1
GND
X2
Open
Figure 4.11 Pin Connection when Not Using Subclock
4.4.3
External Clock Input
Connect the external clock to pin X1 and leave pin X2 open, as shown in figure 4.12.
Note that input of an external clock is not supported on the H8/38104 Group.
External clock input
X1
X2
Open
Figure 4.12 Pin Connection when Inputting External Clock
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Section 4 Clock Pulse Generators
Frequency
Subclock (φ
φw)
Duty
45% to 55%
4.5
Prescalers
4.5.1
Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from
the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system
clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot
read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules.
The division ratio can be set separately for each on-chip peripheral function. In active (mediumspeed) mode and sleep mode, the clock input to prescaler S is determined by the division ratio
designated by the MA1 and MA0 bits in SYSCR2.
4.5.2
Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φW/4) as its
input clock. The divided output is used for clock time base operation of timer A. Prescaler W is
initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby
mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 in TMA.
4.6
Usage Notes
4.6.1
Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit constants will differ
depending on the resonator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the resonator manufacturer.
Design the circuit so that the resonator never receives voltages exceeding its maximum rating.
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Section 4 Clock Pulse Generators
PB3
X1
X2
Vss
OSC2
OSC1
TEST
(Vss)
Figure 4.13 Example of Crystal and Ceramic Resonator Arrangement
Figure 4.14 (1) shows an example of the measurement circuit for the negative resistor which is
recommended by the resonator manufacturer. Note that if the negative resistor in this circuit does
not reach the level which is recommended by the resonator manufacturer, the main oscillator may
be hard to start oscillation.
If the negative resistor does not reach the level which is recommended by the resonator
manufacturer and oscillation is not started, changes as shown in figure 4.14 (2) to (4) should be
made. The proposed change and capacitor size to be applied should be determined according to the
evaluation result of the negative resistor and frequency deviation, etc.
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Section 4 Clock Pulse Generators
Change
OSC1
OSC1
C1
C1
Rf
Rf
OSC2
OSC2
C2
C2
Negative resistor -R added
(1) Negative resistor measurement circuit
(2) Proposed Change in Oscillator Circuit 1
Change
Change
C3
OSC1
OSC1
C1
C1
Rf
Rf
OSC2
OSC2
C2
C2
(3) Proposed Change in Oscillator Circuit 2
(4) Proposed Change in Oscillator Circuit 3
Figure 4.14 Negative Resistor Measurement and Proposed Changes in Circuit
4.6.2
Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the
resonator circuit to prevent induction from interfering with correct oscillation (see figure 4.15).
Avoid
Signal A
Signal B
C1
OSC1
C2
OSC2
Figure 4.15 Example of Incorrect Board Design
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Section 4 Clock Pulse Generators
4.6.3
Definition of Oscillation Stabilization Standby Time
Figure 4.16 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with a resonator connected to the system clock
oscillator.
As shown in figure 4.16, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation stabilization time and standby time) is required.
1. Oscillation stabilization time (trc)
The time from the point at which the oscillation waveform of the system clock oscillator starts to
change when an interrupt is generated, until the amplitude of the oscillation waveform increases
and the oscillation frequency stabilizes.
2. Standby time
The time required for the CPU and peripheral functions to begin operating after the oscillation
waveform frequency and system clock have stabilized.
The standby time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to
4 in the system control register 1 (SYSCR1)).
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Section 4 Clock Pulse Generators
Oscillation waveform
(OSC2)
System clock
(φ)
Oscillation stabilization time
Standby time
Standby mode,
Operating mode watch mode,
or subactive mode
Oscillation stabilization standby time
Active (high-speed) mode
or
active (medium-speed) mode
Interrupt accepted
Figure 4.16 Oscillation Stabilization Standby Time
When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a
transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to
change at the point at which the interrupt is accepted. Therefore, when a resonator is connected in
standby mode, watch mode, or subactive mode, since the system clock oscillator is halted, the time
from the point at which this oscillation waveform starts to change until the amplitude of the
oscillation waveform increases and the oscillation frequency stabilizes—that is, the oscillation
stabilization time—is required.
The oscillation stabilization time in the case of these state transitions is the same as the oscillation
stabilization time at power-on (the time from the point at which the power supply voltage reaches
the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time trc "
in the AC characteristics.
Meanwhile, once the system clock has halted, a standby time is necessary in order for the CPU
and peripheral functions to operate normally.
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation stabilization time and standby time. This
total time is called the oscillation stabilization standby time, and is expressed by equation (1)
below.
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Section 4 Clock Pulse Generators
Oscillation stabilization standby time = oscillation stabilization time + standby time
= trc +(8 to 16,384 states) *1................. (1)
(to 131,072 states) *2
Notes: 1. H8/3802 Group, H8/38004 and H8/38002S Group
2. H8/38104 Group
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with a resonator connected to the system clock
oscillator, careful evaluation must be carried out on the installation circuit before deciding on the
oscillation stabilization standby time. In particular, since the oscillation settling time is affected by
installation circuit constants, stray capacitance, and so forth, suitable constants should be
determined in consultation with the resonator manufacturer.
4.6.4
Notes on Use of Resonator
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual resonator characteristics, the
oscillation waveform amplitude may not be sufficiently large immediately after the oscillation
stabilization standby time, making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential. In this state, the oscillation waveform may be disrupted,
leading to an unstable system clock and erroneous operation of the microcomputer.
If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer standby time.
For example, if erroneous operation occurs with a standby time setting of 16 states, check the
operation with a standby time setting of 1,024* states or more.
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
Note: * This figure applies to the H8/3802, H8/38004 and H8/38002S Groups. The number of
states on the H8/38104 Group is 8,192 or more.
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Section 4 Clock Pulse Generators
4.6.5
Notes on H8/38104 Group
When using the on-chip emulator, system clock precision is necessary for programming or erasing
the flash memory. However, the on-chip oscillator frequency can vary due to changes in
conditions such as voltage or temperature. Consequently, when using the on-chip emulator, pins
OSC1 and OSC2 should be connected to an oscillator, or an external clock should be supplied, if
the on-chip oscillator is selected. In this case, the LSI uses the on-chip oscillator when user
programs are being executed and the system clock oscillator when programming or erasing flash
memory. The process is controlled by the on-chip emulator.
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REJ09B0024-0600
Section 5 Power-Down Modes
Section 5 Power-Down Modes
This LSI has eight modes of operation after a reset. These include a normal active (high-speed)
mode and seven power-down modes, in which power consumption is significantly reduced. The
module standby function reduces power consumption by selectively halting on-chip module functions.
• Active (medium-speed) mode
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc/16, φosc/32, φosc/64, and φosc/128.
• Subactive mode
The CPU and all on-chip peripheral modules are operable on the subclock. The subclock frequency can be selected from φw/2, φw/4, and φw/8.
• Sleep (high-speed) mode
The CPU halts. On-chip peripheral modules are operable on the system clock.
• Sleep (medium-speed) mode
The CPU halts. On-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc/16, φosc/32, φosc/64, and φosc/128.
• Subsleep mode
The CPU halts. The timer A, timer F, SCI3, AEC, and LCD controller/driver are operable on
the subclock. The subclock frequency can be selected from φw/2, φw/4, and φw/8.
• Watch mode
The CPU halts. Timer A's timekeeping function, timer F, AEC, and LCD controller/driver are
operable on the subclock.
• Standby mode
The CPU and all on-chip peripheral modules halt.
• Module standby function
Independent of the above modes, power consumption can be reduced by halting on-chip peripheral modules that are not used in module units.
Note: In this manual, active (high-speed) mode and active (medium-speed) mode are collectively
called active mode.
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Section 5 Power-Down Modes
5.1
Register Descriptions
The registers related to power-down modes are as follows.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Clock halt registers 1 and 2 (CKSTPR1 and CKSTPR2)
5.1.1
System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit
Bit Name
Initial
Value
R/W
Description
7
SSBY
0
R/W
Software Standby
Selects the mode to transit after the execution of the
SLEEP instruction.
0: A transition is made to sleep mode or subsleep mode.
1: A transition is made to standby mode or watch mode.
For details, see table 5.2.
6
STS2
0
R/W
Standby Timer Select 2 to 0
5
STS1
0
R/W
4
STS0
0
R/W
Designate the time the CPU and peripheral modules wait
for stable clock operation after exiting from standby
mode, subactive mode, subsleep mode, or watch mode
to active mode or sleep mode due to an interrupt. The
designation should be made according to the operating
frequency so that the waiting time is at least equal to the
oscillation stabilization time. The relationship between the
specified value and the number of wait states is shown in
tables 5.1(1) and 5.1(2).
When an external clock is to be used, the minimum value
(STS2 = 1, STS1 = 0, STS0 = 1) is recommended. 8,192
states (STS2 = STS1 = STS0 = 0) is recommended if the
on-chip oscillator is used on the H8/38104 Group. If the
setting other than the recommended value is made, operation may start before the end of the waiting time.
3
LSON
0
R/W
Selects the system clock (φ) or subclock (φSUB) as the
CPU operating clock when watch mode is cleared.
0: The CPU operates on the system clock (φ)
1: The CPU operates on the subclock (φSUB)
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Section 5 Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
2

1

Reserved
1
MA1
1
R/W
Active Mode Clock Select 1 and 0
0
MA0
1
R/W
Select φOSC/16, φOSC/32, φOSC/64, or φOSC/128 as the operating clock in active (medium-speed) mode and sleep
(medium-speed) mode. The MA1 and MA0 bits should be
written to in active (high-speed) mode or subactive mode.
This bit is always read as 1 and cannot be modified.
00: φOSC/16
01: φOSC/32
10: φOSC/64
11: φOSC/128
Table 5.1(1) Operating Frequency and Waiting Time (H8/3802 Group, H8/38004 Group,
H8/38002S Group)
Bit
Operating Frequency
STS2
STS1
STS0
0
0
0
1
1
1
0
1
Waiting Time
5 MHz
2 MHz
8,192 states
1.638
4.1
16,384 states
3.277
8.2
0
1,024 states
0.205
0.512
1
2,048 states
0.410
1.024
0
4,096 states
0.819
2.048
1
2 states (external clock input)
0.0004
0.001
0
8 states
0.002
0.004
1
16 states
0.003
0.008
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Section 5 Power-Down Modes
Table 5.1(2) Operating Frequency and Waiting Time (H8/38104 Group)
Bit
Operating Frequency
STS2
STS1
STS0
0
0
0
1
1
0
1
Waiting Time
5 MHz
2 MHz
8,192 states
1.638
4.1
1
16,384 states
3.277
8.2
0
32,768 states
6.554
16.4
1
65,536 states
13.108
32.8
0
131,072 states
26.216
65.5
1
2 states (external clock input)
0.0004
0.001
0
8 states
0.002
0.004
1
16 states
0.003
0.008
Note: The time unit is ms.
If external clock input is used, STS2 to STS0 should be set to the external clock input mode
before the mode transition is executed. In addition, STS2 to STS0 should not be set to the
external clock input mode if external clock input is not used. When the on-chip clock oscillator is used on the H8/38104 Group, a setting of 8,192 states (STS2 = STS1 = STS0 = 0)
is recommended.
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Section 5 Power-Down Modes
5.1.2
System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5

All 1

Reserved
These bits are always read as 1 and cannot be modified.
4
NESEL
1
R/W
Noise Elimination Sampling Frequency Select
Selects the frequency at which the watch clock signal
(φW ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (φOSC) generated
by the system clock pulse generator. When φOSC = 2 to
16 MHz, clear this bit to 0.
0: Sampling rate is φOSC/16.
1: Sampling rate is φOSC/4.
3
DTON
0
R/W
Direct Transfer on Flag
Selects the mode to which the transition is made after
the SLEEP instruction is executed with bits SSBY and
LSON in SYSCR1, bit MSON in SYSCR2, and bit TMA3
in TMA.
For details, see table 5.2.
2
MSON
0
R/W
Medium Speed on Flag
After standby, watch, or sleep mode is cleared, this bit
selects active (high-speed) or active (medium-speed)
mode.
0: Operation in active (high-speed) mode
1: Operation in active (medium-speed) mode
1
SA1
0
R/W
Subactive Mode Clock Select 1 and 0
0
SA0
0
R/W
Select the operating clock frequency in subactive and
subsleep modes. The operating clock frequency
changes to the set frequency after the SLEEP instruction is executed.
00: φW /8
01: φW /4
1X: φW /2
Legend: X: Don't care.
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Section 5 Power-Down Modes
5.1.3
Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2)
CKSTPR1 and CKSTPR2 allow the on-chip peripheral modules to enter a standby state in module
units.
• CKSTPR1
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
5
S32CKSTP
1
R/W
SCI Module Standby
SCI3 enters standby mode when this bit is cleared to
0.*1
4
ADCKSTP
1
R/W
A/D Converter Module Standby
A/D converter enters standby mode when this bit is
cleared to 0.
3

1

Reserved
2
TFCKSTP
1
R/W
Timer F Module Standby
Timer F enters standby mode when this bit is cleared to
0.
1

1

Reserved
0
TACKSTP
1
R/W
Timer A Module Standby*2
Timer A enters standby mode when this bit is cleared to
0.
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Section 5 Power-Down Modes
• CKSTPR2
Bit
Bit Name
Initial
Value
R/W
7
LVDCKSTP
1
R/W
Description
LVD module standby
The LVD module enters standby status when this bit is
cleared to 0.
Note: On products other than the H8/38104 Group,
this bit is reserved like bits 6 and 5.
6, 5
4

All 1
PW2CKSTP 1

Reserved
R/W *3
PWM2 Module Standby
PWM2 enters standby mode when this bit is cleared to
0.
3
AECKSTP
1
R/W
Asynchronous Event Counter Module Standby
Asynchronous event counter enters standby mode
when this bit is cleared to 0
2
WDCKSTP
1
R/W *4
Watchdog Timer Module Standby
Watchdog timer enters standby mode when this bit is
cleared to 0
1
PW1CKSTP 1
R/W
PWM1 Module Standby
PWM1 enters standby mode when this bit is cleared to
0
0
LDCKSTP
1
R/W
LCD Module Standby
LCD controller/driver enters standby mode when this bit
is cleared to 0
Notes: 1. When the SCI module standby is set, all registers in the SCI3 enter the reset state.
2. When the timer A module standby is set, the TMA3 bit in TMA cannot be rewritten.
When the TMA3 bit is rewritten, the TACKSTP bit in CKSTPR1 should be set to 1 in
advance.
3. This bit cannot be read or written in the H8/3802 Group.
4. This bit cannot be read or written in the H8/3802 Group. This bit is valid when the
WDON bit in TCSRW is 0. If this bit is cleared to 0 while the WDON bit is set to 1 (while
the watchdog timer is operating), this bit is cleared to 0. However, the watchdog timer
does not enter module standby mode and continues operating. When the watchdog
timer stops operating and the WDON bit is cleared to 0 by software, this bit is valid and
the watchdog timer enters module standby mode.
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Section 5 Power-Down Modes
5.2
Mode Transitions and States of LSI
Figure 5.1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state
of the program. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program. The operating frequency can also
be changed in the same modes by making a transition directly from active mode to active mode,
and from subactive mode to subactive mode. RES input enables transitions from a mode to the
reset state. Table 5.2 shows the transition conditions of each mode after the SLEEP instruction is
executed and a mode to return by an interrupt. Table 5.3 shows the internal states of the LSI in
each mode.
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Section 5 Power-Down Modes
Program
execution state
Reset state
Program
SLEEP d
instruction
halt state
Standby
SLEEP
instruction a
Active
(high-speed
mode)
a
P n
E
E tio
SL truc
s
in
g
d SLEEP
instruction
f
SLEEP
instruction
P n
EE tio
SL truc
s
in
SLEEP
instruction
Sleep
(high-speed)
mode
3
4
mode
Program
halt state
4
b
SLEEP b
instruction
Active
(medium-speed)
mode
e
SLEEP
instruction
1
Sleep
(medium-speed)
mode
j
SLEEP
instruction
S
ins LE
tru EP
cti
on
e
i
1
Watch
3
SLEEP
instruction
i
h
SLEEP
instruction
e
SLEEP
instruction
Subactive
1
mode
mode
SLEEP
instruction
SLEEP
instruction c
Subsleep
2
: Transition is made after exception handling
mode
Power-down modes
is executed.
Mode Transition Conditions (1)
LSON
Mode Transition Conditions (2)
MSON SSBY
Interrupt Sources
TMA3
DTON
a
0
0
0
*
0
b
0
1
0
*
0
c
1
*
0
1
0
d
0
*
1
0
0
e
*
*
1
1
0
f
0
0
0
*
1
3
All interrupts
g
0
1
0
*
1
4
IRQ1 or IRQ0, WKP7 to WKP0 interrupts
h
0
1
1
1
1
i
1
*
1
1
1
j
0
0
1
1
1
1
Timer A, Timer F, IRQ0 interrupt,
WKP7 to WKP0 interrupts
2
Timer A, Timer F, SCI3 interrupt, IRQ1 and
IRQ0, IRQAEC interrupts, WKP7 o WKP0
interrupts, AEC
Legend: * Don't care
Note: A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupts are enabled.
Figure 5.1 Mode Transition Diagram
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Section 5 Power-Down Modes
Table 5.2
Transition Mode after SLEEP Instruction Execution and Interrupt Handling
LSON
MSON
SSBY
TMA3
DTON
Transition Mode after
SLEEP Instruction
Execution
0
0
0
X
0
Sleep (high-speed) mode Active (high-speed) mode
0
1
0
X
0
Sleep (medium-speed)
mode
Active (medium-speed)
mode
1
X
0
1
0
Subsleep mode
Subactive mode
0
X
1
0
0
Standby mode
Active mode
X
X
1
1
0
Watch mode
Active mode, subactive
mode
0
0
0
X
1
Active (high-speed) mode 
0
1
0
X
1
Active (medium-speed)
mode

0
1
1
1
1
Active (medium-speed)
mode

1
X
1
1
1
Subactive mode (direct
transition)

0
0
1
1
1
Active (high-speed) mode 
(direct transition)
Legend: X: Don’t care.
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Transition Mode due to
Interrupt
Section 5 Power-Down Modes
Table 5.3
Internal State in Each Operating Mode
Active Mode
Sleep Mode
Subactive
Mode
Subsleep Stand-by
Mode
Mode
Halted
Halted
Halted
Halted
Functioning
Functioning
Functioning
Functioning
Functioning
Halted
Halted
Functioning
Halted
Halted
Function
Highspeed
Medium- Highspeed
speed
Medium- Watch
speed
Mode
System clock oscillator
Functioning
Functioning
Functioning
Functioning
Subclock oscillator
Functioning
Functioning
Functioning
CPU
Functioning
Functioning
Halted
Instructions
RAM
Retained Retained Retained
Retained Retained
Registers
I/O
External IRQ0
interrupts
Re1
tained*
Functioning
Functioning
Functioning
Functioning
IRQ1
WKP7 to
WKP0
Timer A
Functioning
Functioning
Retained*5
IRQAEC
Peripheral
modules
Functioning
Retained*5
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Functioning
Func4
tioning *
Func4
tioning *
Func4
tioning *
Retained
Asynchronous
counter
Func6
tioning *
Functioning
Functioning
Func6
tioning *
Timer F
Function- Function- Function- Retained
ing/reta- ing/reta- ing/reta7
7
7
ined*
ined*
ined*
WDT
Function- Function- Function- Functioning/reta- ing/reta- ing/reta- ing/reta9
8
9
10
ined*
ined*
ined*
ined*
SCI3
Functioning
Functioning
Functioning
Functioning
Reset
Function- Function- Reset
ing/reta- ing/reta2
2
ined*
ined*
PWM
Functioning
Functioning
Functioning
Functioning
Retained Retained Retained Retained
Rev. 6.00 Mar 15, 2005 page 119 of 502
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Section 5 Power-Down Modes
Active Mode
Subactive
Mode
Highspeed
Medium- Highspeed
speed
Medium- Watch
Mode
speed
A/D converter
Functioning
Functioning
Functioning
Functioning
Retained Retained Retained Retained
LCD
Functioning
Functioning
Functioning
Functioning
Function- Function- Function- Retained
ing/reta- ing/reta- ing/reta3
3
3
ined*
ined*
ined*
LVD
Functioning
Functioning
Functioning
Functioning
Functioning
Function
Peripheral
modules
Sleep Mode
Functioning
Subsleep Stand-by
Mode
Mode
Functioning
Functioning
Notes: 1. Register contents are retained. Output is the high-impedance state.
2. Functioning if φW /2 is selected as an internal clock, or halted and retained otherwise.
3. Functioning if φw, φw/2, or φw/4 is selected as a clock to be used. Halted and retained
otherwise.
4. Functioning if the timekeeping time-base function is selected.
5. An external interrupt request is ignored. Contents of the interrupt request register are
not affected.
6. The counter can be incremented. An interrupt cannot occur.
7. Functioning if φw/4 is selected as an internal clock. Halted and retained otherwise.
8. On the H8/38104 Group, operates when φw/32 is selected as the internal clock or the
on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004,
H8/38002S Group, operates when φw/32 is selected as the internal clock; otherwise
stops and stands by.
9. On the H8/38104 Group, operates when φw/32 is selected as the internal clock or the
on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004,
H8/38002S Group, stops and stands by.
10. On the H8/38104 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38004, H8/38002S Group, stops and stands by.
5.2.1
Sleep Mode
In sleep mode, CPU operation is halted but the system clock oscillator, subclock oscillator, and
on-chip peripheral modules function. In sleep (medium-speed) mode, the on-chip peripheral modules function at the clock frequency set by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Sleep mode is cleared by an interrupt. When an interrupt is requested, sleep mode is cleared and
interrupt exception handling starts. Sleep mode is not cleared if the I bit in CCR is set to 1 or the
requested interrupt is disabled by the interrupt enable bit. After sleep mode is cleared, a transition
is made from sleep (high-speed) mode to active (high-speed) mode or from sleep (medium-speed)
mode to active (medium-speed) mode.
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Section 5 Power-Down Modes
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. Since an
interrupt request signal is synchronous with the system clock, the maximum time of 2/φ (s) may be
delayed from the point at which an interrupt request signal occurs until the interrupt exception
handling is started.
Furthermore, it sometimes operates with half state early timing at the time of transition to sleep
(medium-speed) mode.
5.2.2
Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop
functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, onchip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, standby mode is
cleared and interrupt exception handling starts. After standby mode is cleared, a transition is made
to active (high-speed) or active (medium-speed) mode according to the MSON bit in SYSCR2.
Standby mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled by
the interrupt enable bit.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
5.2.3
Watch Mode
In watch mode, the system clock oscillator and CPU operation stop and on-chip peripheral modules stop functioning except for the timer A, timer F, asynchronous event counter, and LCD controller/driver. However, as long as the rated voltage is supplied, the contents of CPU registers,
some on-chip peripheral module registers, and on-chip RAM are retained. The I/O ports retain
their state before the transition.
Watch mode is cleared by an interrupt. When an interrupt is requested, watch mode is cleared and
interrupt exception handling starts. When watch mode is cleared by an interrupt, a transition is
made to active (high-speed) mode, active (medium-speed) mode, or subactive mode depending on
the settings of the LSON bit in SYSCR1 and the MSON bit in SYSCR2. When the transition is
made to active mode, after the time set in bits STS2 to STS0 in SYSCR1 has elapsed, interrupt
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Section 5 Power-Down Modes
exception handling starts. Watch mode is not cleared if the I bit in CCR is set to 1 or the requested
interrupt is disabled by the interrupt enable bit.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
5.2.4
Subsleep Mode
In subsleep mode, the CPU operation stops but on-chip peripheral modules other than the A/D
converter and PWM function. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O
ports keep the same states as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. After subsleep mode is cleared, a transition is made to
subactive mode. Subsleep mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
5.2.5
Subactive Mode
In subactive mode, the system clock oscillator stops but on-chip peripheral modules other than the
A/D converter and PWM function. As long as a required voltage is applied, the contents of some
registers of the on-chip peripheral modules are retained.
Subactive mode is cleared by the SLEEP instruction. When subacitve mode is cleared, a transition
to subsleep mode, active mode, or watch mode is made, depending on the combination of bits
SSBY and LSON in SYSCR1, bits MSON and DTON in SYSCR2, and bit TMA3 in TMA.
Subactive mode is not cleared if the I bit in CCR is set to 1 or the requested interrupt is disabled in
the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
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Section 5 Power-Down Modes
The operating frequency of subactive mode is selected from φW/2, φW/4, and φW/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is executed, the operating frequency changes to
the frequency which is set before the execution.
5.2.6
Active (Medium-Speed) Mode
In active (medium-speed) mode, the system clock oscillator, subclock oscillator, CPU, and on-chip
peripheral modules function.
Active (medium-speed) mode is cleared by the SLEEP instruction. When active (medium-speed)
mode is cleared, a transition to standby mode is made depending on the combination of bits SSBY
and LSON in SYSCR1 and bit TMA3 in TMA, a transition to watch mode is made depending on
the combination of bit SSBY in SYSCR1 and bit TMA3 in TMA, or a transition to sleep mode is
made depending on the combination of bits SSBY and LSON in SYSCR1. Moreover, a transition
to active (high-speed) mode or subactive mode is made by a direct transition. Active (mediumsleep) mode is not entered if the I bit in CCR is set to 1 or the requested interrupt is disabled in the
interrupt enable register. When the RES pin goes low, the CPU goes into the reset state and active
(medium-sleep) mode is cleared.
Furthermore, it sometimes operates with half state early timing at the time of transition to active
(medium-speed) mode.
In active (medium-speed) mode, the on-chip peripheral modules function at the clock frequency
set by the MA1 and MA0 bits in SYSCR1.
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Section 5 Power-Down Modes
5.3
Direct Transition
The CPU can execute programs in two modes: active and subactive mode. A direct transition is a
transition between these two modes without stopping program execution. A direct transition can
be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct
transition also enables operating frequency modification in active or subactive mode. After the
mode transition, direct transition interrupt exception handling starts.
If the direct transition interrupt is disabled in interrupt permission register 2, a transition is made
instead to sleep or watch mode. Note that if a direct transition is attempted while the I bit in CCR
is set to 1, sleep or watch mode will be entered, and the resulting mode cannot be cleared by
means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the
DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep
mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0,
the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (high-speed) mode via watch mode after the waiting time set in bits STS2 to
STS0 in SYSCR1 has elapsed.
• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON
bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA
is set to 1, a transition is made to subactive mode via watch mode.
Rev. 6.00 Mar 15, 2005 page 124 of 502
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Section 5 Power-Down Modes
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the
DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in bits STS2
to STS0 in SYSCR1 has elapsed.
5.3.1
Direct Transition from Active (High-Speed) Mode to Active (Medium-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (1).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} • (tcyc before transition) + (Number of interrupt exception handling execution states) • (tcyc after transition)
…………………(1)
Example:
Direct transition time = (2 + 1) • 2tosc + 14 • 16tosc = 230tosc (when φ/8 is selected as the CPU operating clock)
Legend:
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
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Section 5 Power-Down Modes
5.3.2
Direct Transition from Active (Medium-Speed) Mode to Active (High-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (2).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} • (tcyc before transition) + (Number of interrupt exception handling execution states) • (tcyc after transition)
………………..(2)
Example:
Direct transition time = (2 + 1) • 16tosc + 14 • 2tosc = 76tosc (when φ/8 is selected as the CPU operating clock)
Legend:
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
5.3.3
Direct Transition from Subactive Mode to Active (High-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (3).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} • (tsubcyc before transition) + {(Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states)} • (tcyc after transition)
………………..(3)
Example:
Legend:
tosc:
tw:
tcyc:
tsubcyc:
Direct transition time = (2 + 1) • 8tw + (8192 + 14) • 2tosc = 24tw + 16412tosc
(when φw/8 is selected as the CPU operating clock and wait time = 8192 states)
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
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Section 5 Power-Down Modes
5.3.4
Direct Transition from Subactive Mode to Active (Medium-Speed) Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (4).
Direct transition time = {(Number of SLEEP instruction execution states) + (Number of internal
processing states)} • (tsubcyc before transition) + {(Wait time set in bits
STS2 to STS0) + (Number of interrupt exception handling execution
states)} • (tcyc after transition)
………………..(4)
Example:
Legend:
tosc:
tw:
tcyc:
tsubcyc:
5.3.5
Direct transition time = (2 + 1) • 8tw + (8192 + 14) • 16tosc = 24tw +
131296tosc (when φw/8 or φ/8 is selected as the CPU operating clock and wait
time = 8192 states)
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
Notes on External Input Signal Changes before/after Direct Transition
• Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
• Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 5.5.2, Notes on External
Input Signal Changes before/after Standby Mode.
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Section 5 Power-Down Modes
5.4
Module Standby Function
The module-standby function can be set to any peripheral module. In module standby mode, the
clock supply to modules stops to enter the power-down mode. Module standby mode enables each
on-chip peripheral module to enter the standby state by clearing a bit that corresponds to each
module in CKSTPR1 and CKSTPR2 to 0 and cancels the mode by setting the bit to 1. (See section
5.1.3, Clock Halt Registers 1 and 2 (CKSTPR1 and CKSTPR2).)
5.5
Usage Notes
5.5.1
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows the
timing in this case.
φ
Internal data bus
SLEEP instruction fetch
Next instruction fetch
SLEEP instruction execution
Pins
Internal processing
Port output
Active (high-speed) mode or active (medium-speed) mode
High-impedance
Standby mode
Figure 5.2 Standby Mode Transition and Pin States
5.5.2
Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode
When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and
low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB
(referred to together in this section as the internal clock). As the internal clock stops in standby
mode and watch mode, the width of external input signals requires careful attention when a
transition is made via these operating modes. Ensure that external input signals conform to the
conditions stated in 3, Recommended timing of external input signals, below.
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Section 5 Power-Down Modes
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is shown in figure 5.3.
As shown in the case marked "Capture not possible," when an external input signal falls immediately after a transition to active (high-speed or medium-speed) mode or subactive mode,
after oscillation is started by an interrupt via a different signal, the external input signal cannot
be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc.
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch
mode, as shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case
2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
Operating mode
Active (high-speed, medium-speed)
mode or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
Standby mode or
watch mode
Wait for oscillation
stabilization
Active (high-speed, medium-speed)
mode or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
φ or φSUB
External input signal
Capture possible: case 1
Capture possible: case 2
Capture possible: case 3
Capture not possible
Interrupt by different signal
Figure 5.3 External Input Signal Capture when Signal Changes before/after Standby Mode
or Watch Mode
4. Input pins to which these notes apply:
IRQ1, IRQ0, WKP7 to WKP0, and IRQAEC
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Section 5 Power-Down Modes
Rev. 6.00 Mar 15, 2005 page 130 of 502
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Section 6 ROM
Section 6 ROM
The H8/3802 has 16 kbytes of the on-chip mask ROM, the H8/3801 has 12 kbytes, and the
H8/3800 has 8 kbytes. The H8/38004 and H8/38104 have 32 kbytes of the on-chip mask ROM,
the H8/38003 and H8/38103 have 24 kbytes, the H8/38002, H8/38002S and H8/38102 have 16
kbytes, the H8/38001, H8/38001S and H8/38101 have 12 kbytes, and the H8/38000, H8/38000S
and H8/38100 have 8 kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing
high-speed two-state access for both byte data and word data. The H8/3802 has a ZTAT version
with 16-kbyte PROM. The H8/38004, H8/38002, H8/38104, and H8/38102 have F-ZTAT™
versions with 32-kbyte flash memory and 16-kbyte flash memory, respectively.
6.1
Block Diagram
Figure 6.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0000
H'0001
H'0002
H'0002
H'0003
On-chip ROM
H'3FFE
H'3FFE
H'3FFF
Even address
Odd address
Figure 6.1 Block Diagram of ROM (H8/3802)
ROM3322A_000020020900
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Section 6 ROM
6.2
6.2.1
H8/3802 PROM Mode
Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcomputer and allows the PROM to be programmed in the same way as the standard
HN27C101 EPROM. However, page programming is not supported.
Table 6.1 shows how to set the chip to PROM mode.
Table 6.1
Setting to PROM Mode
Pin Name
Setting
TEST
High level
PB0/AN0
Low level
PB1/AN1
PB2/AN2
6.2.2
High level
Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 32 pins.
Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map.
Rev. 6.00 Mar 15, 2005 page 132 of 502
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Section 6 ROM
H8/3802
FP-64A, FP-64E
DP-64S
8
16
40
48
39
38
EPROM socket
Pin
Pin
HN27C101 (32 pins)
VPP
1
P60
EO0
13
47
P61
EO1
14
46
P62
EO2
15
37
45
P63
EO3
17
36
44
P64
EO4
18
35
43
P65
EO5
19
34
42
P66
EO6
20
33
41
P67
EO7
21
57
1
P40
EA0
12
58
2
P41
EA1
11
10
18
P32
EA2
10
11
19
P33
EA3
9
12
20
P34
EA4
8
13
21
P35
EA5
7
14
22
P36
EA6
6
15
23
P37
EA7
5
32
40
P70
EA8
27
60
4
P43
EA9
26
30
38
P72
EA10
23
29
37
P73
EA11
25
28
36
P74
EA12
4
27
35
P75
EA13
28
26
34
P76
EA14
29
52
60
P93
EA15
3
53
61
P94
EA16
25
33
P77
22
31
39
P71
24
51
59
P92
16
24
VCC
61
5
AVCC
7
15
TEST
2
10
X1
64
8
PB2
49
57
P90
50
58
P91
54
62
P95
55
63
VSS
4
12
AVSS
62
6
PB0
63
7
PB1
2
31
VCC
32
VSS
16
Note: Pins not shown in the figure should be open.
Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101)
Rev. 6.00 Mar 15, 2005 page 133 of 502
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Section 6 ROM
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip PROM
H'3FFF
H'3FFF
Uninstalled area*
H'1FFFF
Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore,
when programming with a PROM programmer, be sure to specify addresses from H'0000
to H'3FFF. If programming is inadvertently performed from H'4000 onward, it may not be
possible to continue PROM programming and verification.
When programming, H'FF should be set as the data in this address area (H'4000 to H'1FFFF).
Figure 6.3 H8/3802 Memory Map in PROM Mode
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Section 6 ROM
6.3
H8/3802 Programming
The write, verify, and other modes are selected as shown in table 6.2 in H8/3802 PROM mode.
Table 6.2
Mode Selection in PROM Mode (H8/3802)
Pins
Mode
CE
OE
PGM
Vpp
Vcc
EO7 to EO0
EA16 to EA0
Write
L
H
L
Vpp
Vcc
Data input
Address input
Verify
L
L
H
Vpp
Vcc
Data output
Address input
Programming
disabled
L
L
L
Vpp
Vcc
High impedance
Address input
L
H
H
H
L
L
H
H
H
Legend:
L:
Low level
H:
High level
Vpp:
Vpp level
Vcc:
Vcc level
The specifications for writing and reading are identical to those for the standard HN27C101
EPROM. However, page programming is not supported, and so page programming mode must not
be set. A PROM programmer that only supports page programming mode cannot be used. When
selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte
programming. Also, be sure to specify addresses from H'0000 to H'3FFF.
6.3.1
Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data.
The basic flow of this high-speed, high-reliability programming method is shown in figure 6.4.
Rev. 6.00 Mar 15, 2005 page 135 of 502
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Section 6 ROM
Start
Set write/verify mode
VCC = 6.0 V±0.25 V, VPP = 12.5 V±0.3 V
Address = 0
n=0
n+1→n
Yes
No
Write time tpw = 0.2 ms±5%
n < 25
No
Address + 1 → address
Verify
Yes
Write time topw = 0.2n ms
Last address?
No
Yes
Set read mode
VCC = 5.0 V±0.25 V, VPP = VCC
Error
No
Read all addresses?
Yes
End
Figure 6.4 High-Speed, High-Reliability Programming Flowchart
Table 6.3 and table 6.4 give the electrical characteristics in programming mode.
Rev. 6.00 Mar 15, 2005 page 136 of 502
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Section 6 ROM
Table 6.3
DC Characteristics
(Conditions: Vcc = 6.0 V ±0.25 V, Vpp = 12.5 V ±0.3 V, Vss = 0 V, Ta = 25°C ±5°C)
Item
Input highlevel voltage
Symbol
EO7 to EO0, VIH
EA16 to EA0,
OE, CE, PGM
Input low-level EO7 to EO0, VIL
voltage
EA16 to EA0,
OE, CE, PGM
Min
Typ
Max
Unit
2.4
—
Vcc + 0.3
V
–0.3
—
0.8
V
Test Condition
Output highlevel voltage
EO7 to EO0
VOH
2.4
—
—
V
IOH = –200 µA
Output lowlevel voltage
EO7 to EO0
VOL
—
—
0.45
V
IOL = 0.8 mA
Input leakage
current
EO7 to EO0, | ILI |
EA16 to EA0,
OE, CE, PGM
—
—
2
µA
Vin = 5.25 V/0.5
V
Vcc current
ICC
—
—
40
mA
Vpp current
IPP
—
—
40
mA
Rev. 6.00 Mar 15, 2005 page 137 of 502
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Section 6 ROM
Table 6.4
AC Characteristics
(Conditions: Vcc = 6.0 V ±0.25 V, Vpp = 12.5 V ±0.3 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Typ
Max
Unit
Test Condition
Address setup time
tAS
2
—
—
µs
Figure 6.5*1
tOES
2
—
—
µs
Data setup time
tDS
2
—
—
µs
Address hold time
tAH
0
—
—
µs
Data hold time
2
—
—
µs
Data output disable time
tDH
tDF*2
—
—
130
µs
Vpp setup time
tVPS
2
—
—
µs
Programming pulse width
tPW
0.19
0.20
0.21
ms
0.19
—
5.25
ms
OE setup time
PGM pulse width for
tOPW
CE setup time
tCES
2
—
—
µs
Vcc setup time
tVCS
2
—
—
µs
Data output delay time
tOE
0
—
200
ns
*3
overwrite programming
Notes: 1. Input pulse level: 0.45 V to 2.4 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 0.8 V, 2.0 V
Output: 0.8 V, 2.0 V
2. tDF is defined at the point at which the output is floating and the output level cannot be
read.
3. tOPW is defined by the value given in figure 6.4, High-Speed, High-Reliability
Programming Flow Chart.
Figure 6.5 shows a PROM write/verify timing.
Rev. 6.00 Mar 15, 2005 page 138 of 502
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Section 6 ROM
Write
Verify
Address
tAS
Data
tAH
Input data
tDS
VPP
tDH
tDF
VPP
VCC
VCC
Output data
tVPS
VCC+1
VCC
tVCS
tCES
tPW
tOES
tOE
tOPW*
Note: * tOPW is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing
6.3.2
Programming Precautions
• Use the specified programming voltage and timing.
The programming voltage in PROM mode (Vpp) is 12.5 V. Use of a higher voltage can
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
Setting the PROM programmer to Renesas (former Hitachi) specifications for the HN27C101
will result in correct Vpp of 12.5 V.
• Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before
programming, be sure that the chip is properly mounted in the PROM programmer.
• Avoid touching the socket adapter or chip while programming, since this may cause contact
faults and write errors.
Rev. 6.00 Mar 15, 2005 page 139 of 502
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Section 6 ROM
• Take care when setting the programming mode, as page programming is not supported.
• When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'3FFF. If programming is inadvertently performed from H'4000 onward, it may not be
possible to continue PROM programming and verification. When programming, H'FF should
be set as the data in address area H'4000 to H'1FFFF.
6.4
Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips
at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 6.6 shows the recommended screening procedure.
Program chip and verify
programmed data
Bake chip for 24 to 48 hours at
125˚C to 150˚C with power off
Read and check program
Install
Figure 6.6 Recommended Screening Procedure
If a Group of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects.
Please inform Renesas of any abnormal conditions noted during or after programming or in
screening of program data after high-temperature baking.
Rev. 6.00 Mar 15, 2005 page 140 of 502
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Section 6 ROM
6.5
6.5.1
Overview of Flash Memory
Features
The features of the 32-kbyte or 16-kbyte flash memory built into the flash memory version are
summarized below.
• Programming/erase methods
 The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The flash memory of the HD64F38004 and HD64F38104 are configured as follows:
1 kbyte × 4 blocks and 28 kbytes × 1 block. The flash memory of the HD64F38002 and
HD64F38102 are configured as follows: 1 kbyte × 4 blocks and 12 kbytes × 1 block. To
erase the entire flash memory, each block must be erased in turn.
• On-board programming
 On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
 Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
 For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
 Sets software protection against flash memory programming/erasing.
• Power-down mode
 Operation of the power supply circuit can be partly halted in subactive mode. As a result,
flash memory can be read with low power consumption.
Note: The system clock oscillator must be used when programming or erasing the flash memory
of the HD64F38104 and HD64F38102.
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Section 6 ROM
6.5.2
Block Diagram
Internal address bus
Internal data bus (16 bits)
FLMCR1
Module bus
FLMCR2
Bus interface/controller
EBR
Operating
mode
FLPWCR
FENR
Flash memory
Legend:
FLMCR1:
FLMCR2:
EBR:
FLPWCR:
FENR:
Flash memory control register 1
Flash memory control register 2
Erase block register
Flash memory power control register
Flash memory enable register
Figure 6.7 Block Diagram of Flash Memory
Rev. 6.00 Mar 15, 2005 page 142 of 502
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TEST pin
P95 pin
P34 pin
Section 6 ROM
6.5.3
Block Configuration
Figure 6.8 shows the block configuration of 32-kbyte flash memory. The thick lines indicate
erasing units, the narrow lines indicate programming units, and the values are addresses. The 32kbyte flash memory is divided into 1 kbyte × 4 blocks and 28 kbytes × 1 block. Erasing is
performed in these units. The 16-kbyte flash memory is divided into 1 kbyte × 4 blocks and 12
kbytes × 1 block. Programming is performed in 128-byte units starting from an address with lower
eight bits H'00 or H'80.
Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'00FF
H'0380
H'0381
H'0382
H'03FF
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'0780
H'0781
H'0782
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'7F80
H'7F81
H'7F82
H'7FFF
Programming unit: 128 bytes
H'007F
1 kbyte
Erase unit
Programming unit: 128 bytes
H'047F
H'04FF
1 kbyte
Erase unit
H'07FF
Programming unit: 128 bytes
H'087F
H'08FF
1 kbyte
Erase unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 kbyte
Erase unit
H'0FFF
Programming unit: 128 bytes
H'107F
28 kbytes
Figure 6.8(1) Block Configuration of 32-kbyte Flash Memory
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Erase unit
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'00FF
H'0380
H'0381
H'0382
H'03FF
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'0780
H'0781
H'0782
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'10FF
H'3F80
H'3F81
H'3F82
H'3FFF
Programming unit: 128 bytes
H'007F
1 kbyte
Erase unit
Programming unit: 128 bytes
H'047F
H'04FF
1 kbyte
Erase unit
H'07FF
Programming unit: 128 bytes
H'087F
H'08FF
1 kbyte
Erase unit
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
1 kbyte
Erase unit
H'0FFF
Programming unit: 128 bytes
H'107F
12 kbytes
Figure 6.8(2) Block Configuration of 16-kbyte Flash Memory
6.6
Register Descriptions
The flash memory has the following registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register (EBR)
• Flash memory power control register (FLPWCR)
• Flash memory enable register (FENR)
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Section 6 ROM
6.6.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash
Memory Programming/Erasing.
Bit
Bit Name
Initial
Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0.
6
SWE
0
R/W
Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is cleared
to 0, flash memory programming/erasing is invalid. Other
FLMCR1 bits and all EBR bits cannot be set.
5
ESU
0
R/W
Erase Setup
When this bit is set to 1, the flash memory changes to the
erase setup state. When it is cleared to 0, the erase setup
state is cancelled. Set this bit to 1 before setting the E bit
to 1 in FLMCR1.
4
PSU
0
R/W
Program Setup
When this bit is set to 1, the flash memory changes to the
program setup state. When it is cleared to 0, the program
setup state is cancelled. Set this bit to 1 before setting the
P bit in FLMCR1.
3
EV
0
R/W
Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
2
PV
0
R/W
Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0, programverify mode is cancelled.
1
E
0
R/W
Erase
When this bit is set to 1, and while the SWE = 1 and ESU
= 1 bits are 1, the flash memory changes to erase mode.
When it is cleared to 0, erase mode is cancelled.
0
P
0
R/W
Program
When this bit is set to 1, and while the SWE = 1 and PSU
= 1 bits are 1, the flash memory changes to program
mode. When it is cleared to 0, program mode is
cancelled.
Note: Bits SWE, PSU, EV, PV, E, and P should not be set at the same time.
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Section 6 ROM
6.6.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit
Bit Name
Initial
Value
R/W
Description
7
FLER
0
R
Flash Memory Error
Indicates that an error has occurred during an operation
on flash memory (programming or erasing). When flash
memory goes to the error-protection state, this bit is set to
1.
See section 6.9.3, Error Protection, for details.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
6.6.3
Erase Block Register (EBR)
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 5
—
All 0
—
Reserved
These bits are always read as 0.
4
EB4
0
R/W
When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased in the HD64F38004 and HD64F38104.
When this bit is set to 1, 12 kbytes of H'1000 to H'3FFF
will be erased in the HD64F38002 and HD64F38102.
3
EB3
0
R/W
When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF will
be erased.
2
EB2
0
R/W
When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF will
be erased.
1
EB1
0
R/W
When this bit is set to 1, 1 kbyte of H'0400 to H'07FF will
be erased.
0
EB0
0
R/W
When this bit is set to 1, 1 kbyte of H'0000 to H'03FF will
be erased.
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Section 6 ROM
6.6.4
Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mode and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit
Bit Name
Initial
Value
R/W
Description
7
PDWND
0
R/W
Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to subactive
mode.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
6.6.5
Flash Memory Enable Register (FENR)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR, and FLPWCR.
Bit
Bit Name
Initial
Value
R/W
Description
7
FLSHE
0
R/W
Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers cannot
be accessed when this bit is set to 0.
6 to 0
—
All 0
—
Reserved
These bits are always read as 0.
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Section 6 ROM
6.7
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST
pin settings, P95 pin settings, and input level of each port, as shown in table 6.5. The input level of
each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 6.5
Setting Programming Modes
TEST
P95
P34
PB0
PB1
PB2
LSI State after Reset End
0
1
X
X
X
X
User Mode
0
0
1
X
X
X
Boot Mode
1
X
X
0
0
0
Programmer Mode
Legend: X: Don’t care.
6.7.1
Boot Mode
Table 6.6 shows the boot mode operations between reset end and branching to the programming
control program.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 6.8, Flash Memory Programming/Erasing.
2. The SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1
stop bit, and no parity. Since the inversion function of SPCR is configured not to inverse data
of the TXD pin and RXD pin, do not place an inversion circuit between the host and this LSI.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
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Section 6 ROM
4.
5.
6.
7.
8.
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit
rate and system clock frequency of this LSI within the ranges listed in table 6.7.
In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the TEST pin and P95 pin. Boot mode is also cleared when a
WDT overflow occurs.
Do not change the TEST pin and P95 pin input levels in boot mode.
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Section 6 ROM
Boot Mode Operation
Host Operation
Communication Contents
Processing Contents
Transfer of number of bytes of
programming control program
Flash memory erase
Bit rate adjustment
Boot mode initiation
Item
Table 6.6
LSI Operation
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
H'00, H'00 . . . H'00
Continuously transmits data H'00
at specified bit rate.
H'00
Transmits data H'55 when data H'00
is received error-free.
H'55
H'FF
Boot program
erase error
H'AA
H'AA reception
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Upper bytes, lower bytes
Transmits 1-byte of programming
control program (repeated for N times)
H'AA reception
Echoback
H'XX
Echoback
H'AA
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Transmits data H'AA to host.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
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Section 6 ROM
Table 6.7
Oscillation Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible (fOSC)
Product Group
Host Bit Rate
Oscillation Frequency Range of LSI (fOSC)
H8/38004F Group
4,800 bps
8 to 10 MHz
2,400 bps
4 to 10 MHz
1,200 bps
2 to 10 MHz
19,200 bps
16 to 20 MHz
9,600 bps
8 to 20 MHz
4,800 bps
4 to 20 MHz
2,400 bps
2 to 20 MHz
1,200 bps
2 to 20 MHz
H8/38104F Group
6.7.2
Programming/Erasing in User Program Mode
User program mode means the execution state of the user program. On-board
programming/erasing of an individual flash memory block can also be performed in user program
mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 6.9 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 6.8,
Flash Memory Programming/Erasing.
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Section 6 ROM
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode
6.7.3
Notes on On-Board Programming
1. You must use the system clock oscillator when programming or erasing flash memory on the
H8/38104F Group. The on-chip oscillator should not be used for programming or erasing flash
memory. See section 4.3.4, On-Chip Oscillator Selection Method, for information on switching
between the system clock oscillator and the on-chip oscillator.
2. On the H8/38104F Group the watchdog timer operates after a reset is canceled. When
executing a program prepared by the user that performs programming and erasing in the user
mode, the watchdog timer’s overflow cycle should be set to an appropriate value. Refer to
section 6.8.1, Program/Program-Verify, for information on the appropriate watchdog timer
overflow cycle for programming, and to 6.8.2, Erase/Erase-Verify, for information on the
appropriate watchdog timer overflow cycle for erasing.
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Section 6 ROM
6.8
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 6.8.1, Program/Program-Verify and section 6.8.2,
Erase/Erase-Verify, respectively.
6.8.1
Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 6.10 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory without subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 6.8, and additional programming data
computation according to table 6.9.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Table 6.10 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower one
bit is B'0. Verify data can be read in word units from the address to which a dummy write was
performed.
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Section 6 ROM
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
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Section 6 ROM
Write pulse application subroutine
START
Apply Write Pulse
Set SWE bit in FLMCR1
WDT enable
Wait 1 µs
Set PSU bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
Wait 50 µs
n←1
Set P bit in FLMCR1
m←0
Wait (Wait time=programming time)
Clear P bit in FLMCR1
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Wait 5 µs
Apply Write pulse
Clear PSU bit in FLMCR1
Set PV bit in FLMCR1
Wait 4 µs
Wait 5 µs
Disable WDT
Set block start address as
verify address
End Sub
H'FF dummy write to verify address
n←n+1
Wait 2 µs
Read verify data
Increment address
No
Verify data =
write data?
m←1
Yes
No
n≤6?
Yes
Additional-programming data computation
Reprogram data computation
No
128-byte
data verification completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
No
n ≤ 6?
Yes
Successively write 128-byte data from additionalprogramming data area in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
No
m= 0 ?
n ≤ 1000 ?
Yes
Yes
Clear SWE bit in FLMCR1
No
Clear SWE bit in FLMCR1
Wait 100 µs
Wait 100 µs
End of programming
Programming failure
Figure 6.10 Program/Program-Verify Flowchart
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Section 6 ROM
Table 6.8
Reprogram Data Computation Table
Program Data
Verify Data
Reprogram Data
Comments
0
0
1
Programming completed
0
1
0
Reprogram bit
1
0
1
—
1
1
1
Remains in erased state
Table 6.9
Additional-Program Data Computation Table
Reprogram Data
Verify Data
Additional-Program
Data
Comments
0
0
0
Additional-program bit
0
1
1
No additional programming
1
0
1
No additional programming
1
1
1
No additional programming
n
Programming
(Number of Writes) Time
In Additional
Programming
Comments
1 to 6
30
10
7 to 1,000
200
—
Table 6.10 Programming Time
Note: Time shown in µs.
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Section 6 ROM
6.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is B'0. Verify data can be read in word units from the address to which a dummy write was
performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
6.8.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
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Section 6 ROM
Erase start
SWE bit ← 1
Wait 1 µs
n←1
Set EBR
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 0
Wait 10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
n←n+1
Read verify data
No
Verify data = all 1s ?
Increment address
Yes
No
Last address of block ?
Yes
No
EV bit ← 0
EV bit ← 0
Wait 4 µs
Wait 4µs
All erase block erased ?
n ≤100 ?
Yes
No
SWE bit ← 0
SWE bit ← 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Figure 6.11 Erase/Erase-Verify Flowchart
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Yes
Section 6 ROM
6.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
6.9.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode,
or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), and erase block register (EBR) are initialized. In a reset via the RES pin, the reset
state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the
AC Characteristics section.
6.9.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00,
erase protection is set for all blocks.
6.9.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is
aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered
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Section 6 ROM
by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be
made to verify mode. Error protection can be cleared only by a power-on reset.
6.10
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-kbyte flash memory
(FZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to programmer
mode, see table 6.5.
6.10.1
Socket Adapter
The socket adapter converts the pin allocation of the HD64F38004, HD64F38002, HD64F38104,
and HD64F38102 to that of the discrete flash memory HN28F101. The address of the on-chip
flash memory is H'0000 to H'7FFF. Figure 6.12(1) shows a socket-adapter-pin correspondence
diagram of the HD64F38004 and HD64F38002. Figure 6.12(2) shows a socket-adapter-pin
correspondence of the HD64F38104 and HD64F38102.
6.10.2
Programmer Mode Commands
The following commands are supported in programmer mode.
•
•
•
•
Memory Read Mode
Auto-Program Mode
Auto-Erase Mode
Status Read Mode
Status polling is used for auto-programming, auto-erasing, and status read modes. In status read
mode, detailed internal information is output after the execution of auto-programming or autoerasing. Table 6.11 shows the sequence of each command. In auto-programming mode, 129 cycles
are required since 128 bytes are written at the same time. In memory read mode, the number of
cycles depends on the number of address write cycles (n).
Rev. 6.00 Mar 15, 2005 page 160 of 502
REJ09B0024-0600
Section 6 ROM
Table 6.11 Command Sequence in Programmer Mode
1st Cycle
2nd Cycle
Command
Name
Number of
Cycles
Mode
Address
Data
Mode
Address
Data
Memory
read
1+n
Write
X
H'00
Read
RA
Dout
Autoprogram
129
Write
X
H'40
Write
WA
Din
Auto-erase 2
Write
X
H'20
Write
X
H'20
Status read 2
Write
X
H'71
Write
X
H'71
Legend: n: Number of address write cycles
Rev. 6.00 Mar 15, 2005 page 161 of 502
REJ09B0024-0600
Section 6 ROM
H8/38004F, H8/38002F
Pin No.
FP-64A
FP-64E
Pin Name
Socket Adapter
(Conversion to
32-Pin
Arrangement)
HN28F101 (32 Pins)
Pin Name
Pin No.
FWE
1
A9
26
A16
2
31
P71
25
P77
A15
3
49
P90
WE
31
40
P60
I/O0
13
39
P61
I/O1
14
38
P62
I/O2
15
37
P63
I/O3
17
36
P64
I/O4
18
35
P65
I/O5
19
34
P66
I/O6
20
33
P67
I/O7
21
57
P40
A0
12
58
P41
A1
11
10
P32
A2
10
11
P33
A3
9
12
P34
A4
8
13
P35
A5
7
14
P36
A6
6
15
P37
A7
5
32
P70
A8
27
59
P42
OE
24
30
P72
A10
23
29
P73
A11
25
28
P74
A12
4
27
P75
A13
28
26
P76
A14
29
60
P43
CE
22
16
Vcc
Vcc
32
61
AVcc
Vss
16
2
X1
7
TEST
17
V1
50
P91
54
P95
4
Vss
55
Vss
62
PB0
63
PB1
Legend:
FWE:
I/O7 to I/O0:
A16 to A0:
CE:
OE:
WE:
64
PB2
6, 5
OSC1,OSC2
Oscillator circuit
8
Other than above
RES
(OPEN)
Power-on
reset circuit
Flash-write enable
Data input/output
Address input
Chip enable
Output enable
Write enable
Note: The oscillation frequency of
the oscillator circuit should
be 10 MHz.
Figure 6.12(1) Socket Adapter Pin Correspondence Diagram (H8/38004F, H8/38002F)
Rev. 6.00 Mar 15, 2005 page 162 of 502
REJ09B0024-0600
Section 6 ROM
H8/38104F, H8/38102F
Pin No.
FP-64A
FP-64E
Pin Name
Socket Adapter
(Conversion to
32-Pin
Arrangement)
HN28F101 (32 Pins)
Pin Name
Pin No.
FWE
1
A9
26
A16
2
31
P71
25
P77
A15
3
49
P90
WE
31
40
P60
I/O0
13
39
P61
I/O1
14
38
P62
I/O2
15
37
P63
I/O3
17
36
P64
I/O4
18
35
P65
I/O5
19
34
P66
I/O6
20
33
P67
I/O7
21
57
P40
A0
12
58
P41
A1
11
10
P32
A2
10
11
P33
A3
9
12
P34
A4
8
13
P35
A5
7
14
P36
A6
6
15
P37
A7
5
32
P70
A8
27
59
P42
OE
24
30
P72
A10
23
29
P73
A11
25
28
P74
A12
4
27
P75
A13
28
26
P76
A14
29
60
P43
CE
22
16
Vcc
Vcc
32
61
AVcc
Vss
16
2
X1
7
TEST
17
V1
50
P91
53, 54
CVcc, P95
4
Vss
55
Vss
62
PB0
63
PB1
Legend:
FWE:
I/O7 to I/O0:
A16 to A0:
CE:
OE:
WE:
64
PB2
6, 5
OSC1,OSC2
Oscillator circuit
8
Other than above
RES
(OPEN)
Power-on
reset circuit
Flash-write enable
Data input/output
Address input
Chip enable
Output enable
Write enable
Note: The oscillation frequency of
the oscillator circuit should
be 10 MHz.
Figure 6.12(2) Socket Adapter Pin Correspondence Diagram (H8/38104F, H8/38102F)
Rev. 6.00 Mar 15, 2005 page 163 of 502
REJ09B0024-0600
Section 6 ROM
6.10.3
Memory Read Mode
After completion of auto-program/auto-erase/status read operations, a transition is made to the
command wait state. When reading memory contents, a transition to memory read mode must first
be made with a command write, after which the memory contents are read. Once memory read
mode has been entered, consecutive reads can be performed.
1. In memory read mode, command writes can be performed in the same way as in the command
wait state.
2. After powering on, memory read mode is entered.
3. Tables 6.12 to 6.14 show the AC characteristics.
Table 6.12 AC Characteristics in Transition to Memory Read Mode
(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Max
Unit
Test Condition
Command write cycle
tnxtc
20
—
µs
Figure 6.13
tceh
0
—
ns
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
CE hold time
CE setup time
Write pulse width
WE rise time
WE fall time
twep
70
—
ns
tr
—
30
ns
tf
—
30
ns
Rev. 6.00 Mar 15, 2005 page 164 of 502
REJ09B0024-0600
Section 6 ROM
Command write
Memory read mode
A15 to A0
Address stable
tces
tceh
tnxtc
twep
tf
tr
tds
tdh
I/O7 to I/O0
Note: Data is latched on the rising edge of
.
Figure 6.13 Timing Waveforms for Memory Read after Command Write
Table 6.13 AC Characteristics in Transition from Memory Read Mode to Another Mode
(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Max
Unit
Test Condition
Command write cycle
tnxtc
20
—
µs
Figure 6.14
tceh
0
—
ns
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
tr
—
30
ns
tf
—
30
ns
CE hold time
CE setup time
WE rise time
WE fall time
Rev. 6.00 Mar 15, 2005 page 165 of 502
REJ09B0024-0600
Section 6 ROM
Other mode command write
Memory read mode
A15 to A0
Address stable
tnxtc
tceh
tces
tf
twep
tr
tds
tdh
I/O7 to I/O0
Note: Do not enable
and
at the same time.
Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode
Table 6.14 AC Characteristics in Memory Read Mode
(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Max
Unit
Test Condition
Access time
tacc
—
20
µs
Figures 6.15 and 6.16
tce
—
150
ns
toe
—
150
ns
Output disable delay time
tdf
—
100
ns
Data output hold time
toh
5
—
ns
CE output delay time
OE output delay time
A15 to A0
Address stable
Address stable
tacc
tacc
toh
toh
I/O7 to I/O0
Figure 6.15 Timing Waveforms in CE and OE Enable State Read
Rev. 6.00 Mar 15, 2005 page 166 of 502
REJ09B0024-0600
Section 6 ROM
A15 to A0
Address stable
Address stable
tce
tce
toe
toe
tacc
tacc
toh
tdf
toh
tdf
I/O7 to I/O0
Figure 6.16 Timing Waveforms in CE and OE Clock System Read
6.10.4
Auto-Program Mode
1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming.
2. Perform auto-programming once only on the same address block. It is not possible to program
an address block that has already been programmed.
3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when
programming fewer than 128 bytes. In this case, H'FF data must be written to the extra
addresses.
4. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
5. Memory address transfer is performed in the second cycle (figure 6.17). Do not perform
transfer after the third cycle.
6. Do not perform a command write during a programming operation.
7. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
10. Table 6.15 shows the AC characteristics.
Rev. 6.00 Mar 15, 2005 page 167 of 502
REJ09B0024-0600
Section 6 ROM
Table 6.15 AC Characteristics in Auto-Program Mode
(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Max
Unit
Test Condition
Command write cycle
tnxtc
20
—
µs
Figure 6.17
tceh
0
—
ns
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
twsts
1
—
ms
Status polling access time tspa
—
150
ns
Address setup time
tas
0
—
ns
Address hold time
tah
60
—
ns
Memory write time
twrite
1
3000
ms
WE rise time
WE fall time
tr
—
30
ns
tf
—
30
ns
CE hold time
CE setup time
Address stable
A15 to A0
tces
tf
tceh
twep
tnxtc
tnxtc
tas
tr
tah
Data transfer
1 to 128 bytes
tds
tdh
twsts
tspa
twrite
I/O7
Write operation end
decision signal
I/O6
Write normal end
decision signal
I/O5 to I/O0
H'40
Figure 6.17 Timing Waveforms in Auto-Program Mode
Rev. 6.00 Mar 15, 2005 page 168 of 502
REJ09B0024-0600
H'00
Section 6 ROM
6.10.5
Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.
2. Do not perform a command write during auto-erasing.
3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also
be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).
4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
5. Table 6.16 shows the AC characteristics.
Table 6.16 AC Characteristics in Auto-Erase Mode
(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Max
Unit
Test Condition
Command write cycle
tnxtc
20
—
µs
Figure 6.18
tceh
0
—
ns
CE hold time
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
tests
1
—
ms
Status polling access time tspa
—
150
ns
Memory erase time
terase
100
40000
ms
WE rise time
WE fall time
tr
—
30
ns
tf
—
30
ns
Rev. 6.00 Mar 15, 2005 page 169 of 502
REJ09B0024-0600
Section 6 ROM
A15 to A0
tces
tf
tceh
twep
tnxtc
tnxtc
tests
tr
tds
tspa
terase
tdh
I/O7
Erase end decision
signal
I/O6
Erase normal end
decision signal
H'20
I/O5 to I/O0
H'20
H'00
Figure 6.18 Timing Waveforms in Auto-Erase Mode
6.10.6
Status Read Mode
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than command write in status read
mode is executed.
3. Table 6.17 shows the AC characteristics and table 6.18 shows the return codes.
Rev. 6.00 Mar 15, 2005 page 170 of 502
REJ09B0024-0600
Section 6 ROM
Table 6.17 AC Characteristics in Status Read Mode
(Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Max
Unit
Test Condition
20
—
µs
Figure 6.19
tceh
0
—
ns
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
OE output delay time
toe
—
150
ns
Disable delay time
tdf
—
100
ns
tce
—
150
ns
tr
—
30
ns
tf
—
30
ns
Read time after command tnxtc
write
CE hold time
CE setup time
CE output delay time
WE rise time
WE fall time
A15 to A0
tces
tceh
tnxtc
tces
tceh
tnxtc
tnxtc
tce
tf
twep
tr
tds
tdh
H'71
I/O7 to I/O0
tf
twep
toe
tr
tds
tdh
tdf
H'71
Note: I/O2 and I/O3 are undefined.
Figure 6.19 Timing Waveforms in Status Read Mode
Rev. 6.00 Mar 15, 2005 page 171 of 502
REJ09B0024-0600
Section 6 ROM
Table 6.18 Return Codes in Status Read Mode
Pin Name
Initial Value
Description
I/O7
0
1: Abnormal end
0: Normal end
I/O6
0
1: Command error
0: Otherwise
I/O5
0
1: Programming error
0: Otherwise
I/O4
0
1: Erasing error
0: Otherwise
I/O3
0
Undefined
I/O2
0
Undefined
I/O1
0
1: Over counting of writing or erasing
0: Otherwise
I/O0
0
1: Effective address error
0: Otherwise
6.10.7
Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 6.19 Status Polling Output
I/O7
I/O6
I/O0 to I/O5
Status
0
0
0
During internal operation
1
0
0
Abnormal end
1
1
0
Normal end
0
1
0
—
Rev. 6.00 Mar 15, 2005 page 172 of 502
REJ09B0024-0600
Section 6 ROM
6.10.8
Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 6.20 Stipulated Transition Times to Command Wait State
Item
Symbol
Min
Max
Unit
Test Condition
Oscillation stabilization time tosc1
(crystal resonator)
10
—
ms
Figure 6.20
Oscillation stabilization time
(ceramic resonator)
5
—
ms
Programmer mode setup
time
tbmv
10
—
ms
VCC hold time
tdwn
0
—
ms
tosc1
tbmv
Auto-program mode
Auto-erase mode
tdwn
VCC
Figure 6.20 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence
6.10.9
Notes on Memory Programming
1. When performing programming using programmer mode on a chip that has been
programmed/erased in on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
2. The flash memory is initially in the erased state when the device is shipped by Renesas. For
other chips for which the erasure history is unknown, it is recommended that auto-erasing be
executed to check and supplement the initialization (erase) level.
Rev. 6.00 Mar 15, 2005 page 173 of 502
REJ09B0024-0600
Section 6 ROM
6.11
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.21 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the
external clock is being used.
Table 6.21 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State
PDWND = 0 (Initial value)
PDWND = 1
Active mode
Normal operating mode
Normal operating mode
Subactive mode
Power-down mode
Normal operating mode
Sleep mode
Normal operating mode
Normal operating mode
Subsleep mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Watch mode
Standby mode
Standby mode
Rev. 6.00 Mar 15, 2005 page 174 of 502
REJ09B0024-0600
Section 7 RAM
Section 7 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification
RAM Size
RAM Address
H8/38004
1 kbyte
H'FB80 to H'FF7F
H8/38002
1 kbyte
H'FB80 to H'FF7F
H8/38104
1 kbyte
H'FB80 to H'FF7F
H8/38102
1 kbyte
H'FB80 to H'FF7F
PROM version
H8/3802
1 kbyte
H'FB80 to H'FF7F
Mask ROM version
H8/3802
1 kbyte
H'FB80 to H'FF7F
H8/3801
512 bytes
H'FD80 to H'FF7F
H8/3800
512 bytes
H'FD80 to H'FF7F
H8/38004
1 kbyte
H'FB80 to H'FF7F
H8/38003
1 kbyte
H'FB80 to H'FF7F
H8/38002
1 kbyte
H'FB80 to H'FF7F
H8/38001
512 bytes
H'FD80 to H'FF7F
H8/38000
512 bytes
H'FD80 to H'FF7F
H8/38002S
512 bytes
H'FD80 to H'FF7F
H8/38001S
512 bytes
H'FD80 to H'FF7F
H8/38000S
512 bytes
H'FD80 to H'FF7F
H8/38104
1 kbyte
H'FB80 to H'FF7F
H8/38103
1 kbyte
H'FB80 to H'FF7F
H8/38102
1 kbyte
H'FB80 to H'FF7F
H8/38101
512 bytes
H'FD80 to H'FF7F
H8/38100
512 bytes
H'FD80 to H'FF7F
Flash memory version
Rev. 6.00 Mar 15, 2005 page 175 of 502
REJ09B0024-0600
Section 7 RAM
7.1
Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'FB80
H'FB80
H'FB81
H'FB82
H'FB82
H'FB83
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even address
Odd address
Figure 7.1 Block Diagram of RAM (H8/3802)
Rev. 6.00 Mar 15, 2005 page 176 of 502
REJ09B0024-0600
Section 8 I/O Ports
Section 8 I/O Ports
This LSI is provided with three 8-bit I/O ports, one 7-bit I/O port, one 4-bit I/O port, one 3-bit I/O
port, one 1-bit I/O port, one 4-bit input-only port, one 1-bit input-only port, and one 6-bit outputonly port.
Each port is configured by the port control register (PCR) that controls input and output, and the
port data register (PDR) that stores output data. Input or output can be assigned to individual bits.
Ports 5, 6, 7, 8, and A are also used as liquid crystal display segment and common pins, selectable
in 4-bit units.
See section 2.9.4, Bit Manipulation Instructions, for information on executing bit-manipulation
instructions to write data in PCR or PDR. Block diagrams of each port are given in Appendix B,
I/O Port Block Diagrams. Table 8.1 lists the functions of each port.
Table 8.1
Port Functions
Function
Switching
Registers
Port
Description
Pins
Other Functions
Port 3
•
7-bit I/O port
•
Input pull-up MOS option
1
Large-current port*
P37/AEVL
P36/AEVH
P35
P34
P33
PMR3
Asynchronous event
counter event inputs AEVL,
AEVH
P32/TMOFH
P31/TMOFL
Timer F output compare
output
PMR3
•
Port 4
Port 5
Port 6
Port 7
•
1-bit input-only port
P43/IRQ0
External interrupt 0
PMR2
•
3-bit I/O port
P42/TXD32
P41/RXD32
P40/SCK32
SCI3 data output (TXD32),
data input (RXD32), clock
input/output (SCK32)
SCR3
SMR
•
8-bit I/O port
•
Input pull-up MOS option
P57 to P50/
WKP7 to
WKP0/
SEG8 to
SEG1
Wakeup input (WKP7 to
WKP0), segment output
(SEG8 to SEG1)
PMR5
LPCR
•
8-bit I/O port
•
Input pull-up MOS option
P67 to P60/
SEG16 to
SEG9
Segment output (SEG16 to LPCR
SEG9)
•
8-bit I/O port
P77 to P70/
SEG24 to
SEG17
Segment output (SEG24 to LPCR
SEG17)
Rev. 6.00 Mar 15, 2005 page 177 of 502
REJ09B0024-0600
Section 8 I/O Ports
Port
Other Functions
Function
Switching
Registers
Segment output (SEG25)
LPCR
None
(LVD reference voltage
external input pin)*3
(LVDSR)*3
Description
Pins
Port 8
•
1-bit I/O port
P80/SEG25
Port 9
•
P95 to P92
(P95, P92,
High-voltage, large-current
P93/Vref)*3
2
port*
P91, P90/
PWM2, PWM1
10-bit PWM output
PMR9
•
High-voltage, input port*4
IRQAEC
None
Port A
•
4-bit I/O port
PA3 to PA0/
COM4 to
COM1
Common output (COM4 to
COM1)
LPCR
Port B
•
4-bit input-only port
PB3/AN3/
IRQ1
A/D converter analog input
External interrupt 1
AMR
PMRB
PB2/AN2
A/D converter analog input
AMR
PB1/AN1/
(extU)*5
PB0/AN0/
(extD)*5
A/D converter analog input
(LVD detection voltage
external input pin)*5
AMR
(LVDCR)*5
•
6-bit output-only port
Notes: 1. Implemented on H8/3802 Group and H8/38104 Group only.
2. Implemented on H8/3802 Group only. Standard high-voltage port on H8/38104 Group,
H8/38002S Group and H8/38004 Group.
3. Implemented on H8/38104 Group only. Pin 94 does not function on H8/38104 Group.
4. Implemented on H8/3802 Group only. Input port on H8/38004 Group, H8/38002S Group
and H8/38104 Group.
5. Implemented on H8/38104 Group only.
Rev. 6.00 Mar 15, 2005 page 178 of 502
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Section 8 I/O Ports
8.1
Port 3
Port 3 is an I/O port also functioning as an asynchronous event counter input pin and timer F
output pin. Figure 8.1 shows its pin configuration.
P37/AEVL
P36/AEVH
P35
Port 3
P34
P33
P32/TMOFH
P31/TMOFL
Figure 8.1 Port 3 Pin Configuration
Port 3 has the following registers.
•
•
•
•
•
Port data register 3 (PDR3)
Port control register 3 (PCR3)
Port pull-up control register 3 (PUCR3)
Port mode register 3 (PMR3)
Port mode register 2 (PMR2)
Rev. 6.00 Mar 15, 2005 page 179 of 502
REJ09B0024-0600
Section 8 I/O Ports
8.1.1
Port Data Register 3 (PDR3)
PDR3 is a register that stores data of port 3.
Bit
Bit Name
Initial
Value
R/W
Description
7
P37
0
R/W
6
P36
0
R/W
5
P35
0
R/W
If port 3 is read while PCR3 bits are set to 1, the values
stored in PDR3 are read, regardless of the actual pin
states. If port 3 is read while PCR3 bits are cleared to 0,
the pin states are read.
4
P34
0
R/W
3
P33
0
R/W
2
P32
0
R/W
1
P31
0
R/W
0



8.1.2
Reserved
Port Control Register 3 (PCR3)
PCR3 controls whether each of the port 3 pins functions as an input pin or output pin.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR37
0
W
6
PCR36
0
W
5
PCR35
0
W
4
PCR34
0
W
Setting a PCR3 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR3 and in PDR3 are valid
only when the corresponding pin is designated in PMR3
as a general I/O pin.
3
PCR33
0
W
2
PCR32
0
W
1
PCR31
0
W
0


W
PCR3 is a write-only register. Bits 7 to 1 are always read
as 1.
Reserved
The write value should always be 0.
Rev. 6.00 Mar 15, 2005 page 180 of 502
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Section 8 I/O Ports
8.1.3
Port Pull-Up Control Register 3 (PUCR3)
PUCR3 controls whether the pull-up MOS of each of the port 3 pins is on or off.
Bit
Bit Name
Initial
Value
R/W
Description
7
PUCR37
0
R/W
6
PUCR36
0
R/W
5
PUCR35
0
R/W
When a PCR3 bit is cleared to 0, setting the
corresponding PUCR3 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0 turns
off the pull-up MOS.
4
PUCR34
0
R/W
3
PUCR33
0
R/W
2
PUCR32
0
R/W
1
PUCR31
0
R/W
0


W
Reserved
The write value should always be 0.
Rev. 6.00 Mar 15, 2005 page 181 of 502
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Section 8 I/O Ports
8.1.4
Port Mode Register 3 (PMR3)
PMR3 controls the selection of pin functions for port 3 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
AEVL
0
R/W
P37/AEVL Pin Function Switch
This bit selects whether pin P37/AEVL is used as P37
or as AEVL.
0: P37 I/O pin
1: AEVL input pin
6
AEVH
0
R/W
P36/AEVH Pin Function Switch
This bit selects whether pin P36/AEVH is used as P36
or as AEVH.
0: P36 I/O pin
1: AEVH input pin
5 to 3


W
2
TMOFH
0
R/W
Reserved
The write value should always be 0.
P32/TMOFH Pin Function Switch
This bit selects whether pin P32/TMOFH is used as P32
or as TMOFH.
0: P32 I/O pin
1: TMOFH output pin
1
TMOFL
0
R/W
P31/TMOFL Pin Function Switch
This bit selects whether pin P31/TMOFL is used as P31
or as TMOFL.
0: P31 I/O pin
1: TMOFL output pin
0


W
Reserved
The write value should always be 0.
Rev. 6.00 Mar 15, 2005 page 182 of 502
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Section 8 I/O Ports
8.1.5
Port Mode Register 2 (PMR2)
PMR2 controls the PMOS on/off state for the P35 pin, selects a pin function for the P43/IRQ0 pin,
and selects a clock of the watchdog timer.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
5
POF1
0
R/W
P35 Pin PMOS Control
This bit controls the on/off state of the PMOS of the P35
pin output buffer.
0: CMOS output
1: NMOS open-drain output
4, 3

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
2
WDCKS
0
R/W
Watchdog Timer Source Clock Select
This bit selects the input clock for the watchdog timer.
Note that this bit is implemented differently on the
H8/38004, H8/38002S Group and on H8/38104 Group.
H8/38004, H8/38002S Group:
0: φ/8,192
1: φw/32
H8/38104 Group: 0: Clock specified by timer mode
register W (TMW)
1: φw/32
Note: This bit is reserved and only 0 can be written in
the H8/3802 Group.
1


W
Reserved
The write value should always be 0.
0
IRQ0
0
R/W
P43/IRQ0 Pin Function Switch
This bit selects whether pin P43/IRQ0 is used as P43 or
as IRQ0.
0: P43 input pin
1: IRQ0 input pin
Note: * See section 9.5, Watchdog Timer, for details.
Rev. 6.00 Mar 15, 2005 page 183 of 502
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Section 8 I/O Ports
8.1.6
Pin Functions
The port 3 pin functions are shown below.
• P37/AEVL pin
The pin function depends on the combination of bit AEVL in PMR3 and bit PCR37 in PCR3.
AEVL
PCR37
Pin Function
0
1
0
1
*
P37 input pin
P37 output pin
AEVL input pin
Legend: *: Don't care.
• P36/AEVH pin
The pin function depends on the combination of bit AEVH in PMR3 and bit PCR36 in PCR3.
AEVH
PCR36
Pin Function
0
1
0
1
*
P36 input pin
P36 output pin
AEVH input pin
Legend: *: Don't care.
• P35 to P33 pins
The pin function depends on the corresponding bit in PCR3.
(n = 5 to 3)
PCR3n
Pin Function
0
1
P3n input pin
P3n output pin
• P32/TMOFH pin
The pin function depends on the combination of bit TMOFH in PMR3 and bit PCR32 in PCR3.
TMOFH
PCR32
Pin Function
0
1
0
1
*
P32 input pin
P32 output pin
TMOFH output pin
Legend: *: Don't care.
Rev. 6.00 Mar 15, 2005 page 184 of 502
REJ09B0024-0600
Section 8 I/O Ports
• P31/TMOFL pin
The pin function depends on the combination of bit TMOFL in PMR3 and bit PCR31 in PCR3.
TMOFL
0
PCR31
Pin Function
1
0
1
*
P31 input pin
P31 output pin
TMOFL output pin
Legend: *: Don't care.
8.1.7
Input Pull-Up MOS
Port 3 has an on-chip input pull-up MOS function that can be controlled by software. When the
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 1)
PCR3n
PUCR3n
Input Pull-Up MOS
0
1
0
1
*
Off
On
Off
Legend: *: Don't care.
Rev. 6.00 Mar 15, 2005 page 185 of 502
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Section 8 I/O Ports
8.2
Port 4
Port 4 is an I/O port also functioning as an interrupt input pin and SCI I/O pin. Figure 8.2 shows
its pin configuration.
P43/
P42/TXD32
Port 4
P41/RXD32
P40/SCK32
Figure 8.2 Port 4 Pin Configuration
Port 4 has the following registers.
• Port data register 4 (PDR4)
• Port control register 4 (PCR4)
• Serial port control register (SPCR)
8.2.1
Port Data Register 4 (PDR4)
PDR4 is a register that stores data of port 4.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

1

Reserved
These bits are always read as 1.
3
P43
1
R
2
P42
0
R/W
1
P41
0
R/W
0
P40
0
R/W
If port 4 is read while PCR4 bits are set to 1, the values
stored in PDR4 are read, regardless of the actual pin
states. If port 4 is read while PCR4 bits are cleared to 0,
the pin states are read.
Rev. 6.00 Mar 15, 2005 page 186 of 502
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Section 8 I/O Ports
8.2.2
Port Control Register 4 (PCR4)
PCR4 controls whether each of the port 4 pins functions as an input pin or output pin.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3

All 1

Reserved
These bits are always read as 1.
2
PCR42
0
W
1
PCR41
0
W
0
PCR40
0
W
Setting a PCR4 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR4 and in PDR4 are valid
only when the corresponding pin is designated in SCR3
and SCR2 as a general I/O pin.
PCR4 is a write-only register. Bits 2 to 0 are always
read as 1.
8.2.3
Serial Port Control Register (SPCR)
SPCR performs input/output data inversion switching of the RXD32 and TXD32 pins. Figure 8.3
shows the configuration.
SCINV2
RXD32
P41/RXD32
SCINV3
P42/TXD32
TXD32
Figure 8.3 Input/Output Data Inversion Function
Rev. 6.00 Mar 15, 2005 page 187 of 502
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Section 8 I/O Ports
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
5
SPC32
0
R/W
P42/TXD32 Pin Function Switch
These bits are always read as 1 and cannot be modified.
This bit selects whether pin P42/TXD32 is used as P42 or
as TXD32.
0: P42 I/O pin
1: TXD32 output pin*
Note: * Set the TE bit in SCR3 after setting this bit to 1.
4


W
Reserved
The write value should always be 0.
3
SCINV3
0
R/W
TXD32 Pin Output Data Inversion Switch
This bit selects whether or not the logic level of the
TXD32 pin output data is inverted.
0: TXD32 output data is not inverted
1: TXD32 output data is inverted
2
SCINV2
0
R/W
RXD32 Pin Input Data Inversion Switch
This bit selects whether or not the logic level of the
RXD32 pin input data is inverted.
0: RXD32 input data is not inverted
1: RXD32 input data is inverted
1, 0


W
Reserved
The write value should always be 0.
Note: When the serial port control register is modified, the data being input or output up to that
point is inverted immediately after the modification, and an invalid data change is input or
output. When modifying the serial port control register, modification must be made in a state
in which data changes are invalidated.
Rev. 6.00 Mar 15, 2005 page 188 of 502
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Section 8 I/O Ports
8.2.4
Pin Functions
The port 4 pin functions are shown below.
• P43/IRQ0 pin
The pin function depends on the IRQ0 bit in PMR2.
IRQ0
Pin Function
0
1
P43 input pin
IRQ0
input pin
• P42/TXD32 pin
The pin function depends on the combination of bit TE in SCR3, bit SPC32 in SPCR, and bit
PCR42 in PCR4.
SPC32
0
1
TE
0
1
PCR42
Pin Function
0
1
*
P42 input pin
P42 output pin
TXD32 output pin
Legend: *: Don't care.
• P41/RXD32 pin
The pin function depends on the combination of bit RE in SCR3 and bit PCR41 in PCR4.
RE
PCR41
Pin Function
0
1
0
1
*
P41 input pin
P41 output pin
RXD32 input pin
Legend: *: Don't care.
Rev. 6.00 Mar 15, 2005 page 189 of 502
REJ09B0024-0600
Section 8 I/O Ports
• P40/SCK32 pin
The pin function depends on the combination of bits CKE1 and CKE0 in SCR3, bit COM in SMR,
and bit PCR40 in PCR4.
CKE1
0
CKE0
1
0
COM
0
PCR40
Pin Function
1
1
*
*
*
0
1
*
*
P40 input pin
P40 output pin
SCK32 output pin
SCK32 input pin
Legend: *: Don't care.
8.3
Port 5
Port 5 is an I/O port also functioning as a wakeup interrupt request input pin and LCD segment
output pin. Figure 8.4 shows its pin configuration.
Port 5
P57/
/SEG8
P56/
/SEG7
P55/
/SEG6
P54/
/SEG5
P53/
/SEG4
P52/
/SEG3
P51/
/SEG2
P50/
/SEG1
Figure 8.4 Port 5 Pin Configuration
Port 5 has the following registers.
•
•
•
•
Port data register 5 (PDR5)
Port control register 5 (PCR5)
Port pull-up control register 5 (PUCR5)
Port mode register 5 (PMR5)
Rev. 6.00 Mar 15, 2005 page 190 of 502
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Section 8 I/O Ports
8.3.1
Port Data Register 5 (PDR5)
PDR5 is a register that stores data of port 5.
Bit
Bit Name
Initial
Value
R/W
Description
7
P57
0
R/W
6
P56
0
R/W
5
P55
0
R/W
If port 5 is read while PCR5 bits are set to 1, the values
stored in PDR5 are read, regardless of the actual pin
states. If port 5 is read while PCR5 bits are cleared to 0,
the pin states are read.
4
P54
0
R/W
3
P53
0
R/W
2
P52
0
R/W
1
P51
0
R/W
0
P50
0
R/W
8.3.2
Port Control Register 5 (PCR5)
PCR5 controls whether each of the port 5 pins functions as an input pin or output pin.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR57
0
W
6
PCR56
0
W
5
PCR55
0
W
4
PCR54
0
W
Setting a PCR5 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR5 and in PDR5 are valid
only when the corresponding pin is designated by PMR5
and the SGS3 to SGS0 bits in LPCR as a general I/O pin.
3
PCR53
0
W
2
PCR52
0
W
1
PCR51
0
W
0
PCR50
0
W
PCR5 is a write-only register. Bits 7 to 0 are always read
as 1.
Rev. 6.00 Mar 15, 2005 page 191 of 502
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Section 8 I/O Ports
8.3.3
Port Pull-Up Control Register 5 (PUCR5)
PUCR5 controls whether the pull-up MOS of each of the port 5 pins is on or off.
Bit
Bit Name
Initial
Value
R/W
Description
7
PUCR57
0
R/W
6
PUCR56
0
R/W
5
PUCR55
0
R/W
When a PCR5 bit is cleared to 0, setting the
corresponding PUCR5 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0 turns
off the pull-up MOS.
4
PUCR54
0
R/W
3
PUCR53
0
R/W
2
PUCR52
0
R/W
1
PUCR51
0
R/W
0
PUCR50
0
R/W
8.3.4
Port Mode Register 5 (PMR5)
PMR5 controls the selection of pin functions for port 5 pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
WKP7
0
R/W
P5n/WKPn/SEGn+1 Pin Function Switch
6
WKP6
0
R/W
5
WKP5
0
R/W
4
WKP4
0
R/W
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1,
these bits select whether the pin is used as P5n or
WKPn.
3
WKP3
0
R/W
2
WKP2
0
R/W
1
WKP1
0
R/W
0
WKP0
0
R/W
0: P5n I/O pin
1: WKPn input pin
(n = 7 to 0)
Note: For use as SEGn+1, see section 13.3.1, LCD Port Control Register (LPCR).
Rev. 6.00 Mar 15, 2005 page 192 of 502
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Section 8 I/O Ports
8.3.5
Pin Functions
The port 5 pin functions are shown below.
• P57/WKP7/SEG8 to P54/WKP4/SEG5 pins
The pin function depends on the combination of bit WKPn in PMR5, bit PCR5n in PCR5, and bits
SGS3 to SGS0 in LPCR.
(n = 7 to 4)
SGS3 to
SGS0
Other than B′0010, B′0011, B′0100, B′0101,
B′0110, B′0111, B′1000, B′1001
WKPn
PCR5n
0
0
Pin Function P5n input pin
B′0010, B′0011, B′0100, B′0101,
B′0110, B′0111, B′1000, B′1001
1
*
1
*
*
P5n output pin
WKPn input pin
SEGn+1 output pin
Legend: *: Don't care.
• P53/WKP3/SEG4 to P50/WKP0/SEG1 pins
The pin function depends on the combination of bit WKPm in PMR5, bit PCR5m in PCR5, and
bits SGS3 to SGS0 in LPCR.
(m = 3 to 0)
SGS3 to
SGS0
Other than B′0001, B′0010, B′0011, B′0100,
B′0101, B′0110, B′0111, B′1000
WKPm
PCR5m
0
0
1
B′0001, B′0010, B′0011, B′0100,
B′0101, B′0110, B′0111, B′1000
1
*
*
*
Pin Function P5m input pin P5m output pin WKPm input pin
SEGm+1 output pin
Legend: *: Don't care.
Rev. 6.00 Mar 15, 2005 page 193 of 502
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Section 8 I/O Ports
8.3.6
Input Pull-Up MOS
Port 5 has an on-chip input pull-up MOS function that can be controlled by software. When the
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0)
PCR5n
0
PUCR5n
Input Pull-Up MOS
1
0
1
*
Off
On
Off
Legend: *: Don't care.
8.4
Port 6
Port 6 is an I/O port also functioning as an LCD segment output pin. Figure 8.5 shows its pin
configuration.
P67/SEG16
P66/SEG15
P65/SEG14
Port 6
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Figure 8.5 Port 6 Pin Configuration
Port 6 has the following registers.
• Port data register 6 (PDR6)
• Port control register 6 (PCR6)
• Port pull-up control register 6 (PUCR6)
Rev. 6.00 Mar 15, 2005 page 194 of 502
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Section 8 I/O Ports
8.4.1
Port Data Register 6 (PDR6)
PDR6 is a register that stores data of port 6.
Bit
Bit Name
Initial
Value
R/W
Description
7
P67
0
R/W
6
P66
0
R/W
5
P65
0
R/W
If port 6 is read while PCR6 bits are set to 1, the values
stored in PDR6 are read, regardless of the actual pin
states. If port 6 is read while PCR6 bits are cleared to 0,
the pin states are read.
4
P64
0
R/W
3
P63
0
R/W
2
P62
0
R/W
1
P61
0
R/W
0
P60
0
R/W
8.4.2
Port Control Register 6 (PCR6)
PCR6 controls whether each of the port 6 pins functions as an input pin or output pin.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR67
0
W
6
PCR66
0
W
5
PCR65
0
W
4
PCR64
0
W
Setting a PCR6 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR6 and in PDR6 are valid
only when the corresponding pin is designated by the
SGS3 to SGS0 bits in LPCR as a general I/O pin.
3
PCR63
0
W
2
PCR62
0
W
1
PCR61
0
W
0
PCR60
0
W
PCR6 is a write-only register. Bits 7 to 0 are always read
as 1.
Rev. 6.00 Mar 15, 2005 page 195 of 502
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Section 8 I/O Ports
8.4.3
Port Pull-Up Control Register 6 (PUCR6)
PUCR6 controls whether the pull-up MOS of each of the port 6 pins is on or off.
Bit
Bit Name
Initial
Value
R/W
Description
7
PUCR67
0
R/W
6
PUCR66
0
R/W
5
PUCR65
0
R/W
When a PCR6 bit is cleared to 0, setting the
corresponding PUCR6 bit to 1 turns on the pull-up MOS
for the corresponding pin, while clearing the bit to 0 turns
off the pull-up MOS.
4
PUCR64
0
R/W
3
PUCR63
0
R/W
2
PUCR62
0
R/W
1
PUCR61
0
R/W
0
PUCR60
0
R/W
8.4.4
Pin Functions
The port 6 pin functions are shown below.
• P67/SEG16 to P64/SEG13 pins
The pin function depends on the combination of bit PCR6n in PCR6 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 4)
SGS3 to
SGS0
Other than B′0100, B′0101, B′0110, B′0111,
B′1000, B′1001, B′1010, B′1011
PCR6n
Pin Function
B′0100, B′0101, B′0110, B′0111,
B′1000, B′1001, B′1010, B′1011
0
1
*
P6n input pin
P6n output pin
SEGn+9 output pin
Legend: *: Don't care.
Rev. 6.00 Mar 15, 2005 page 196 of 502
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Section 8 I/O Ports
• P63/SEG12 to P60/SEG9 pins
The pin function depends on the combination of bit PCR6m in PCR6 and bits SGS3 to SGS0 in
LPCR.
(m = 3 to 0)
SGS3 to
SGS0
Other than B′0011, B′0100, B′0101, B′0110,
B′0111, B′1000, B′1001, B′1010
PCR6m
Pin Function
B′0011, B′0100, B′0101, B′0110,
B′0111, B′1000, B′1001, B′1010
0
1
*
P6m input pin
P6m output pin
SEGm+9 output pin
Legend: *: Don't care.
8.4.5
Input Pull-Up MOS
Port 6 has an on-chip input pull-up MOS function that can be controlled by software. When the
PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the input pull-up MOS
for that pin. The input pull-up MOS function is in the off state after a reset.
(n = 7 to 0)
PCR6n
PUCR6n
Input Pull-Up MOS
0
1
0
1
*
Off
On
Off
Legend: *: Don't care.
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Section 8 I/O Ports
8.5
Port 7
Port 7 is an I/O port also functioning as an LCD segment output pin. Figure 8.6 shows its pin
configuration.
P77/SEG24
P76/SEG23
P75/SEG22
Port 7
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Figure 8.6 Port 7 Pin Configuration
Port 7 has the following registers.
• Port data register 7 (PDR7)
• Port control register 7 (PCR7)
8.5.1
Port Data Register 7 (PDR7)
PDR7 is a register that stores data of port 7.
Bit
Bit Name
Initial
Value
R/W
Description
7
P77
0
R/W
6
P76
0
R/W
5
P75
0
R/W
If port 7 is read while PCR7 bits are set to 1, the values
stored in PDR7 are read, regardless of the actual pin
states. If port 7 is read while PCR7 bits are cleared to 0,
the pin states are read.
4
P74
0
R/W
3
P73
0
R/W
2
P72
0
R/W
1
P71
0
R/W
0
P70
0
R/W
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Section 8 I/O Ports
8.5.2
Port Control Register 7 (PCR7)
PCR7 controls whether each of the port 7 pins functions as an input pin or output pin.
Bit
Bit Name
Initial
Value
R/W
Description
7
PCR77
0
W
6
PCR76
0
W
5
PCR75
0
W
4
PCR74
0
W
Setting a PCR7 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR7 and in PDR7 are valid
only when the corresponding pin is designated by the
SGS3 to SGS0 bits in LPCR as a general I/O pin.
3
PCR73
0
W
2
PCR72
0
W
1
PCR71
0
W
0
PCR70
0
W
8.5.3
Pin Functions
PCR7 is a write-only register. Bits 7 to 0 are always read
as 1.
The port 7 pin functions are shown below.
• P77/SEG24 to P74/SEG21 pins
The pin function depends on the combination of bit PCR7n in PCR7 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 4)
SGS3 to
SGS0
Other than B'0110, B'0111, B'1000, B'1001,
B'1010, B'1011, B'1100, B'1101
PCR7n
Pin Function
B'0110, B'0111, B'1000, B'1001,
B'1010, B'1011, B'1100, B'1101
0
1
*
P7n input pin
P7n output pin
SEGn+17 output pin
Legend: *: Don't care.
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Section 8 I/O Ports
• P73/SEG20 to P70/SEG17 pins
The pin function depends on the combination of bit PCR7m in PCR7 and bits SGS3 to SGS0 in
LPCR.
(m = 3 to 0)
SGS3 to
SGS0
Other than B'0101, B'0110, B'0111, B'1000,
B'1001, B'1010, B'1011, B'1100
PCR7m
Pin Function
B'0101, B'0110, B'0111, B'1000,
B'1001, B'1010, B'1011, B'1100
0
1
*
P7m input pin
P7m output pin
SEGm+17 output pin
Legend: *: Don't care.
8.6
Port 8
Port 8 is an I/O port also functioning as an LCD segment output pin. Figure 8.7 shows its pin
configuration.
Port 8
P80/SEG25
Figure 8.7 Port 8 Pin Configuration
Port 8 has the following registers.
• Port data register 8 (PDR8)
• Port control register 8 (PCR8)
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Section 8 I/O Ports
8.6.1
Port Data Register 8 (PDR8)
PDR8 is a register that stores data of port 8.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1



Reserved
0
P80
0
R/W
If port 8 is read while PCR8 bits are set to 1, the values
stored in PDR8 are read, regardless of the actual pin
states. If port 8 is read while PCR8 bits are cleared to 0,
the pin states are read.
8.6.2
Port Control Register 8 (PCR8)
PCR8 controls whether each of the port 8 pins functions as an input pin or output pin.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 1


W
Reserved
The write value should always be 0.
0
PCR80
0
W
Setting a PCR8 bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCR8 and in PDR8 are valid
only when the corresponding pin is designated by the
SGS3 to SGS0 bits in LPCR as a general I/O pin.
PCR8 is a write-only register.
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Section 8 I/O Ports
8.6.3
Pin Functions
The port 8 pin functions are shown below.
• P80/SEG25 pin
The pin function depends on the combination of bit PCR80 in PCR8 and bits SGS3 to SGS0 in
LPCR.
SGS3 to
SGS0
Other than B'0111, B'1000, B'1001, B'1010,
B'1011, B'1100, B'1101, B'1110
PCR80
Pin Function
B'0111, B'1000, B'1001, B'1010,
B'1011, B'1100, B'1101, B'1110
0
1
*
P80 input pin
P80 output pin
SEG25 output pin
Legend: *: Don't care.
8.7
Port 9
Port 9 is a dedicated current port for NMOS output that also functions as a PWM output pin.
Figure 8.8 shows its pin configuration.
P95
P94*1
P93/Vref*2
Port 9
P92
P91/PWM2
P90/PWM1
Notes: 1. There is no pin 94, and its function is not implemented, on the H8/38104 Group.
2. The Vref pin is implemented on the H8/38104 Group only.
Figure 8.8 Port 9 Pin Configuration
Port 9 has the following registers.
• Port data register 9 (PDR9)
• Port mode register 9 (PMR9)
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Section 8 I/O Ports
8.7.1
Port Data Register 9 (PDR9)
PDR9 is a register that stores data of port 9.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
5
P95
1
R/W
4
P94*
1
R/W
3
P93
1
R/W
2
P92
1
R/W
1
P91
1
R/W
0
P90
1
R/W
The initial value should not be changed.
If PDR9 is read, the values stored in PDR9 are read.
Note: * There is no pin 94, and its function is not implemented, on the H8/38104 Group. However,
the register is read/write enabled.
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Section 8 I/O Ports
8.7.2
Port Mode Register 9 (PMR9)
PMR9 controls the selection of the P90 and P91 pin functions.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

All 1

Reserved
The initial value should not be changed.
3
PIOFF
0
R/W
P92 to P90 Step-Up Circuit Control
This bit turns on and off the P92 to P90 step-up circuit.
0: Step-up circuit of large-current port is turned on
1: Step-up circuit of large-current port is turned off
Note: This bit is valid in the H8/3802 Group only. It
functions as a readable/writable reserved bit in
versions other than the H8/3802 Group.
2


W
Reserved
The write value should always be 0.
1
PWM2
0
R/W
P9n/PWMn+1 Pin Function Switch
0
PWM1
0
R/W
These bits select whether pin P9n/PWMn+1 is used as
P9n or as PWMn+1. (n = 1, 0)
0: P9n output pin
1: PWMn+1 output pin
Note: When turning the step-up circuit on or off, the register must be rewritten only when the
buffer NMOS is off (port data is 1).
When turning the step-up circuit on, first clear PIOFF to 0, then wait for the elapse of 30
system clock before turning the buffer NMOS on (clearing port data to 0).
Without the elapse of the 30 system clock interval the step-up circuit will not start up, and it
will not be possible for a large current to flow, making operation unstable.
8.7.3
Pin Functions
The port 9 pin functions are shown below.
• P91/PWMn+1 to P90/PWMn+1 pins
(n = 1, 0)
PMR9n
Pin Function
0
1
P9n output pin
PWMn+1 output pin
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Section 8 I/O Ports
• P93/Vref
As shown below, switching is performed based on the setting of VREFSEL in LVDSR. Note that
this function is implemented on the H8/38104 Group only. The Vref pin is the input pin for the
LVD’s external reference voltage.
VREFSEL
Pin Function
8.8
0
1
P93 output pin
Vref input pin
Port A
Port A is an I/O port also functioning as an LCD common output pin. Figure 8.9 shows its pin
configuration.
PA3/COM4
Port A
PA2/COM3
PA1/COM2
PA0/COM1
Figure 8.9 Port A Pin Configuration
Port A has the following registers.
• Port data register A (PDRA)
• Port control register A (PCRA)
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Section 8 I/O Ports
8.8.1
Port Data Register A (PDRA)
PDRA is a register that stores data of port A.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

All 1

Reserved
3
PA3
0
R/W
2
PA2
0
R/W
1
PA1
0
R/W
0
PA0
0
R/W
The initial value should not be changed.
8.8.2
If port A is read while PCRA bits are set to 1, the values
stored in PDRA are read, regardless of the actual pin
states. If port A is read while PCRA bits are cleared to 0,
the pin states are read.
Port Control Register A (PCRA)
PCRA controls whether each of the port A pins functions as an input pin or output pin.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

All 1

Reserved
The initial value should not be changed.
3
PCRA3
0
W
2
PCRA2
0
W
1
PCRA1
0
W
0
PCRA0
0
W
Setting a PCRA bit to 1 makes the corresponding pin an
output pin, while clearing the bit to 0 makes the pin an
input pin. The settings in PCRA and in PDRA are valid
only when the corresponding pin is designated in LPCR
as a general I/O pin.
PCRA is a write-only register. Bits 3 to 0 are always read
as 1.
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Section 8 I/O Ports
8.8.3
Pin Functions
The port A pin functions are shown below.
• PA3/COM4 pin
The pin function depends on the combination of bit PCRA3 in PCRA and bits SGS3 to SGS0 in
LPCR.
SGS3 to SGS0
PCRA3
Pin Function
B'0000
B'0000
Other than B'0000
0
1
*
PA3 input pin
PA3 output pin
COM4 output pin
Legend: *: Don't care.
• PA2/COM3 pin
The pin function depends on the combination of bit PCRA2 in PCRA and bits SGS3 to SGS0 in
LPCR.
SGS3 to SGS0
PCRA2
Pin Function
B'0000
B'0000
Other than B'0000
0
1
*
PA2 input pin
PA2 output pin
COM3 output pin
Legend: *: Don't care.
• PA1/COM2 pin
The pin function depends on the combination of bit PCRA1 in PCRA and bits SGS3 to SGS0 in
LPCR.
SGS3 to SGS0
PCRA1
Pin Function
B'0000
B'0000
Other than B'0000
0
1
*
PA1 input pin
PA1 output pin
COM2 output pin
Legend: *: Don't care.
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Section 8 I/O Ports
• PA0/COM1 pin
The pin function depends on the combination of bit PCRA0 in PCRA and bits SGS3 to SGS0 in
LPCR.
SGS3 to SGS0
PCRA0
Pin Function
B'0000
B'0000
Other than B'0000
0
1
*
PA0 input pin
PA0 output pin
COM1 output pin
Legend: *: Don't care.
8.9
Port B
Port B is an input-only port also functioning as an analog input pin and interrupt input pin. Figure
8.10 shows its pin configuration.
PB3/AN3/IRQ1
Port B
PB2/AN2
PB1/AN1/extU*
PB0/AN0/extD*
Note: * The extU and extD pins are implemented on the H8/38104 Group only.
Figure 8.10 Port B Pin Configuration
Port B has the following registers.
• Port data register B (PDRB)
• Port mode register B (PMRB)
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Section 8 I/O Ports
8.9.1
Port Data Register B (PDRB)
PDRB is a register that stores data of port B.
Bit
Bit Name
Initial
Value
7 to 4

Undefined 
Reserved
3
PB3
Undefined R
2
PB2
R
1
PB1
R
Reading PDRB always gives the pin states. However, if
a port B pin is selected as an analog input channel for
the A/D converter by bits CH3 to CH0 in AMR, that pin
reads 0 regardless of the input voltage.
0
PB0
R
8.9.2
R/W
Description
Port Mode Register B (PMRB)
PMRB controls the selection of the PB3 pin functions.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
3
IRQ1
0
R/W
PB3/AN3/IRQ1 Pin Function Switch
This bit selects whether pin PB3/AN3/IRQ1 is used as
PB3/AN3 or as IRQ1.
0: PB3/AN3 input pin
1: IRQ1 input pin
2 to 0

All 1

Reserved
These bits are always read as 1 and cannot be
modified.
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Section 8 I/O Ports
8.9.3
Pin Functions
The port B pin functions are shown below.
• PB3/AN3/IRQ1 pin
The pin function depends on the combination of bits CH3 to CH0 in AMR and bit IRQ1 in PMRB.
IRQ1
0
1
CH3 to CH0
Other than B'0111
B'0111
Pin Function
PB3 input pin
AN3 input pin
*
IRQ1
input pin
Legend: *: Don't care.
• PB2/AN2 pin
The pin function depends on bits CH3 to CH0 in AMR.
CH3 to CH0
Other than B'0110
B'0110
Pin Function
PB2 input pin
AN2 input pin
• PB1/AN1/extU pin
Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in LVDCR as
shown below. Note that the extU pin and VINTUSEL are implemented on the H8/38104 Group
only.
VINTUSEL
0
1
CH3 to CH0
Other than B'0101
B'0101
*
Pin Function
PB1 input pin
AN1 input pin
extU input pin
Legend: *: Don't care
• PB0/AN0/extD pin
Switching is accomplished by combining CH3 to CH0 in AMR and VINTDSEL in LVDCR as
shown below. Note that the extD pin and VINTDSEL are implemented on the H8/38104 Group
only.
VINTDSEL
0
1
CH3 to CH0
Other than B'0100
B'0100
*
Pin Function
PB0 input pin
AN0 input pin
extD input pin
Legend: *: Don't care
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Section 8 I/O Ports
8.10
8.10.1
Usage Notes
How to Handle Unused Pin
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, handle it in one of the following ways:
 Pull it up to Vcc with an on-chip pull-up MOS.
 Pull it up to Vcc with an external resistor of approximately 100 kΩ.
 Pull it down to Vss with an external resistor of approximately 100 kΩ.
 For a pin also used by the A/D converter, pull it up to AVcc.
• If an unused pin is an output pin, handle it in one of the following ways:
 Set the output of the unused pin to high and pull it up to Vcc with an on-chip pull-up MOS.
 Set the output of the unused pin to high and pull it up to Vcc with an external resistor of
approximately 100 kΩ.
 Set the output of the unused pin to low and pull it down to GND with an external resistor of
approximately 100 kΩ.
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Section 8 I/O Ports
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Section 9 Timers
Section 9 Timers
9.1
Overview
The H8/3802 Group provides three timers: timer A, timer F, and asynchronous event counter. The
H8/38004 Group, H8/38002S Group and H8/38104 Group provide four timers: timer A, timer F,
asynchronous event counter, and watchdog timer.
The functions of these timers are summarized in table 9.1.
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Section 9 Timers
Table 9.1
Timer Functions
Name
Functions
Internal Clock
Event Input Waveform
Pin
Output Pin
Timer A
•
8-bit timer
φ/8 to φ/8192
—
•
Interval function
(8 choices)
•
Clock time base
φW /128 (choice
of 4 overflow
periods)
•
16-bit timer
φ/4 to φ/32, φW /4 —
TMOFL
•
Also usable as two
independent 8-bit
timers.
(4 choices)
TMOFH
•
Output compare
output function
•
16-bit counter
φ/2 to φ/8
AEVL
•
Also usable as two
independent 8-bit
counters
(3 choices)
AEVH
Timer F
Asynchronous event
counter
Watchdog
timer*
•
Counts events
asynchronous to φ
and φW
•
Can count
asynchronous events
(rising/falling/both
edges) independently of the MCU's
internal clock
•
φ/8192, φW /32
Generates a reset
signal by overflow of
8-bit counter
φ/64 to φ/8192
φw/32
On-chip
oscillator
Remarks
—
—
IRQAEC


H8/38004,
H8/38002S
Group
H8/38104
Group
Note: * The watchdog timer functions differently on the H8/38004, H8/38002S and H8/38104
Group. See section 9.5, Watchdog Timer, for details.
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Section 9 Timers
9.2
Timer A
The timer A is an 8-bit timer with interval timing and realtime clock time-base functions. The
clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 9.1
shows a block diagram of the timer A.
9.2.1
Features
• The timer A can be used as an interval timer or a clock time base.
• An interrupt is requested when the counter overflows.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
Interval Timer
• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, and
φ8)
Clock Time Base
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, and 31.25 ms) when timer A is used as a
clock time base (using a 32.768 kHz crystal oscillator).
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Section 9 Timers
1/4
PSW
φW/4
TMA
Internal data bus
φW
φW/128
φ
÷256*
÷128*
÷64*
φ/8192, φ/4096,
φ/2048, φ/512,
φ/256, φ/128,
φ/32, φ/8
÷8*
TCA
PSS
IRRTA
Legend:
TMA: Timer mode register A
TCA:
Timer counter A
IRRTA: Timer A overflow interrupt request flag
PSW: Prescaler W
PSS:
Prescaler S
Note: * Can be selected only when the prescaler W output (φW/128) is used as the TCA input clock.
Figure 9.1 Block Diagram of Timer A
9.2.2
Register Descriptions
The timer A has the following registers.
• Timer mode register A (TMA)
• Timer counter A (TCA)
Timer Mode Register A (TMA): TMA selects the operating mode, the divided clock output, and
the input clock.
Bit
Bit Name
Initial
Value
R/W
Description
7


W
Reserved
6


W
The write value should always be 0.
5


W
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Section 9 Timers
Bit
Bit Name
Initial
Value
R/W
Description
4

1

Reserved
3
TMA3
0
R/W
This bit is always read as 1.
Internal Clock Select 3
Selects the operating mode of the timer A.
0: Functions as an interval timer to count the outputs of
prescaler S.
1: Functions as a clock-time base to count the outputs of
prescaler W.
2
TMA2
0
R/W
Internal Clock Select 2 to 0
1
TMA1
0
R/W
Select the clock input to TCA when TMA3 = 0.
0
TMA0
0
R/W
000: φ/8192
001: φ/4096
010: φ/2048
011: φ/512
100: φ/256
101: φ/128
110: φ/32
111: φ/8
These bits select the overflow period when TMA3 = 1
(when a 32.768 kHz crystal oscillator is used as φw).
000: 1 s
001: 0.5 s
010: 0.25 s
011: 0.03125 s
1XX: Both PSW and TCA are reset
Legend: X: Don't care.
Timer Counter A (TCA): TCA is an 8-bit readable up-counter, which is incremented by internal
clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in TMA.
TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When
TCA overflows, the IRRTA bit in the interrupt request register 1 (IRR1) is set to 1. TCA is cleared
by setting bits TMA3 and TMA2 in TMA to B'11. TCA is initialized to H'00.
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Section 9 Timers
9.2.3
Operation
Interval Timer Operation: When bit TMA3 in TMA is cleared to 0, the timer A functions as an
8-bit interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of the timer A
resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to
TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt Flag Register 1 (IRR1). If IENTA = 1 in the interrupt
enable register 1 (IENR1), a CPU interrupt is requested. At overflow, TCA returns to H'00 and
starts counting up again. In this mode the timer A functions as an interval timer that generates an
overflow output at intervals of 256 input clock pulses.
Clock Time Base Operation: When bit TMA3 in TMA is set to 1, the timer A functions as a
clock-timer base by counting clock signals output by prescaler W. The overflow period of timer A
is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In clock time base
operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to H'00.
9.2.4
Timer A Operating States
Table 9.2 summarizes the timer A operating states.
Table 9.2
Timer A Operating States
Operating Mode
Reset
Active
Sleep
Watch
Sub-active Sub-sleep
Standby
Module
Standby
TCA
Reset
Functions
Functions
Halted
Halted
Halted
Halted
Halted
Functions*
Functions*
Functions
Functions
Functions
Halted
Halted
Functions
Retained
Retained
Functions
Retained
Retained
Retained
Interval
Clock
Reset
time base
TMA
Note:
Reset
*
When the clock time base function is selected as the internal clock of TCA in active
mode or sleep mode, the internal clock is not synchronous with the system clock, so it
is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s)
in the count cycle.
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Section 9 Timers
9.3
Timer F
The timer F has a 16-bit timer having an output compare function. The timer F also provides for
counter resetting, interrupt request generation, toggle output, etc., using compare match signals.
Thus, it can be applied to various systems. The timer F can also be used as two independent 8-bit
timers (timer FH and timer FL). Figure 9.2 shows a block diagram of the timer F.
9.3.1
Features
• Choice of four internal clock sources (φ/32, φ/16, φ/4, and φW/4)
• Toggle output function
Toggle output is performed to the TMOFH pin (TMOFL pin) using a single compare match
signal.
The initial value of toggle output can be set.
• Counter resetting by a compare match signal
• Two interrupt sources: One compare match, one overflow
• Choice of 16-bit or 8-bit mode by settings of bits CKSH2 to CKSH0 in TCRF
• Can operate in watch mode, subactive mode, and subsleep mode
When φW/4 is selected as an internal clock, the timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
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Section 9 Timers
φ
PSS
IRRTFL
TCRF
φW/4
TCFL
Toggle
circuit
Comparator
Internal data bus
TMOFL
OCRFL
TCFH
Toggle
circuit
TMOFH
Comparator
Match
OCRFH
TCSRF
IRRTFH
Legend:
TCRF:
Timer control register F
TCSRF: Timer control status register F
TCFH:
8-bit timer counter FH
TCFL:
8-bit timer counter FL
OCRFH: Output compare register FH
OCRFL: Output compare register FL
IRRTFH: Timer FH interrupt request flag
IRRTFL: Timer FL interrupt request flag
PSS:
Prescaler S
Figure 9.2 Block Diagram of Timer F
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Section 9 Timers
9.3.2
Input/Output Pins
Table 9.3 shows the pin configuration of the timer F.
Table 9.3
Pin Configuration
Name
Abbreviation I/O
Function
Timer FH output
TMOFH
Output
Timer FH toggle output pin
Timer FL output
TMOFL
Output
Timer FL toggle output pin
9.3.3
Register Descriptions
The timer F has the following registers.
•
•
•
•
Timer counters FH and FL (TCFH,TCFL)
Output compare registers FH and FL (OCRFH, OCRFL)
Timer control register F (TCRF)
Timer control status register F (TCSRF)
Timer Counters FH and FL (TCFH, TCFL): TCF is a 16-bit read/write up-counter configured
by cascaded connection of 8-bit timer counters TCFH and TCFL. In addition to the use of TCF as
a 16-bit counter with TCFH as the upper 8 bits and TCFL as the lower 8 bits, TCFH and TCFL
can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see section 9.3.4, CPU Interface. TCFH and TCFL are initialized to H'00 upon reset.
• 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input clock
is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
• 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
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Section 9 Timers
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH (CCLRL)
in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF. If
OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and if
IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
Output Compare Registers FH and FL (OCRFH, OCRFL): OCRF is a 16-bit read/write
register composed of the two registers OCRFH and OCRFL. In addition to the use of OCRF as a
16-bit register with OCRFH as the upper 8 bits and OCRFL as the lower 8 bits, OCRFH and
OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see section 9.3.4, CPU Interface. OCRFH and OCRFL are initialized to H'FF upon reset.
• 16-bit mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents are
constantly compared with TCF, and when both values match, CMFH is set to 1 in TCSRF. At
the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this time, an interrupt
request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and the
output level can be set (high or low) by means of TOLH in TCRF.
• 8-bit mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with TCFL.
When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is set to 1 in
TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH (IENTFL) in
IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in TCRF.
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Section 9 Timers
Timer Control Register F (TCRF): TCRF switches between 16-bit mode and 8-bit mode, selects
the input clock from among four internal clock sources, and sets the output level of the TMOFH
and TMOFL pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
TOLH
0
W
6
5
4
CKSH2
CKSH1
CKSH0
0
0
0
W
W
W
Toggle Output Level H
Sets the TMOFH pin output level.
0: Low level
1: High level
Clock Select H
Select the clock input to TCFH from among four internal
clock sources or TCFL overflow.
000: 16-bit mode, counting on TCFL overflow signal
001: 16-bit mode, counting on TCFL overflow signal
010: 16-bit mode, counting on TCFL overflow signal
011: Using prohibited
100: Internal clock: counting on φ/32
101: Internal clock: counting on φ/16
110: Internal clock: counting on φ/4
111: Internal clock: counting on φW /4
3
TOLL
0
W
Toggle Output Level L
Sets the TMOFL pin output level.
0: Low level
1: High level
2
CKSL2
0
W
Clock Select L
1
CKSL1
0
W
0
CKSL0
0
W
Select the clock input to TCFL from among four internal
clock sources or external event input.
000: Non-operational
001: Using prohibited
010: Using prohibited
011: Using prohibited
100: Internal clock: counting on φ/32
101: Internal clock: counting on φ/16
110: Internal clock: counting on φ/4
111: Internal clock: counting on φW /4
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Section 9 Timers
Timer Control Status Register F (TCSRF): TCSRF performs counter clear selection, overflow
flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Bit
7
Bit Name
OVFH
Initial
Value
R/W
Description
0
R/W *
Timer Overflow Flag H
[Setting condition]
When TCFH overflows from H’FF to H’00
[Clearing condition]
When this bit is written to 0 after reading OVFH = 1
6
CMFH
0
R/W *
Compare Match Flag H
This is a status flag indicating that TCFH has matched
OCRFH.
[Setting condition]
When the TCFH value matches the OCRFH value
[Clearing condition]
When this bit is written to 0 after reading CMFH = 1
5
OVIEH
0
R/W
Timer Overflow Interrupt Enable H
Selects enabling or disabling of interrupt generation when
TCFH overflows.
0: TCFH overflow interrupt request is disabled
1: TCFH overflow interrupt request is enabled
4
CCLRH
0
R/W
Counter Clear H
In 16-bit mode, this bit selects whether TCF is cleared
when TCF and OCRF match. In 8-bit mode, this bit
selects whether TCFH is cleared when TCFH and
OCRFH match.
In 16-bit mode:
0: TCF clearing by compare match is disabled
1: TCF clearing by compare match is enabled
In 8-bit mode:
0: TCFH clearing by compare match is disabled
1: TCFH clearing by compare match is enabled
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Section 9 Timers
Bit
Bit Name
3
OVFL
Initial
Value
R/W
Description
0
R/W *
Timer Overflow Flag L
This is a status flag indicating that TCFL has overflowed.
[Setting condition]
When TCFL overflows from H’FF to H’00
[Clearing condition]
When this bit is written to 0 after reading OVFL = 1
2
CMFL
0
R/W *
Compare Match Flag L
This is a status flag indicating that TCFL has matched
OCRFL.
[Setting condition]
When the TCFL value matches the OCRFL value
[Clearing condition]
When this bit is written to 0 after reading CMFL = 1
1
OVIEL
0
R/W
Timer Overflow Interrupt Enable L
Selects enabling or disabling of interrupt generation when
TCFL overflows.
0: TCFL overflow interrupt request is disabled
1: TCFL overflow interrupt request is enabled
0
CCLRL
0
R/W
Counter Clear L
Selects whether TCFL is cleared when TCFL and OCRFL
match.
0: TCFL clearing by compare match is disabled
1: TCFL clearing by compare match is enabled
Note:
9.3.4
*
Only 0 can be written to clear the flag.
CPU Interface
TCF and OCRF are 16-bit readable/writable registers, but the CPU is connected to the on-chip
peripheral modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses
an 8-bit temporary register (TEMP).
When performing TCF read/write access or OCRF write access in 16-bit mode, data will not be
transferred correctly if only the upper byte or only the lower byte is accessed. Access must be
performed for all 16 bits (using two consecutive byte-size MOV instructions), and the upper byte
must be accessed before the lower byte.
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Section 9 Timers
In 8-bit mode, there are no restrictions on the order of access.
Write Access: Write access to the upper byte results in transfer of the upper-byte write data to
TEMP. Next, write access to the lower byte results in transfer of the data in TEMP to the upper
register byte, and direct transfer of the lower-byte write data to the lower register byte.
Figure 9.3 shows an example in which H'AA55 is written to TCF.
Write to upper byte
Module data bus
CPU
[H'AA]
Bus interface
TEMP
[H'AA]
TCFH
[
]
TCFL
[
]
Write to lower byte
Module data bus
CPU
[H'55]
Bus interface
TEMP
[H'AA]
TCFH
[H'AA]
TCFL
[H'55]
Figure 9.3 Write Access to TCF (CPU → TCF)
Read Access: In access to TCF, when the upper byte is read the upper-byte data is transferred
directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is
read, the lower-byte data in TEMP is transferred to the CPU.
In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the
CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU.
Figure 9.4 shows an example in which TCF is read when it contains H'AAFF.
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Section 9 Timers
Read upper byte
CPU
[H'AA]
Module data bus
Bus interface
TEMP
[H'FF]
TCFH
[H'AA]
TCFL
[H'FF]
Read lower byte
Module data bus
CPU
[H'FF]
Bus interface
TEMP
[H'FF]
TCFH
[AB] *
TCFL
[00] *
Note: ∗ H'AB00 if counter has been updated once.
Figure 9.4 Read Access to TCF (TCF → CPU)
9.3.5
Operation
The timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in the output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. The timer F can
also function as two independent 8-bit timers.
Timer F Operation: The timer F has two operating modes, 16-bit timer mode and 8-bit timer
mode. The operation in each of these modes is described below.
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Section 9 Timers
• Operation in 16-bit timer mode
When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16-bit
timer.
The timer F operating clock can be selected from three internal clocks output by prescaler S by
means of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is set
to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the CPU,
and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF is cleared.
TMOFH pin output can also be set by TOLH in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
• Operation in 8-bit timer mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH and
TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to CKSL0 in
TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in
TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at the
same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF is 1,
TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by TOLH/TOLL in
TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request is
sent to the CPU.
TCF Increment Timing: TCF is incremented by clock input (internal clock input). Bits CKSH2
to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (φ/32, φ/16,
φ/4, or φW/4) created by dividing the system clock (φ or φW).
TMOFH/TMOFL Output Timing: In TMOFH/TMOFL output, the value set in TOLH/TOLL in
TCRF is output. The output is toggled by the occurrence of a compare match.
Figure 9.5 shows the output timing.
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Section 9 Timers
φ
Count input clock
TCF
OCRF
N
N+1
N
N
N+1
N
Compare match signal
TMOFH, TMOFL
Figure 9.5 TMOFH/TMOFL Output Timing
TCF Clear Timing: TCF can be cleared by a compare match with OCRF.
Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows from H'FFFF to
H'0000.
Compare Match Flag Set Timing: The compare match flag (CMFH or CMFL) is set to 1 when
the TCF and OCRF values match. The compare match signal is generated in the last state during
which the values match (when TCF is updated from the matching value to a new value). When
TCF matches OCRF, the compare match signal is not generated until the next counter clock.
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Section 9 Timers
9.3.6
Timer F Operating States
The timer F operating states are shown in table 9.4.
Table 9.4
Timer F Operating States
Operating
Mode
Reset
Active
Sleep
Watch
Sub-active Sub-sleep Standby
TCF
Reset
Functions*
Functions*
Functions/
Halted*
Functions/
Halted*
Functions/
Halted*
Halted
Halted
OCRF
Reset
Functions
Retained
Retained
Functions
Retained
Retained
Retained
TCRF
Reset
Functions
Retained
Retained
Functions
Retained
Retained
Retained
TCSRF
Reset
Functions
Retained
Retained
Functions
Retained
Retained
Retained
Note:
9.3.7
*
Module
Standby
When φW /4 is selected as the TCF internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, φW /4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
Usage Notes
The following types of contention and operation can occur when the timer F is used.
16-Bit Timer Mode: In toggle output, TMOFH pin output is toggled when all 16 bits match and a
compare match signal is generated. If a TCRF write by a MOV instruction and generation of the
compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of
the TCRF write. TMOFL pin output is unstable in 16-bit mode, and should not be used; the
TMOFL pin should be used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
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Section 9 Timers
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
8-Bit Timer Mode:
• TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF write
by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. The compare match signal is output in
synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is not
output.
• TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write
by a MOV instruction and generation of the compare match signal occur simultaneously,
TOLL data is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match
signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is not
output.
Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer Overflow
Flags H, L (OVFH, OVFL), and Compare Match Flags H, L (CMFH, CMFL): When φW/4 is
selected as the internal clock, “Interrupt source generation signal” will be operated with φW and
the signal will be outputted with φW width. And, “Overflow signal” and “Compare match signal”
are controlled with 2 cycles of φW signals. Those signals are outputted with 2 cycles width of φW
(figure 9.6)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt source generation signal”, same interrupt request flag is set. (1 in
figure 9.6) And, the timer overflow flag and compare match flag cannot be cleared during the term
of validity of “Overflow signal” and “Compare match signal”.
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Section 9 Timers
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (2 in figure 9.6) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula.
For ST of (1) formula, please substitute the longest number of execution states in used instruction.
(10 states of RTE instruction when MULXU, DIVXU instruction is not used, 14 states when
MULXU, DIVXU instruction is used)
In subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
The term of validity of “Interrupt source generation signal”
= 1 cycle of φW + waiting time for completion of executing instruction
+ interrupt time synchronized with φ
= 1/φW + ST × (1/φ) + (2/φ) (second).....(1)
ST: Executing number of execution states
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
3. After reading the timer control status register F (TCSRF), clear the timer overflow flags
(OVFH, OVFL) and compare match flags (CMFH, CMFL).
4. Enable interrupts (set IENFH, IENFL to 1).
Method 2
1. Set interrupt handling routine time to more than time that calculated with (1) formula.
2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
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Section 9 Timers
Interrupt request
flag clear
Interrupt request
flag clear
2
Program processing
Interrupt
Interrupt
Normal
φw
Interrupt source generation
signal (internal signal,
nega-active)
Overflow signal, compare
match signal (internal signal,
nega-active)
Interrupt request flag
(IRRTFH, IRRTFL)
1
Figure 9.6 Clear Interrupt Request Flag when Interrupt Source Generation Signal is Valid
Timer Counter (TCF) Read/Write: When φW/4 is selected as the internal clock in active (highspeed, medium-speed) mode, write on TCF is impossible. And when reading TCF, as the system
clock and internal clock are mutually asynchronous, TCF synchronizes with synchronization
circuit. This results in a maximum TCF read value error of ±1.
When reading or writing TCF in active (high-speed, medium-speed) mode is needed, please select
the internal clock except for φW/4 before read/write is performed.
In subactive mode, even if φW /4 is selected as the internal clock, TCF can be read from or written
to normally.
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Section 9 Timers
9.4
Asynchronous Event Counter (AEC)
The asynchronous event counter is incremented by external event clock or internal clock input.
Figure 9.7 shows a block diagram of the asynchronous event counter.
9.4.1
Features
• Can count asynchronous events
Can count external events input asynchronously without regard to the operation of system
clocks φ and φSUB
• Can be used as two-channel independent 8-bit event counter or single-channel independent 16bit event counter.
• Event/clock input is enabled only when IRQAEC is high or event counter PWM output
(IECPWM) is high.
• Both edge sensing can be used for IRQAEC or event counter PWM output (IECPWM)
interrupts. When the asynchronous counter is not used, they can be used as independent
interrupts.
• When an event counter PWM is used, event clock input enabling/disabling can be controlled
automatically in a fixed cycle.
• External event input or a prescaler output clock can be selected by software for the ECH and
ECL clock sources. φ/2, φ/4, or φ/8 can be selected as the prescaler output clock.
• Both edge counting is possible for AEVL and AEVH.
• Counter resetting and halting of the count-up function can be controlled by software
• Automatic interrupt generation on detection of an event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
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Section 9 Timers
IRREC
φ
ECCR
PSS
ECCSR
φ/2
φ/4, φ/8
OVH
ECL
(8 bits)
CK
Edge sensing circuit
OVL
AEVL
CK
Edge sensing circuit
IRQAEC
To CPU interrupt
(IRREC2)
IECPWM
Edge sensing circuit
Internal data bus
AEVH
ECH
(8 bits)
ECPWCRL
ECPWCRH
PWM waveform generator
φ/2, φ/4,
φ/8, φ/16,
φ/32, φ/64
ECPWDRL
ECPWDRH
AEGSR
Legend:
ECPWCRH:
ECPWDRH:
AEGSR:
ECCSR:
ECL:
Event counter PWM compare register H
Event counter PWM data register H
Input pin edge select register
Event counter control/status register
Event counter L
ECPWCRL:
ECPWDRL:
ECCR:
ECH:
Event counter PWM compare register L
Event counter PWM data register L
Event counter control register
Event counter H
Figure 9.7 Block Diagram of Asynchronous Event Counter
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Section 9 Timers
9.4.2
Input/Output Pins
Table 9.5 shows the pin configuration of the asynchronous event counter.
Table 9.5
Pin Configuration
Name
Abbreviation I/O
Function
Asynchronous event input H AEVH
Input
Event input pin for input to event counter H
Asynchronous event input L
AEVL
Input
Event input pin for input to event counter L
Event input enable interrupt
input
IRQAEC
Input
Input pin for interrupt enabling event input
9.4.3
Register Descriptions
The asynchronous event counter has the following registers.
•
•
•
•
•
•
•
•
•
Event counter PWM compare register H (ECPWCRH)
Event counter PWM compare register L (ECPWCRL)
Event counter PWM data register H (ECPWDRH)
Event counter PWM data register L (ECPWDRL)
Input pin edge select register (AEGSR)
Event counter control register (ECCR)
Event counter control/status register (ECCSR)
Event counter H (ECH)
Event counter L (ECL)
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Event Counter PWM Compare Register H (ECPWCRH): ECPWCRH sets the one conversion
period of the event counter PWM waveform.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECPWCRH7
1
R/W
6
ECPWCRH6
1
R/W
One conversion period of event counter PWM
waveform
5
ECPWCRH5
1
R/W
4
ECPWCRH4
1
R/W
3
ECPWCRH3
1
R/W
2
ECPWCRH2
1
R/W
1
ECPWCRH1
1
R/W
0
ECPWCRH0
1
R/W
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore
ECPWCRH should not be modified.
When changing the conversion period, the event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRH.
Event Counter PWM Compare Register L (ECPWCRL): ECPWCRL sets the one conversion
period of the event counter PWM waveform.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECPWCRL7
1
R/W
6
ECPWCRL6
1
R/W
One conversion period of event counter PWM
waveform
5
ECPWCRL5
1
R/W
4
ECPWCRL4
1
R/W
3
ECPWCRL3
1
R/W
2
ECPWCRL2
1
R/W
1
ECPWCRL1
1
R/W
0
ECPWCRL0
1
R/W
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore
ECPWCRL should not be modified.
When changing the conversion period, the event counter PWM must be halted by clearing
ECPWME to 0 in AEGSR before modifying ECPWCRL.
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Event Counter PWM Data Register H (ECPWDRH): ECPWDRH controls data of the event
counter PWM waveform generator.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECPWDRH7
0
W
6
ECPWDRH6
0
W
Data control of event counter PWM waveform
generator
5
ECPWDRH5
0
W
4
ECPWDRH4
0
W
3
ECPWDRH3
0
W
2
ECPWDRH2
0
W
1
ECPWDRH1
0
W
0
ECPWDRH0
0
W
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore
ECPWDRH should not be modified.
When changing the data, the event counter PWM must be halted by clearing ECPWME to 0
in AEGSR before modifying ECPWDRH.
Event Counter PWM Data Register L (ECPWDRL): ECPWDRL controls data of the event
counter PWM waveform generator.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECPWDRL7
0
W
6
ECPWDRL6
0
W
Data control of event counter PWM waveform
generator
5
ECPWDRL5
0
W
4
ECPWDRL4
0
W
3
ECPWDRL3
0
W
2
ECPWDRL2
0
W
1
ECPWDRL1
0
W
0
ECPWDRL0
0
W
Notes: When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore
ECPWDRL should not be modified.
When changing the data, the event counter PWM must be halted by clearing ECPWME to 0
in AEGSR before modifying ECPWDRL.
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Input Pin Edge Select Register (AEGSR): AEGSR selects rising, falling, or both edge sensing
for the AEVH, AEVL, and IRQAEC pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
AHEGS1
0
R/W
AEC Edge Select H
6
AHEGS0
0
R/W
Select rising, falling, or both edge sensing for the AEVH
pin.
00: Falling edge on AEVH pin is sensed
01: Rising edge on AEVH pin is sensed
10: Both edges on AEVH pin are sensed
11: Setting prohibited
5
ALEGS1
0
R/W
AEC Edge Select L
4
ALEGS0
0
R/W
Select rising, falling, or both edge sensing for the AEVL
pin.
00: Falling edge on AEVL pin is sensed
01: Rising edge on AEVL pin is sensed
10: Both edges on AEVL pin are sensed
11: Setting prohibited
3
AIEGS1
0
R/W
IRQAEC Edge Select
2
AIEGS0
0
R/W
Select rising, falling, or both edge sensing for the
IRQAEC pin.
00: Falling edge on IRQAEC pin is sensed
01: Rising edge on IRQAEC pin is sensed
10: Both edges on IRQAEC pin are sensed
11: Setting prohibited
1
ECPWME
0
R/W
Event Counter PWM Enable
Controls operation of event counter PWM and selection
of IRQAEC.
0: AEC PWM halted, IRQAEC selected
1: AEC PWM enabled, IRQAEC not selected
0

0
R/W
Reserved
This bit can be read from or written to. However, this bit
should not be set to 1.
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Event Counter Control Register (ECCR): ECCR controls the counter input clock and
IRQAEC/IECPWM.
Bit
Bit Name
Initial
Value
R/W
Description
7
ACKH1
0
R/W
AEC Clock Select H
6
ACKH0
0
R/W
Select the clock used by ECH.
00: AEVH pin input
01: φ/2
10: φ/4
11: φ/8
5
ACKL1
0
R/W
AEC Clock Select L
4
ACKL0
0
R/W
Select the clock used by ECL.
00: AEVL pin input
01: φ/2
10: φ/4
11: φ/8
3
PWCK2
0
R/W
Event Counter PWM Clock Select
2
PWCK1
0
R/W
Select the event counter PWM clock.
1
PWCK0
0
R/W
000: φ/2
001: φ/4
010: φ/8
011: φ/16
1X0: φ/32
1X1 φ/64
0

0
R/W
Reserved
This bit can be read from or written to. However, this bit
should not be set to 1.
Legend: X: Don't care.
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Event Counter Control/Status Register (ECCSR): ECCSR controls counter overflow detection,
counter clear resetting, and the count-up function.
Bit
7
Bit Name
OVH
Initial
Value
R/W
Description
0
R/W *
Counter Overflow H
This is a status flag indicating that ECH has overflowed.
[Setting condition]
When ECH overflows from H’FF to H’00
[Clearing condition]
When this bit is written to 0 after reading OVH = 1
6
OVL
0
R/W *
Counter Overflow L
This is a status flag indicating that ECL has overflowed.
[Setting condition]
When ECL overflows from H'FF to H'00
[Clearing condition]
When this bit is written to 0 after reading OVL = 1
5

0
R/W
Reserved
This bit can be read from or written to. However, the initial
value should not be changed.
4
CH2
0
R/W
Channel Select
Selects how ECH and ECL event counters are used
0: ECH and ECL are used together as a single-channel
16-bit event counter
1: ECH and ECL are used as two-channel 8-bit event
counter
3
CUEH
0
R/W
Count-Up Enable H
Enables event clock input to ECH.
0: ECH event clock input is disabled (ECH value is
retained)
1: ECH event clock input is enabled
2
CUEL
0
R/W
Count-Up Enable L
Enables event clock input to ECL.
0: ECL event clock input is disabled (ECL value is
retained)
1: ECL event clock input is enabled
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Section 9 Timers
Bit
Bit Name
Initial
Value
R/W
Description
1
CRCH
0
R/W
Counter Reset Control H
Controls resetting of ECH.
0: ECH is reset
1: ECH reset is cleared and count-up function is enabled
0
CRCL
0
R/W
Counter Reset Control L
Controls resetting of ECL.
0: ECL is reset
1: ECL reset is cleared and count-up function is enabled
Note:
*
Only 0 can be written to clear the flag.
Event Counter H (ECH): ECH is an 8-bit read-only up-counter that operates as an independent
8-bit event counter. ECH also operates as the upper 8-bit up-counter of a 16-bit event counter
configured in combination with ECL.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECH7
0
R
6
ECH6
0
R
5
ECH5
0
R
Either the external asynchronous event AEVH pin, φ/2,
φ/4, or φ/8, or the overflow signal from lower 8-bit counter
ECL can be selected as the input clock source. ECH can
be cleared to H'00 by software.
4
ECH4
0
R
3
ECH3
0
R
2
ECH2
0
R
1
ECH1
0
R
0
ECH0
0
R
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Section 9 Timers
Event Counter L (ECL): ECL is an 8-bit read-only up-counter that operates as an independent 8bit event counter. ECL also operates as the lower 8-bit up-counter of a 16-bit event counter
configured in combination with ECH.
Bit
Bit Name
Initial
Value
R/W
Description
7
ECL7
0
R
6
ECL6
0
R
Either the external asynchronous event AEVL pin, φ/2,
φ/4, or φ/8 can be selected as the input clock source. ECL
can be cleared to H'00 by software.
5
ECL5
0
R
4
ECL4
0
R
3
ECL3
0
R
2
ECL2
0
R
1
ECL1
0
R
0
ECL0
0
R
9.4.4
Operation
16-Bit Counter Operation: When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a
16-bit event counter.
Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of
bits ACKL1 and ACKL0 in ECCR.
When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.8 shows an example of the software processing when ECH and ECL are used as
a 16-bit event counter.
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Section 9 Timers
Start
Clear CH2 to 0
Set ACKL1, ACKL0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.8 Example of Software Processing when Using ECH and ECL as
16-Bit Event Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset,
and as ACKL1 and ACKL0 are cleared to B′00, the operating clock is asynchronous event input
from the AEVL pin (using falling edge sensing).
When the next clock is input after the count value reaches H'FF in both ECH and ECL, ECH and
ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the ECH and ECL
count values each return to H'00, and counting up is restarted. When overflow occurs, the IRREC
bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to
the CPU.
8-Bit Counter Operation: When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as
independent 8-bit event counters.
φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of
bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the
input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Input sensing is selected with bits AHEGS1 and AHEGS0 when AEVH pin input is selected, and
with bits ALEGS1 and ALEGS0 when AEVL pin input is selected.
The input clock is enabled only when IRQAEC is high or IECPWM is high. When IRQAEC is
low or IECPWM is low, the input clock is not input to the counter, which therefore does not
operate. Figure 9.9 shows an example of the software processing when ECH and ECL are used as
8-bit event counters.
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Section 9 Timers
Start
Set CH2 to 1
Set ACKH1, ACKH0, ACKL1, ACKL0,
AHEGS1, AHEGS0, ALEGS1, and ALEGS0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.9 Example of Software Processing when Using ECH and ECL as
8-Bit Event Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.9. When the next clock is input after the ECH count value reaches H'FF,
ECH overflows, the OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and
counting up is restarted. Similarly, when the next clock is input after the ECL count value reaches
H'FF, ECL overflows, the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00,
and counting up is restarted. When an overflow occurs, the IRREC bit is set to 1 in IRR2. If the
IENEC bit in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
IRQAEC Operation: When ECPWME in AEGSR is 0, the ECH and ECL input clocks are
enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the
counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be
controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled
individually.
IRQAEC can also operate as an interrupt source. In this case the vector number is 6 and the vector
addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IRQAEC interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge sensing can be selected for the IRQAEC input pin with bits AIAGS1
and AIAGS0 in AEGSR.
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Section 9 Timers
Note: On the H8/38104 Group, control of switching between the system clock oscillator and the
on-chip oscillator during resets should be performed by setting the IRQAEC input level.
Refer to section 4.4, Subclock Generator, for details.
Event Counter PWM Operation: When ECPWME in AEGSR is 1, the ECH and ECL input
clocks are enabled only when event counter PWM output (IECPWM) is high. When IECPWM is
low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and
ECL count operations can therefore be controlled cyclically from outside by controlling event
counter PWM. In this case, ECH and ECL cannot be controlled individually.
IECPWM can also operate as an interrupt source. In this case the vector number is 6 and the
vector addresses are H'000C and H'000D.
Interrupt enabling is controlled by IENEC2 in IENR1. When an IECPWM interrupt is generated,
IRR1 interrupt request flag IRREC2 is set to 1. If IENEC2 in IENR1 is set to 1 at this time, an
interrupt request is sent to the CPU.
Rising, falling, or both edge detection can be selected for IECPWM interrupt sensing with bits
AIAGS1 and AIAGS0 in AEGSR.
Figure 9.10 and table 9.6 show examples of event counter PWM operation.
toff = T • (Ndr +1)
ton
tcm = T • (Ncm +1)
Legend:
ton: Clock input enable time
toff: Clock input disable time
tcm: One conversion period
ECPWM input clock cycle
T:
Ndr: Value of ECPWDRH and ECPWDRL
Fixed low when Ndr = H'FFFF
Ncm: Value of ECPWCRH and ECPWCRL
Figure 9.10 Event Counter Operation Waveform
Note: Ndr and Ncm above must be set so that Ndr < Ncm. If the settings do not satisfy this
condition, do not set ECPWME to 1 in AEGSR.
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Section 9 Timers
Table 9.6
Examples of Event Counter PWM Operation
Conditions: fosc = 4 MHz, fφ = 2 MHz, high-speed active mode, ECPWCR value (Ncm) =
H'7A11, ECPWDR value (Ndr) = H'16E3
Clock
Source
Selection
Clock
Source
ECPWMCR ECPWMDR
Cycle (T)* Value (Ncm) Value (Ndr)
toff = T •
(Ndr + 1)
tcm = T •
(Ncm + 1)
ton = tcm –
toff
φ/2
1 µs
H'7A11
H'16E3
5.86 ms
31.25 ms
25.39 ms
φ/4
2 µs
D'31249
D'5859
11.72 ms
62.5 ms
50.78 ms
φ/8
4 µs
23.44 ms
125.0 ms
101.56 ms
φ/16
8 µs
46.88 ms
250.0 ms
203.12 ms
φ/32
16 µs
93.76 ms
500.0 ms
406.24 ms
φ/64
32 µs
187.52 ms
1000.0 ms
812.48 ms
Note:
*
toff minimum width
Clock Input Enable/Disable Function Operation: The clock input to the event counter can be
controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by the event counter PWM
output, IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock
input by each signal, a maximum error of one count will occur depending on the IRQAEC or
IECPWM timing.
Figure 9.11 shows an example of the operation of this function.
Input event
IRQAEC or IECPWM
Edge generated by clock return
Actually counted clock source
Counter value
N
N+1
N+2
N+3
N+4
N+5
N+6
Clock stopped
Figure 9.11 Example of Clock Control Operation
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Section 9 Timers
9.4.5
Operating States of Asynchronous Event Counter
The operating states of the asynchronous event counter are shown in table 9.7.
Table 9.7
Operating States of Asynchronous Event Counter
Operating
Mode
Reset
Active
Sleep
Watch
Subactive
Sub-sleep Standby
AEGSR
Reset
Functions
Functions
Retained*1
Functions
Functions
Retained*1
Retained
ECCR
Reset
Functions
Functions
Retained*1
Functions
Functions
Retained*1
Retained
Functions
*1
Functions
*1
Retained
ECCSR
ECH
ECL
Reset
Reset
Reset
Functions
Functions
Functions
Retained
*1*2
*2
*2
*1*2
Halted
Halted
Functions
Functions
Functions
Functions*1*2
Functions*2 Functions*2 Functions*1*2
Functions
Retained
Reset
Functions
Functions
Event counter Reset
Functions
Functions
Retained
Functions
Retained
Functions
Retained*3
IRQAEC
Functions
Module
Standby
Functions
Functions
Retained*3
Retained*4
Retained
Retained
Retained
PWM
Notes: 1. When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
2. Functions when asynchronous external events are selected; halted and retained
otherwise.
3. Clock control by IRQAEC operates, but interrupts do not.
4. As the clock is stopped in module standby mode, IRQAEC has no effect.
9.4.6
Usage Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR in
8-bit mode and clear bit CUEL to 0 in 16-bit mode to prevent asynchronous event input to the
counter. The correct value will not be returned if the event counter increments while being
read.
2. The maximum clock frequency that may be input to the AEVH and AEVL pins is 16 MHz*1.
Furthermore, the clock high width and low width should be half or more the OSC clock cycle
time. The duty ratio does not matter as long as the high width and low width satisfy the
minimum requirement.
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Section 9 Timers
Mode
Maximum Clock Frequency
Input to AEVH/AEVL Pin
Active (high-speed), sleep (high-speed)
16 MHz*
Active (medium-speed), sleep (medium-speed)
fOSC = 1 MHz to 4 MHz
Watch, subactive, subsleep, standby
φW = 32.768 kHz or 38.4 kHz*2
1
(φ/16)
2 • fOSC
(φ/32)
fOSC
(φ/64)
1/2 • fOSC
(φ/128)
1/4 • fOSC
(φW /2)
1000 kHz
(φW /4)
500 kHz
(φW /8)
250 kHz
Notes: 1. Up to 10 MHz in the H8/38004, H8/38002S Group.
2. Does not apply to H8/38104 Group.
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to 1 first, set CRCH in ECCSR to 1
second, or set both CUEH and CRCH to 1 at same time before clock input. While AEC is
operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
4. When ECPWME in AEGSR is 1, the event counter PWM is operating and therefore
ECPWCRH, ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, the event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
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Section 9 Timers
9.5
Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
However, as shown in watchdog timer block diagrams figure 9.12 (1) and figure 9.12 (2), the
implementation differs in the H8/38004, H8/38002S Group and the H8/38104 Group.
9.5.1
Features
• Selectable from two counter input clocks (H8/38004, H8/38002S Group).
Two clock sources (φ/8192 or φW/32) can be selected as the timer-counter clock.
• On the H8/38104 Group, 10 internal clocks are available for selection. Ten internal clocks
(φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φw/32, or watchdog on-chip
oscillator) can be selected as the timer-counter clock.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
φw/32
PSS
φ/8192
Legend:
TCSRW: Timer control/status register W
TCW:
Timer counter W
PSS:
Prescaler S
TCW
Internal data bus
φ
TCSRW
Internal reset
signal
Figure 9.12(1) Block Diagram of Watchdog Timer (H8/38004, H8/38002S Group)
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Section 9 Timers
Watchdog
on-chip
oscillator
φ
Internal data bus
TMW
TCSRW
PSS
TCW
φW/32
Interrupt/reset
controller
Legend:
TCSRW:
TCW:
TMW:
PSS:
Internal reset signal or
interrupt request signal
Timer control/status register W
Timer counter W
Timer mode register W
Prescaler S
Figure 9.12(2) Block Diagram of Watchdog Timer (H8/38104 Group)
9.5.2
Register Descriptions
The watchdog timer has the following registers.
• Timer control/status register W (TCSRW)
• Timer counter W (TCW)
• Timer mode register W (TMW)*
Note: * This register is implemented on the H8/38104 Group only.
Timer Control/Status Register W (TCSRW): TCSRW performs the TCSRW and TCW write
control. TCSRW also controls the watchdog timer operation and indicates the operating state.
TCSRW must be rewritten by using the MOV instruction. The bit manipulation instruction cannot
be used to change the setting value.
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Section 9 Timers
Bit
Bit Name
Initial
Value
R/W
Description
7
B6WI
1
R
Bit 6 Write Inhibit
The TCWE bit can be written only when the write value of
the B6WI bit is 0.
6
TCWE
0
This bit is always read as 1.
1
*
R/(W) Timer Counter W Write Enable
TCW can be written when the TCWE bit is set to 1.
When writing data to this bit, the value for bit 7 must be 0.
5
B4WI
1
R
Bit 4 Write Inhibit
The TCSRWE bit can be written only when the write
value of the B4WI bit is 0. This bit is always read as 1.
4
TCSRWE
0
R/(W)*1 Timer Control/Status Register W Write Enable
The WDON and WRST bits can be written when the
TCSRWE bit is set to 1.
When writing data to this bit, the value for bit 5 must be 0.
3
B2WI
1
R
Bit 2 Write Inhibit
This bit can be written to the WDON bit only when the
write value of the B2WI bit is 0.
2
WDON
0/1*2
This bit is always read as 1.
1
*
R/(W) Watchdog Timer On
TCW starts counting up when WDON is set to 1 and halts
when WDON is cleared to 0.
[Setting condition]
When 1 is written to the WDON bit while writing 0 to the
B2WI bit when the TCSRWE bit=1
[Clearing condition]
1
B0WI
1
R
•
Reset by RES pin*3
•
When 0 is written to the WDON bit while writing 0 to
the B2WI when the TCSRWE bit=1
Bit 0 Write Inhibit
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read as
1.
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Section 9 Timers
Bit
0
Bit Name
WRST
Initial
Value
R/W
0
1
R/(W)* Watchdog Timer Reset
Description
[Setting condition]
When TCW overflows and an internal reset signal is
generated
[Clearing condition]
•
Reset by RES pin
•
When 0 is written to the WRST bit while writing 0 to
the B0WI bit when the TCSRWE bit = 1
Notes: 1. These bits can be written only when the writing conditions are satisfied.
2. Initial value 0 on H8/38004, H8/38002S Group and 1 on H8/38104 Group.
3. On reset, cleared to 0 on H8/38004, H8/38002S Group and set to 1 on H8/38104
Group.
Timer Counter W (TCW): TCW is an 8-bit readable/writable up-counter. When TCW overflows
from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRW is set to 1.
TCW is initialized to H'00.
Timer Mode Register W (TMW): TMW selects the input clock. Clock source selection using
this register is enabled when WDCKS in port mode register 2 (PMR2) is cleared to 0. If WDCKS
is set to 1, φw/32 is selected as the clock source, regardless of the setting of TMW.
Note: TMW is implemented on H8/38104 Group only.
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Section 9 Timers
Bit
Bit Name
Initial
Value
R/W
Description
7 to 4
—
All 1
—
This bit is reserved. It is always read as 1.
3
CKS3
1
R/W
Clock Select 3 to 0
2
CKS2
1
R/W
Selects the clock input to TCWD.
1
CKS1
1
R/W
0
CKS0
1
R/W
1000: Internal clock: counting on φ/64
1001: Internal clock: counting on φ/128
1010: Internal clock: counting on φ/256
1011: Internal clock: counting on φ/512
1100: Internal clock: counting on φ/1,024
1101: Internal clock: counting on φ/2,048
1110: Internal clock: counting on φ/4,096
1111: Internal clock: counting on φ/8,192
0XXX: On-chip oscillator
See section 17, Electrical Characteristics, for information
on the overflow period of the on-chip oscillator.
Legend:
X: Don't care
9.5.3
Operation
The watchdog timer is provided with an 8-bit counter. The input clock is selected by the WDCKS
bit in the port mode register 2 (PMR2)*: On the H8/38004, H8/38002S Group, φ/8192 is selected
when the WDCKS bit is cleared to 0, and φw/32 when set to 1. On the H8/38104 Group, the clock
specified by timer mode register W (TMW) is selected when WDCKS is cleared to 0, and φw/32
is selected when WDCKS is set to 1. If 1 is written to WDON while writing 0 to B2WI when the
TCSRWE bit in TCSRW is set to 1, TCW begins counting up. (To operate the watchdog timer,
two write accesses to TCSRW are required. However, on the H8/38104 Group, TCW begins
counting up even if no write access occurs, because WDON is set to 1 when the reset is cleared.)
When a clock pulse is input after the TCW count value has reached H'FF, the watchdog timer
overflows and an internal reset signal is generated. The internal reset signal is output for a period
of 512 φosc clock cycles. TCW is a writable counter, and when a value is set in TCW, the count-up
starts from that value. An overflow period in the range of 1 to 256 input clock cycles can therefore
be set, according to the TCW set value.
Note: * For details, refer to section 8.1.5, Port Mode Register 2 (PMR2).
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Section 9 Timers
Figure 9.13 shows an example of watchdog timer operation.
Example:
With 30-ms overflow period when φ = 4 MHz
4 • 106
8192
• 30 • 10–3 = 14.6
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
TCW overflow
H'FF
H'F1
TCW
count value
H'00
Start
H'F1 written
to TCW
H'F1 written to TCW
Reset generated
Internal reset
signal
512 φosc clock cycles
Figure 9.13 Example of Watchdog Timer Operation
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Section 9 Timers
9.5.4
Operating States of Watchdog Timer
Tables 9.8(1) and 9.8(2) summarize the operating states of the watchdog timer for the H8/38004,
H8/38002S Group and H8/38104 Group, respectively.
Table 9.8(1) Operating States of Watchdog Timer (H8/38004, H8/38002S Group)
Operating
Mode
Reset
Active
Sleep
Watch
TCW
Reset
Functions
Functions
Halted
Standby
Module
Standby
Halted
Halted
Halted
Retained
Retained
Retained
Sub-active Sub-sleep
Functions/
Halted*
TCSRW
Note:
Reset
*
Functions
Functions
Retained
Functions/
Halted*
Functions when φW /32 is selected as the input clock.
Table 9.8(2) Operating States of Watchdog Timer (H8/38104 Group)
Operating
Module
Mode
Reset
Active
Sleep
Watch
Sub-active
Sub-sleep
Standby
Standby
TCW
Reset
Functions
Functions
Functions/
Halted*1
Functions/
Halted*1
Functions/
Halted*1
Functions/
Halted*2
Halted
TCSRW
Reset
Functions
Functions
Functions/ Functions/
Retained*1 Halted*1
Functions/
Retained*1
Functions/
Retained*2
Retained
TMW
Reset
Functions
Functions
Functions/ Functions/
Retained*1 Halted*1
Functions/
Retained*1
Functions/
Retained*2
Retained
Notes: 1. Functions when φw/32 or the on-chip clock oscillator is selected as the internal clock.
2. Functions only when the on-chip clock oscillator is selected.
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Section 10 Serial Communication Interface 3 (SCI3)
Section 10 Serial Communication Interface 3 (SCI3)
Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous
serial communication. In the asynchronous method, serial data communication can be carried out
using standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication between processors (multiprocessor
communication function).
Figure 10.1 shows a block diagram of the SCI3.
10.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• External clock or on-chip baud rate generator can be selected as a transfer clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
Note: On the H8/38104 Group, the system clock generator must be used when carrying out this
function.
Asynchronous mode
•
•
•
•
•
Data length: 7, 8, or 5 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Receive error detection: Parity, overrun, and framing errors
Break detection: Break can be detected by reading the RXD32 pin level directly in the case of
a framing error
SCI0012A_000020020900
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Section 10 Serial Communication Interface 3 (SCI3)
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
SCK32
Internal clock (φ/64, φ/16, φw/2, φ)
External clock
Baud rate generator
BRC
BRR
SMR
Transmit/receive
control circuit
SCR3
SSR
TXD32
TSR
TDR
RSR
RDR
Internal data bus
Clock
SPCR
RXD32
Legend:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
SPCR:
Interrupt request
(TEI, TXI, RXI, ERI)
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Serial port control register
Figure 10.1 Block Diagram of SCI3
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Section 10 Serial Communication Interface 3 (SCI3)
10.2
Input/Output Pins
Table 10.1 shows the SCI3 pin configuration.
Table 10.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
SCI3 clock
SCK32
I/O
SCI3 clock input/output
SCI3 receive data input
RXD32
Input
SCI3 receive data input
SCI3 transmit data output
TXD32
Output
SCI3 transmit data output
10.3
Register Descriptions
The SCI3 has the following registers.
•
•
•
•
•
•
•
•
•
Receive shift register (RSR)
Receive data register (RDR)
Transmit shift register (TSR)
Transmit data register (TDR)
Serial mode register (SMR)
Serial control register 3 (SCR3)
Serial status register (SSR)
Bit rate register (BRR)
Serial port control register (SPCR)
10.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input from the RXD32 pin and convert it
into parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU. RDR is initialized to H'00 at a reset and in standby,
watch, or module standby mode.
10.3.3
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR automatically, then sends the data that starts from the
LSB to the TXD32 pin. Data transfer from TDR to TSR is not performed if no data has been
written to TDR (if the TDRE bit in SSR is set to 1). TSR cannot be directly accessed by the CPU.
10.3.4
Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The doublebuffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF at a reset and in standby, watch, or module standby mode.
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator
clock source. SMR is initialized to H'00 at a reset and in standby, watch, or module standby mode.
Bit
Bit Name
Initial
Value
R/W
7
COM
0
R/W
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous mode)
0: Selects 8 or 5 bits as the data length.
1: Selects 7 or 5 bits as the data length.
When 7-bit data is selected, the MSB (bit 7) in TDR is not
transmitted. To select 5 bits as the data length, set 1 to
both the PE and MP bits. The three most significant bits
(bits 7, 6, and 5) in TDR are not transmitted. In clocked
synchronous mode, the data length is fixed to 8 bits
regardless of the CHR bit setting.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data before transmission, and the parity bit is checked in
reception. In clocked synchronous mode, parity bit
addition and checking is not performed regardless of the
PE bit setting.
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Section 10 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
4
PM
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
When even parity is selected, a parity bit is added in
transmission so that the total number of 1 bits in the
transmit data plus the parity bit is an even number; in
reception, a check is carried out to confirm that the
number of 1 bits in the receive data plus the parity bit is
an even number.
When odd parity is selected, a parity bit is added in
transmission so that the total number of 1 bits in the
transmit data plus the parity bit is an odd number; in
reception, a check is carried out to confirm that the
number of 1 bits in the receive data plus the parity bit is
an odd number.
If parity bit addition and checking is disabled in clocked
synchronous mode and asynchronous mode, the PM bit
setting is invalid.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked, regardless
of the value in the bit. If the second stop bit is 0, it is
treated as the start bit of the next transmit character.
2
MP
0
R/W
Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and PM
bit settings are invalid. In clocked synchronous mode, this
bit should be cleared to 0.
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Section 10 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
1
CKS1
0
R/W
Clock Select 0 and 1
0
CKS0
0
R/W
These bits select the clock source for the on-chip baud
rate generator.
00: φ clock (n = 0)
01: φw/2 or φw clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
When the setting value is 01 in active mode and sleep
mode, φw/2 clock is set. In subactive mode and subsleep
mode, φw clock is set. The SCI3 is enabled only when φw
/2 is selected for the CPU operating clock.
For the relationship between the bit rate register setting
and the baud rate, see section 10.3.8, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 10.3.8, Bit Rate Register (BRR)).
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.6
Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. SCR3 is initialized to H'00 at a reset and in standby,
watch, or module standby mode. For details on interrupt requests, refer to section 10.7, Interrupts.
Bit
Bit Name
Initial
Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled. TXI can be released by clearing the TDRE bit or
TIE bit to 0.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled. RXI and ERI can be released by clearing bit
RDRF or the FER, PER, or OER error flag to 0, or by
clearing bit RIE to 0.
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled. When
this bit is 0, the TDRE bit in SSR is fixed at 1. When
transmit data is written to TDR while this bit is 1, bit
TDRE in SSR is cleared to 0 and serial data transmission
is started. Be sure to carry out SMR settings, and setting
of bit SPC32 in SPCR, to decide the transmission format
before setting bit TE to 1.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled. In this
state, serial data reception is started when a start bit is
detected in asynchronous mode or serial clock input is
detected in clocked synchronous mode. Be sure to carry
out the SMR settings to decide the reception format
before setting bit RE to 1.
Note that the RDRF, FER, PER, and OER flags in SSR
are not affected when bit RE is cleared to 0, and retain
their previous state.
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Section 10 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is prohibited.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 10.6, Multiprocessor
Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, the TEI interrupt request is
enabled. TEI can be released by clearing bit TDRE to 0
and clearing bit TEND to 0 in SSR, or by clearing bit TEIE
to 0.
1
CKE1
0
R/W
Clock Enable 0 and 1
0
CKE0
0
R/W
Selects the clock source.
Asynchronous mode:
00: Internal baud rate generator
01: Internal baud rate generator
Outputs a clock of the same frequency as the bit rate
from the SCK32 pin.
10: External clock
Inputs a clock with a frequency 16 times the bit rate
from the SCK32 pin.
11:Reserved
Clocked synchronous mode:
00: Internal clock (SCK32 pin functions as clock output)
01:Reserved
10: External clock (SCK32 pin functions as clock input)
11:Reserved
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. SSR is
initialized to H'84 at a reset and in standby, watch, or module standby mode.
Bit
7
Bit Name
TDRE
Initial
Value
R/W
1
R/(W)* Transmit Data Register Empty
Description
Indicates that transmit data is stored in TDR.
[Setting conditions]
•
When the TE bit in SCR3 is 0
•
When data is transferred from TDR to TSR
[Clearing conditions]
•
6
RDRF
0
When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
*
R/(W) Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading RDRF = 1
•
When data is read from RDR
If an error is detected in reception, or if the RE bit in
SCR3 has been cleared to 0, RDR and bit RDRF are not
affected and retain their previous state.
Note that if data reception is completed while bit RDRF is
still set to 1, an overrun error (OER) will occur and the
receive data will be lost.
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Section 10 Serial Communication Interface 3 (SCI3)
Bit
5
Bit Name
OER
Initial
Value
R/W
0
R/(W)* Overrun Error
Description
[Setting condition]
•
When an overrun error occurs in reception
[Clearing condition]
•
When 0 is written to OER after reading OER = 1
When bit RE in SCR3 is cleared to 0, bit OER is not
affected and retains its previous state.
When an overrun error occurs, RDR retains the receive
data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be
continued with bit OER set to 1, and in clocked
synchronous mode, transmission cannot be continued
either.
4
FER
0
R/(W)* Framing Error
[Setting condition]
•
When a framing error occurs in reception
[Clearing condition]
•
When 0 is written to FER after reading FER = 1
When bit RE in SCR3 is cleared to 0, bit FER is not
affected and retains its previous state.
Note that, in 2-stop-bit mode, only the first stop bit is
checked for a value of 1, and the second stop bit is not
checked. When a framing error occurs, the receive data
is transferred to RDR but bit RDRF is not set. Reception
cannot be continued with bit FER set to 1. In clocked
synchronous mode, neither transmission nor reception is
possible when bit FER is set to 1.
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Section 10 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
3
PER
Initial
Value
R/W
0
R/(W)* Parity Error
Description
[Setting condition]
•
When a parity error is generated during reception
[Clearing condition]
•
When 0 is written to PER after reading PER = 1
When bit RE in SCR3 is cleared to 0, bit PER is not
affected and retains its previous state.
Receive data in which a parity error has occurred is still
transferred to RDR, but bit RDRF is not set. Reception
cannot be continued with bit PER set to 1. In clocked
synchronous mode, neither transmission nor reception is
possible when bit PER is set to 1.
2
TEND
1
R
Transmit End
[Setting conditions]
•
When the TE bit in SCR3 is 0
•
When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character
[Clearing conditions]
1
MPBR
0
R
•
When 0 is written to TDRE after reading TDRE = 1
•
When the transmit data is written to TDR
Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is cleared to 0,
its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit character data.
Note:
*
Only 0 can be written for clearing a flag.
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Section 10 Serial Communication Interface 3 (SCI3)
10.3.8
Bit Rate Register (BRR)
BRR is an 8-bit readable/writable register that adjusts the bit rate. BRR is initialized to H'FF at a
reset and in standby, watch, or module standby mode. Table 10.2 shows the relationship between
the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode.
Table 10.4 shows the maximum bit rate for each frequency in asynchronous mode. The values
shown in both tables 10.2 and 10.4 are values in active (high-speed) mode. Table 10.5 shows the
relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 in SMR in
clocked synchronous mode. The values are shown in table 10.5. The N setting in BRR and error
for other operating frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N=
–1
B (bit rate obtained from n, N, φ) – R (bit rate in left-hand column in table 10.2)
R (bit rate in left-hand column in table 10.2)
Error (%) =
Legend:
φ
32 • 22n • B
B:
N:
φ:
n:
• 100
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (Hz)
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.3.)
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
φ
16.4 kHz
19.45 kHz
1 MHz
1.2288 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
—
—
—
—
—
—
2
17
–1.36
2
21
–0.83
150
—
—
—
0
3
0
2
12
0.16
3
3
0
200
—
—
—
0
2
0
2
9
–2.34
3
2
0
250
0
1
2.5
—
—
—
3
1
–2.34
0
153
–0.26
300
—
—
—
0
1
0
0
103
0.16
3
1
0
600
—
—
—
0
0
0
0
51
0.16
3
0
0
—
—
—
0
25
0.16
2
1
0
2400
0
12
0.16
2
0
0
4800
—
—
—
0
7
0
9600
—
—
—
0
3
0
19200
—
—
—
0
1
0
31250
0
0
0
—
—
—
38400
—
—
—
0
0
0
1200
Rev. 6.00 Mar 15, 2005 page 270 of 502
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
φ
2 MHz
5 MHz
8 MHz
10 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
8
–1.36
3
21
0.88
3
35
–1.36
3
43
0.88
150
2
25
0.16
3
15
1.73
3
25
0.16
3
32
–1.36
200
3
4
–2.34
3
11
1.73
3
19
–2.34
3
23
1.73
250
2
15
–2.34
3
9
–2.34
3
15
–2.34
3
19
–2.34
300
2
12
0.16
3
7
1.73
3
12
0.16
3
15
1.73
600
0
103 0.16
3
3
1.73
2
25
0.16
3
7
1.73
1200
0
51
0.16
3
1
1.73
2
12
0.16
3
3
1.73
2400
0
25
0.16
3
0
1.73
0
103
0.16
3
1
1.73
4800
0
12
0.16
2
1
1.73
0
51
0.16
3
0
1.73
9600
—
—
—
2
0
1.73
0
25
0.16
2
1
1.73
19200
—
—
—
0
7
1.73
0
12
0.16
2
0
1.73
31250
0
1
0
0
4
0
0
7
0
0
9
0
38400
—
—
—
0
3
1.73
—
—
—
0
7
1.73
Legend:
No indication: Setting not possible.
:
A setting is available but error occurs
Table 10.3 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φW /2*1/φW *2
0
1
2
φ/16
1
0
3
φ/64
1
1
Notes: 1. φW /2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode
2. φW clock in subactive mode and subsleep mode
In subactive or subsleep mode, the SCI3 can be operated when CPU clock is φW /2 only.
Rev. 6.00 Mar 15, 2005 page 271 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Table 10.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)
φ (MHz)
Maximum Bit Rate (bit/s)
n
N
0.0384*
0.0192
600
0
0
2
1
31250
0
0
2.4576
1.2288
38400
0
0
4
2
62500
0
0
10
5
156250
0
0
16
8
250000
0
0
20
10
312500
0
0
Note:
*
When CKS1 = 0 and CKS0 = 1 in SMR
Table 10.5 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1)
φ
19.2 kHz
1 MHz
2 MHz
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
200
0
23
0
—
—
—
—
—
—
250
—
—
—
—
—
—
2
124
0
300
2
0
0
—
—
—
—
—
—
500
—
—
—
—
—
—
1k
0
249
0
—
—
—
2.5k
0
99
0
0
199
0
5k
0
49
0
0
99
0
10k
0
24
0
0
49
0
25k
0
9
0
0
19
0
50k
0
4
0
0
9
0
100k
—
—
—
0
4
0
250k
0
0
0
0
1
0
0
0
0
500k
1M
Rev. 6.00 Mar 15, 2005 page 272 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Table 10.5 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)
φ
Bit Rate
(bit/s)
5 MHz
8 MHz
10 MHz
n
N
Error (%)
n
N
Error (%)
n
N
Error (%)
200
—
—
—
—
—
—
0
12499
0
250
—
—
—
3
124
0
2
624
0
300
—
—
—
—
—
—
0
8332
0
500
—
—
—
2
249
0
0
4999
0
1k
—
—
—
2
124
0
0
2499
0
2.5k
—
—
—
2
49
0
0
999
0
5k
0
249
0
2
24
0
0
499
0
10k
0
124
0
0
199
0
0
249
0
25k
0
49
0
0
79
0
0
99
0
50k
0
24
0
0
39
0
0
49
0
100k
—
—
—
0
19
0
0
24
0
250k
0
4
0
0
7
0
0
9
0
500k
—
—
—
0
3
0
0
4
0
1M
—
—
—
0
1
0
—
—
—
Legend:
Blankx: No setting is available.
—:
A setting is available but error occurs.
Note:
The value set in BRR is given by the following formula:
N=
B:
N:
φ:
n:
φ
8 • 22n • B
–1
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (Hz)
Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.6.)
Rev. 6.00 Mar 15, 2005 page 273 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Table 10.6 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φW /2 /φW
0
1
2
φ/16
1
0
3
φ/64
1
1
*1
*2
Notes: 1. φW /2 clock in active (medium-speed/high-speed) mode and sleep (medium-speed/highspeed) mode
2. φW clock in subactive mode and subsleep mode
In subactive or subsleep mode, the SCI3 can be operated when CPU clock is φW /2 only.
10.3.9
Serial Port Control Register (SPCR)
SPCR selects whether input/output data of the RXD32 and TXD32 pins is inverted or not.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 1

Reserved
These bits are always read as 1 and cannot be modified.
5
SPC32
0
R/W
P42/TXD32 Pin Function Switch
This bit selects whether pin P42/TXD32 is used as P42 or
as TXD32.
0: P42 I/O pin
1: TXD32 output pin*
Note: * Set the TE bit in SCR3 after setting this bit to 1.
4


W
Reserved
The write value should always be 0.
3
SCINV3
0
R/W
TXD32 Pin Output Data Inversion Switch
This bit selects whether or not the logic level of the
TXD32 pin output data is inverted.
0: TXD32 output data is not inverted
1: TXD32 output data is inverted
Rev. 6.00 Mar 15, 2005 page 274 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Bit
Bit Name
Initial
Value
R/W
Description
2
SCINV2
0
R/W
RXD32 Pin Input Data Inversion Switch
This bit selects whether or not the logic level of the
RXD32 pin input data is inverted.
0: RXD32 input data is not inverted
1: RXD32 input data is inverted
1, 0


W
Reserved
The write value should always be 0.
Note: When the serial port control register is modified, the data being input or output up to that
point is inverted immediately after the modification, and an invalid data change is input or
output. When modifying the serial port control register, modification must be made in a state
in which data changes are invalidated.
10.4
Operation in Asynchronous Mode
Figure 10.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). In asynchronous mode, synchronization is performed at the falling
edge of the start bit during reception. The data is sampled on the 8th pulse of a clock with a
frequency 16 times the bit period, so that the transfer data is latched at the center of each bit.
Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex. Both the
transmitter and the receiver also have a double-buffered structure, so data can be read or written
during transmission or reception, enabling continuous data transfer. Table 10.7 shows the 16 data
transfer formats that can be set in asynchronous mode. The format is selected by the settings in
SMR as shown in table 10.8.
LSB
Serial Start
data
bit
1 bit
MSB
1
Parity
bit
Transmit/receive data
5, 7, or 8 bits
1 bit,
or none
Stop bit
Mark state
1 or
2 bits
One unit of transfer data (character or frame)
Figure 10.2 Data Format in Asynchronous Communication
Rev. 6.00 Mar 15, 2005 page 275 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
10.4.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK32 pin can be selected as the SCI3’s serial clock source, according to the setting of the
COM bit in SMR and the CKE0 and CKE1 bits in SCR3. For details on selection of the clock
source, see table 10.9. When an external clock is input at the SCK32 pin, the clock frequency
should be 16 times the bit rate used. When the SCI3 is operated on an internal clock, the clock can
be output from the SCK32 pin. The frequency of the clock output in this case is equal to the bit
rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as
shown in figure 10.3.
Clock
Serial data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (frame)
Figure 10.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Rev. 6.00 Mar 15, 2005 page 276 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Table 10.7 Data Transfer Formats (Asynchronous Mode)
SMR
Serial Data Transfer Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
START
8-bit data
STOP
0
0
0
1
START
8-bit data
STOP
STOP
0
0
1
0
START
8-bit data
MPB
STOP
0
0
1
1
START
8-bit data
MPB
STOP
0
1
0
0
START
8-bit data
P
STOP
0
1
0
1
START
8-bit data
P
STOP
0
1
1
0
START
5-bit data
STOP
0
1
1
1
START
5-bit data
STOP
1
0
0
0
START
7-bit data
STOP
1
0
0
1
START
7-bit data
STOP
STOP
1
0
1
0
START
7-bit data
MPB
STOP
1
0
1
1
START
7-bit data
MPB
STOP
1
1
0
0
START
7-bit data
P
STOP
1
1
0
1
START
7-bit data
P
STOP
1
1
1
0
START
5-bit data
P
STOP
1
1
1
1
START
5-bit data
P
STOP
2
3
4
5
6
7
8
9
10
11
12
STOP
STOP
STOP
STOP
STOP
STOP
Legend:
Don't care
*:
START: Start bit
STOP: Stop bit
P:
Parity bit
MPB
Multiprocessor bit
Rev. 6.00 Mar 15, 2005 page 277 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Table 10.8 SMR Settings and Corresponding Data Transfer Formats
SMR
Data Transfer Format
Bit 7
COM
Bit 6
CHR
Bit 2
MP
Bit 5
PE
Bit 3
STOP
0
0
0
0
0
1
1
0
0
0
Mode
Data
Length
Multiprocessor
Bit
Asynchronous 8-bit data No
mode
Parity
Bit
Stop Bit
Length
No
1 bit
2 bits
Yes
1 bit
No
1 bit
1
1
2 bits
7-bit data
1
1
2 bits
Yes
0
2 bits
1
0
1
0
0
8-bit data Yes
No
1
1
0
0
0
5-bit data No
1 bit
7-bit data Yes
1 bit
2 bits
1
1
2 bits
0
5-bit data No
Yes
1
1
Legend:
*
0
*
*
1 bit
2 bits
1
1
1 bit
1 bit
2 bits
Clocked
synchronous
mode
*: Don’t care
Rev. 6.00 Mar 15, 2005 page 278 of 502
REJ09B0024-0600
8-bit data No
No
No
Section 10 Serial Communication Interface 3 (SCI3)
Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR
SCR3
Bit 7
Bit 1
Bit 0
COM
CKE1
CKE0
Mode
Clock Source
SCK32 Pin Function
0
0
0
Asynchronous
mode
Internal
I/O port (SCK32 pin not used)
1
Transmit/Receive Clock
Outputs clock with same
frequency as bit rate
1
0
External
0
0
1
0
Internal
Clocked
synchronous mode External
0
1
1
Reserved (Do not specify these combinations)
1
0
1
1
1
1
1
Inputs clock with frequency 16
times bit rate
Outputs serial clock
Inputs serial clock
Rev. 6.00 Mar 15, 2005 page 279 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
10.4.2
SCI3 Initialization
Follow the flowchart as shown in figure 10.4 to initialize the SCI3. When the TE bit is cleared to
0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of
the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization. When the external
clock is used in clocked synchronous mode, the clock must not be supplied during initialization.
[1]
Start initialization
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in clocked
synchronous mode, clock is output
immediately after CKE1, CKE0, and RE
are set to 1.
Clear TE and RE bits in SCR3 to 0
[1]
Set CKE1 and CKE0 bits in SCR3
Set data transfer format in SMR
[2]
Set value in BRR
[3]
Wait
[2]
Set the data transfer format in SMR.
[3]
Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4]
Wait at least one bit interval, then set the
TE bit or RE bit in SCR3 to 1. Setting
bits TE and RE enables the TXD32 and
RXD32 pins to be used. Also set the
RIE, TIE, TEIE, and MPIE bits,
depending on whether interrupts are
required. In asynchronous mode, the bits
are marked at transmission and idled at
reception to wait for the start bit.
No
1-bit interval elapsed?
Yes
Set SPC32 bit in SPCR to 1
Set TE and RE bits in
SCR3 to 1, and set RIE, TIE, TEIE,
and MPIE bits.
[4]
Set the clock selection in SCR3.
Be sure to clear bits RIE, TIE, TEIE, and
MPIE, and bits TE and RE, to 0.
<Initialization completion>
Figure 10.4 Sample SCI3 Initialization Flowchart
Rev. 6.00 Mar 15, 2005 page 280 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
10.4.3
Data Transmission
Figure 10.5 shows an example of operation for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1.
2.
3.
4.
5.
6.
The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.
Continuous transmission is possible because the TXI interrupt routine writes next transmit
data to TDR before transmission of the current transmit data has been completed.
The SCI3 checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
“mark state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a
TEI interrupt request is generated.
Figure 10.6 shows a sample flowchart for transmission in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
1 frame
Parity Stop Start
bit
bit bit
0/1
1
0
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
Mark
state
1
1 frame
TDRE
TEND
LSI
TXI interrupt
operation request
generated
User
processing
TDRE flag
cleared to 0
TXI interrupt request generated
TEI interrupt request
generated
Data written
to TDR
Figure 10.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Rev. 6.00 Mar 15, 2005 page 281 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Start transmission
Set SPC32 bit in SPCR to 1
[1]
Read TDRE flag in SSR
No
TDRE = 1
Yes
Write transmit data to TDR
Yes
[2]
All data transmitted?
No
[1] Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. When data is
written to TDR, the TDRE flag is
automaticaly cleared to 0.
(After the TE bit is set to 1, one
frame of 1 is output, then
transmission is possible.)
[2] To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR. When data
is written to TDR, the TDRE flag is
automaticaly cleared to 0.
[3] To output a break in serial
transmission, after setting PCR to 1
and PDR to 0, clear the TE bit in
SCR3 to 0.
Read TEND flag in SSR
No
TEND = 1
Yes
[3]
No
Break output?
Yes
Clear PDR to 0 and
set PCR to 1
Clear TE bit in SCR3 to 0
<End>
Figure 10.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
Rev. 6.00 Mar 15, 2005 page 282 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
10.4.4
Serial Data Reception
Figure 10.7 shows an example of operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1.
The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
• Parity check
The SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or
even) set in bit PM in the serial mode register (SMR).
• Stop bit check
The SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
The SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred
from RSR to RDR.
2.
3.
4.
5.
If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR.
If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and
receive data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI
interrupt request is generated.
If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the
receive data transferred to RDR before reception of the next receive data has been completed.
Rev. 6.00 Mar 15, 2005 page 283 of 502
REJ09B0024-0600
Section 10 Serial Communication Interface 3 (SCI3)
Start
bit
Serial
data
1
0
Receive
data
D0
D1
Parity Stop Start
bit
bit bit
D7
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
Mark state
(idle state)
0
1
1 frame
RDRF
FER
LSI
operation
RXI request
User
processing
RDRF
cleared to 0
0 stop bit
detected
RDR data read
ERI request in
response to
framing error
Framing error
processing
Figure 10.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Table 10.10 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.8 shows a sample
flowchart for serial data reception.
Table 10.10 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
OER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR Framing error
0
0
0
1
Transferred to RDR Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR Framing error + parity error
1
1
1
1
Lost
Note:
*
Overrun error + framing error +
parity error
The RDRF flag retains the state it had before data reception. However, note that if RDR
is read after an overrun error has occurred in a frame because reading of the receive
data in the previous frame was delayed, the RDRF flag will be cleared to 0.
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Section 10 Serial Communication Interface 3 (SCI3)
Start reception
Read OER, PER, and
FER flags in SSR
[1]
Yes
OER+PER+FER = 1
[4]
No
Error processing
(Continued on next page)
Read RDRF flag in SSR
[2]
No
RDRF = 1
Yes
Read receive data in RDR
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
[2] Read SSR and check that RDRF = 1,
then read the receive data in RDR.
The RDRF flag is cleared automatically.
[3] To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag and read
RDR.
The RDRF flag is cleared automatically.
[4] If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure
that the OER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RXD32 pin.
Yes
All data received?
(A)
[3]
No
Clear RE bit in SCR3 to 0
<End>
Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
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Section 10 Serial Communication Interface 3 (SCI3)
[4]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
Framing error processing
No
PER = 1
Yes
Parity error processing
(A)
Clear OER, PER, and
FER flags in SSR to 0
<End>
Figure 10.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (2)
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Section 10 Serial Communication Interface 3 (SCI3)
10.5
Operation in Clocked Synchronous Mode
Figure 10.9 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clocked
synchronous serial communication, data on the transmission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the
SCI3, the transmitter and receiver are independent units, enabling full-duplex communication
through the use of a common clock. Both the transmitter and the receiver also have a doublebuffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
8-bit
One unit of transfer data (character or frame)
*
*
Synchronization
clock
LSB
Bit 0
Serial data
MSB
Bit 1
Don’t care
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 10.9 Data Format in Clocked Synchronous Communication
10.5.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK32 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 and CKE1 bits in SCR3. When the SCI3 is operated on an internal clock,
the serial clock is output from the SCK32 pin. Eight serial clock pulses are output in the transfer of
one character, and when no transfer is performed the clock is fixed high.
10.5.2
SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 10.4.
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Section 10 Serial Communication Interface 3 (SCI3)
10.5.3
Serial Data Transmission
Figure 10.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In serial transmission, the SCI3 operates as described below.
1.
2.
3.
4.
5.
6.
7.
The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data
has been written to TDR, and transfers the data from TDR to TSR.
The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
this time, a transmit data empty interrupt (TXI) is generated.
8-bit data is sent from the TXD32 pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial data is transmitted sequentially from the LSB (bit 0), from the
TXD32 pin.
The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
The SCK32 pin is fixed high.
Figure 10.11 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
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Section 10 Serial Communication Interface 3 (SCI3)
Serial
clock
Serial
data
Bit 0
Bit 1
1 frame
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
TXI interrupt
LSI
operation request
generated
TDRE flag
cleared
to 0
User
processing
Data written
to TDR
TXI interrupt request generated
TEI interrupt request
generated
Figure 10.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
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Section 10 Serial Communication Interface 3 (SCI3)
Start transmission
Set SPC32 bit in SPCR to 1
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
[2]
Yes
Write transmit data to TDR
[2]
All data transmitted?
Read SSR and check that the TDRE flag is
set to 1, then write transmit data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0. When clock
output is selected and data is written to
TDR, clocks are output to start the data
transmission.
To continue serial transmission, be sure to
read 1 from the TDRE flag to confirm that
writing is possible, then write data to TDR.
When data is written to TDR, the TDRE flag
is automatically cleared to 0.
Yes
No
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR3 to 0
<End>
Figure 10.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
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Section 10 Serial Communication Interface 3 (SCI3)
10.5.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 10.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1.
2.
3.
4.
The SCI3 performs internal initialization synchronous with a synchronous clock input or
output, starts receiving data.
The SCI3 stores the received data in RSR.
If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
User
processing
RXI interrupt
request
generated
RDRF flag
cleared
to 0
RDR data read
RXI interrupt request generated
RDR data has
not been read
(RDRF = 1)
ERI interrupt request
generated by
overrun error
Overrun error
processing
Figure 10.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 10.13 shows a sample flowchart
for serial data reception.
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Section 10 Serial Communication Interface 3 (SCI3)
Start reception
[1]
[1]
Read OER flag in SSR
[2]
Yes
OER = 1
[4]
No
Error processing
[3]
(Continued below)
Read RDRF flag in SSR
[2]
[4]
No
RDRF = 1
Yes
Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.
Read receive data in RDR
Yes
All data received?
[3]
No
Clear RE bit in SCR3 to 0
<End>
[4]
Error processing
Overrun error processing
Clear OER flag in SSR to 0
<End>
Figure 10.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
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Section 10 Serial Communication Interface 3 (SCI3)
10.5.5
Simultaneous Serial Data Transmission and Reception
Figure 10.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mode, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
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Section 10 Serial Communication Interface 3 (SCI3)
Start transmission/reception
Set SPC32 bit in SPCR to 1
Read TDRE flag in SSR
[1]
[1]
No
TDRE = 1
Yes
Write transmit data to TDR
Read OER flag in SSR
OER = 1
No
Read RDRF flag in SSR
Yes
[4]
Error processing
[2]
No
RDRF = 1
Yes
Read receive data in RDR
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR.
When data is written to TDR, the
TDRE flag is automatically cleared to
0. When data is read from RDR, the
RDRF flag is automatically cleared to
0.
[4] If an overrun error occurs, read the
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 10.13.
Yes
All data received?
[3]
No
Clear TE and RE bits in SCR to 0
<End>
Figure 10.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)
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Section 10 Serial Communication Interface 3 (SCI3)
10.6
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 10.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code of
the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is
set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
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Section 10 Serial Communication Interface 3 (SCI3)
Transmitting
station
Serial transmission line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'AA
H'01
(MPB = 1)
(MPB = 0)
ID transmission cycle = Data transmission cycle =
receiving station
Data transmission to
specification
receiving station specified by ID
Legend:
MPB: Multiprocessor bit
Figure 10.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H’AA to Receiving Station A)
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Section 10 Serial Communication Interface 3 (SCI3)
10.6.1
Multiprocessor Serial Data Transmission
Figure 10.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
Start transmission
Set SPC32 bit in SPCR to 1
[1]
[1]
Read TDRE flag in SSR
No
TDRE = 1
[2]
Yes
Set MPBT bit in SSR
[3]
Write transmit data to TDR
Yes
[2]
Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.
All data transmitted?
No
Read TEND flag in SSR
No
TEND = 1
Yes
No
[3]
Break output?
Yes
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0
<End>
Figure 10.16 Sample Multiprocessor Serial Transmission Flowchart
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Section 10 Serial Communication Interface 3 (SCI3)
10.6.2
Multiprocessor Serial Data Reception
Figure 10.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure
10.18 shows an example of SCI3 operation for multiprocessor format reception.
Start reception
[1]
[2]
Set MPIE bit in SCR3 to 1
[1]
Read OER and FER flags in SSR
[2]
[3]
Yes
FER+OER = 1
No
Read RDRF flag in SSR
[3]
No
[4]
[5]
RDRF = 1
Yes
Read receive data in RDR
No
This station’s ID?
Set the MPIE bit in SCR3 to 1.
Read OER and FER in SSR to check for
errors. Receive error processing is performed
in cases where a receive error occurs.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and compare it with this station’s ID.
If the data is not this station’s ID, set the MPIE
bit to 1 again.
When data is read from RDR, the RDRF flag
is automatically cleared to 0.
Read SSR and check that the RDRF flag is
set to 1, then read the data in RDR.
If a receive error occurs, read the OER and
FER flags in SSR to identify the error. After
performing the appropriate error processing,
ensure that the OER and FER flags are all
cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break can be
detected by reading the RXD32 pin value.
Yes
Read OER and FER flags in SSR
Yes
FER+OER = 1
No
Read RDRF flag in SSR
[4]
No
RDRF = 1
[5]
Error processing
Yes
Read receive data in RDR
Yes
(Continued on
next page)
All data received?
No
[A]
Clear RE bit in SCR3 to 0
<End>
Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 10 Serial Communication Interface 3 (SCI3)
[5]
Error processing
No
OER = 1
Yes
Overrun error processing
No
FER = 1
Yes
Yes
Break?
No
[A]
Framing error processing
Clear OER, and
FER flags in SSR to 0
<End>
Figure 10.17 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 10 Serial Communication Interface 3 (SCI3)
Start
bit
Serial
data
1
0
Receive
data (ID1)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data1)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
RDRF flag
cleared
to 0
RXI interrupt
request
MPIE cleared
to 0
User
processing
RXI interrupt request
is not generated, and
RDR retains its state
RDR data read
When data is not
this station's ID,
MPIE is set to 1
again
(a) When data does not match this receiver's ID
Start
bit
Serial
data
1
0
Receive
data (ID2)
D0
D1
D7
MPB
1
Stop Start
bit bit
1
0
Receive data
(Data2)
D0
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
1 frame
MPIE
RDRF
RDR
value
LSI
operation
User
processing
ID1
ID2
RXI interrupt
request
MPIE cleared
to 0
RDRF flag
cleared
to 0
RDR data read
Data2
RXI interrupt
request
When data is
this station's
ID, reception
is continued
RDRF flag
cleared
to 0
RDR data read
MPIE set to 1
again
(b) When data matches this receiver's ID
Figure 10.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 10 Serial Communication Interface 3 (SCI3)
10.7
Interrupts
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty,
receive data full, and receive errors (overrun error, framing error, and parity error). Table 10.11
shows the interrupt sources.
Table 10.11 SCI3 Interrupt Requests
Interrupt Requests
Abbreviation
Interrupt Sources
Enable Bit
Receive Data Full
RXI
Setting RDRF in SSR
RIE
Transmit Data Empty
TXI
Setting TDRE in SSR
TIE
Transmission End
TEI
Setting TEND in SSR
TEIE
Receive Error
ERI
Setting OER, FER, or PER in SSR
RIE
Each interrupt request can be enabled or disabled by means of bits TIE, RIE and TEIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit data to TDR, a TXI interrupt request is generated even if the transmit data
is not ready. The initial value of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sent. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To prevent the
generation of these interrupt requests (TXI and TEI), set the enable bits (TIE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
For further details, see section 3, Exception Handling.
The SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.12.
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Section 10 Serial Communication Interface 3 (SCI3)
Table 10.12 Transmit/Receive Interrupts
Interrupt
Flag and
Enable
Bit
Interrupt Request Conditions
RXI
RDRF
TXI
TDRE
TIE
TEI
TEND
TEIE
When serial reception is performed
normally and receive data is
transferred from RSR to RDR, bit
RDRF is set to 1, and if bit RIE is set
to 1 at this time, RXI is enabled and an
interrupt is requested. (See figure
10.19(a).)
The RXI interrupt routine reads the
receive data transferred to RDR
and clears bit RDRF to 0.
Continuous reception can be
performed by repeating the above
operations until reception of the
next RSR data is completed.
When TSR is found to be empty (on
completion of the previous
transmission) and the transmit data
placed in TDR is transferred to TSR,
bit TDRE is set to 1. If bit TIE is set to
1 at this time, TXI is enabled and an
interrupt is requested. (See figure
10.19(b).)
The TXI interrupt routine writes the
next transmit data to TDR and
clears bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations
until the data transferred to TSR
has been transmitted.
When the last bit of the character in
TSR is transmitted, if bit TDRE is set
to 1, bit TEND is set to 1. If bit TEIE is
set to 1 at this time, TEI is enabled
and an interrupt is requested. (See
figure 10.19(c).)
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is transmitted.
RDR
RDR
RSR↑ (reception completed, transfer)
RSR (reception in progress)
RXD32 pin
RXD32 pin
RDRF = 0
RDRF
→
RIE
Notes
1
(RXI request when RIE = 1)
Figure 10.19(a) RDRF Setting and RXI Interrupt
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Section 10 Serial Communication Interface 3 (SCI3)
TDR (next transmit data)
TDR
TSR (transmission in progress)
↓
TSR (transmission completed, transfer)
TXD32 pin
TXD32 pin
TDRE
→
TDRE = 0
1
(TXI request when TIE = 1)
Figure 10.19(b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmission in progress)
TSR (transmission completed)
TXD32 pin
TXD32 pin
TEND
→
TEND = 0
1
(TEI request when TEIE = 1)
Figure 10.19(c) TEND Setting and TEI Interrupt
10.8
10.8.1
Usage Notes
Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RXD32 pin
value directly. In a break, the input from the RXD32 pin becomes all 0, setting the FER flag, and
possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a
break, even if the FER flag is cleared to 0, it will be set to 1 again.
10.8.2
Mark State and Break Sending
When TE is 0, the TXD32 pin is used as an I/O port whose direction (input or output) and level
are determined by PCR and PDR. This can be used to set the TXD32 pin to mark state (high level)
or send a break during serial data transmission. To maintain the communication line at mark state
until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TXD32 pin
becomes an I/O port, and 1 is output from the TXD32 pin. To send a break during serial
transmission, first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the
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Section 10 Serial Communication Interface 3 (SCI3)
transmitter is initialized regardless of the current transmission state, the TXD32 pin becomes an
I/O port, and 0 is output from the TXD32 pin.
10.8.3
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
10.8.4
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 10.20.
Thus, the reception margin in asynchronous mode is given by formula (1) below.


1
D – 0.5
M = (0.5 –
)–
– (L – 0.5) F • 100(%)
2N
N


... Formula (1)
Where N
D
L
F
: Ratio of bit rate to clock (N = 16)
: Clock duty (D = 0.5 to 1.0)
: Frame length (L = 9 to 12)
: Absolute value of clock rate deviation
Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 • 16)} • 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed for in
system design.
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Section 10 Serial Communication Interface 3 (SCI3)
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal basic
clock
Receive data
(RXD32)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10.20 Receive Data Sampling Timing in Asynchronous Mode
10.8.5
Note on Switching SCK32 Function
If pin SCK32 is used as a clock output pin by the SCI3 in clocked synchronous mode and is then
switched to a general input/output pin (a pin with a different function), the pin outputs a low level
signal for half a system clock (φ) cycle immediately after it is switched.
This can be prevented by either of the following methods according to the situation.
When an SCK32 function is switched from clock output to non clock-output
When stopping data transfer, issue one instruction to clear bits TE and RE to 0 and to set bits
CKE1 and CKE0 in SCR3 to 1 and 0, respectively.
In this case, bit COM in SMR should be left 1. The above prevents SCK32 from being used as
a general input/output pin. To avoid an intermediate level of voltage from being applied to
SCK32, the line connected to SCK32 should be pulled up to the VCC level via a resistor, or
supplied with output from an external device.
b. When an SCK32 function is switched from clock output to general input/output
When stopping data transfer,
(i) Issue one instruction to clear bits TE and RE to 0 and to set bits CKE1 and CKE0 in
SCR3 to 1 and 0, respectively.
(ii) Clear bit COM in SMR to 0
(iii) Clear bits CKE1 and CKE0 in SCR3 to 0
Note that special care is also needed here to avoid an intermediate level of voltage from being
applied to SCK32.
a.
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Section 10 Serial Communication Interface 3 (SCI3)
10.8.6
Relation between Writing to TDR and Bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When the SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost if it has not yet
been transferred to TSR. Accordingly, to ensure that serial transmission is performed dependably,
you should first check that bit TDRE is set to 1, then write the transmit data to TDR only once (not
two or more times).
10.8.7
Relation between RDR Reading and bit RDRF
In a receive operation, the SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0
when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if RDR is
read more than once, the second and subsequent read operations will be performed while bit
RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to 0,
if the read operation coincides with completion of reception of a frame, the next frame of data may
be read. This is shown in figure 10.21.
Communication line
Frame 1
Frame 2
Frame 3
Data 1
Data 2
Data 3
Data 1
Data 2
RDRF
RDR
(A)
RDR read
(B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 10.21 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
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Section 10 Serial Communication Interface 3 (SCI3)
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To be
precise in terms of timing, the RDR read should be completed before bit 7 is transferred in clocked
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
10.8.8
Transmit and Receive Operations when Making State Transition
Make sure that transmit and receive operations have completely finished before carrying out state
transition processing.
10.8.9
Setting in Subactive or Subsleep Mode
In subactive or subsleep mode, the SCI3 can operate only when the CPU clock is φW/2. The SA1
bit in SYSCR2 should be set to 1.
10.8.10 Oscillator Use with Serial Communication Interface 3 in Asynchronous Mode
(H8/38104 Group Only)
When implementing serial communication interface 3 in asynchronous mode on the H8/38104
Group, the system clock oscillator must be used. The on-chip oscillator should not be used in this
case. See section 4.3.4, On-Chip Oscillator Selection Method, for information on switching
between the system clock oscillator and the on-chip oscillator.
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Section 10 Serial Communication Interface 3 (SCI3)
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Section 11 10-Bit PWM
Section 11 10-Bit PWM
This LSI has a two-channel 10-bit PWM. The PWM with a low-path filter connected can be used
as a D/A converter. Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/3802
Group, H8/38004 Group and H8/38002S Group. Figure 11.1(2) shows a block diagram of the 10bit PWM of the H8/38104 Group.
11.1
Features
• Choice of four conversion periods
A conversion period of 4096/φ with a minimum modulation width of 4/φ, a conversion period
of 2048/φ with a minimum modulation width of 2/φ, a conversion period of 1024/φ with a
minimum modulation width of 1/φ, or a conversion period of 512/φ with a minimum
modulation width of 1/2φ can be selected.
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
• On the H8/38104 Group it is possible to select between two types of PWM output: pulsedivision 10-bit PWM and event counter PWM (PWM incorporating AEC). (The H8/3802
Group, H8/38004 Group and H8/38002S Group can only produce 10-bit PWM output.) Refer
to section 9.4, Asynchronous Event Counter, for information on event counter PWM.
PWM1000A_000020020900
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Section 11 10-Bit PWM
PWDRL
PWDRU
φ
φ/8
φ/4
φ/2
PWM waveform
generator
Legend:
PWCR:
PWDRL:
PWDRU:
PWM:
Internal data bus
PWCR
PWM
PWM control register
PWM data register L
PWM data register U
PWM output pin
Figure 11.1(1) Block Diagram of 10-Bit PWM
(H8/3802 Group, H8/38004 Group, H8/38002S Group)
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Section 11 10-Bit PWM
PWDRL
PWDRU
φ
φ/8
φ/4
φ/2
Internal data bus
PWCR
PWM waveform
generator
PWM
(IECPWM)
IECPWM
Legend:
PWCR:
PWDRL:
PWDRU:
PWM:
IECPWM:
PWM control register
PWM data register L
PWM data register U
PWM output pin
Event counter PWM (PWM incorporating AEC)
Figure 11.1(2) Block Diagram of 10-Bit PWM (H8/38104 Group)
11.2
Input/Output Pins
Table 11.1 shows the 10-bit PWM pin configuration.
Table 11.1 Pin Configuration
Name
Abbreviation
I/O
Function
10-bit PWM square-wave
output 1
PWM1
Output
Channel 1: 10-bit PWM waveform
output pin/event counter PWM output
pin*
10-bit PWM square-wave
output 2
PWM2
Output
Channel 2: 10-bit PWM waveform
output pin/event counter PWM output
pin*
Note: * The event counter PWM output pin is valid on the H8/38104 Group only.
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Section 11 10-Bit PWM
11.3
Register Descriptions
The 10-bit PWM has the following registers.
• PWM control register (PWCR)
• PWM data register U (PWDRU)
• PWM data register L (PWDRL)
11.3.1
PWM Control Register (PWCR)
On the H8/3802 Group, H8/38004 Group and H8/38002S Group, PWCR selects the conversion
period.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
6

1

5

1

These bits are always read as 1, and cannot be
modified.
4

1

3

1

2

1

1
PWCR1
0
W
Clock Select 1, 0
0
PWCR0
0
W
00: The input clock is φ (tφ = 1/φ)
 The conversion period is 512/φ, with a minimum
modulation width of 1/2φ
01: The input clock is φ/2 (tφ = 2/φ)
 The conversion period is 1024/φ, with a
minimum modulation width of 1/φ
10: The input clock is φ/4 (tφ = 4/φ)
 The conversion period is 2048/φ, with a
minimum modulation width of 2/φ
11: The input clock is φ/8 (tφ = 8/φ)
 The conversion period is 4096/φ, with a
minimum modulation width of 4/φ
Legend: tφ: Period of PWM clock input
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Section 11 10-Bit PWM
Selects the PWCR output format and the conversion period on the H8/38104 Group.
Bit
Bit Name
Initial
Value
R/W
Description
7

1

Reserved
6

1

5

1

This bit is reserved. It is always read as 1 and cannot
be written to.
4

1

3

1

2
PWCR2
0
W
Output Format Select
0: 10-bit PWM
1: Event counter PWM (PWM incorporating AEC)
1
PWCR1
0
W
Clock Select 1, 0
0
PWCR0
0
W
00: The input clock is φ (tφ = 1/φ)
— The conversion period is 512/φ, with a minimum
modulation width of 1/2φ
01: The input clock is φ/2 (tφ = 2/φ)
— The conversion period is 1,024/φ, with a
minimum modulation width of 1/φ
10: The input clock is φ/4 (tφ = 4/φ)
— The conversion period is 2,048/φ, with a
minimum modulation width of 2/φ
11: The input clock is φ/8 (tφ = 8/φ)
— The conversion period is 4,096/φ, with a
minimum modulation width of 4/φ
Legend: tφ: Period of PWM clock input
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Section 11 10-Bit PWM
11.3.2
PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and
PWDRL are 10-bit write-only registers, with the upper 2 bits assigned to PWDRU and the lower 8
bits to PWDRL. When read, all bits are always read as 1.
Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed
if word access is performed. When 10-bit data is written in PWDRU and PWDRL, the contents
are latched in the PWM waveform generator and the PWM waveform generation data is updated.
When writing the 10-bit data, the order is as follows: PWDRL to PWDRU.
PWDRU and PWDRL are initialized to H'FC00.
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Section 11 10-Bit PWM
11.4
Operation
11.4.1
Operation
When using the 10-bit PWM, set the registers in this sequence:
1. Set the PWM2 and/or PWM1 bits in port mode register 9 (PMR9) to 1 to set the P91/PWM2
pin or P90/PWM1 pin, or both, to function as PWM output pins.
2. Set the PWCR0 and PWCR1 bits in PWCR to select a conversion period of either. On the
H8/38104 Group, the output format is selected using the PWCR2 bit. Refer to section 9.4,
Asynchronous Event Counter, for information on how to select event counter PWM (PWM
incorporating AEC), one of the two available output formats.
3. Set the output waveform data in PWDRU and PWDRL. Be sure to write byte data first to
PWDRL and then to PWDRU. When the data is written in PWDRU, the contents of these
registers are latched in the PWM waveform generator, and the PWM waveform generation
data is updated in synchronization with internal signals.
One conversion period consists of four pulses, as shown in figure 11.2. The total high-level width
during this period (TH) corresponds to the data in PWDRU and PWDRL. This relation can be
expressed as follows:
TH = (data value in PWDRU and PWDRL + 4) • tφ/2
where tφ is the period of PWM clock input: 1/φ (PWCR1 = 0, PWCR0 = 0), 2/φ (PWCR1 = 0,
PWCR0 = 1), 4/φ (PWCR1 = 1, PWCR0 = 0), or 8/φ (PWCR1 = 1, PWCR0 = 1).
If the data value in PWDRU and PWDRL is from H'FFFC to H'FFFF, the PWM output stays high.
When the data value is H'FC3C, TH is calculated as follows:
TH = 64 • tφ/2 = 32 • tφ
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Section 11 10-Bit PWM
One conversion period
tf2
tf3
tf1
tH1
tH2
tH3
tf4
tH4
TH = tH1 + tH2 + tH3 + tH4
tf1 = tf2 = tf3 = tf4
Figure 11.2 Waveform Output by 10-Bit PWM
11.4.2
PWM Operating States
Table 11.2 shows the PWM operating states.
Table 11.2 PWM Operating States
Operating
Mode
Reset
Active
Sleep
Watch
Sub-active Sub-sleep
Standby
Module
Standby
PWCR
Reset
Functions
Functions
Retained
Retained
Retained
Retained
Retained
PWDRU
Reset
Functions
Functions
Retained
Retained
Retained
Retained
Retained
PWDRL
Reset
Functions
Functions
Retained
Retained
Retained
Retained
Retained
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Section 12 A/D Converter
Section 12 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to four
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
12.1.
12.1
Features
• 10-bit resolution
• Four input channels
• Conversion time: at least 12.4 µs per channel (φ = 5 MHz operation)/6.2 µs (φ = 10 MHz
operation)*
• Sample and hold function
• Conversion start method
 Software
• Interrupt request
 An A/D conversion end interrupt request (ADI) can be generated
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
Note: * H8/38104 Group only.
ADCMS3AA_000020020900
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Section 12 A/D Converter
AMR
ADSR
AN0
Multiplexer
Internal data bus
AN1
AN2
AN3
AVCC
+
Comparator
Control logic
-
AVCC
AVSS
Reference
voltage
ADRRH
ADRRL
AVSS
IRRAD
Legend:
AMR:
A/D mode register
ADSR:
A/D start register
ADRRH, L: A/D result registers H and L
IRRAD:
A/D conversion end interrupt request flag
Figure 12.1 Block Diagram of A/D Converter
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Section 12 A/D Converter
12.2
Input/Output Pins
Table 12.1 shows the input pins used by the A/D converter.
Table 12.1 Pin Configuration
Pin Name
Abbreviation
I/O
Function
Analog power supply pin
AVcc
Input
Analog ground pin
AVss
Input
Analog input pin 0
Analog input pin 1
Analog input pin 2
Analog input pin 3
AN0
AN1
AN2
AN3
Input
Input
Input
Input
Power supply and reference voltage of
analog part
Ground and reference voltage of analog
part
Analog input pins
12.3
Register Descriptions
The A/D converter has the following registers.
• A/D result registers H and L (ADRRH and ADRRL)
• A/D mode register (AMR)
• A/D start register (ADSR)
12.3.1
A/D Result Registers H and L (ADRRH and ADRRL)
ADRRH and ADRRL are 16-bit read-only registers that store the results of A/D conversion.
The upper 8 bits of the data are stored in ADRRH, and the lower 2 bits in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are undefined. After A/D conversion is completed, the conversion result is
stored as 10-bit data, and this data is retained until the next conversion operation starts.
The initial values of ADRRH and ADRRL are undefined.
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Section 12 A/D Converter
12.3.2
A/D Mode Register (AMR)
AMR sets the A/D conversion time and analog input pins.
Bit
Bit Name
Initial
Value
R/W
Description
7
CKS
0
R/W
Clock Select
Sets the A/D conversion time.
0: Conversion time = 62 states
1: Conversion time = 31 states
6

0
R/W
Reserved
Only 0 can be written to this bit.
5

1

Reserved
4

1

These bits are always read as 1 and cannot be modified.
3
CH3
0
R/W
Channel Select 3 to 0
2
CH2
0
R/W
Selects the analog input channel.
1
CH1
0
R/W
00XX: No channel selected
0
CH0
0
R/W
0100: AN0
0101: AN1
0110: AN2
0111: AN3
1XXX: Using prohibited
The channel selection should be made while the ADSF bit
is cleared to 0.
Legend: X: Don't care.
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Section 12 A/D Converter
12.3.3
A/D Start Register (ADSR)
ADSR starts and stops the A/D conversion.
Bit
Bit Name
Initial
Value
R/W
Description
7
ADSF
0
R/W
When this bit is set to 1, A/D conversion is started. When
conversion is completed, the converted data is set in
ADRRH and ADRRL and at the same time this bit is
cleared to 0. If this bit is written to 0, A/D conversion can
be forcibly terminated.
6 to 0

All 1

Reserved
These bits are always read as 1 and cannot be modified.
12.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. When changing
the conversion time or analog input channel, in order to prevent incorrect operation, first clear the
bit ADSF to 0 in ADSR.
12.4.1
1.
2.
3.
4.
A/D Conversion
A/D conversion is started from the selected channel when the ADSF bit in ADSR is set to 1,
according to software.
When A/D conversion is completed, the result is transferred to the A/D result register.
On completion of conversion, the IRRAD flag in IRR2 is set to 1. If the IENAD bit in IENR2
is set to 1 at this time, an A/D conversion end interrupt request is generated.
The ADSF bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADSF
bit is automatically cleared to 0 and the A/D converter enters the wait state.
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Section 12 A/D Converter
12.4.2
Operating States of A/D Converter
Table 12.2 shows the operating states of the A/D converter.
Table 12.2 Operating States of A/D Converter
Operating
Mode
Reset
Active
Sleep
Watch
Sub-active Sub-sleep Standby
Module
Standby
AMR
Reset
Functions
Functions
Retained
Retained
Retained
Retained
Retained
ADSR
Reset
Functions
Functions
Reset
Reset
Reset
Reset
Reset
ADRRH
Retained*
Functions
Functions
Retained
Retained
Retained
Retained
Retained
ADRRL
Retained*
Functions
Functions
Retained
Retained
Retained
Retained
Retained
Note:
12.5
*
Undefined in a power-on reset.
Example of Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.2 shows the operation timing.
1.
2.
3.
4.
5.
6.
Bits CH3 to CH0 in the A/D mode register (AMR) are set to 0101, making pin AN1 the
analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D
conversion is started by setting bit ADSF to 1.
When A/D conversion is completed, bit IRRAD is set to 1, and the A/D conversion result is
stored in ADRRH and ADRRL. At the same time bit ADSF is cleared to 0, and the A/D
converter goes to the idle state.
Bit IENAD = 1, so an A/D conversion end interrupt is requested.
The A/D interrupt handling routine starts.
The A/D conversion result is read and processed.
The A/D interrupt handling routine ends.
If bit ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.3 and 12.4 show flowcharts of procedures for using the A/D converter.
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Idle
A/D conversion starts
Note: * ↓ indicates instruction execution by software.
ADRRH
ADRRL
Channel 1 (AN1)
operating state
ADSF
IENAD
Interrupt (IRRAD)
A/D conversion (1)
Set*
Set*
A/D conversion result (1)
↓ Read conversion result
Idle
A/D conversion (2)
Set*
↓ Read conversion result
A/D conversion result (2)
Idle
Section 12 A/D Converter
Figure 12.2 Example of A/D Conversion Operation
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Section 12 A/D Converter
Start
Set A/D conversion speed and input channel
Disable A/D conversion end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRRH/ADRRL data
Yes
Perform A/D conversion?
No
End
Figure 12.3 Flowchart of Procedure for Using A/D Converter (Polling by Software)
Start
Set A/D conversion speed and input channel
Enable A/D conversion end interrupt
Start A/D conversion
Yes
A/D conversion end
interrupt generated?
No
Clear IRRAD bit in IRR2 to 0
Read ADRRH/ADRRL data
Yes
Perform A/D conversion?
No
End
Figure 12.4 Flowchart of Procedure for Using A/D Converter (Interrupts Used)
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Section 12 A/D Converter
12.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.5).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value 0000000000 to 0000000001
(see figure 12.6).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 12.6).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristics between zero voltage and
full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error.
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Section 12 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
8
2
8
3
8
4
8
5
8
6
8
7 FS
8
Analog
input voltage
Figure 12.5 A/D Conversion Accuracy Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 12.6 A/D Conversion Accuracy Definitions (2)
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Section 12 A/D Converter
12.7
12.7.1
Usage Notes
Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 10 kΩ or less. This specification is provided to enable
the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling
time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not
be possible to guarantee A/D conversion accuracy.
As a countermeasure, a large capacitance can be provided externally to the analog input pin. This
will cause the actual input resistance to comprise only the internal input resistance of 10 kΩ,
allowing the signal source impedance to be ignored. This countermeasure has the disadvantage of
creating a low-pass filter from the signal source impedance and capacitance, with the result that it
may not be possible to follow analog signals having a large differential coefficient (e.g., 5 mV/µs
or greater) (see figure 12.7). When converting a high-speed analog signal, a low-impedance buffer
should be inserted.
12.7.2
Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI
Sensor output
impedance
to 10 kΩ
A/D converter
equivalent circuit
10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
20 pF
Figure 12.7 Example of Analog Input Circuit
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Section 12 A/D Converter
12.7.3
1.
2.
3.
4.
Additional Usage Notes
ADRRH and ADRRL should be read only when the ADSF bit in ADSR is cleared to 0.
Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
When A/D conversion is started after clearing module standby mode, wait for 10φ clock
cycles before starting A/D conversion.
In active mode and sleep mode, the analog power supply current flows in the ladder resistance
even when the A/D converter is on standby. Therefore, if the A/D converter is not used, it is
recommended that AVcc be connected to the system power supply and the ADCKSTP bit be
cleared to 0 in CKSTPR1.
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Section 13 LCD Controller/Driver
Section 13 LCD Controller/Driver
This LSI has an on-chip segment-type LCD control circuit, LCD driver, and power supply circuit,
enabling it to directly drive an LCD panel.
13.1
Features
• Display capacity
Duty Cycle
Internal Driver
Static
25 SEG
1/2
25 SEG
1/3
25 SEG
1/4
25 SEG
• LCD RAM capacity
8 bits × 13 bytes (104 bits)
• Word access to LCD RAM
• The segment output pins can be used as ports.
SEG24 to SEG1 pins can be used as ports in groups of four.
• Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection).
With 1/2 duty, parallel connection of COM1 to COM2, and of COM3 to COM4, can be used
In static mode, parallel connection of COM1 to COM2, COM3, and COM4 can be used
• Choice of 11 frame frequencies
• A or B waveform selectable by software
• On-chip power supply split-resistance
Removal of split-resistance can be controlled in software. Note that this capability is
implemented in the H8/38104 Group only.
• Display possible in operating modes other than standby mode
• Use of module standby mode enables this module to be placed in standby mode independently
when not used. (For details, refer to section 5.4, Module Standby Function.)
LCDSG02A_000020020900
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Section 13 LCD Controller/Driver
Figures 13.1(1) and 13.1(2) show a block diagram of the LCD controller/driver.
Vcc
LCD drive
power supply
V1
V2
V3
Vss
φ/2 to φ/256
Common
data latch
Internal data bus
φw
Common
driver
COM1
COM4
SEG25
SEG24
SEG23
SEG22
SEG21
LPCR
LCR
LCR2
25-bit
shift
register
Display timing generator
Segment
driver
LCD RAM
13 bytes
SEG1
SEGn
Legend:
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Figure 13.1(1) Block Diagram of LCD Controller/Driver
(H8/3802 Group, H8/38004 Group, H8/38002S Group)
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Section 13 LCD Controller/Driver
Vcc
V1
LCD drive
power supply
V2
V3
Vss
φ/2 to φ/256
Common
data latch
Internal data bus
φw
Common
driver
COM1
COM4
SEG25
SEG24
SEG23
SEG22
SEG21
LPCR
LCR
LCR2
25-bit
shift
register
Display timing generator
Segment
driver
LCD RAM
13 bytes
SEG1
SEGn
Legend:
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Figure 13.1(2) Block Diagram of LCD Controller/Driver
(H8/38104 Group)
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Section 13 LCD Controller/Driver
13.2
Input/Output Pins
Table 13.1 shows the LCD controller/driver pin configuration.
Table 13.1 Pin Configuration
Name
Abbreviation
I/O
Function
Segment output
pins
SEG25 to SEG1
Output
LCD segment drive pins
Common output
pins
COM4 to COM1
LCD power supply
pins
V1, V2, V3
All pins are multiplexed as port pins (setting
programmable)
Output
LCD common drive pins
Pins can be used in parallel with static or
1/2 duty
—
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Used when a bypass capacitor is connected
externally, and when an external power supply
circuit is used
Section 13 LCD Controller/Driver
13.3
Register Descriptions
The LCD controller/driver has the following registers.
•
•
•
•
LCD port control register (LPCR)
LCD control register (LCR)
LCD control register 2 (LCR2)
LCD RAM
13.3.1
LCD Port Control Register (LPCR)
LPCR selects the duty cycle, LCD driver, and pin functions.
Bit
Bit Name
Initial
Value
R/W
Description
7
DTS1
0
R/W
Duty Cycle Select 1 and 0
6
DTS0
0
R/W
Common Function Select
5
CMX
0
R/W
The combination of DTS1 and DTS0 selects static, 1/2,
1/3, or 1/4 duty.
CMX specifies whether or not the same waveform is to be
output from multiple pins to increase the common drive
power when not all common pins are used because of the
duty setting.
For details, see table 13.2.
4
—
—
W
Reserved
Only 0 can be written to this bit.
3
SGS3
0
R/W
Segment Driver Select 3 to 0
2
SGS2
0
R/W
Select the segment drivers to be used.
1
SGS1
0
R/W
For details, see table 13.3.
0
SGS0
0
R/W
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Section 13 LCD Controller/Driver
Table 13.2 Duty Cycle and Common Function Selection
Bit 7:
DTS1
Bit 6:
DTS0
Bit 5:
CMX
Duty Cycle
Common Drivers Notes
0
0
0
Static
COM1
Do not use COM4, COM3, and COM2
COM4 to COM1
COM4, COM3, and COM2 output the
same waveform as COM1
COM2 to COM1
Do not use COM4 and COM3
COM4 to COM1
COM4 outputs the same waveform as
COM3, and COM2 outputs the same
waveform as COM1
COM3 to COM1
Do not use COM4
COM4 to COM1
Do not use COM4
COM4 to COM1
—
1
1
0
1/2 duty
1
1
0
0
1/3 duty
1
1
X
1/4 duty
Legend:
X:
Don’t care
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Section 13 LCD Controller/Driver
Table 13.3 Segment Driver Selection
Function of Pins SEG25 to SEG1
Bit 3: Bit 2: Bit 1: Bit 0:
SGS3 SGS2 SGS1 SGS0
SEG25
SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to
SEG21
SEG17
SEG13
SEG9
SEG5
SEG4 to
SEG1
0
0
Port
Port
Port
Port
Port
Port
Port
1
Port
Port
Port
Port
Port
Port
SEG
0
Port
Port
Port
Port
Port
SEG
SEG
1
Port
Port
Port
Port
SEG
SEG
SEG
0
Port
Port
Port
SEG
SEG
SEG
SEG
1
Port
Port
SEG
SEG
SEG
SEG
SEG
0
Port
SEG
SEG
SEG
SEG
SEG
SEG
1
SEG
SEG
SEG
SEG
SEG
SEG
SEG
0
SEG
SEG
SEG
SEG
SEG
SEG
SEG
1
SEG
SEG
SEG
SEG
SEG
SEG
Port
0
SEG
SEG
SEG
SEG
SEG
Port
Port
1
SEG
SEG
SEG
SEG
Port
Port
Port
0
SEG
SEG
SEG
Port
Port
Port
Port
1
SEG
SEG
Port
Port
Port
Port
Port
0
SEG
Port
Port
Port
Port
Port
Port
1
Port
Port
Port
Port
Port
Port
Port
0
0
1
1
0
1
1
0
0
1
1
0
1
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Section 13 LCD Controller/Driver
13.3.2
LCD Control Register (LCR)
LCR controls LCD drive power supply and display data, and selects the frame frequency.
Bit
Bit Name
Initial
Value
R/W
Description
7
—
1
—
Reserved
6
PSW
0
R/W
This bit is always read as 1 and cannot be modified.
LCD Drive Power Supply Control
Can be used to disconnect the LCD drive power supply
from Vcc when LCD display is not required in powerdown mode, or when an external power supply is used.
When the ACT bit is cleared to 0, and also in standby
mode, the LCD drive power supply is disconnected from
Vcc regardless of the setting of this bit.
0: LCD drive power supply is disconnected from Vcc
1: LCD drive power supply is connected to Vcc
5
ACT
0
R/W
Display Function Activate
Specifies whether or not the LCD controller/driver is used.
Clearing this bit to 0 halts operation of the LCD
controller/driver. The LCD drive power supply is also
turned off, regardless of the setting of the PSW bit.
However, register contents are retained.
0: LCD controller/driver operation halted
1: LCD controller/driver operation enabled
4
DISP
0
R/W
Display Data Control
Specifies whether the LCD RAM contents are displayed
or blank data is displayed regardless of the LCD RAM
contents.
0: Blank data is displayed
1: LCD RAM data is displayed
3
CKS3
0
R/W
Frame Frequency Select 3 to 0
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Select the operating clock and the frame frequency. In
subactive mode, watch mode, and subsleep mode, the
system clock (φ) is halted, and therefore display
operations are not performed if one of the clocks from φ/2
to φ/256 is selected. If LCD display is required in these
modes, φW , φW /2, or φW /4 must be selected as the
operating clock.
For details, see table 13.4.
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Section 13 LCD Controller/Driver
Table 13.4 Frame Frequency Selection
Frame Frequency*1
Bit 3:
CKS3
Bit 2:
CKS2
Bit 1:
CKS1
Bit 0:
CKS0
Operating Clock
φ = 2 MHz
φ = 250 kHz*3
0
X
0
0
φW
1
φW /2
128 Hz*2
64 Hz*2
128 Hz*2
64 Hz*2
1
X
φW /4
32 Hz*2
32 Hz*2
0
0
φ/2
—
244 Hz
1
φ/4
977 Hz
122 Hz
0
φ/8
488 Hz
61 Hz
1
φ/16
244 Hz
30.5 Hz
0
φ/32
122 Hz
—
1
φ/64
61 Hz
—
0
φ/128
30.5 Hz
—
1
φ/256
—
—
1
0
1
1
0
1
Legend:
X:
Don’t care
Notes: 1. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
2. This is the frame frequency when φW = 32.768 kHz.
3. This is the frame frequency in active (medium-speed, φOSC/16) mode when φ = 2 MHz.
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Section 13 LCD Controller/Driver
13.3.3
LCD Control Register 2 (LCR2)
LCR2 controls switching between the A waveform and B waveform and removal of splitresistance. Note that removal of split-resistance control is only implemented on the H8/38104
Group.
Bit
Bit Name
Initial
Value
R/W
Description
7
LCDAB
0
R/W
A Waveform/B Waveform Switching Control
Bit 7 specifies whether the A waveform or B waveform is
used as the LCD drive waveform.
0: Drive using A waveform
1: Drive using B waveform
6, 5
—
All 1
—
Reserved
These bits are always read as 1 and cannot be modified.
4
—
—
W
Reserved
This bit is always read as 0.
3 to 0* CDS3
CDS2
CDS1
CDS0
All 0
R/W
Removal of Split-Resistance Control
These bits control whether the split-resistance is removed
or connected.
CDS3 = 0, CDS2 = CDS1 = CDS0 = 1: Split-resistance
removed
All other settings: Split-resistance connected
Note: * Applies to H8/38104 Group only. On the H8/3802 Group, H8/38004 Group or H8/38002S
Group, these bits are reserved like bit 4.
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Section 13 LCD Controller/Driver
13.4
Operation
13.4.1
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
1. Hardware Settings
A. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.2.
VCC
V1
V2
V3
VSS
Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty
B. Large-panel display
As the impedance of the on-chip power supply split-resistance is large, it may not be
suitable for driving a large panel. If the display lacks sharpness when using a large panel,
refer to section 13.4.4, Boosting LCD Drive Power Supply. When static or 1/2 duty is
selected, the common output drive capability can be increased. Set CMX to 1 when
selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output
the same waveform, and with 1/2 duty the COM1 waveform is output from pins COM2 and
COM1, and the COM2 waveform is output from pins COM4 and COM3.
C. LCD drive power supply setting
With this LSI, there are two ways of providing LCD power: by using the on-chip power
supply circuit, or by using an external power supply circuit.
When an external power supply circuit is used for the LCD drive power supply, connect the
external power supply to the V1 pin.
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Section 13 LCD Controller/Driver
2. Software Settings
A. Duty selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits
DTS1 and DTS0.
B. Segment selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
C. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 13.4.3, Operation
in Power-Down Modes.
D. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
E. LCD drive power supply selection
When an external power supply circuit is used, turn the LCD drive power supply off with
the PSW bit.
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Section 13 LCD Controller/Driver
13.4.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
SEG2
SEG2
SEG2
SEG2
H'F74C
COM4
COM3
COM2
COM1
Bit 3
Bit 2
Bit 1
Bit 0
SEG1
SEG1
SEG1
SEG1
SEG25
SEG25
SEG25
SEG25
COM4
COM3
COM2
COM1
Figure 13.3 LCD RAM Map (1/4 Duty)
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Section 13 LCD Controller/Driver
Bit 7
H'F740
Bit 6
Bit 5
Bit 4
SEG2
SEG2
SEG2
Bit 3
H'F74C
COM3
COM2
COM1
Bit 2
Bit 1
Bit 0
SEG1
SEG1
SEG1
SEG25
SEG25
SEG25
COM3
COM2
COM1
Space not used for display
Figure 13.4 LCD RAM Map (1/3 Duty)
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Display space
SEG25
H'F746
SEG25
Space not used
for display
H'F74C
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13.5 LCD RAM Map (1/2 Duty)
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Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Display space
SEG25
H'F743
Space not used
for display
H'F74C
COM1
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13.6 LCD RAM Map (Static Mode)
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Section 13 LCD Controller/Driver
1 frame
1 frame
M
M
Data
Data
COM1
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
(a) Waveform with 1/4 duty
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
COM1
COM2
COM1
V1
V2,V3
VSS
SEGn
V1
V2,V3
VSS
SEGn
V1
V1
V2,V3
VSS
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
(c) Waveform with 1/2 duty
Figure 13.7 Output Waveforms for Each Duty Cycle (A Waveform)
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Section 13 LCD Controller/Driver
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
1 frame
1 frame
1 frame
COM1
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM2
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM3
V1
V2
V3
VSS
COM4
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
SEGn
V1
V2
V3
VSS
(a) Waveform with 1/4 duty
1 frame
1 frame
1 frame
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
V1
V2,V3
VSS
COM1
COM2
V1
V2,V3
VSS
SEGn
SEGn
V1
V2,V3
VSS
COM1
1 frame
1 frame
1 frame
V1
VSS
V1
VSS
(d) Waveform with static output
M: LCD alternation signal
(c) Waveform with 1/2 duty
Figure 13.8 Output Waveforms for Each Duty Cycle (B Waveform)
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Section 13 LCD Controller/Driver
Table 13.5 Output Levels
Data
0
0
1
1
M
0
1
0
1
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Static
1/2 duty
1/3 duty
1/4 duty
M:
13.4.3
LCD alternation signal
Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
13.6.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φW, φW/2, or φW/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to the
LCD panel in this case, it is essential to ensure that φW, φW/2, or φW/4 is selected.
In active (medium-speed) mode, the system clock is switched, and therefore bits CKS3 to CKS0
must be modified to ensure that the frame frequency does not change.
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Section 13 LCD Controller/Driver
Table 13.6 Power-Down Modes and Display Operation
Reset
Active
Sleep
Watch
Subactive
Subsleep
Module
Standby Standby
φ
Runs
Runs
Runs
Stops
Stops
Stops
Stops
Stops*4
φw
Runs
Runs
Runs
Runs
Runs
Runs
Stops*1
Stops*4
Display
ACT = 0 Stops
operation
ACT = 1 Stops
Stops
Stops
Stops
Stops*2
Stops
Stops*2
Stops
Mode
Clock
Stops
Functions Functions Functions
*3
Functions
Stops
*3
Functions
*3
Notes: 1. The subclock oscillator does not stop, but clock supply is halted.
2. The LCD drive power supply is turned off regardless of the setting of the PSW bit.
3. Display operation is performed only if φW , φW /2, or φW /4 is selected as the operating
clock.
4. The clock supplied to the LCD stops.
13.4.4
Boosting LCD Drive Power Supply
When the on-chip power supply capacity is insufficient for the LCD panel drivability, the powersupply impedance must be reduced. This can be done by connecting bypass capacitors of around
0.1 to 0.3 µF to pins V1 to V3, as shown in figure 13.9, or by adding a split-resistor externally.
VCC
R
V1
R
This LSI
R = several kΩ to
several MΩ
V2
R
C = 0.1 to 0.3 µF
V3
R
VSS
Figure 13.9 Connection of External Split-Resistance
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Section 13 LCD Controller/Driver
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Section 14 Power-On Reset and Low-Voltage Detection
Circuits (H8/38104 Group Only)
This LSI can include a power-on reset circuit.
The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect)
and LVDR (reset by low voltage detect) circuits.
This circuit is used to prevent abnormal operation (runaway execution) from occurring due to the
power supply voltage fall and to recreate the state before the power supply voltage fall when the
power supply voltage rises again.
Even if the power supply voltage falls, the unstable state when the power supply voltage falls
below the guaranteed operating voltage can be removed by entering standby mode when
exceeding the guaranteed operating voltage and during normal operation. Thus, system stability
can be improved. If the power supply voltage falls more, the reset state is automatically entered. If
the power supply voltage rises again, the reset state is held for a specified period, then active mode
is automatically entered.
Figure 14.1 is a block diagram of the power-on reset circuit and the low-voltage detection circuit.
Note: * The voltage maintained in standby mode is the same as the RAM data maintenance
voltage (VRAM). See section 17.6.2, DC Characteristics, for information on maintenance
voltage electrical characteristics.
14.1
Features
• Power-on reset circuit
Uses an external capacitor to generate an internal reset signal when power is first supplied.
• Low-voltage detection circuit
LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the
voltage falls below a specified value.
LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls
below or rises above respective specified values.
Two pairs of detection levels for reset generation voltage are available: when only the LVDR
circuit is used, or when the LVDI and LVDR circuits are both used.
In addition, power supply rise/drop detection voltages and a detection voltage reference
voltage may be input from an external source, allowing the detection level to be set freely by
the user.
LVI0000A_000020030300
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
φ
CK
R
RES
OVF
PSS
R
Noise
canceler
Q
S
LVDCR
Vcc
External
power
supply
Vreset
−
Vint
LVDRES
+
−
extD
External
ladder
resistor
+
LVDINT
extU
Interrupt
control
circuit
LVDSR
Internal data bus
Power-on reset circuit
Noise
canceler
Ladder
resistor
Internal reset
signal
Vref
Interrupt
request
On-chip
reference voltage
generator
External
reference voltage
generator
Low-voltage detection circuit
Legend:
PSS:
LVDCR:
LVDSR:
LVDRES:
LVDINT:
Vreset:
Vint:
extD:
extU:
Vref:
Prescaler S
Low-voltage-detection control register
Low-voltage-detection status register
Low-voltage-detection reset signal
Low-voltage-detection interrupt signal
Reset detection voltage
Power-supply fall/rise detection voltage
Power supply drop detection voltage input pin
Power supply rise detection voltage input pin
Reference voltage input pin
Figure 14.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
14.2
Register Descriptions
The low-voltage detection circuit has the following registers.
• Low-voltage-detection control register (LVDCR)
• Low-voltage-detection status register (LVDSR)
• Low-voltage detection counter (LVDCNT)
14.2.1
Low-Voltage Detection Control Register (LVDCR)
LVDCR is used to control whether or not the low-voltage detection circuit is used, settings for
external input of power supply drop and rise detection voltages, the LVDR detection level setting,
enabling or disabling of resets triggered by the low-voltage detection reset circuit (LVDR), and
enabling or disabling of interrupts triggered by power supply voltage drops or rises.
Table 14.1 shows the relationship between LVDCR settings and function selections. Refer to table
14.1 when making settings to LVDCR.
Bit
7
Bit Name
Initial
Value
R/W
Description
LVDE
0*
R/W
LVD Enable
0: Low-voltage detection circuit not used (standby status)
1: Low-voltage detection circuit used
6

0
R/W
This bit is reserved.
5
VINTDSEL
0
R/W
Power Supply Drop (LVDD) Detection Level External
Input Select
0: LVDD detection level generated by on-chip ladder
resistor
1: LVDD detection level input to extD pin
4
VINTUSEL
0
R/W
Power Supply Rise (LVDU) Detection Level External
Input Select
0: LVDU detection level generated by on-chip ladder
resistor
1: LVDU detection level input to extU pin
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Bit
3
Bit Name
Initial
Value
R/W
Description
LVDSEL
0*
R/W
LVDR Detection Level Select
0: Reset detection voltage 2.3 V (typ.)
1: Reset detection voltage 3.3 V (typ.)
Select 2.3 V (typical) reset if voltage rise and drop
detection interrupts are to be used. For reset detection
only, Select 3.3 V (typical) reset.
2
0*
LVDRE
R/W
LVDR Enable
0: LVDR resets disabled
1: LVDR resets enabled
1
LVDDE
0
R/W
Voltage Drop Interrupt Enable
0: Voltage drop interrupt requests disabled
1: Voltage drop interrupt requests enabled
0
LVDUE
0
R/W
Voltage Rise Interrupt Enable
0: Voltage rise interrupt requests disabled
1: Voltage rise interrupt requests enabled
Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by power-on
resets and watchdog timer resets.
Table 14.1 LVDCR Settings and Select Functions
LVDCR Settings
Select Functions
LVDE
LVDSEL
LVDRE
LVDDE
LVDUE
Power-On
Reset
LVDR
Low-VoltageDetection
Falling
Interrupt
0
*
*
*
*
O



1
1
1
0
0
O
O


1
0
0
1
0
O

O

1
0
0
1
1
O

O
O
1
0
1
1
1
O
O
O
O
Legend:
* means invalid.
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Low-VoltageDetection
Rising
Interrupt
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
14.2.2
Low-Voltage Detection Status Register (LVDSR)
LVDSR is used to control external input selection, indicates when the reference voltage is stable,
and indicates if the power supply voltage goes below or above a specified range.
Bit
Bit Name
Initial
Value
R/W
Description
7
OVF
0*
R/W
LVD Reference Voltage Stabilized Flag
Setting condition:
When the low-voltage detection counter (LVDCNT)
overflows
Clearing condition:
When 0 is written after reading 1
6 to 4

0
R/W
These are read/write enabled reserved bits.
3
VREFSEL 0
R/W
Reference Voltage External Input Select
0: The on-chip circuit is used to generate the reference
voltage
1: The reference voltage is input to the Vref pin from an
external source
2

0
R/W
This bit is reserved. It is always read as 0 and cannot be
written to.
1
LVDDF
0*
R/W
LVD Power Supply Voltage Drop Flag
Setting condition:
When the power supply voltage drops below Vint(D)
Clearing condition:
When 0 is written after reading 1
0
LVDUF
0*
R/W
LVD Power Supply Voltage Rise Flag
Setting condition:
When the power supply voltage drops below Vint(D) while
the LVDUE bit in LVDCR is set to 1, and it rises above
Vint(U) before dropping below Vreset1
Clearing condition:
When 0 is written after reading 1
Note: * These bits are initialized by resets trigged by LVDR.
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
14.2.3
Low-Voltage Detection Counter (LVDCNT)
LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE. The
counter increments using φ/4 as the clock source until it overflows by switching from H'FF to
H'00, at which time the OVF bit in the LVDSR register is set to 1, indicating that the on-chip
reference voltage generator has stabilized. If the LVD function is used, it is necessary to stand by
until the counter has overflowed. The initial value of LVDCNT is H'00.
14.3
14.3.1
Operation
Power-On Reset Circuit
Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply
voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via
the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the RES pin is transmitted within the
chip, the prescaler S and the entire chip are in their reset states. When the level on the RES pin
reaches the specified value, the prescaler S is released from its reset state and it starts counting.
The OVF signal is generated to release the internal reset signal after the prescaler S has counted
131,072 clock (φ) cycles. The noise cancellation circuit of approximately 100 ns is incorporated to
prevent the incorrect operation of the chip by noise on the RES pin.
To achieve stable operation of this LSI, the power supply needs to rise to its full level and settles
within the specified time. The maximum time required for the power supply to rise and settle after
power has been supplied (tPWON) is determined by the oscillation frequency (fOSC) and capacitance
which is connected to RES pin (CRES). If tPWON means the time required to reach 90 % of power
supply voltage, the power supply circuit should be designed to satisfy the following formula.
tPWON (ms) ≤ 80 • CRES (µF) ± 10/fOSC (MHz)
(tPWON ≤ 3000 ms, CRES ≥ 0.22 µF, and fOSC = 10 in 2-MHz to 10-MHz operation)
Note that the power supply voltage (Vcc) must fall below Vpor = 100 mV and rise after charge on
the RES pin is removed. To remove charge on the RES pin, it is recommended that the diode
should be placed near Vcc. If the power supply voltage (Vcc) rises from the point above Vpor, a
power-on reset may not occur.
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
tPWON
Vcc
Vpor
Vss
Vss
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.2 Operational Timing of Power-On Reset Circuit
14.3.2
Low-Voltage Detection Circuit
LVDR (Reset by Low Voltage Detect) Circuit:
Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state
after a power-on reset is canceled. To operate the LVDR, set the LVDE bit in LVDCR to 1, wait
for 150 µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have
stabilized, based on overflow of LVDCNT, then set the LVDRE bit in LVDCR to 1. After that, the
output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDRE bit should be cleared to 0 and then the LVDE bit should be cleared to 0. The LVDE and
LVDRE bits must not be cleared to 0 simultaneously because incorrect operation may occur.
When the power-supply voltage falls below the Vreset voltage (typ. = 2.3 V or 3.3 V), the LVDR
clears the LVDRES signal to 0, and resets the prescaler S. The low-voltage detection reset state
remains in place until a power-on reset is generated. When the power-supply voltage rises above
the Vreset voltage again, the prescaler S starts counting. It counts 131,072 clock (φ) cycles, and
then releases the internal reset signal. In this case, the LVDE, LVDSEL, and LVDRE bits in
LVDCR are not initialized.
Note that if the power supply voltage (Vcc) falls below VLVDRmin = 1.0 V and then rises from that
point, the low-voltage detection reset may not occur.
If the power supply voltage (Vcc) falls below Vpor = 100 mV, a power-on reset occurs.
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
VCC
Vreset
VLVDRmin
VSS
PSS-reset
signal
OVF
Internal reset
signal
131,072 cycles
PSS counter starts
Reset released
Figure 14.3 Operational Timing of LVDR Circuit
LVDI (Interrupt by Low Voltage Detect) Circuit:
Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 150
µs (tLVDON) until the reference voltage and the low-voltage-detection power supply have stabilized,
based on overflow of LVDNT, then set the LVDDE and LVDUE bits in LVDCR to 1. After that,
the output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0.
The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode, watch mode,
or subsleep mode. Until this processing is completed, the power supply voltage must be higher
than the lower limit of the guaranteed operating voltage.
When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously
generated.
If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function
is performed.
Vint (U)
Vint (D)
Vcc
Vreset1
VSS
LVDDE
LVDDF
LVDUE
LVDUF
IRQ0 interrupt generated IRQ0 interrupt generated
Figure 14.4 Operational Timing of LVDI Circuit
The reference voltage, power supply voltage drop detection level, and power supply voltage rise
detection level can be input to the LSI from external sources via the Vref, extD, and extU pins.
Figure 14.5 shows the operational timing using input from the Vref, extD, and extU pins.
First, make sure that the voltages input to pins extD and extU are set to higher levels than the
interrupt detection voltage Vexd. After initial settings are made, a power supply drop interrupt is
generated if the extD input voltage drops below Vexd. After a power supply drop interrupt is
generated, if the external power supply voltage rises and the extU input voltage rises higher than
Vexd, a power supply rise interrupt is generated. As with the on-chip circuit, the above function
should be used in conjunction with LVDR (Vreset1) when the LVDI function is used.
Rev. 6.00 Mar 15, 2005 page 357 of 502
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
External power
supply voltage
extD input voltage
extU input voltage (1)
(2)
(3)
Vexd
(4) Vreset1
VSS
LVDINTD
LVDDF
LVDINTU
LVDUF
IRQ0 interrupt
generated
IRQ0 interrupt
generated
Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit
(Using Pins Vref, extD, and extU)
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU.
LVDCR
On-chip
ladder
resistor
R1
R2
D1
External power
supply voltage
R1 =
517 kΩ
U1
D2
U2
+
−
LVDRES
+
−
LVDINT
Interrupt
controller
extD
R2 =
33 kΩ
LVDSR
Interrupt
request
extU
R3 =
450 kΩ
Vref
External reference
voltage 1.3 V
On-chip reference
voltage generator
Setting conditions:
• Vref = 1.3 V external input (This Vref value results in a Vreset value of 2.5 V.)
• Power supply drop detection voltage input of 2.7 V from extD
• Power supply rise detection voltage input of 2.9 V from extU
• 1 MΩ variable resistor connected externally
Figure 14.6 LVD Function Usage Example Employing Pins Vref, extD, and extU
Below is an explanation of the method for calculating the external resistor values when using the
Vref, extD, and extU pins for input of reference and detection voltages from sources external to
the LSI.
Procedure:
1. First, determine the overall resistance value, R. The current consumed by the resistor is
determined by the value of R. A lower R will result in a greater current flow, and a higher R
will result in a reduced current flow. The value of R is dependent on the configuration of the
system in which the LSI is installed.
2. Determine the power supply drop detection voltage (Vint(D)) and the power supply rise
detection voltage (Vint(U)).
3. Using a resistance value calculation table like the one shown below, plug in values for R,
Vreset1, Vint(D), and Vint(U) to calculate the values of Vref, R1, R2, and R3.
Rev. 6.00 Mar 15, 2005 page 359 of 502
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Resistance Value Calculation Table
Ex. No
Vref (V)
R (kΩ
Ω)
Vreset1
Vint(D)
Vint(U)
R1 (kΩ
Ω)
R2 (kΩ
Ω)
R3 (kΩ
Ω)
1
1.30
1000
2.5
2.7
2.9
517
33
450
2
1.41
1000
2.7
2.9
3
514
16
470
3
1.57
1000
3
3.2
3.5
511
42
447
4
2.09
1000
4
4.5
4.7
536
20
444
4. Using an error calculation table like the one shown below, plug in values for R1, R2, R3, and
Vref to calculate the deviation of Vreset1, Vint(D), and Vint(U). Make sure to double check
the maximum and minimum values for each value.
Error Calculation Table
Vref (V)
R1
(kΩ
Ω)
R2
(kΩ
Ω)
R3
(kΩ
Ω)
1.3
517
33
450
Resistance Value
Error (%)
5
Comparator Vreset1
Error (V)
(V)
Vint(D)
(V)
Vint(U)
(V)
R1+Err, R2/R3-Err
0.1
2.59
2.94
3.15
0
2.49
2.84
3.05
-0.1
2.39
2.74
2.95
0.1
2.59
2.66
2.85
0
2.49
2.56
2.75
-0.1
2.39
2.46
2.65
0.1
2.59
2.79
2.99
0
2.49
2.69
2.89
-0.1
2.39
2.59
2.79
0.1
2.59
2.93
3.16
0
2.49
2.83
3.06
-0.1
2.39
2.73
2.96
0.1
2.59
2.67
2.84
0
2.49
2.57
2.74
-0.1
2.39
2.47
2.64
R1-Err, R2/R3+Err
R1/R2/R3 No Err
R1/R2+Err, R3-Err
R1/R2-Err, R3+Err
Rev. 6.00 Mar 15, 2005 page 360 of 502
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Procedures for Clearing Settings when Using LVDR and LVDI:
To operate or release the low-voltage detection circuit normally, follow the procedure described
below. Figure 14.7 shows the timing for the operation and release of the low-voltage detection
circuit.
1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1.
2. Wait for 150 µs (tLVDON) until the reference voltage and the low-voltage-detection power
supply have stabilized, based on overflow of LVDNT. Then, clear the LVDDF and LVDUF
bits in LVDSR to 0 and set the LVDRE, LVDDE, and LVDUE bits in LVDCR to 1, as
required.
3. To release the low-voltage detection circuit, start by clearing all of the LVDRE, LVDDE, and
LVDUE bits to 0. Then clear the LVDE bit to 0. The LVDE bit must not be cleared to 0 at the
same timing as the LVDRE, LVDDE, and LVDUE bits because incorrect operation may occur.
LVDE
LVDRE
LVDDE
LVDUE
tLVDON
Figure 14.7 Timing for Operation/Release of Low-Voltage Detection Circuit
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Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page 362 of 502
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Section 15 Power Supply Circuit (H8/38104 Group Only)
Section 15 Power Supply Circuit
(H8/38104 Group Only)
This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the
voltage of the power supply connected to the external VCC pin. As a result, the current consumed
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the
internal voltage will be practically the same as the external voltage. It is, of course, also possible to
use the same level of external power supply voltage and internal power supply voltage without
using the internal power supply step-down circuit.
15.1
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF between CVCC and VSS, as shown in figure 15.1. The internal step-down circuit is made
effective simply by adding this external circuit. In the external circuit interface, the external power
supply voltage connected to VCC and the GND potential connected to VSS are the reference levels.
For example, for port input/output levels, the VCC level is the reference for the high level, and the
VSS level is that for the low level. The A/D converter analog power supply is not affected by the
internal step-down circuit.
VCC
Step-down circuit
Internal
logic
VCC = 2.7 to 5.5 V
CVCC
Stabilization
capacitance
(approx. 0.1 µF)
Internal
power
supply
VSS
Figure 15.1 Power Supply Connection when Internal Step-Down Circuit is Used
PSCKT00A_000020020200
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Section 15 Power Supply Circuit (H8/38104 Group Only)
15.2
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the CVCC pin and VCC pin, as shown in figure 15.2. The external power supply is then input
directly to the internal power supply. The permissible range for the power supply voltage is 2.7 V
to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more
than 3.6 V) is input.
VCC
Step-down circuit
Internal
logic
VCC = 2.7 to 3.6 V
CVCC
Internal
power
supply
VSS
Figure 15.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
Rev. 6.00 Mar 15, 2005 page 364 of 502
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Section 16 List of Registers
Section 16 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1.
•
•
•
•
Register addresses (address order)
Registers are listed from the lower allocation addresses.
Registers are classified by functional modules.
The data bus width is indicated.
The number of access states is indicated.
2.
•
•
•
Register bits
Bit configurations of the registers are described in the same order as the register addresses.
Reserved bits are indicated by  in the bit name column.
When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 6.00 Mar 15, 2005 page 365 of 502
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Section 16 List of Registers
16.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbreviation
Module
Bit No Address Name
Data Bus Access
Width
State
Flash memory control register 1
FLMCR1
8
H'F020
ROM
8
2
Flash memory control register 2
FLMCR2
8
H'F021
ROM
8
2
Flash memory power control
register
FLPWCR
8
H'F022
ROM
8
2
Erase block register
EBR
8
H'F023
ROM
8
2
Flash memory enable register
FENR
8
H'F02B
ROM
8
2
Low-voltage detection control
register*4
LVDCR
8
H'FF86
LVD
8
2
Low-voltage detection status
register*4
LVDSR
8
H'FF87
LVD
8
2
Event counter PWM compare
register H
ECPWCRH 8
H'FF8C
AEC*1
8
2
Event counter PWM compare
register L
ECPWCRL 8
H'FF8D
AEC*1
8
2
Event counter PWM data register ECPWDRH 8
H
H'FF8E
AEC*1
8
2
Event counter PWM data register ECPWDRL 8
L
H'FF8F
AEC*1
8
2
Wakeup edge select register
WEGR
8
H'FF90
Interrupts
8
2
Serial port control register
SPCR
8
H'FF91
8
2
Input pin edge select register
AEGSR
8
H'FF92
SCI3
AEC*1
8
2
Event counter control register
ECCR
8
H'FF94
AEC*1
8
2
*1
8
2
1
Event counter control/status
register
ECCSR
8
H'FF95
AEC
Event counter H
ECH
8
H'FF96
8
2
Event counter L
ECL
8
H'FF97
AEC*
AEC*1
8
2
Serial mode register
SMR
8
H'FFA8
SCI3
8
3
Bit rate register
BRR
8
H'FFA9
SCI3
8
3
Serial control register 3
SCR3
8
H'FFAA
SCI3
8
3
Rev. 6.00 Mar 15, 2005 page 366 of 502
REJ09B0024-0600
Section 16 List of Registers
Register Name
Abbreviation
Module
Bit No Address Name
Data Bus Access
Width
State
Transmit data register
TDR
8
H'FFAB
SCI3
8
3
Serial status register
SSR
8
H'FFAC
SCI3
8
3
Receive data register
RDR
8
H'FFAD
SCI3
8
3
Timer mode register A
TMA
8
H'FFB0
Timer A
8
2
Timer counter A
TCA
8
H'FFB1
8
2
Timer control/status register W
TCSRW
8
H'FFB2
Timer A
WDT*2
8
2
*2
8
2
Timer counter W
TCW
8
H'FFB3
WDT
Timer control register F
TCRF
8
H'FFB6
Timer F
8
2
Timer control status register F
TCSRF
8
H'FFB7
Timer F
8
2
8-bit timer counter FH
TCFH
8
H'FFB8
Timer F
8
2
8-bit timer counter FL
TCFL
8
H'FFB9
Timer F
8
2
Output compare register FH
OCRFH
8
H'FFBA
Timer F
8
2
Output compare register FL
OCRFL
8
H'FFBB
8
2
LCD port control register
LPCR
8
H'FFC0
Timer F
LCD*3
8
2
8
2
8
2
*3
LCD control register
LCR
8
H'FFC1
LCD control register 2
LCR2
8
H'FFC2
LCD
LCD*3
Low-voltage detection counter*4
LVDCNT
8
H'FFC3
LVD
8
2
A/D result register H
ADRRH
8
H'FFC4
A/D converter 8
2
A/D result register L
ADRRL
8
H'FFC5
A/D converter 8
2
A/D mode register
AMR
8
H'FFC6
A/D converter 8
2
A/D start register
ADSR
8
H'FFC7
A/D converter 8
2
Port mode register 2
PMR2
8
H'FFC9
I/O port
8
2
Port mode register 3
PMR3
8
H'FFCA
I/O port
8
2
Port mode register 5
PMR5
8
H'FFCC
I/O port
8
2
PWM2 control register
PWCR2
8
H'FFCD
10-bit PWM
8
2
PWM2 data register U
PWDRU2
8
H'FFCE
10-bit PWM
8
2
PWM2 data register L
PWDRL2
8
H'FFCF
10-bit PWM
8
2
PWM1 control register
PWCR1
8
H'FFD0
10-bit PWM
8
2
PWM1 data register U
PWDRU1
8
H'FFD1
10-bit PWM
8
2
PWM1 data register L
PWDRL1
8
H'FFD2
10-bit PWM
8
2
Port data register 3
PDR3
8
H'FFD6
I/O port
8
2
Port data register 4
PDR4
8
H'FFD7
I/O port
8
2
Rev. 6.00 Mar 15, 2005 page 367 of 502
REJ09B0024-0600
Section 16 List of Registers
Register Name
Abbreviation
Module
Bit No Address Name
Data Bus Access
Width
State
Port data register 5
PDR5
8
H'FFD8
I/O port
8
2
Port data register 6
PDR6
8
H'FFD9
I/O port
8
2
Port data register 7
PDR7
8
H'FFDA
I/O port
8
2
Port data register 8
PDR8
8
H'FFDB
I/O port
8
2
Port data register 9
PDR9
8
H'FFDC
I/O port
8
2
Port data register A
PDRA
8
H'FFDD
I/O port
8
2
Port data register B
PDRB
8
H'FFDE
I/O port
8
2
Port pull-up control register 3
PUCR3
8
H'FFE1
I/O port
8
2
Port pull-up control register 5
PUCR5
8
H'FFE2
I/O port
8
2
Port pull-up control register 6
PUCR6
8
H'FFE3
I/O port
8
2
Port control register 3
PCR3
8
H'FFE6
I/O port
8
2
Port control register 4
PCR4
8
H'FFE7
I/O port
8
2
Port control register 5
PCR5
8
H'FFE8
I/O port
8
2
Port control register 6
PCR6
8
H'FFE9
I/O port
8
2
Port control register 7
PCR7
8
H'FFEA
I/O port
8
2
Port control register 8
PCR8
8
H'FFEB
I/O port
8
2
Port mode register 9
PMR9
8
H'FFEC
I/O port
8
2
Port control register A
PCRA
8
H'FFED
I/O port
8
2
Port mode register B
PMRB
8
H'FFEE
I/O port
8
2
System control register 1
SYSCR1
8
H'FFF0
SYSTEM
8
2
System control register 2
SYSCR2
8
H'FFF1
SYSTEM
8
2
IRQ edge select register
IEGR
8
H'FFF2
Interrupts
8
2
Interrupt enable register 1
IENR1
8
H'FFF3
Interrupts
8
2
Interrupt enable register 2
Oscillator control register*4
IENR2
8
H'FFF4
Interrupts
8
2
OSCCR
8
H'FFF5
CPG
8
2
Interrupt request register 1
IRR1
8
H'FFF6
Interrupts
8
2
Interrupt request register 2
Timer mode register W *4
IRR2
8
H'FFF7
8
2
TMW
8
H'FFF8
Interrupts
WDT*2
8
2
Wakeup interrupt request register IWPR
8
H’FFF9
Interrupts
8
2
Clock stop register 1
CKSTPR1 8
H'FFFA
SYSTEM
8
2
Clock stop register 2
CKSTPR2 8
H'FFFB
SYSTEM
8
2
Rev. 6.00 Mar 15, 2005 page 368 of 502
REJ09B0024-0600
Section 16 List of Registers
Notes: 1.
2.
3.
4.
AEC: Asynchronous event counter
WDT: Watchdog timer
LCD: LCD controller/driver
H8/38104 Group only
Rev. 6.00 Mar 15, 2005 page 369 of 502
REJ09B0024-0600
Section 16 List of Registers
16.2
Register Bits
Register bit names of the on-chip peripheral modules are described below.
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
ROM
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
FLMCR2
FLER
—
—
—
—
—
—
—
FLPWCR
PDWND
—
—
—
—
—
—
—
EBR
—
—
—
EB4
EB3
EB2
EB1
EB0
FENR
FLSHE
—
—
—
—
—
—
—
LVDCR*4
LVDE
—
VINTDSEL VINTUSEL LVDSL
LVDSR*
OVF
—
—
ECPWCRH
ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 AEC *
ECPWCRL
ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0
ECPWDRH
ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0
4
—
LVDRE
VREFSEL —
LVDDE
LVDUE
LVDDF
LVDUF
Lowvoltage
detect
circuit
1
ECPWDRL
ECPWDRL7 ECPWDRL6 ECPWDRL5 ECPWDRL4 ECPWDRL3 ECPWDRL2 ECPWDRL1 ECPWDRL0
WEGR
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Interrupts
SPCR
—
SCINV3
SCINV2
—
AEGSR
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1
AIEGS0
ECPWME —
ECCR
ACKH1
—
SPC32
—
—
ACKH0
ACKL1
ACKL0
PWCK2
PWCK1
PWCK0
—
ECCSR
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
ECH
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
ECL
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
SMR
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
BRR
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
SCR3
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
SSR
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
RDR
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
TMA
—
—
—
—
TMA3
TMA2
TMA1
TMA0
TCA
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
TCSRW
B6WI
TCWE
B4WI
TCSRWE B2WI
WDON
BOWI
WRST
TCW
TCW7
TCW6
TCW5
TCW4
TCW2
TCW1
TCW0
Rev. 6.00 Mar 15, 2005 page 370 of 502
REJ09B0024-0600
TCW3
SCI3
AEC*1
SCI3
Timer A
WDT*2
Section 16 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
TCRF
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Timer F
TOLH
TCSRF
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
TCFH
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
TCFL
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
OCRFH
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
OCRFL
OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
LPCR
DTS1
DTS0
CMX
—
SGS3
LCR
—
PSW
ACT
DISP
CKS3
SGS2
SGS1
CKS2
*4
CDS2
SGS0
CKS1
*4
CKS0
*4
CDS0*4
LCR2
LCDAB
—
—
—
CDS3
LVDCNT*4
CNT7
CNT6
CNT5
CNT4
CNT3
ADRRH
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADRRL
ADR1
ADR0
—
—
—
—
AMR
CKS
—
—
—
CH3
CH2
CH1
CH0
ADSR
ADSF
—
—
—
—
—
—
—
PMR2
—
—
POF1
—
—
WDCKS
—
IRQ0
PMR3
AEVL
AEVH
—
—
—
TMOFH
TMOFL
—
WKP1
WKP0
CNT2
CDS1
LCD*3
CNT1
CNT0
Lowvoltage
detect
circuit
ADR3
ADR2
—
—
A/D
converter
I/O port
PMR5
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
PWCR2
—
—
—
—
—
PWCR22*4 PWCR21 PWCR20 10-bit
PWDRU2
—
—
—
—
—
—
PWDRL2
PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20
PWCR1
—
—
—
—
—
PWCR12*4 PWCR11 PWCR10
PWDRU1
—
—
—
—
—
—
PWDRL1
PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10
PDR3
P37
PDR4
PDR5
PWDRU21 PWDRU20
PWM
PWDRU11 PWDRU10
P36
P35
P34
P33
P32
P31
—
—
—
—
—
P43
P42
P41
P40
P57
P56
P55
P54
P53
P52
P51
P50
PDR6
P67
P66
P65
P64
P63
P62
P61
P60
PDR7
P77
P76
P75
P74
P73
P72
P71
P70
PDR8
—
—
—
—
—
—
—
P80
PDR9
—
—
P95
P94
P93
P92
P91
P90
PDRA
—
—
—
—
PA3
PA2
PA1
PA0
PDRB
—
—
—
—
PB3
PB2
PB1
PB0
I/O port
Rev. 6.00 Mar 15, 2005 page 371 of 502
REJ09B0024-0600
Section 16 List of Registers
Register
Abbreviation Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PUCR3
PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 —
PUCR5
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PUCR6
PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
PCR3
PCR37
PCR36
PCR35
PCR34
PCR33
PCR32
PCR31
Module
Name
I/O port
—
PCR4
—
—
—
—
—
PCR42
PCR41
PCR40
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
PCR6
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
PCR7
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
PCR8
—
—
—
—
—
—
—
PCR80
PMR9
—
—
—
—
PIOFF
—
PWM2
PWM1
PCRA
—
—
—
—
PCRA3
PCRA2
PCRA1
PCRA0
PMRB
—
—
—
—
IRQ1
—
—
—
SYSCR1
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
SYSCR2
—
—
—
NESEL
DTON
MSON
SA1
SA0
IEGR
—
—
—
—
—
—
IEG1
IEG0
IENR1
IENTA
—
IENWP
—
—
IENEC2
IEN1
IEN0
IENR2
IENDT
IENAD
—
—
IENTFH
IENTFL
—
IENEC
OSCCR*4
SUBSTP —
—
—
—
IRQAECF OSCF
—
CPG
IRR1
IRRTA
—
—
—
—
IRREC2
IRRI1
IRRI0
Interrupts
IRR2
IRRDT
IRRAD
—
—
IRRTFH
IRRTFL
—
IRREC
TMW *4
—
—
—
—
CKS3
CKS2
CKS1
CKS0
WDT*2
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Interrupts
CKSTPR1
—
—
CKSTPR2
LVDCKSTP —
*4
Notes: 1.
2.
3.
4.
S32CKSTP ADCKSTP —
—
PW2CKSTP
AEC: Asynchronous event counter
WDT: Watchdog timer
LCD: LCD controller/driver
H8/38104 Group only
Rev. 6.00 Mar 15, 2005 page 372 of 502
REJ09B0024-0600
TFCKSTP —
SYSTEM
Interrupts
TACKSTP SYSTEM
AECKSTP WDCKSTP PW1CKSTP LDCKSTP
Section 16 List of Registers
16.3
Register States in Each Operating Mode
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive Subsleep Standby
Module
ROM
FLMCR1
Initialized
—
—
Initialized
Initialized
Initialized
Initialized
FLMCR2
Initialized
—
—
—
—
—
—
FLPWCR
Initialized
—
—
—
—
—
—
EBR
Initialized
—
—
Initialized
Initialized
Initialized
Initialized
FENR
Initialized
—
—
—
—
—
—
LVDCR*4
Initialized
—
—
—
—
—
—
4
LVDSR*
Initialized
—
—
—
—
—
—
Lowvoltage
detect
circuit
ECPWCRH
Initialized
—
—
—
—
—
—
AEC*
ECPWCRL
Initialized
—
—
—
—
—
—
ECPWDRH
Initialized
—
—
—
—
—
—
ECPWDRL
Initialized
—
—
—
—
—
—
WEGR
Initialized
—
—
—
—
—
—
Interrupts
SPCR
Initialized
—
—
—
—
—
—
SCI3
AEGSR
Initialized
—
—
—
—
—
—
AEC*1
ECCR
Initialized
—
—
—
—
—
—
ECCSR
Initialized
—
—
—
—
—
—
ECH
Initialized
—
—
—
—
—
—
ECL
Initialized
—
—
—
—
—
—
SMR
Initialized
—
—
Initialized
—
—
Initialized
BRR
Initialized
—
—
Initialized
—
—
Initialized
SCR3
Initialized
—
—
Initialized
—
—
Initialized
TDR
Initialized
—
—
Initialized
—
—
Initialized
SSR
Initialized
—
—
Initialized
—
—
Initialized
RDR
Initialized
—
—
Initialized
—
—
Initialized
TMA
Initialized
—
—
—
—
—
—
TCA
Initialized
—
—
—
—
—
—
TCSRW
Initialized
—
—
—
—
—
—
TCW
Initialized
—
—
—
—
—
—
1
SCI3
Timer A
WDT*2
Rev. 6.00 Mar 15, 2005 page 373 of 502
REJ09B0024-0600
Section 16 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive Subsleep Standby
Module
TCRF
Initialized
—
—
—
—
Timer F
TCSRF
Initialized
—
—
—
—
—
—
TCFH
Initialized
—
—
—
—
—
—
TCFL
Initialized
—
—
—
—
—
—
—
—
OCRFH
Initialized
—
—
—
—
—
—
OCRFL
Initialized
—
—
—
—
—
—
LPCR
Initialized
—
—
—
—
—
—
LCR
Initialized
—
—
—
—
—
—
LCR2
Initialized
—
—
—
—
—
—
LVDCNT*4
Initialized
—
—
—
—
—
—
Lowvoltage
detect
circuit
ADRRH
—
—
—
—
—
—
—
ADRRL
—
—
—
—
—
—
—
A/D
converter
AMR
Initialized
—
—
—
—
—
—
ADSR
Initialized
—
—
Initialized
Initialized
Initialized
Initialized
PMR2
Initialized
—
—
—
—
—
—
PMR3
Initialized
—
—
—
—
—
—
PMR5
Initialized
—
—
—
—
—
—
PWCR2
Initialized
—
—
—
—
—
—
PWDRU2
Initialized
—
—
—
—
—
—
PWDRL2
Initialized
—
—
—
—
—
—
PWCR1
Initialized
—
—
—
—
—
—
PWDRU1
Initialized
—
—
—
—
—
—
PWDRL1
Initialized
—
—
—
—
—
—
PDR3
Initialized
—
—
—
—
—
—
PDR4
Initialized
—
—
—
—
—
—
PDR5
Initialized
—
—
—
—
—
—
PDR6
Initialized
—
—
—
—
—
—
PDR7
Initialized
—
—
—
—
—
—
PDR8
Initialized
—
—
—
—
—
—
PDR9
Initialized
—
—
—
—
—
—
PDRA
Initialized
—
—
—
—
—
—
PDRB
Initialized
—
—
—
—
—
—
Rev. 6.00 Mar 15, 2005 page 374 of 502
REJ09B0024-0600
3
LCD*
I/O port
10-bit
PWM
I/O port
Section 16 List of Registers
Register
Abbreviation
Reset
Active
Sleep
Watch
Subactive Subsleep Standby
Module
PUCR3
Initialized
—
—
—
—
—
—
I/O port
PUCR5
Initialized
—
—
—
—
—
—
PUCR6
Initialized
—
—
—
—
—
—
PCR3
Initialized
—
—
—
—
—
—
PCR4
Initialized
—
—
—
—
—
—
PCR5
Initialized
—
—
—
—
—
—
PCR6
Initialized
—
—
—
—
—
—
PCR7
Initialized
—
—
—
—
—
—
PCR8
Initialized
—
—
—
—
—
—
PMR9
Initialized
—
—
—
—
—
—
PCRA
Initialized
—
—
—
—
—
—
PMRB
Initialized
—
—
—
—
—
—
SYSCR1
Initialized
—
—
—
—
—
—
SYSCR2
Initialized
—
—
—
—
—
—
IEGR
Initialized
—
—
—
—
—
—
IENR1
Initialized
—
—
—
—
—
—
IENR2
Initialized
—
—
—
—
—
—
OSCCR*4
Initialized
—
—
—
—
—
—
CPG
IRR1
Initialized
—
—
—
—
—
—
Interrupts
IRR2
Initialized
—
—
—
—
—
—
4
TMW *
Initialized
—
—
—
—
—
—
2
WDT*
IWPR
Initialized

—
—
—
—
—
Interrupts
CKSTPR1
Initialized
—
—
—
—
—
—
SYSTEM
CKSTPR2
Initialized


—
—
—
—
SYSTEM
Interrupts
Notes:  is not initialized
1. AEC: Asynchronous event counter
2. WDT: Watchdog timer
3. LCD: LCD controller/driver
4. H8/38104 Group only
Rev. 6.00 Mar 15, 2005 page 375 of 502
REJ09B0024-0600
Section 16 List of Registers
Rev. 6.00 Mar 15, 2005 page 376 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Section 17 Electrical Characteristics
17.1
Absolute Maximum Ratings of H8/3802 Group (ZTAT Version,
Mask ROM Version)
Table 17.1 lists the absolute maximum ratings.
Table 17.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.0
V
Input voltage
Other than port B and
IRQAEC
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
IRQAEC
HVin
–0.3 to +7.3
V
Port 9 pin voltage
VP9
–0.3 to +7.3
V
Operating temperature
Topr
Regular specifications:
–20 to +75
°C
Wide-range temperature
specifications: –40 to +85
Storage temperature
Note:
*
Tstg
–55 to +125
°C
Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
Rev. 6.00 Mar 15, 2005 page 377 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.2
Electrical Characteristics of H8/3802 Group (ZTAT Version, Mask
ROM Version)
17.2.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
38.4
fW (kHz)
fosc (MHz)
16.0
10.0
32.768
4.0
2.0
1.8
2.7
4.5
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Note 1: The fosc values are those when a resonator
is used; when an external clock is used, the
minimum value of fosc is 1 MHz.
Rev. 6.00 Mar 15, 2005 page 378 of 502
REJ09B0024-0600
1.8
3.0
4.5
5.5
VCC (V)
• All operating modes
Note 2: When a resonator is used, hold Vcc at 2.2 V
to 5.5 V from power-on until the oscillation
stabilization time has elapsed.
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range
8.0
5.0
16.384
2.0
1.0
(0.5)
9.6
1.8
2.7
4.5
5.5
VCC (V)
φSUB (kHz)
φ (MHz)
19.2
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
Note 1: The values in parentheses is the minimum operating
frequency when an external clock is input. When
8.192
4.8
4.096
using a resonator, the minimum operating frequency
(φ) is 1 MHz.
1.8
3.6
5.5
VCC (V)
• Subactive mode
1000
• Subsleep mode (except CPU)
φ (kHz)
• Watch mode (except CPU)
625
250
15.625
(7.8125)
1.8
2.7
4.5
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
(except A/D converter)
Note 2: The values in parentheses is the minimum operating
frequency when an external clock is input. When
using a resonator, the minimum operating frequency
(φ) is 15.625 kHz.
Rev. 6.00 Mar 15, 2005 page 379 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range
1000
φ (kHz)
φ (MHz)
5.0
1.0
625
500
(0.5)
1.8
2.7
4.5
5.5
AVCC (V)
1.8
2.7
4.5
5.5
AVCC (V)
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
Note: When AVcc = 1.8 V to 2.7 V, the operating range is limited to φ = 1.0 MHz when using a resonator
and is φ = 0.5 MHz to 1.0 MHz when using an external clock.
Rev. 6.00 Mar 15, 2005 page 380 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.2.2
DC Characteristics
Table 17.2 lists the DC characteristics.
Table 17.2 DC Characteristics (1)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Test Condition
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
Min
Typ
Max
Unit
VCC = 4.0 V to 5.5 V VCC × 0.8 —
VCC + 0.3
V
AEVL, AEVH,
SCK32
Other than above
VCC × 0.9 —
VCC + 0.3
RXD32
VCC = 4.0 V to 5.5 V VCC × 0.7 —
VCC + 0.3
VCC × 0.8 —
VCC + 0.3
VCC = 4.0 V to 5.5 V VCC × 0.8 —
VCC + 0.3
VCC × 0.9 —
VCC + 0.3
X1
VCC = 1.8 V to 5.5 V VCC × 0.9 —
VCC + 0.3
V
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
VCC = 4.0 V to 5.5 V VCC × 0.7 —
VCC + 0.3
V
VCC × 0.8 —
VCC + 0.3
PB0 to PB3
VCC = 4.0 V to 5.5 V VCC × 0.7 —
AVCC + 0.3
VCC × 0.8 —
AVCC + 0.3
Other than above
OSC1
Other than above
Other than above
Other than above
IRQAEC
VCC = 4.0 V to 5.5 V VCC × 0.8 —
7.3
VCC × 0.9 —
7.3
Other than above
Notes
V
V
V
V
Note: Connect the TEST pin to VSS.
Rev. 6.00 Mar 15, 2005 page 381 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (2)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Values
Item
Symbol
Input low
voltage
VIL
Applicable Pins
Typ
Max
Unit
VCC = 4.0 V to 5.5 V – 0.3
—
VCC × 0.2
V
IRQAEC,
AEVL, AEVH,
SCK32
Other than above
– 0.3
—
VCC × 0.1
RXD32
VCC = 4.0 V to 5.5 V – 0.3
—
VCC × 0.3
Other than above
– 0.3
—
VCC × 0.2
VCC = 4.0 V to 5.5 V – 0.3
—
VCC × 0.2
Other than above
– 0.3
—
VCC × 0.1
X1
VCC = 1.8 V to 5.5 V – 0.3
—
VCC × 0.1
V
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3,
PB0 to PB3
VCC = 4.0 V to 5.5 V – 0.3
—
VCC × 0.3
V
Other than above
—
VCC × 0.2
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
OSC1
Output
high
voltage
VOH
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
Test Condition
Min
– 0.3
VCC = 4.0 V to 5.5 V VCC – 1.0 —
—
–IOH = 1.0 mA
VCC = 4.0 V to 5.5 V VCC – 0.5 —
—
–IOH = 0.5 mA
–IOH = 0.1 mA
Rev. 6.00 Mar 15, 2005 page 382 of 502
REJ09B0024-0600
VCC – 0.3 —
—
V
V
V
Notes
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (3)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Values
Item
Symbol
Output low VOL
voltage
Applicable Pins
Test Condition
Min
P40 to P42
VCC = 4.0 V to 5.5 V —
Typ
Max
Unit
—
0.6
V
Notes
IOL = 1.6 mA
IOL = 0.4 mA
—
—
0.5
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
IOL = 0.4 mA
—
—
0.5
P31 to P37
VCC = 4.0 V to 5.5 V —
—
1.5
—
0.6
—
—
0.5
VCC = 2.2 V to 5.5 V —
—
0.5
IOL = 10 mA
VCC = 4.0 V to 5.5 V —
IOL = 1.6 mA
IOL = 0.4 mA
P90 to P92
*5
IOL = 25 mA
IOL = 15 mA
*6
IOL = 10 mA
P93 to P95
Input/
output
leakage
current
| IIL |
IOL = 10 mA
—
—
0.5
VIN = 0.5 V to VCC – —
0.5 V
—
20.0
—
—
1.0
OSC1, X1,
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80, IRQAEC,
PA0 to PA3,
P90 to P95
VIN = 0.5 V to VCC – —
0.5 V
—
1.0
PB0 to PB3
VIN = 0.5 V to AVCC —
– 0.5 V
—
1.0
RES, P43
µA
*2
*1
µA
Rev. 6.00 Mar 15, 2005 page 383 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (4)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Values
Item
Symbol
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Pull-up
MOS
current
–Ip
P31 to P37,
P50 to P57,
P60 to P67
VCC = 5.0 V,
VIN = 0.0 V
50.0
—
300.0
µA
VCC = 2.7 V,
VIN = 0.0 V
—
35.0
—
Input
capacitance
Cin
f = 1 MHz,
All input pins
VIN = 0.0 V,
except power
supply, RES, P43, Ta = 25°C
IRQAEC, PB0 to
PB3 pins
—
—
15.0
IRQAEC
—
—
30.0
RES
—
—
80.0
*2
—
—
15.0
*1
—
—
50.0
*2
—
—
15.0
*1
—
—
15.0
Active (high-speed) —
mode
VCC = 5.0 V,
fOSC = 10 MHz
7.0
10.0
Active (mediumspeed) mode
VCC = 5.0 V,
fOSC = 10 MHz,
φOSC/128
—
2.2
VCC = 5.0 V,
fOSC = 10 MHz
—
P43
PB0 to PB3
Active
IOPE1
mode
current
consumption
IOPE2
ISLEEP
Sleep
mode
current
consumption
VCC
VCC
VCC
Rev. 6.00 Mar 15, 2005 page 384 of 502
REJ09B0024-0600
Notes
Reference
value
pF
mA
*3
*4
3.0
mA
*3
*4
3.8
5.0
mA
*3
*4
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (5)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Values
Item
Symbol
Subactive ISUB
mode
current
consumption
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
VCC
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /2)
—
15.0
30.0
µA
*3
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /8)
—
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /2)
—
VCC = 2.7 V,
LCD not used,
32-kHz crystal
resonator used
—
Subsleep ISUBSP
mode
current
consumption
VCC
IWATCH
Watch
mode
current
consumption
VCC
*4
8.0
*3
—
*4
Reference
value
7.5
16.0
µA
*3
*4
3.8
6.0
µA
*2
*3
*4
*1
2.8
*3
*4
ISTBY
Standby
mode
current
consumption
VCC
RAM data VRAM
retaining
voltage
VCC
32-kHz crystal
resonator not
used
—
1.0
5.0
µA
*3
*4
1.5
—
—
V
Rev. 6.00 Mar 15, 2005 page 385 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.2 DC Characteristics (6)
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Item
Symbol
Allowable output low
current (per pin)
IOL
Applicable
Pins
Test
Condition
Typ
Max
Unit
Output pins
VCC = 4.0 V to —
except ports 3 5.5 V
and 9
—
2.0
mA
Port 3
VCC = 4.0 V to —
5.5 V
—
10.0
—
—
0.5
VCC = 2.2 V to —
5.5 V
—
25.0
—
—
15.0
—
—
10.0
—
—
10.0
Output pins
VCC = 4.0 V to —
except ports 3 5.5 V
and 9
—
40.0
Port 3
VCC = 4.0 V to —
5.5 V
—
80.0
Output pins
except port 9
—
—
20.0
Port 9
—
—
80.0
All output pins VCC = 4.0 V to —
5.5 V
—
2.0
—
—
0.2
All output pins VCC = 4.0 V to —
5.5 V
—
15.0
—
10.0
Output pins
except port 9
P90 to P92
P93 to P95
Allowable output low
current (total)
∑IOL
Allowable output high –IOH
current (per pin)
Other than
above
Allowable output high
current (total)
∑–IOH
Values
Other than
above
Min
—
Notes: 1. Applies to the mask-ROM version.
2. Applies to the HD6473802.
3. Pin states when current consumption is measured
Rev. 6.00 Mar 15, 2005 page 386 of 502
REJ09B0024-0600
Notes
*5
mA
mA
mA
Section 17 Electrical Characteristics
Mode
Active (high-speed)
mode (IOPE1)
RES Pin
Internal State
Other Pins
LCD Power
Supply
VCC
Only CPU operates
VCC
Stops
Active (mediumspeed) mode (IOPE2)
Oscillator Pins
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Sleep mode
VCC
Only timers operate
VCC
Stops
Subactive mode
VCC
Subsleep mode
VCC
Only CPU operates
VCC
Stops
Only timers operate
VCC
Stops
Subclock:
crystal resonator
CPU stops
Watch mode
VCC
Standby mode
VCC
Only clock time base
operates
System clock:
crystal resonator
VCC
Stops
VCC
Stops
CPU stops
CPU and timers
both stop
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Notes: 4. Except current which flows to the pull-up MOS or output buffer
5. When the PIOFF bit in the port mode register 9 is 0
6. When the PIOFF bit in the port mode register 9 is 1
Rev. 6.00 Mar 15, 2005 page 387 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.2.3
AC Characteristics
Table 17.3 lists the control signal timing and table 17.4 lists the serial interface timing.
Table 17.3 Control Signal Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Item
Symbol
System clock
oscillation
frequency
fOSC
OSC clock (φOSC)
cycle time
tOSC
Applicable
Pins
Test Condition
OSC1,
OSC2
OSC1,
OSC2
Values
Min
Typ
Max
Unit
VCC = 4.5 V to 5.5 V 2.0
—
16.0
MHz
VCC = 2.7 V to 5.5 V 2.0
—
10.0
Other than above
—
4.0
VCC = 4.5 V to 5.5 V 62.5
2.0
—
VCC = 2.7 V to 5.5 V 100
—
500
ns
(1000)
500
Other than above
250
—
500
2
—
128
tOSC
—
—
128
µs
Reference
Figure
Figure 17.1*2
(1000)
(1000)
System clock (φ)
cycle time
tcyc
Subclock
oscillation
frequency
fW
X1, X2
—
32.768
or 38.4
—
kHz
Watch clock (φW )
cycle time
tW
X1, X2
—
30.5 or
26.0
—
µs
Figure 17.1
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
VCC = 2.2 V to 5.5 V —
in figure 17.7
20
45
µs
Other than above
Instruction cycle
time
Oscillation
stabilization time
trc
OSC1,
OSC2
X1, X2
—
—
50
ms
VCC = 2.7 V to 5.5 V —
—
2.0
s
VCC = 2.2 V to 5.5 V —
—
10.0
Rev. 6.00 Mar 15, 2005 page 388 of 502
REJ09B0024-0600
Figure 17.7
*3
Section 17 Electrical Characteristics
Item
Symbol
Applicable
Pins
Test Condition
External clock
high width
tCPH
OSC1
Typ
Max
Unit
Reference
Figure
VCC = 4.5 V to 5.5 V 25
—
—
ns
Figure 17.1
VCC = 2.7 V to 5.5 V 40
—
—
100
—
—
—
15.26 or —
13.02
µs
VCC = 4.5 V to 5.5 V 25
—
—
ns
VCC = 2.7 V to 5.5 V 40
—
—
100
—
—
—
15.26 or —
13.02
µs
VCC = 4.5 V to 5.5 V —
—
6
ns
VCC = 2.7 V to 5.5 V —
—
10
Other than above
—
—
25
—
—
55.0
ns
ns
Other than above
X1
External clock
low width
tCPL
OSC1
Other than above
X1
External clock
rise time
tCPr
OSC1
X1
External clock
fall time
RES pin low
tCPf
OSC1
Values
Min
VCC = 4.5 V to 5.5 V —
—
6
VCC = 2.7 V to 5.5 V —
—
10
Other than above
—
—
25
Figure 17.1
Figure 17.1
Figure 17.1
X1
—
—
55.0
ns
tREL
RES
10
—
—
tcyc
Figure 17.2
tIH
IRQ0,
IRQ1,
2
—
—
tcyc
tsubcyc
Figure 17.3
0.5
—
—
tOSC
2
—
—
tcyc
tsubcyc
0.5
—
—
tOSC
width
Input pin high
width
IRQAEC,
WKP0 to
WKP7,
AEVL,
AEVH
Input pin low
width
tIL
IRQ0,
IRQ1,
Figure 17.3
IRQAEC,
WKP0 to
WKP7,
AEVL,
AEVH
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. Values in parentheses indicate tOSC max. when the external clock is used.
3. After powering on, hold VCC at 2.2 V to 5.5 V until the oscillation stabilization time has
elapsed.
Rev. 6.00 Mar 15, 2005 page 389 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.4 Serial Interface (SCI3) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Values
Item
Symbol Test Condition
Input clock Asynchronous tscyc
cycle
Clocked
synchronous
Input clock pulse width
tSCKW
Transmit data delay time
(clocked synchronous)
tTXD
Receive data setup time
(clocked synchronous)
tRXS
Receive data hold time
(clocked synchronous)
tRXH
Reference
Figure
Min
Typ
Max
Unit
4
—
—
tcyc or tsubcyc Figure 17.4
6
—
—
—
0.6
tscyc
VCC = 4.0 V to 5.5 V —
0.4
—
1
tcyc or tsubcyc Figure 17.5
Other than above
—
1
VCC = 4.0 V to 5.5 V 200.0
—
—
Other than above
400.0
—
—
VCC = 4.0 V to 5.5 V 200.0
—
—
Other than above
—
—
Rev. 6.00 Mar 15, 2005 page 390 of 502
REJ09B0024-0600
—
400.0
Figure 17.4
ns
Figure 17.5
ns
Figure 17.5
Section 17 Electrical Characteristics
17.2.4
A/D Converter Characteristics
Table 17.5 shows the A/D converter characteristics.
Table 17.5 A/D Converter Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (product with regular
specifications), Ta = –40°C to +85°C (product with wide-range temperature specifications), Ta =
+75°C (bare die product), unless otherwise specified
Values
Applicable Test
Pins
Condition
Min
Typ Max
Unit
Reference
Figure
Analog power supply AVCC
voltage
AVCC
1.8
—
5.5
V
*1
Analog input voltage
AN0 to
AN3
– 0.3
—
AVCC + 0.3 V
—
1.5
mA
600
—
µA
Item
Symbol
AVIN
Analog power supply AIOPE
current
AISTOP1
AVCC
AVCC = 5.0 V —
AVCC
—
*2
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
Analog input
capacitance
CAIN
AN0 to
AN3
—
—
15.0
pF
Allowable signal
source impedance
RAIN
—
—
10.0
kΩ
—
—
10
bit
AVCC = 2.7 V —
to 5.5 V
VCC = 2.7 V to
5.5 V
—
±2.5
LSB
AVCC = 2.0 V —
to 5.5 V
VCC = 2.0 V to
5.5 V
—
±5.5
Other than
above
—
—
±7.5
—
—
±0.5
Resolution
(data length)
Nonlinearity error
Quantization error
*3
*4
LSB
Rev. 6.00 Mar 15, 2005 page 391 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Item
Symbol
Applicable Test
Pins
Condition
Absolute accuracy
Conversion time
Values
Min
Typ Max
Unit
AVCC = 2.7 V —
to 5.5 V
VCC = 2.7 V to
5.5 V
—
±3.0
LSB
AVCC = 2.0 V —
to 5.5 V
VCC = 2.0 V to
5.5 V
—
±6.0
Other than
above
—
±8.0
—
124
—
124
—
AVCC = 2.7 V 12.4
to 5.5 V
VCC = 2.7 V to
5.5 V
Other than
above
62
Reference
Figure
*4
µs
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. The conversion time is 62 µs.
Rev. 6.00 Mar 15, 2005 page 392 of 502
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Section 17 Electrical Characteristics
17.2.5
LCD Characteristics
Table 17.6 shows the LCD characteristics.
Table 17.6 LCD Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
(including subactive mode), Ta = –20°C to +75°C (product with regular specifications), Ta = –
40°C to +85°C (product with wide-range temperature specifications), Ta = +75°C (bare die
product)
Values
Applicable
Pins
Test Condition
Item
Symbol
Segment driver
step-down voltage
VDS
SEG1 to
SEG25
Common driver
step-down voltage
VDC
COM1 to
COM4
LCD power supply
split-resistance
RLCD
Liquid crystal
display voltage
VLCD
V1
Typ
Max
Unit
Reference
Figure
ID = 2 µA
—
V1 = 2.7 V to 5.5 V
—
0.6
V
*1
ID = 2 µA
—
V1 = 2.7 V to 5.5 V
—
0.3
V
*1
Between V1 and
VSS
0.5
3.0
9.0
MΩ
2.2
—
5.5
V
Min
*2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment
pin or common pin.
2. When the liquid crystal display voltage is supplied from an external power supply,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 6.00 Mar 15, 2005 page 393 of 502
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Section 17 Electrical Characteristics
17.3
Absolute Maximum Ratings of H8/38004 Group (F-ZTAT Version,
Mask ROM Version), H8/38002S Group (Mask ROM Version)
Table 17.7 lists the absolute maximum ratings.
Table 17.7 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +4.3
V
*1
Analog power supply voltage
AVCC
–0.3 to +4.3
V
Input voltage
Other than port B
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
Port 9 pin voltage
VP9
–0.3 to VCC +0.3
V
Operating temperature
Topr
Regular specifications:
2
–20 to +75*
°C
Wide-range temperature
specifications:
–40 to +85*3
Bare die product: +75*4
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
2. When the operating voltage is VCC = 2.7 to 3.6 V during flash memory reading, the
operating temperature ranges from –20°C to +75°C when programming or erasing the
flash memory. When the operating voltage is VCC = 2.2 to 3.6 V during flash memory
reading, the operating temperature ranges from –20°C to +50°C when programming or
erasing the flash memory.
3. The operating temperature ranges from –20°C to +75°C when programming or erasing
the flash memory.
4. The current-carrying temperature ranges from –20°C to +75°C.
Rev. 6.00 Mar 15, 2005 page 394 of 502
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Section 17 Electrical Characteristics
17.4
Electrical Characteristics of H8/38004 Group (F-ZTAT Version,
Mask ROM Version), H8/38002S Group (Mask ROM Version)
17.4.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range (F-ZTAT Version)
38.4
fw(kHz)
fosc(MHz)
10.0
32.768
4.0
2.0
2.2
2.7
3.6
Vcc (V)
2.2
• Active (high-speed) mode
2.7
3.6
Vcc (V)
• All operating modes
• Sleep (high-speed) mode
4 MHz specification
10 MHz specification
Power Supply Voltage and Oscillation Frequency Range (Mask ROM Version)
38.4
fw(kHz)
fosc(MHz)
10.0
32.768
4.0
2.0
1.8
2.7
3.6
Vcc (V)
1.8
2.7
3.6
Vcc (V)
• Active (high-speed) mode
• All operating modes
• Sleep (high-speed) mode
• When a resonator is used, hold Vcc at
2.2 V to 3.6 V from power-on until the
oscillation stabilization time has elapsed.
Rev. 6.00 Mar 15, 2005 page 395 of 502
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Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (F-ZTAT Version)
19.2
φ (MHz)
φ SUB (kHz)
5.0
16.384
9.6
8.192
2.0
4.8
1.0
4.096
2.2
2.7
3.6
Vcc (V)
2.2
2.7
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
3.6
Vcc (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
φ (kHz)
625
250
15.625
2.2
2.7
3.6
Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 396 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (Mask ROM Version)
19.2
φ (MHz)
φ SUB (kHz)
5.0
16.384
9.6
8.192
2.0
4.8
1.0
4.096
1.8
2.7
3.6
Vcc (V)
1.8
2.7
• Active (high-speed) mode
3.6
Vcc (V)
• Subactive mode
• Sleep (high-speed) mode (except CPU)
• Subsleep mode (except CPU)
• Watch mode (except CPU)
φ (kHz)
625
250
15.625
1.8
2.7
3.6
Vcc (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 397 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range (F-ZTAT Version)
φ (kHz)
φ (MHz)
5.0
625
1.0
500
2.2
2.7
3.6
AVcc (V)
2.7
3.6
AVcc (V)
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
Note: When AVcc = 2.2 V to 2.7 V, the operating range is limited to φ = 1.0 MHz.
Analog Power Supply Voltage and A/D Converter Operating Range (Mask ROM Version)
φ (kHz)
φ (MHz)
5.0
625
1.0
500
1.8
2.7
3.6
AVcc (V)
2.7
3.6
AVcc (V)
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
Note: When AVcc = 1.8 V to 2.7 V, the operating range is limited to φ = 1.0 MHz.
Rev. 6.00 Mar 15, 2005 page 398 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.4.2
DC Characteristics
Table 17.8 lists the DC characteristics.
Table 17.8 DC Characteristics
One of following conditions is applied unless otherwise specified.
Condition A (F-ZTAT version):
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V,
VSS = AVSS = 0.0 V
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Min
Typ
Max
Unit
VCC × 0.9
—
VCC +
0.3
V
RXD32
VCC × 0.8
—
VCC +
0.3
V
OSC1
VCC × 0.9
—
VCC +
0.3
V
VCC = 1.8 V to 5.5 V VCC × 0.9
—
VCC +
0.3
V
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
VCC × 0.8
—
VCC +
0.3
V
PB0 to PB3
VCC × 0.8
—
AVCC +
0.3
V
IRQAEC, P95*5
VCC × 0.9
—
VCC +
0.3
V
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
Test Condition
Notes
AEVL, AEVH,
SCK32
X1
Rev. 6.00 Mar 15, 2005 page 399 of 502
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Section 17 Electrical Characteristics
Values
Item
Symbol
Input low
voltage
VIL
Applicable Pins
Test Condition
Min
Typ
Max
Unit
– 0.3
—
VCC ×
0.1
V
RXD32
– 0.3
—
VCC ×
0.2
V
OSC1
– 0.3
—
VCC ×
0.1
V
X1
– 0.3
—
VCC ×
0.1
V
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3,
PB0 to PB3
– 0.3
—
VCC ×
0.2
V
—
—
V
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
5
IRQAEC, P95* ,
AEVL, AEVH,
SCK32
Input low
voltage
Output
high
voltage
VOH
Output low VOL
voltage
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3,
P31 to P37
P90 to P95
VCC = 2.7 V to 3.6 V VCC – 1.0
–IOH = 1.0 mA
–IOH = 0.1 mA
VCC – 0.3
—
—
IOL = 0.4 mA
—
—
0.5
VCC = 2.2 V to 3.6 V —
—
0.5
IOL = 10.0 mA
VCC = 1.8 V to 3.6 V
IOL = 8.0 mA
Rev. 6.00 Mar 15, 2005 page 400 of 502
REJ09B0024-0600
V
Notes
Section 17 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Input/
output
leakage
current
| IIL |
RES, P43,
OSC1, X1,
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80, IRQAEC,
PA0 to PA3,
P90 to P95
Typ
Max
Unit
VIN = 0.5 V to VCC – —
0.5 V
Test Condition
Min
—
1.0
µA
PB0 to PB3
VIN = 0.5 V to AVCC
– 0.5 V
—
—
1.0
Pull-up
MOS
current
–Ip
P31 to P37,
P50 to P57,
P60 to P67
VCC = 3.0 V,
VIN = 0.0 V
30
—
180
µA
Input
capacitance
Cin
All input pins
except power
supply pin
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
—
—
15.0
pF
VCC
Active (high-speed)
mode
VCC = 1.8 V,
fOSC = 2 MHz
—
0.4
—
mA
Active (high-speed)
mode
VCC = 3 V,
fOSC = 2 MHz
—
Active
IOPE1
mode
current
consumption
Active (high-speed)
mode
VCC = 3 V,
fOSC = 4 MHz
Notes
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
0.6
—
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
1.0
—
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
1.2
—
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
1.6
2.8
*2 *3 *4
Condition
B
Rev. 6.00 Mar 15, 2005 page 401 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Values
Item
Symbol
Active
IOPE1
mode
current
consumption
IOPE2
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
VCC
Active (high-speed)
mode
VCC = 3 V,
fOSC = 10 MHz
—
3.1
6.0
mA
*1 *3 *4
—
3.6
6.0
VCC
*2 *3 *4
Condition
A
Active (mediumspeed) mode
VCC = 1.8 V,
fOSC = 2 MHz,
φOSC/128
—
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 2 MHz,
φOSC/128
—
0.06
—
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
0.1
—
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
0.5
—
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
0.2
—
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
0.7
1.3
*2 *3 *4
Condition
B
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 10 MHz,
φOSC/128
Rev. 6.00 Mar 15, 2005 page 402 of 502
REJ09B0024-0600
—
0.6
1.8
*1 *3 *4
—
1.0
1.8
*2 *3 *4
Condition
A
Section 17 Electrical Characteristics
Values
Item
Symbol
Sleep
ISLEEP
mode
current
consumption
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
VCC
VCC = 1.8 V,
fOSC = 2 MHz
—
0.16
—
mA
*1 *3 *4
VCC = 3 V,
fOSC = 2 MHz
—
0.3
—
—
0.6
—
Approx.
max. value
= 1.1 ×
Typ.
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
VCC = 3 V,
fOSC = 4 MHz
VCC = 3 V,
fOSC = 10 MHz
—
0.5
*1 *3 *4
—
Approx.
max. value
= 1.1 ×
Typ.
—
0.9
2.2
*2 *3 *4
Condition
B
—
1.3
4.8
*1 *3 *4
—
1.7
4.8
*2 *3 *4
Condition
A
Subactive ISUB
mode
current
consumption
VCC
6.2
—
µA
*1 *3 *4
VCC = 1.8 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /2)
—
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /8)
—
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /2)
—
10
40
*1 *3 *4
—
28
50
*2 *3 *4
Reference
value
4.4
—
*1 *3 *4
Reference
value
—
8.0
—
*2 *3 *4
Reference
value
Rev. 6.00 Mar 15, 2005 page 403 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Values
Item
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
Subsleep ISUBSP
mode
current
consumption
Symbol
VCC
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /2)
—
4.6
16
µA
*3 *4
IWATCH
Watch
mode
current
consumption
VCC
VCC = 1.8 V,
Ta = 25°C,
32-kHz crystal
resonator used,
LCD not used
—
1.2
—
µA
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator used,
LCD not used
—
VCC = 2.7 V,
32-kHz crystal
resonator used,
LCD not used
—
2.0
6.0
VCC = 1.8 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
0.1
—
VCC = 3.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
32-kHz crystal
resonator not used
—
1.0
5.0
Standby
ISTBY
mode
current
consumption
VCC
2.0
*3 *4
—
Reference
value
*3 *4
µA
0.3
*3 *4
—
Reference
value
*3 *4
VCC
1.5
—
—
V
Allowable IOL
output low
current
(per pin)
Output pins
except port 9
—
—
0.5
mA
VCC = 2.2 V to 3.6 V —
—
10.0
Other than above
—
—
8.0
Output pins
except port 9
—
—
20.0
Port 9
—
—
60.0
Allowable
output low
current
(total)
∑IOL
Rev. 6.00 Mar 15, 2005 page 404 of 502
REJ09B0024-0600
*1 *3 *4
Reference
value
RAM data VRAM
retaining
voltage
P90 to P95
*1 *3 *4
Reference
value
mA
Section 17 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Test Condition
Typ
Max
Unit
Allowable
output
high
current
(per pin)
–IOH
All output pins
VCC = 2.7 V to 3.6 V —
—
2.0
mA
Other than above
—
—
0.2
—
—
10.0
Allowable
output
high
current
(total)
∑–IOH
All output pins
Min
Notes
mA
Notes: Connect the TEST pin to VSS.
1. Applies to the mask-ROM version.
2. Applies to the F-ZTAT version.
3. Pin states when current consumption is measured
Mode
Active (high-speed)
mode (IOPE1)
RES Pin
Internal State
Other Pins
LCD Power
Supply
VCC
Only CPU operates
VCC
Stops
Active (mediumspeed) mode (IOPE2)
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Sleep mode
VCC
Only all on-chip timers
operate
VCC
Stops
Subactive mode
VCC
Only CPU operates
VCC
Stops
Subsleep mode
VCC
Only all on-chip timers
operate
VCC
Stops
VCC
Only clock time base
operates
System clock:
crystal resonator
Subclock:
crystal resonator
CPU stops
Watch mode
Oscillator Pins
VCC
Stops
VCC
Stops
CPU stops
Standby mode
VCC
CPU and timers
both stop
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Notes: 4. Except current which flows to the pull-up MOS or output buffer
5. Used when user mode or boot mode is determined after canceling a reset in the FZTAT version
Rev. 6.00 Mar 15, 2005 page 405 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.4.3
AC Characteristics
Table 17.9 lists the control signal timing and table 17.10 lists the serial interface timing.
Table 17.9 Control Signal Timing
One of following conditions is applied unless otherwise specified.
Condition A (F-ZTAT version):
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V,
VSS = AVSS = 0.0 V
Item
Symbol
System clock
oscillation
frequency
fOSC
OSC clock (φOSC)
cycle time
System clock (φ)
cycle time
tOSC
Applicable
Pins
Values
Test Condition
Min
Typ
Max
Unit
2.0
—
10.0
MHz
Other than above in 2.0
condition C and
condition B
—
4.0
100
—
500
Other than above in 250
condition C and
condition B
—
500
2
—
128
tOSC
—
—
64
µs
OSC1, OSC2 VCC = 2.7 V to 3.6
V in conditions A
and C
OSC1, OSC2 VCC = 2.7 V to 3.6
V in conditions A
and C
tcyc
ns
Reference
Figure
Figure 17.1
Subclock oscillation fW
frequency
X1, X2
—
32.768
or 38.4
—
kHz
Watch clock (φW )
cycle time
tW
X1, X2
—
30.5 or
26.0
—
µs
Figure 17.1
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*
2
—
—
tcyc
tsubcyc
Instruction cycle
time
Rev. 6.00 Mar 15, 2005 page 406 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Item
Symbol
Oscillation
stabilization time
trc
trc
Applicable
Pins
OSC1,
OSC2
X1, X2
Values
Typ
Max
Unit
Reference
Figure
VCC = 2.7 V to 3.6 —
V when using
crystal resonator in
figure 17.8
0.8
2.0
ms
Figure 17.8
VCC = 2.2 V to 3.6 —
V when using
crystal resonator in
figure 17.8 and in
conditions B and C
1.2
3.0
Other than above in —
condition C and
when using crystal
resonator in figure
17.8
4.0
—
VCC = 2.7 V to 3.6 —
V when using
ceramic resonator
in figure 17.8 and in
conditions A and C
20
45
VCC = 2.2 V to 3.6 —
V when using
ceramic resonator
(1) in figure 17.8
and in conditions B
and C
20
45
Other than above in —
condition C and
when using ceramic
resonator (1) in
figure 17.8
80
—
Other than above
—
—
50
ms
VCC = 2.7 V to 3.6
V
—
—
2.0
s
VCC = 2.2 V to 3.6 —
V and in conditions
B and C
—
2.0
Other than above in —
condition C
4.0
—
Test Condition
Min
µs
Rev. 6.00 Mar 15, 2005 page 407 of 502
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Section 17 Electrical Characteristics
Item
Symbol
External clock high tCPH
width
Applicable
Pins
OSC1
Values
Test Condition
Min
Typ
Max
Unit
Reference
Figure
VCC = 2.7 V to 3.6
V in conditions A
and C
40
—
—
ns
Figure 17.1
—
—
Other than above in 100
condition C and
condition B
X1
External clock low
width
tCPL
OSC1
VCC = 2.7 V to 3.6
V in conditions A
and C
—
15.26 or —
13.02
µs
40
—
—
ns
—
—
Other than above in 100
condition C and
condition B
X1
External clock rise
time
tCPr
—
15.26 or —
13.02
µs
—
—
10
ns
Other than above in —
condition C and
condition B
—
25
—
—
55.0
ns
—
—
10
ns
Other than above in —
condition C and
condition B
—
25
X1
—
—
55.0
ns
RES
10
—
—
tcyc
2
—
—
Figure 17.3
tcyc
tsubcyc
0.5
—
—
tOSC
OSC1
VCC = 2.7 V to 3.6
V in conditions A
and C
X1
External clock fall
time
RES pin low
width
Input pin high
width
tCPf
tREL
tIH
Figure 17.1
OSC1
VCC = 2.7 V to 3.6
V in conditions A
and C
IRQ0, IRQ1,
IRQAEC,
WKP0 to
WKP7,
AEVL, AEVH
Rev. 6.00 Mar 15, 2005 page 408 of 502
REJ09B0024-0600
Figure 17.1
Figure 17.1
Figure 17.2
Section 17 Electrical Characteristics
Item
Symbol
Input pin low
width
tIL
Applicable
Pins
IRQ0, IRQ1,
IRQAEC,
WKP0 to
WKP7,
AEVL, AEVH
Note:
*
Values
Test Condition
Min
Typ
Max
Unit
Reference
Figure
2
—
—
Figure 17.3
tcyc
tsubcyc
0.5
—
—
tOSC
Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
Rev. 6.00 Mar 15, 2005 page 409 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.10 Serial Interface (SCI3) Timing
One of following conditions is applied unless otherwise specified.
Condition A (F-ZTAT version):
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V,
VSS = AVSS = 0.0 V
Item
Symbol
Input clock Asynchronous
cycle
tscyc
Clocked synchronous
Test
Condition
Values
Min
Typ Max Unit
Reference
Figure
4
—
—
tcyc or
tsubcyc
Figure 17.4
6
—
—
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Figure 17.4
Transmit data delay time
(clocked synchronous)
tTXD
—
—
1
tcyc or
tsubcyc
Figure 17.5
Receive data setup time
(clocked synchronous)
tRXS
400.0
—
—
ns
Figure 17.5
Receive data hold time
(clocked synchronous)
tRXH
400.0
—
—
ns
Figure 17.5
Rev. 6.00 Mar 15, 2005 page 410 of 502
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Section 17 Electrical Characteristics
17.4.4
A/D Converter Characteristics
Table 17.11 shows the A/D converter characteristics.
Table 17.11 A/D Converter Characteristics
One of following conditions is applied unless otherwise specified.
Condition A (F-ZTAT version):
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V,
VSS = AVSS = 0.0 V
Item
Symbol
Analog power supply AVCC
voltage
Analog input voltage
AVIN
Analog power supply AIOPE
current
AISTOP1
Values
Applicable Test
Pins
Condition
Min
Typ
Max
Unit
Reference
Figure
AVCC
Condition A
2.7
—
3.6
V
*1
Condition B
2.2
—
3.6
Condition C
1.8
—
3.6
– 0.3
—
AVCC + 0.3 V
AN0 to
AN3
AVCC
AVCC
AVCC = 3.0 V
—
—
1.0
mA
—
600
—
µA
*2
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
Analog input
capacitance
CAIN
AN0 to
AN3
—
—
15.0
pF
Allowable signal
source impedance
RAIN
—
—
10.0
kΩ
—
—
10
bit
Resolution (data
length)
*3
Rev. 6.00 Mar 15, 2005 page 411 of 502
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Section 17 Electrical Characteristics
Item
Symbol
Applicable Test
Pins
Condition
Nonlinearity error
Min
Typ
Max
Unit
AVCC = 2.7 V
to 3.6 V
—
—
±3.5
LSB
AVCC = 2.2 V
to 3.6 V in
condition B,
AVCC = 2.0 V
to 3.6 V in
condition C
—
—
±5.5
Other than
above in
condition C
—
—
±7.5
—
—
±0.5
LSB
AVCC = 2.7 V
to 3.6 V
—
±2.0
±4.0
LSB
AVCC = 2.2 V
to 3.6 V in
condition B,
AVCC = 2.0 V
to 3.6 V in
condition C
—
±2.5
±6.0
Other than
above in
condition C
—
±2.5
±8.0
AVCC = 2.7 V
to 3.6 V
12.4
—
124
Other than
above
62
—
124
Quantization error
Absolute accuracy
Conversion time
Values
Reference
Figure
*4
*4
µs
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. The conversion time is 62 µs.
Rev. 6.00 Mar 15, 2005 page 412 of 502
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Section 17 Electrical Characteristics
17.4.5
LCD Characteristics
Table 17.12 shows the LCD characteristics.
Table 17.12 LCD Characteristics
One of following conditions is applied unless otherwise specified.
Condition A (F-ZTAT version):
VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition B (F-ZTAT version):
VCC = 2.2 V to 3.6 V, AVCC = 2.2 V to 3.6 V,
VSS = AVSS = 0.0 V
Condition C (Mask ROM version): VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V,
VSS = AVSS = 0.0 V
Values
Applicable
Pins
Test Condition
Item
Symbol
Segment driver
step-down voltage
VDS
SEG1 to
SEG25
Common driver
step-down voltage
VDC
COM1 to
COM4
LCD power supply
split-resistance
RLCD
Liquid crystal
display voltage
VLCD
V1
Typ
Max
Unit
Reference
Figure
—
ID = 2 µA
V1 = 2.7 V to 3.6 V
—
0.6
V
*1
ID = 2 µA
—
V1 = 2.7 V to 3.6 V
—
0.3
V
*1
Between V1 and
VSS
1.5
3.0
7.0
MΩ
2.2
—
3.6
V
Min
*2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment
pin or common pin.
2. When the liquid crystal display voltage is supplied from an external power supply,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 6.00 Mar 15, 2005 page 413 of 502
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Section 17 Electrical Characteristics
17.4.6
Flash Memory Characteristics
Table 17.13 Flash Memory Characteristics
Condition A:
AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (range of
operating voltage when reading), VCC = 3.0 V to 3.6 V (range of operating
voltage when programming/erasing), Ta = –20°C to +75°C (range of operating
temperature when programming/erasing: product with regular specifications,
product with wide-range temperature specifications, bare die product)
Condition B:
AVCC = 2.2 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.2 V to 3.6 V (range of
operating voltage when reading), VCC = 3.0 V to 3.6 V (range of operating
voltage when programming/erasing), Ta = –20°C to +50°C (range of operating
temperature when programming/erasing: product with regular specifications)
Item
Symbol
Test
Conditions
Values
Min
Typ
Max
Unit
tP
—
7
200
ms/
128 bytes
Erase time*1*3*5
tE
—
100
1200 ms/
block
Reprogramming count
NWEC
Data retain period
tDRP
1000*8 10000*9 —
10*10
—
—
year
Programming Wait time after
SWE-bit setting*1
x
1
—
—
µs
Wait time after
PSU-bit setting*1
y
50
—
—
µs
Wait time after
P-bit setting*1*4
z1
1≤n≤6
28
30
32
µs
z2
7 ≤ n ≤ 1000
198
200
202
µs
z3
8
Additional
programming
10
12
µs
Programming time
*1*2*4
times
Wait time after
P-bit clear*1
α
5
—
—
µs
Wait time after
1
PSU-bit clear*
β
5
—
—
µs
Wait time after
PV-bit setting*1
γ
4
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
1
PV-bit clear*
η
2
—
—
µs
Rev. 6.00 Mar 15, 2005 page 414 of 502
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Section 17 Electrical Characteristics
Item
Symbol
Programming Wait time after
SWE-bit clear*1
Erase
Notes:
Test
Conditions
Values
Min
Typ
Max
Unit
θ
100
—
—
µs
Maximum
programming
1 4 5
count* * *
N
—
—
1000 times
Wait time after
1
SWE-bit setting*
x
1
—
—
µs
Wait time after
ESU-bit setting*1
y
100
—
—
µs
Wait time after
E-bit setting*1*6
z
10
—
100
ms
Wait time after
1
E-bit clear*
α
10
—
—
µs
Wait time after
ESU-bit clear*1
β
10
—
—
µs
Wait time after
EV-bit setting*1
γ
20
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
EV-bit clear*1
η
4
—
—
µs
Wait time after
SWE-bit clear*1
θ
100
—
—
µs
Maximum erase
1 6 7
count* * *
N
—
—
120
times
1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1 is set. It
does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does not include
the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = Wait time after P-bit setting (z) • maximum number of writes (N)
5. The maximum number of writes (N) should be set according to the actual set value of z1, z2, and
z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1 and z2) should be alternated according to the number of writes
(n) as follows:
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000
z2 = 200 µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) • maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z to allow
erasing within the maximum erase time (tE (max)).
Rev. 6.00 Mar 15, 2005 page 415 of 502
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Section 17 Electrical Characteristics
8. This minimum value guarantees all characteristics after reprogramming (the guaranteed range is
from 1 to the minimum value).
9. Reference value when the temperature is 25°C (normally reprogramming will be performed by this
count).
10. This is a data retain characteristic when reprogramming is performed within the specification range
including this minimum value.
17.5
Absolute Maximum Ratings of H8/38104 Group (F-ZTAT Version,
Mask ROM Version)
Table 17.14 lists the absolute maximum ratings.
Table 17.14 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*1
CVCC
–0.3 to +4.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Input voltage
Other than port B
Vin
–0.3 to VCC +0.3
V
Port B
AVin
–0.3 to AVCC +0.3
V
Port 9 pin voltage
VP9
–0.3 to VCC +0.3
V
Operating temperature
Topr
Regular specifications:
2
–20 to +75*
°C
Wide-range temperature
specifications:
–40 to +85*2
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
2. The operating temperature ranges from –20°C to +75°C when programming or erasing
the flash memory.
Rev. 6.00 Mar 15, 2005 page 416 of 502
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Section 17 Electrical Characteristics
17.6
Electrical Characteristics of H8/38104 Group (F-ZTAT Version,
Mask ROM Version)
17.6.1
Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected)
fosc (MHz)
fW (kHz)
20.0
32.768
2.0
2.7
5.5
VCC (V)
2.7
• Active (high-speed) mode
• Sleep (high-speed) mode
5.5
VCC (V)
• All operating modes
fW (kHz)
fosc (MHz)
Power Supply Voltage and Oscillation Frequency Range (On-Chip Oscillator Selected)
32.768
2.0
0.7
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
2.7
5.5
VCC (V)
• All operating modes
Rev. 6.00 Mar 15, 2005 page 417 of 502
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Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected)
10.0
φ (MHz)
16.384
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
φSUB (kHz)
1.0
8.192
4.096
2.7
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
φ (kHz)
1250
15.625
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 418 of 502
REJ09B0024-0600
5.5
VCC (V)
Section 17 Electrical Characteristics
Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected)
φSUB (kHz)
φ (MHz)
16.384
1.0
0.35
2.7
5.5
VCC (V)
φ (kHz)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
8.192
4.096
2.7
5.5
VCC (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
125
6.25
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Rev. 6.00 Mar 15, 2005 page 419 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Analog Power Supply Voltage and A/D Converter Operating Range (System Clock
Oscillator Selected)
φ (kHz)
φ (MHz)
10.0
1000
500
1.0
2.7
2.7
5.5
AVCC (V)
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
• Active (high-speed) mode
• Sleep (high-speed) mode
Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator
Selected)
φ (kHz)
φ (MHz)
1.0
125
6.25
0.35
2.7
5.5
AVCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Rev. 6.00 Mar 15, 2005 page 420 of 502
REJ09B0024-0600
2.7
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
Section 17 Electrical Characteristics
17.6.2
DC Characteristics
Table 17.15 lists the DC characteristics.
Table 17.15 DC Characteristics (1)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Typ
Max
Unit
VCC = 4.0 V to 5.5 V VCC • 0.8
—
VCC + 0.3
V
AEVL, AEVH,
SCK32
Other than above
VCC • 0.9
—
VCC + 0.3
RXD32
VCC = 4.0 V to 5.5 V VCC • 0.7
—
VCC + 0.3
Other than above
VCC • 0.8
—
VCC + 0.3
OSC1
VCC = 4.0 V to 5.5 V VCC • 0.8
—
VCC + 0.3
Other than above
VCC • 0.9
—
VCC + 0.3
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
VCC = 4.0 V to 5.5 V VCC • 0.7
—
VCC + 0.3
Other than above
VCC • 0.8
—
VCC + 0.3
PB0 to PB3
VCC = 4.0 V to 5.5 V VCC • 0.7
—
AVCC + 0.3
Other than above
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
IRQAEC, P95*5
Test Condition
Min
VCC • 0.8
—
AVCC + 0.3
VCC = 4.0 V to 5.5 V VCC • 0.8
—
VCC + 0.3
Other than above
—
VCC + 0.3
VCC • 0.9
Notes
V
V
V
V
V
Note: Connect the TEST pin to VSS.
Rev. 6.00 Mar 15, 2005 page 421 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (2)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Input low
voltage
VIL
Applicable Pins
Typ
Max
Unit
VCC = 4.0 V to 5.5 V – 0.3
—
VCC • 0.2
V
IRQAEC, P95* ,
AEVL, AEVH,
SCK32
Other than above
– 0.3
—
VCC • 0.1
RXD32
VCC = 4.0 V to 5.5 V – 0.3
—
VCC • 0.3
Other than above
– 0.3
—
VCC • 0.2
VCC = 4.0 V to 5.5 V – 0.3
—
VCC • 0.2
Other than above
– 0.3
—
VCC • 0.1
P31 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3,
PB0 to PB3
VCC = 4.0 V to 5.5 V – 0.3
—
VCC • 0.3
Other than above
—
VCC • 0.2
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
VCC = 4.0 V to 5.5 V VCC – 1.0 —
RES,
WKP0 to WKP7,
IRQ0, IRQ1,
Test Condition
Min
5
OSC1
Output
high
voltage
VOH
– 0.3
—
–IOH = 1.0 mA
VCC = 4.0 V to 5.5 V VCC – 0.5 —
—
–IOH = 0.5 mA
–IOH = 0.1 mA
Rev. 6.00 Mar 15, 2005 page 422 of 502
REJ09B0024-0600
VCC – 0.3 —
—
V
V
V
V
Notes
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (3)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Output low VOL
voltage
Applicable Pins
Test Condition
P40 to P42
VCC = 4.0 V to 5.5 V —
P50 to P57,
P60 to P67,
P70 to P77,
P80,
PA0 to PA3
P31 to P37
Min
Typ
Max
Unit
—
0.6
V
—
—
0.5
VCC = 4.0 V to 5.5 V —
—
1.0
—
0.6
—
—
0.5
VCC = 4.0 V to 5.5 V —
—
1.5
—
1.0
—
0.8
Notes
IOL = 1.6 mA
IOL = 0.4 mA
IOL = 10 mA
VCC = 4.0 V to 5.5 V —
IOL = 1.6 mA
IOL = 0.4 mA
P90 to P93, P95
IOL = 15 mA
VCC = 4.0 V to 5.5 V —
IOL = 10 mA
VCC = 4.0 V to 5.5 V —
IOL = 8 mA
Input/
output
leakage
current
Pull-up
MOS
current
| IIL |
IOL = 5 mA
—
—
1.0
IOL = 1.6 mA
—
—
0.6
IOL = 0.4 mA
—
—
0.5
VIN = 0.5 V to VCC – —
0.5 V
—
1.0
PB0 to PB3
VIN = 0.5 V to AVCC —
– 0.5 V
—
1.0
P31 to P37,
P50 to P57,
P60 to P67
VCC = 5.0 V,
VIN = 0.0 V
20
—
200
VCC = 2.7 V,
VIN = 0.0 V
—
40
—
RES, P43
OSC1, X1,
P31 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80, IRQAEC,
PA0 to PA3,
P90 to P93, P95
–Ip
µA
µA
Reference
value
Rev. 6.00 Mar 15, 2005 page 423 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (4)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Input
capacitance
Cin
All input pins
except power
supply pin
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
—
—
15.0
µA
VCC
Active (high-speed)
mode
VCC = 2.7 V,
fOSC = 2 MHz
—
0.6
—
mA
—
1.0
—
Active
IOPE1
mode
current
consumption
Notes
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
Active (high-speed)
mode
VCC = 5 V,
fOSC = 2 MHz
—
0.8
—
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
1.5
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
Active (high-speed)
mode
VCC = 5 V,
fOSC = 4 MHz
—
1.6
—
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
2.0
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
Active (high-speed)
mode
VCC = 5 V,
fOSC = 10 MHz
Rev. 6.00 Mar 15, 2005 page 424 of 502
REJ09B0024-0600
—
3.3
7.0
*1 *3 *4
—
4.0
7.0
*2 *3 *4
Section 17 Electrical Characteristics
Table 17.15 DC Characteristics (5)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
IOPE2
Active
mode
current
consumption
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
VCC
Active (mediumspeed) mode
VCC = 2.7 V,
fOSC = 2 MHz,
φOSC/128
—
0.2
—
mA
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
0.5
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 2 MHz,
φOSC/128
—
0.4
—
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
0.8
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 4 MHz,
φOSC/128
—
0.6
—
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
0.9
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz,
φOSC/128
—
0.9
3.0
*1 *3 *4
—
1.2
3.0
*2 *3 *4
Rev. 6.00 Mar 15, 2005 page 425 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Values
Item
Symbol
Sleep
ISLEEP
mode
current
consumption
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
VCC
VCC = 2.7 V,
fOSC = 2 MHz
—
0.3
—
mA
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
0.8
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
VCC = 5 V,
fOSC = 2 MHz
—
0.5
—
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
0.9
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
VCC = 5 V,
fOSC = 4 MHz
VCC = 5 V,
fOSC = 10 MHz
Rev. 6.00 Mar 15, 2005 page 426 of 502
REJ09B0024-0600
—
0.9
—
*1 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
1.3
—
*2 *3 *4
Approx.
max. value
= 1.1 •
Typ.
—
1.5
5.0
*1 *3 *4
—
2.2
5.0
*2 *3 *4
Section 17 Electrical Characteristics
Values
Item
Symbol
Subactive ISUB
mode
current
consumption
Applicable Pins
Test Condition
Min
Typ
Max
Unit
Notes
VCC
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /8)
—
11.3
—
µA
*1 *3 *4
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /2)
—
16.3
50
*1 *3 *4
—
30
50
*2 *3 *4
Reference
value
—
12.7
Reference
value
Subsleep ISUBSP
mode
current
consumption
VCC
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW /2)
—
4.0
16
IWATCH
Watch
mode
current
consumption
VCC
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator used,
LCD not used
—
1.4
—
VCC = 2.7 V,
32-kHz crystal
resonator used,
LCD not used
—
1.8
6.0
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
0.3
—
Standby
ISTBY
mode
current
consumption
VCC
*2 *3 *4
—
µA
*3 *4
*1 *3 *4
Reference
value
—
1.8
*2 *3 *4
—
Reference
value
*3 *4
µA
*1 *3 *4
Reference
value
—
0.5
—
*2 *3 *4
Reference
value
VCC = 2.7 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
—
VCC = 5.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
0.05
—
*4
Reference
value
0.4
—
*1 *3 *4
Reference
value
—
0.6
—
*2 *3 *4
Reference
value
Rev. 6.00 Mar 15, 2005 page 427 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Values
Item
Symbol
Standby
ISTBY
mode
current
consumption
Applicable Pins
Test Condition
Min
Typ
Max
VCC
VCC = 5.0 V,
Ta = 25°C,
SUBSTP (subclock
oscillator control
register) setting = 1
—
0.16
—
32-kHz crystal
resonator not used
—
1.0
5.0
2.0
—
—
V
mA
VCC
Allowable IOL
output low
current
(per pin)
Output pins
except ports 3
and 9
VCC = 4.0 V to 5.5 V —
—
2.0
Port 3
VCC = 4.0 V to 5.5 V —
—
10.0
—
—
0.5
VCC = 4.0 V to 5.5 V —
—
15.0
Other than above
—
—
5.0
Output pins
except ports 3
and 9
VCC = 4.0 V to 5.5 V —
—
40.0
Port 3
VCC = 4.0 V to 5.5 V —
—
80.0
—
—
20.0
Port 9
Allowable
output low
current
(total)
∑IOL
Output pins
except port 9
Port 9
Allowable
output
high
current
(per pin)
Allowable
output
high
current
(total)
–IOH
∑–IOH
All output pins
All output pins
—
—
80.0
VCC = 4.0 V to 5.5 V —
—
2.0
Other than above
—
—
0.2
VCC = 4.0 V to 5.5 V —
—
15.0
Other than above
—
10.0
Notes: Connect the TEST pin to VSS.
1. Applies to the mask-ROM version.
2. Applies to the F-ZTAT version.
Rev. 6.00 Mar 15, 2005 page 428 of 502
REJ09B0024-0600
Notes
*4
Reference
value
RAM data VRAM
retaining
voltage
Output pins
except port 9
Unit
—
*3 *4
mA
mA
mA
*6
Section 17 Electrical Characteristics
3. Pin states when current consumption is measured.
Mode
Active (high-speed)
mode (IOPE1)
RES Pin
Internal State
Other Pins
LCD Power
Supply
VCC
Only CPU operates
VCC
Stops
Oscillator Pins
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Active (mediumspeed) mode (IOPE2)
Sleep mode
VCC
Only all on-chip timers
operate
VCC
Stops
Subactive mode
VCC
Subsleep mode
VCC
Only CPU operates
VCC
Stops
Only all on-chip timers
operate
VCC
Stops
Subclock:
crystal resonator
CPU stops
Watch mode
VCC
Standby mode
VCC
Only clock time base
operates
System clock:
crystal resonator
VCC
Stops
VCC
Stops
CPU stops
CPU and timers
both stop
System clock:
crystal resonator
Subclock:
Pin X1 = GND
4. Except current which flows to the pull-up MOS or output buffer
5. Used when user mode or boot mode is determined after canceling a reset in the FZTAT version
6. Voltage maintained in standby mode
Rev. 6.00 Mar 15, 2005 page 429 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.3
AC Characteristics
Table 17.16 lists the control signal timing and table 17.17 lists the serial interface timing.
Table 17.16 Control Signal Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
Applicable
Pins
System clock
oscillation
frequency
fOSC
OSC1, OSC2
OSC clock (φOSC)
cycle time
tOSC
System clock (φ)
cycle time
tcyc
Values
Test Condition
On-chip oscillator
selected
OSC1, OSC2
On-chip oscillator
selected
Min
Typ
Max
Unit
2.0
—
20.0
MHz
0.7
—
2.0
50.0
—
500
500
—
1429
2
—
128
tOSC
—
—
182
µs
Reference
Figure
*2
ns
Figure 17.1
Subclock oscillation fW
frequency
X1, X2
—
32.768
—
kHz
Watch clock (φW )
cycle time
tW
X1, X2
—
30.5
—
µs
Figure 17.1
Subclock (φSUB)
cycle time
tsubcyc
2
—
8
tW
*1
2
—
—
tcyc
tsubcyc
OSC1,
OSC2
—
—
20
ms
X1, X2
—
—
2.0
s
External clock high tCPH
width
OSC1
20
—
—
ns
Figure 17.1
External clock low
width
tCPL
OSC1
20
—
—
ns
Figure 17.1
External clock rise
time
tCPr
OSC1
—
—
5
ns
Figure 17.1
External clock fall
time
tCPf
OSC1
—
—
5
ns
Figure 17.1
tREL
RES
10
—
—
tcyc
Figure 17.2
Instruction cycle
time
Oscillation
stabilization time
RES pin low
width
trc
Rev. 6.00 Mar 15, 2005 page 430 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Item
Symbol
Input pin high
width
tIH
Applicable
Pins
Values
Test Condition
IRQ0, IRQ1,
IRQAEC,
WKP0 to
WKP7,
AEVL, AEVH
Input pin low
width
tIL
IRQ0, IRQ1,
IRQAEC,
WKP0 to
WKP7,
AEVL, AEVH
Reference
Figure
Min
Typ
Max
Unit
2
—
—
Figure 17.3
tcyc
tsubcyc
0.5
—
—
tOSC
2
—
—
tcyc
Figure 17.3
tsubcyc
0.5
—
—
tOSC
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. These characteristics are given as ranges between minimum and maximum values in
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please see the Web site for this product for actual performance
data.
Table 17.17
Serial Interface (SCI3) Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
Input clock Asynchronous
cycle
Clocked synchronous
tscyc
Test
Condition
Values
Min
Typ Max Unit
Reference
Figure
4
—
—
Figure 17.4
6
—
—
tcyc or
tsubcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tscyc
Figure 17.4
Transmit data delay time
(clocked synchronous)
tTXD
—
—
1
tcyc or
tsubcyc
Figure 17.5
Receive data setup time
(clocked synchronous)
tRXS
150.0
—
—
ns
Figure 17.5
Receive data hold time
(clocked synchronous)
tRXH
150.0
—
—
ns
Figure 17.5
Rev. 6.00 Mar 15, 2005 page 431 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.4
A/D Converter Characteristics
Table 17.18 shows the A/D converter characteristics.
Table 17.18
A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Applicable Test
Pins
Condition
Min
Typ
Max
Unit
Reference
Figure
Analog power supply AVCC
voltage
AVCC
2.7
—
5.5
V
*1
Analog input voltage
AN0 to
AN3
– 0.3
—
AVCC + 0.3 V
—
1.5
mA
600
—
µA
Item
Symbol
AVIN
Analog power supply AIOPE
current
AISTOP1
AVCC
AVCC = 5.0 V —
AVCC
—
*2
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
Analog input
capacitance
CAIN
AN0 to
AN3
—
—
15.0
pF
Allowable signal
source impedance
RAIN
—
—
10.0
kΩ
—
—
10
bit
AVCC = 4.0 V —
to 5.5 V
—
±3.5
LSB
AVCC = 2.7 V —
to 5.5 V
—
±7.5
Resolution (data
length)
Nonlinearity error
Quantization error
—
—
±0.5
LSB
Absolute accuracy
AVCC = 4.0 V —
to 5.5 V
±2.0
±4.0
LSB
AVCC = 2.7 V —
to 5.5 V
±2.0
±8.0
—
124
Conversion time
6.2
*3
µs
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
Rev. 6.00 Mar 15, 2005 page 432 of 502
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Section 17 Electrical Characteristics
17.6.5
LCD Characteristics
Table 17.19 shows the LCD characteristics.
Table 17.19 LCD Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Applicable
Pins
Test Condition
Item
Symbol
Segment driver
step-down voltage
VDS
SEG1 to
SEG25
Common driver
step-down voltage
VDC
COM1 to
COM4
LCD power supply
split-resistance
RLCD
Liquid crystal
display voltage
VLCD
Typ
Max
Unit
Reference
Figure
ID = 2 µA
—
V1 = 2.7 V to 5.5 V
—
0.6
V
*1
ID = 2 µA
—
V1 = 2.7 V to 5.5 V
—
0.3
V
*1
1.5
3.0
7.0
MΩ
2.7
—
5.5
V
Between V1 and
VSS
V1
Min
*2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment
pin or common pin.
2. When the liquid crystal display voltage is supplied from an external power supply,
ensure that the following relationship is maintained: VCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 6.00 Mar 15, 2005 page 433 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.6
Flash Memory Characteristics
Table 17.20
Flash Memory Characteristics
Condition A: AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of
operating voltage when reading), VCC = 3.0 V to 5.5 V (range of operating voltage
when programming/erasing), Ta = –20°C to +75°C (range of operating temperature
when programming/erasing: product with regular specifications, product with widerange temperature specifications)
Test
Conditions
Values
Item
Symbol
Min
Typ
Max
Unit
Programming time*1 *2 *4
tP
—
7
200
ms/128 bytes
1 3 5
Erase time* * *
tE
—
100
1200
Reprogramming count
NWEC
1000*8
10000*9 —
times
Data retain period
tDRP
10*10
—
—
year
Programming
Wait time after
SWE-bit setting*1
x
1
—
—
µs
Wait time after
1
PSU-bit setting *
y
50
—
—
µs
Wait time after
1 4
P-bit setting * *
z1
1≤n≤6
28
30
32
µs
z2
7 ≤ n ≤ 1000
198
200
202
µs
z3
Additional
programming
8
10
12
µs
ms/block
Wait time after
P-bit clear *1
α
5
—
—
µs
Wait time after
PSU-bit clear *1
β
5
—
—
µs
Wait time after
PV-bit setting *1
γ
4
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
PV-bit clear *1
η
2
—
—
µs
Wait time after
SWE-bit clear*1
θ
100
—
—
µs
Maximum
programming
count*1 *4*5
N
—
—
1000
times
Rev. 6.00 Mar 15, 2005 page 434 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Item
Erase
Symbol
Test
Conditions
Values
Min
Typ
Max
Unit
Wait time after
1
SWE-bit setting*
x
1
—
—
µs
Wait time after
ESU-bit setting *1
y
100
—
—
µs
Wait time after
E-bit setting *1 *6
z
10
—
100
ms
Wait time after
E-bit clear *1
α
10
—
—
µs
Wait time after
ESU-bit clear *1
β
10
—
—
µs
Wait time after
EV-bit setting *1
γ
20
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
EV-bit clear *1
η
4
—
—
µs
Wait time after
SWE-bit clear*1
θ
100
—
—
µs
Maximum erase
count*1 *6*7
N
—
—
120
times
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1
is set. It does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = Wait time after P-bit setting (z) • maximum number of writes (N)
5. The maximum number of writes (N) should be set according to the actual set value of
z1, z2, and z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1 and z2) should be alternated according to the
number of writes (n) as follows:
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) • maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z
to allow erasing within the maximum erase time (tE (max)).
8. This minimum value guarantees all characteristics after reprogramming (the guaranteed
range is from 1 to the minimum value).
9. Reference value when the temperature is 25°C (normally reprogramming will be
performed by this count).
Rev. 6.00 Mar 15, 2005 page 435 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
10. This is a data retain characteristic when reprogramming is performed within the
specification range including this minimum value.
17.6.7
Power Supply Voltage Detection Circuit Characteristics
Table 17.21
Power Supply Voltage Detection Circuit Characteristics (1)
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item
Symbol
LVDR operation drop
voltage*
VLVDRmin
LVD stabilization time
VLVDON
Standby mode current
consumption
ISTBY
Test Conditions Min
LVDE = 1
Typ
Max
Unit
1.0
—
—
V
150
—
—
µs
—
—
100
µA
VCC = 5.0 V
32 resonator not
used
Note: * In some cases no reset may occur if the power supply voltage, VCC, drops below
VLVDRmin = 1.0 V and then rises, so thorough evaluation is called for.
Rev. 6.00 Mar 15, 2005 page 436 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.22
Power Supply Voltage Detection Circuit Characteristics (2)
Using on-chip reference voltage and ladder resistor (VREFSEL = VINTDSEL = VINTUSEL = 0)
Rated Values
Item
Symbol
*3
Test Conditions Min
Typ
Max
Unit
Power supply drop
detection voltage
Vint(D)
LVDSEL = 0
3.3
3.7
4.2
V
Power supply rise
detection voltage
Vint(U)*3 LVDSEL = 0
3.6
4.0
4.5
V
Reset detection voltage
1*1
Vreset1*3 LVDSEL = 0
2.0
2.3
2.7
V
Reset detection voltage
2
2*
Vreset2*3 LVDSEL = 1
2.7
3.3
3.9
V
Notes: 1. The above function should be used in conjunction with the voltage drop/rise detection
function.
2. Low-voltage detection reset should be selected for low-voltage detection reset 2 only.
3. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example: If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
Table 17.23
Power Supply Voltage Detection Circuit Characteristics (3)
Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL
and VINTUSEL = 1)
Rated Values
Item
Symbol
extD/extU interrupt
detection level
Vexd
extD/extU pin input
voltage*2
VextD*1
VextU*1
Test Condition
Min
Typ
Max
Unit
0.80
1.20
1.60
V
VCC = 2.7 to 3.3 V –0.3
—
VCC + 0.3 or AVCC
+ 0.3, whichever is
lower
V
VCC = 3.3 to 5.5 V –0.3
—
3.6 or AVCC + 0.3,
whichever is lower
V
Notes: 1. The VextD voltage must always be greater than the VextU voltage.
2. The maximum input voltage of the extD and extU pins is 3.6 V.
Rev. 6.00 Mar 15, 2005 page 437 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
Table 17.24
Power Supply Voltage Detection Circuit Characteristics (4)
Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL =
0)
Item
Test
Condition
Symbol
Rated Values
Min
1
Power supply drop Vint(D) * LVDSEL = 0 3.08 * (Vref1 – 0.1)
Typ
Max
Unit
3.08 * Vref1
3.08 * (Vref1 + 0.1)
V
—
1.68
V
3.33 * Vref2
3.33 * (Vref2 + 0.1)
V
—
1.55
V
1.91 * Vref3
1.91 * (Vref3 + 0.1)
V
—
2.77
V
2.76 * Vref4
2.76 * (Vref4 + 0.1)
V
—
1.89
V
detection voltage
Vref input voltage
(Vint(D))
Power supply rise
detection voltage
Vref1*
2
Vint(D)
0.98
1
Vint(U) * LVDSEL = 0 3.33 * (Vref2 – 0.1)
2
Vref input voltage
(Vint(U))
Vref2*
Reset detection
voltage 1
Vreset1* LVDSEL = 0 1.91 * (Vref3 – 0.1)
Vref input voltage
(Vreset1)
Vref3*
Reset detection
voltage 2
Vreset2* LVDSEL = 1 2.76 * (Vref4 – 0.1)
Vref input voltage
(Vreset2)
Vref4*
Notes:
Vint(U)
0.91
1
2
Vreset1
0.89
1
2
Vreset2
1.08
1. The values of Vint(D), Vint(U), Vreset1, and Vreset2 change relative to each other.
Example:
If Vint(D) is the minimum value, Vint(U), Vreset1, and Vreset2 are also the
minimum values.
2. The Vref input voltage is calculated using the following formula.
2.7 V (= VCC min)
1.5 V (= RAM retention voltage)
Vref1:
Vref2:
Vref3:
Vref4:
2.7 <
2.7 <
1.5 <
2.7 <
3.08
3.33
1.91
2.76
< Vint(D), Vint(U), Vreset2
< Vreset1
* (Vref1 – 0.1), 3.08
* (Vref2 – 0.1), 3.33
* (Vref3 – 0.1), 1.91
* (Vref4 – 0.1), 2.76
Rev. 6.00 Mar 15, 2005 page 438 of 502
REJ09B0024-0600
* (Vref1 +
* (Vref2 +
* (Vref3 +
* (Vref4 +
0.1)
0.1)
0.1)
0.1)
< 5.5 V (= VCC max)
< 5.5 V (= VCC max)
< 5.5 → 0.98 < Vref1 < 1.68
< 5.5 → 0.91 < Vref2 < 1.55
< 5.5 → 0.89 < Vref3 < 2.77
< 5.5 → 1.08 < Vref4 < 1.89
Section 17 Electrical Characteristics
Table 17.25
Power Supply Voltage Detection Circuit Characteristics (5)
Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL =
VINTUSEL = 1)
Rated Values
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Comparator detection
accuracy
Vcdl
| VextU – Vref |
0.1
—
—
V
extD/extU pin input
voltage
VextD*
VextU*
VCC = 2.7 to 3.3 V –0.3
—
VCC + 0.3 or
AVCC + 0.3,
whichever is
lower
V
VCC = 3.3 to 5.5 V –0.3
—
3.6 or AVCC
+ 0.3, whichever
is lower
V
VCC = 2.7 to 5.5 V 0.8
—
2.8
V
Vref pin input voltage
| VextD – Vref |
Vref5
Note: * The VextD voltage must always be greater than the VextU voltage.
17.6.8
Power-On Reset Circuit Characteristics
Table 17.26
Power-On Reset Circuit Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Rated Values
Item
Symbol Test Condition
Min
Typ
Max
Unit
RES pin pull-up
resistance
RRES
65
100
—
kΩ
Power-on reset start
voltage
Vpor
—
—
100
mV
Note: Make sure to drop the power supply voltage, VCC, to below Vpor = 100 mV and then raise it
after the RES pin load had thoroughly dissipated. To drain the load of the RES pin,
attaching a diode to the VCC side is recommended. The power-on reset function may not
work properly if the power supply voltage, VCC, is raised from a level exceeding 100 mV.
Rev. 6.00 Mar 15, 2005 page 439 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.6.9
Watchdog Timer Characteristics
Table 17.27
Watchdog Timer Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
On-chip oscillator
overflow time
tOVF
Applicable
Pins
Rated Values
Test
Condition
Min
Typ
Max
Unit
Note
VCC = 5 V
0.2
0.4
—
s
*
Note: * When the watchdog on-chip oscillator is selected, the timer counts from 0 to 255,
indicating the time remaining until an internal reset is generated.
17.7
Operation Timing
Figures 17.1 to 17.5 show the operation timings.
tOSC, tW
VIH
VIL
OSC1,
X1
tCPH
tCPL
tcpr
tCPf
Figure 17.1 Clock Input Timing
VIL
tREL
Figure 17.2
,
,
to
,
RES Low Width Timing
VIH
VIL
IRQAEC,
tIL
AEVL, AEVH
tIH
Figure 17.3 Input Timing
Rev. 6.00 Mar 15, 2005 page 440 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
tSCKW
SCK32
tscyc
Figure 17.4 SCK3 Input Clock Timing
tscyc
SCK32
VIH or VOH*
VIL or VOL*
tTXD
TXD32
(transmit data)
VOH*
VOL*
tRXS
tRXH
RXD32
(receive data)
Note: * Output timing reference levels
Output high
VOH = 1/2VCC + 0.2 V
Output low
VOL = 0.8 V
Load conditions are shown in figure 17.6.
Figure 17.5 SCI3 Input/Output Timing in Clocked Synchronous Mode
Rev. 6.00 Mar 15, 2005 page 441 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.8
Output Load Condition
VCC
2.4 kΩ
LSI output pin
30 pF
12 kΩ
Figure 17.6 Output Load Circuit
Rev. 6.00 Mar 15, 2005 page 442 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.9
Resonator Equivalent Circuit
LS
CS
RS
OSC1
OSC2
CO
Crystal Resonator Parameter
4
4.193
Ceramic Resonator Parameter
10
Frequency (MHz)
2
4
10
RS (max)
100 Ω 100 Ω 30 Ω
RS (max)
18.3 Ω
6.8 Ω
4.6 Ω
CO (max)
16 pF 16 pF 16 pF
CO (max)
Frequency (MHz)
36.94 pF 36.72 pF 32.31 pF
Figure 17.7 Resonator Equivalent Circuit
LS
CS
RS
OSC2
OSC1
CO
Crystal Resonator Parameter
(Nominal Values by Manufacturer)
Ceramic Resonator Parameter (1)
(Nominal Values by Manufacturer)
Frequency
4
Manufacturer
Frequency
2
Rs (max)
100Ω
Rs (max)
18.3Ω
Co (max)
16pF
NIHON DEMPA
KOGYO
CO., LTD.
Co (max)
Manufacturer
Murata
Manufacturing
36.94pF Co., Ltd.
Ceramic Resonator Parameter (2)
(Nominal Values by Manufacturer)
Frequency
10
Rs (max)
4.6Ω
Co (max)
Manufacturer
Murata
Manufacturing
32.31pF Co., Ltd.
Figure 17.8 Resonator Equivalent Circuit
Rev. 6.00 Mar 15, 2005 page 443 of 502
REJ09B0024-0600
Section 17 Electrical Characteristics
17.10
Usage Note
The ZTAT, F-ZTAT, and mask ROM versions satisfy the electrical characteristics shown in this
manual, but actual electrical characteristic values, operating margins, noise margins, and other
properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns,
and so on.
When system evaluation testing is carried out using the ZTAT or F-ZTAT version, the same
evaluation testing should also be conducted for the mask ROM version when changing over to that
version.
Rev. 6.00 Mar 15, 2005 page 444 of 502
REJ09B0024-0600
Appendix A Instruction Set
Appendix A Instruction Set
A.1
Instruction List
Operation Notation
Symbol
Description
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
Rn8/16
General register (8 or 16 bits )
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#xx:3/8/16
Immediate data (3, 8, or 16 bits)
d:8/16
Displacement (8 or 16 bits)
@aa:8/16
Absolute address (8 or 16 bits)
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move

Logical complement
Rev. 6.00 Mar 15, 2005 page 445 of 502
REJ09B0024-0600
Appendix A Instruction Set
Condition Code Notation
Symbol
Description
Changed according to execution result
*
Undetermined (no guaranteed value)
0
Cleared to 0
—
Not affected by execution result
Rev. 6.00 Mar 15, 2005 page 446 of 502
REJ09B0024-0600
MOV
—
—
—
—
—
—
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
Rs8→@aa:16
#xx:16→Rd
Rs16→Rd16
@Rs16→Rd16
@(d:16, Rs16)→Rd16
@Rs16→Rd16
4
B
W
W
W
W
W
W
W
W
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd)
2
2
4
4
2
4
—
0
—
—
Rs8→@aa:8
2
B
MOV.B Rs, @aa:8
2
—
0
—
—
Rd16-1→Rd16
B
MOV.B Rs, @-Rd
4
—
0
—
—
Rs8→@(d:16, Rd16)
B
MOV.B Rs, @(d:16, Rd)
2
—
0
—
—
Rs8→@Rd16
B
MOV.B Rs, @Rd
4
—
0
—
—
@aa:16→Rd8
4
B
2
—
0
—
—
@aa:8→Rd8
2
B
—
—
—
0
0
0
—
—
—
—
—
—
@aa:16→Rd16
Rs16→@Rd16
Rs16→@(d:16, Rd16)
Rs16+2→Rs16
Rs8→@Rd16
Rs16+1→Rs16
MOV.B @aa:16, Rd
—
0
—
—
@Rs16→Rd8
MOV.B @aa:8, Rd
2
B
—
0
—
—
@(d:16, Rs16)→Rd8
MOV.B @Rs+, Rd
4
B
—
0
—
—
@Rs16→Rd8
MOV.B @(d:16, Rs), Rd
2
B
MOV.B @Rs, Rd
—
0
—
C
—
V
Rs8→Rd8
Z
—
N
0
H
—
I
—
#xx:8→Rd8
B
@@aa —
Condition Code
MOV.B Rs, Rd
2
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Operation
B
Operand
Size
MOV.B #xx:8, Rd
2
#xx:8/16
Addressing Modes/Instruction Length (bytes)
6
4
6
6
6
4
2
4
6
4
6
6
4
6
4
6
6
4
2
2
Number
of Execution
States
Table A.1
Mnemonic
Appendix A Instruction Set
Instruction Set
Rev. 6.00 Mar 15, 2005 page 447 of 502
REJ09B0024-0600
Rev. 6.00 Mar 15, 2005 page 448 of 502
REJ09B0024-0600
C
2
2
SUBX
2
— (1)
Rd16-Rs16→Rd16
2
W
SUB.W Rs, Rd
B
B
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
2
2
2
(2)
(2)
—
—
Rd8-#xx:8-C→Rd8
Rd8-Rs8-C→Rd8
2
2
—
(3)
Rd8-Rs8→Rd8
*
2
—
*
2
—
B
Rd8 decimal adjust→Rd8
—
SUB.B Rs, Rd
2
—
SUB
B
Rd8+1→Rd8
DAA.B Rd
2
DAA
B
2
— —
INC.B Rd
—
—
—
—
Rd16+2→Rd16
2
W
ADDS.W #2, Rd
— —
2
—
—
—
—
Rd16+1→Rd16
2
W
(2)
—
Rd8+Rs8+C→Rd8
ADDS.W #1, Rd
2
(2)
—
Rd8+#xx:8+C→Rd8
INC
ADDS
B
ADDX.B Rs, Rd
2
2
B
ADDX.B #xx:8, Rd
2
2
— (1)
Rd16+Rs16→Rd16
2
W
ADD.W Rs, Rd
ADDX
2
6
—
—
—
0
6
6
6
Rd8+Rs8→Rd8
—
—
—
—
Rd8+#xx:8→Rd8
—
0
0
0
V
2
Z
B
Rs16→@SP
SP-2→SP
—
—
N
B
2
—
—
H
—
ADD.B Rs, Rd
2
I
—
ADD.B #xx:8, Rd
W
SP+2→SP
@SP→Rd16
Rs16→@aa:16
Rs16→@Rd16
Rd16-2→Rd16
ADD
4
@@aa —
PUSH Rs
2
2
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Condition Code
PUSH
W
W
MOV.W Rs, @aa:16
#xx:8/16
Operation
POP Rd
W
Operand
Size
MOV.W Rs, @-Rd
Addressing Modes/Instruction Length (bytes)
Number
of Execution
States
POP
MOV
Mnemonic
Appendix A Instruction Set
SHAL.B Rd
SHAL
B
B
B
XOR.B Rs, Rd
NOT.B Rd
B
B
OR.B Rs, Rd
XOR.B #xx:8, Rd
B
B
B
B
B
B
OR.B #xx:8, Rd
NOT
XOR
OR
AND.B #xx:8, Rd
AND
AND.B Rs, Rd
DIVXU.B Rs, Rd
CMP.W Rs, Rd
DIVXU
W
CMP.B Rs, Rd
MULXU.B Rs, Rd
B
CMP.B #xx:8, Rd
CMP
MULXU
B
NEG.B Rd
NEG
B
DAS.B Rd
DAS
B
DEC.B Rd
2
2
2
2
2
2
2
2
2
b0
—
Rd8 ⊕ Rs8→Rd8
0
—
Rd8 ⊕ #xx:8→Rd8
C
b7
—
—
—
Rd8∨Rs8→Rd8
→Rd
—
—
Rd8∨#xx:8→Rd8
Rd8∧Rs8→Rd8
Rd8∧#xx:8→Rd8
—
—
Rd16 ÷ Rs8→Rd16
(RdH: remainder, RdL: quotient)
—
Rd8×Rs8→Rd16
—
—
—
—
—
—
—
—
—
—
— (1)
Rd16-Rs16
2
2
—
Rd8-Rs8
*
—
2
—
—
—
—
0-Rd→Rd
Rd8 decimal adjust→Rd8
Rd8-1→Rd8
—
—
H
Z
—
—
—
(5) (6)
—
—
—
N
—
0
0
—
—
—
—
0
0
—
—
—
0
0
0
— —
— —
*
2
2
2
2
2
2
2
2
14
14
2
2
2
2
2
2
2
—
2
— —
C
Number
of Execution
States
— —
V
Condition Code
Rd8-#xx:8
2
2
2
—
Rd16-2→Rd16
2
W
SUBS.W #2, Rd
I
—
Rd16-1→Rd16
@@aa —
2
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Operation
W
2
#xx:8/16
Addressing Modes/Instruction Length (bytes)
SUBS.W #1, Rd
Operand
Size
DEC
SUBS
Mnemonic
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 449 of 502
REJ09B0024-0600
Rev. 6.00 Mar 15, 2005 page 450 of 502
REJ09B0024-0600
B
B
B
ROTR.B Rd
BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET
B
ROTXR ROTXR.B Rd
ROTR
B
ROTXL.B Rd
ROTXL
B
B
SHLR.B Rd
SHLR
ROTL.B Rd
B
SHLL.B Rd
SHLL
ROTL
B
SHAR.B Rd
Operand
Size
SHAR
#xx:8/16
2
2
2
2
2
2
2
2
4
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
@@aa —
b7
b7
b7
b7
b7
b7
1
(#xx:3 of @Rd16)
(#xx:3 of Rd8)
C
C
0
C
b7
1
Operation
→
Addressing Modes/Instruction Length (bytes)
→
Mnemonic
b0
b0
b0
b0
b0
b0
b0
C
C
C
0
C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
H
—
I
—
—
—
0
N
—
—
Z
C
— —
— —
0
0
0
0
0
0
0
V
Condition Code
Number
of Execution
States
8
2
2
2
2
2
2
2
2
Appendix A Instruction Set
BTST
BNOT
BCLR
B
BCLR Rn, @aa:8
B
B
B
BTST #xx:3, @aa:8
BTST Rn, Rd
B
BNOT Rn, @aa:8
BTST #xx:3, @Rd
B
BNOT Rn, @Rd
B
B
BNOT Rn, Rd
BTST #xx:3, Rd
B
BNOT #xx:3, @aa:8
B
B
BCLR Rn, @Rd
BNOT #xx:3, @Rd
B
BCLR Rn, Rd
B
B
BCLR #xx:3, @aa:8
BNOT #xx:3, Rd
B
BCLR #xx:3, @Rd
B
BSET Rn, @aa:8
B
B
BSET Rn, @Rd
BCLR #xx:3, Rd
B
Operand
Size
BSET Rn, Rd
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
(#xx:3 of Rd8)
—
—
—
—
—
—
—
—
(#xx:3 of @Rd16)→Z
(#xx:3 of @aa:8)→Z
(Rn8 of Rd8)→Z
—
—
(Rn8 of @aa:8)
—
—
(#xx:3 of Rd8)→Z
(Rn8 of @aa:8)
—
—
—
—
—
—
—
—
—
(Rn8 of @Rd16) —
(Rn8 of Rd8)
(Rn8 of @Rd16)
(Rn8 of Rd8)
(#xx:3 of @aa:8)
(#xx:3 of @aa:8)
(#xx:3 of @Rd16)
(#xx:3 of @Rd16)
(#xx:3 of Rd8)
(Rn8 of @aa:8)
0
—
—
—
—
0
(Rn8 of @Rd16)
(Rn8 of Rd8)
0
—
(#xx:3 of @aa:8)
—
0
—
—
0
—
—
0
—
—
—
—
—
H
—
I
—
—
1
1
(#xx:3 of @Rd16)
(#xx:3 of Rd8)
(Rn8 of @aa:8)
1
1
(Rn8 of @Rd16)
(Rn8 of Rd8)
(#xx:3 of @aa:8)
→
@@aa —
→
→
→
4
→
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
→
→
#xx:8/16
→
B
2
6
6
2
—
—
—
—
—
—
—
—
8
8
2
—
—
—
—
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
—
2
—
—
—
—
8
8
—
—
—
—
—
—
—
—
—
—
—
2
—
8
—
—
—
—
8
—
—
—
—
—
—
—
2
—
8
—
—
—
—
8
—
—
—
—
—
—
—
2
—
8
—
—
—
—
C
—
V
—
Z
—
Number
of Execution
States
—
N
Condition Code
→
→
BSET #xx:3, @aa:8
→
→
→
→
BSET
Operation
→
Addressing Modes/Instruction Length (bytes)
→
Mnemonic
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 451 of 502
REJ09B0024-0600
Rev. 6.00 Mar 15, 2005 page 452 of 502
REJ09B0024-0600
BOR
BIAND
BAND
BIST
BST
BILD
BLD
BTST
B
B
B
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
B
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
B
BIAND #xx:3, @Rd
B
BAND #xx:3, @aa:8
B
B
BAND #xx:3, @Rd
BIAND #xx:3, Rd
B
B
BIST #xx:3, @aa:8
BAND #xx:3, Rd
B
BIST #xx:3, @Rd
B
BST #xx:3, @aa:8
B
B
BST #xx:3, @Rd
BIST #xx:3, Rd
B
B
BILD #xx:3, @aa:8
BST #xx:3, Rd
B
BILD #xx:3, @Rd
B
BLD #xx:3, @aa:8
B
B
BLD #xx:3, @Rd
BILD #xx:3, Rd
B
B
BTST Rn, @aa:8
BLD #xx:3, Rd
B
Operand
Size
BTST Rn, @Rd
Mnemonic
#xx:8/16
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
Addressing Modes/Instruction Length (bytes)
@@aa —
I
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C→(#xx:3 of @Rd16)
C→(#xx:3 of @aa:8)
→(#xx:3 of Rd8)
→(#xx:3 of @Rd16)
→(#xx:3 of @aa:8)
C∧(#xx:3 of Rd8)→C
C∧(#xx:3 of @Rd16)→C
C∧(#xx:3 of @aa:8)→C
C∧(#xx:3 of Rd8)→C
C∧(#xx:3 of @Rd16)→C
C∧(#xx:3 of @aa:8)→C
C∨(#xx:3 of Rd8)→C
C∨(#xx:3 of @Rd16)→C
C∨(#xx:3 of @aa:8)→C
—
(#xx:3 of @aa:8)→C
C→(#xx:3 of Rd8)
—
(#xx:3 of @Rd16)→C
—
—
(#xx:3 of @aa:8)→C
(#xx:3 of Rd8)→C
—
—
—
—
(#xx:3 of @Rd16)→C
(#xx:3 of Rd8)→C
(Rn8 of @aa:8)→Z
(Rn8 of @Rd16)→Z
Operation
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
2
6
6
2
6
6
2
8
8
2
8
—
8
—
—
—
—
—
—
2
—
—
—
—
—
6
—
—
—
—
6
—
—
—
—
—
2
—
—
—
—
6
—
—
—
—
—
—
—
6
—
—
—
—
—
2
—
—
—
—
6
—
—
—
C
—
V
—
Z
—
N
—
Number
of Execution
States
—
H
Condition Code
Appendix A Instruction Set
BCC
BIXOR
BXOR
BIOR
If condition
is true then
PC
else next;
2
2
2
2
—
—
—
—
—
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
4
—
—
—
—
—
—
—
—
—
—
N=1
N ⊕ V=0
N ⊕ V=1
Z∨(N ⊕ V)=0
Z∨(N ⊕ V)=1
2
2
2
2
2
—
—
—
—
—
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
4
4
4
—
—
—
—
—
—
N=0
2
—
BPL d:8
—
4
—
—
—
—
—
—
V=1
2
—
BVS d:8
—
4
—
—
—
—
—
—
V=0
2
—
BVC d:8
—
4
—
—
—
—
—
—
Z=1
2
—
—
4
—
—
—
—
—
—
Z=0
2
—
4
—
—
—
—
—
—
C=1
4
4
—
—
—
—
—
—
—
—
—
—
C∨Z=1
—
4
—
—
—
—
—
—
C∨Z=0
—
4
—
—
4
6
6
—
—
—
2
6
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C=0
PC+d:8
PC
2
—
PC+2
—
C ⊕ (#xx:3 of @aa:8)→C
—
—
—
—
—
—
C ⊕ (#xx:3 of @Rd16)→C
—
—
C ⊕ (#xx:3 of Rd8)→C
PC+d:8
—
C ⊕ (#xx:3 of @aa:8)→C
—
2
—
—
C ⊕ (#xx:3 of @Rd16)→C
—
6
—
—
C ⊕ (#xx:3 of Rd8)→C
—
6
—
—
—
—
—
C∨(#xx:3 of @aa:8)→C
BRN d:8 (BF d:8)
4
4
4
2
—
—
—
—
—
C∨(#xx:3 of @Rd16)→C
C
V
—
Z
—
N
—
H
—
I
Condition Code
—
Branching Condition
Operation
Number
of Execution
States
C∨(#xx:3 of Rd8)→C
PC
4
4
4
@@aa —
2
B
BIXOR #xx:3, @aa:8
2
2
2
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
—
B
BIXOR #xx:3, @Rd
#xx:8/16
BRA d:8 (BT d:8)
B
B
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
B
BXOR #xx:3, @Rd
B
BIOR #xx:3, @aa:8
B
B
BIOR #xx:3, @Rd
BXOR #xx:3, Rd
B
Operand
Size
BIOR #xx:3, Rd
Addressing Modes/Instruction Length (bytes)
→
→
→
Mnemonic
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 453 of 502
REJ09B0024-0600
RTE
RTE
—
—
—
JSR @@aa:8
RTS
—
JSR @aa:16
RTS
—
JSR @Rn
JSR
—
BSR d:8
—
JMP @@aa:8
BSR
—
Operand
Size
JMP @aa:16
2
2
4
4
2
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
2
2
2
2
@@aa —
@aa:8
PC+d:8
Rn16
aa:16
@aa:8
@SP
@SP
@SP
SP+2→SP
PC
SP+2→SP
CCR
SP+2→SP
PC
PC
PC→@SP
SP-2→SP
PC
PC→@SP
SP-2→SP
PC
PC→@SP
SP-2→SP
PC
PC→@SP
SP-2→SP
PC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PC
aa:16
N
—
H
—
I
—
—
—
—
—
—
—
—
Z
—
—
—
—
—
—
—
—
V
Condition Code
—
Operation
Rn16
PC
→
#xx:8/16
→
—
→
→
JMP @Rn
→
Rev. 6.00 Mar 15, 2005 page 454 of 502
REJ09B0024-0600
→
JMP
→
Addressing Modes/Instruction Length (bytes)
→
→
→
Mnemonic
C
—
—
—
—
—
—
—
—
Number
of Execution
States
10
8
8
8
6
6
8
6
4
Appendix A Instruction Set
2
4


XORC #xx:8, CCR
NOP
EEPMOV
XORC
NOP
EEPMOV
2
(6) Set to 1 when the divisor is zero; otherwise cleared to 0.
(5) Set to 1 when the divisor is negative; otherwise cleared to 0.
H8/38004 Group, H8/38002S Group and H8/38104 Group, the number of states required for execution is 4n + 8.
(4) The number of states required for execution is 4n + 9 (n = value of R4L). In the
(3) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(2) Retains its previous value when the result is zero; otherwise cleared to 0.
Notes: (1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
B
B
2
ORC #xx:8, CCR
2
ORC
B
ANDC #xx:8, CCR
2
2
2
@@aa 
ANDC
B
LDC Rs, CCR
2
Rn @Rn @(d:16, Rn) @-Rn/@Rn+ @aa:8/16 @(d:8, PC)
STC CCR, Rd
B
LDC #xx:8, CCR
LDC
#xx:8/16
STC
B
SLEEP

Operand
Size
SLEEP
Addressing Modes/Instruction Length (bytes)
Operation

V


C


2
else next;
Until R4L=0
R4L-1→R4L
R6+1→R6
R5+1→R5
Repeat @R5→@R6
if R4L≠0












(4)
2
2
PC+2
2
CCR ⊕ #xx:8→CCR
PC
2
CCR∨#xx:8→CCR
2
CCR∧#xx:8→CCR
CCR→Rd8
2

Z

2

N

Rs8→CCR

H

I

Condition Code
Number
of Execution
States
#xx:8→CCR
Transit to power-down mode.
→
Mnemonic
Appendix A Instruction Set
Rev. 6.00 Mar 15, 2005 page 455 of 502
REJ09B0024-0600
Appendix A Instruction Set
A.2
Operation Code Map
Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Rev. 6.00 Mar 15, 2005 page 456 of 502
REJ09B0024-0600
2
3
LDC
BNOT
DIVXU
BRN
BCLR
BHI
BTST
BLS
ROTXL
ROTXR
SHLR
ROTL
ROTR
SHAR
STC
4
BOR
5
BSR
BCS
XOR
XORC
6
RTE
BNE
AND
ANDC
7
MOV
NEG
BEQ
NOT
LDC
ADD
BST
BIST
BXOR
BAND
BLT
BIOR
BIXOR
BIAND
BILD
RTS
BCC
OR
ORC
AND
MOV
E
F
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
OR
XOR
D
B
C
CMP
SUBX
A
ADDX
BSET
1
SLEEP
9
8
7
6
BRA
MULXU
SHAL
5
SHLL
4
3
2
1
0
NOP
0
BVC
8
SUB
ADD
MOV
BVS
9
JMP
BPL
DEC
MOV*
EEPMOV
BMI
SUBS
B
ADDS
A
INC
BGE
C
BLT
D
E
JSR
BGT
SUBX
ADDX
Bit manipulation instructions
CMP
MOV
F
BLE
DAS
DAA
Table A.2
Low
High
Appendix A Instruction Set
Operation Code Map
Rev. 6.00 Mar 15, 2005 page 457 of 502
REJ09B0024-0600
Appendix A Instruction Set
A.3
Number of Execution States
The status of execution for each instruction of the H8/300L CPU and the method of calculating the
number of states required for instruction execution are shown below. Table A.4 shows the number
of cycles of each type occurring in each instruction, such as instruction fetch and data read/write.
Table A.3 shows the number of states required for each cycle. The total number of states required
for execution of an instruction can be calculated by the following expression:
Execution states = I • SI + J • SJ + K • SK + L • SL + M • SM + N • SN
Examples: When an instruction is fetched from the on-chip ROM, and the on-chip RAM is
accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 • 2 + 2 • 2 = 8
When an instruction is fetched from the on-chip ROM, a branch address is read from the on-chip
ROM, and the on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,
L=M=N=0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 • 2 + 1 • 2+ 1 • 2 = 8
Rev. 6.00 Mar 15, 2005 page 458 of 502
REJ09B0024-0600
Appendix A Instruction Set
Table A.3
Number of States Required for Execution
Access Location
Execution Status
(Instruction Cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3*
Word data access
SM
—
Internal operation
SN
Note:
*
Table A.4
1
Depends on which on-chip peripheral module is accessed. See section 16.1, Register
Addresses (Address Order).
Number of Cycles in Each Instruction
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W Rs, Rd
1
ADDS.W #1, Rd
1
ADDS.W #2, Rd
1
ADDX.B #xx:8, Rd
1
ADDX.B Rs, Rd
1
AND.B #xx:8, Rd
1
ADDS
ADDX
AND
AND.B Rs, Rd
1
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
BAND #xx:3, @Rd
2
1
BAND #xx:3, @aa:8
2
1
Rev. 6.00 Mar 15, 2005 page 459 of 502
REJ09B0024-0600
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
Bcc
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
BLT d:8
2
BGT d:8
2
BLE d:8
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @Rd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @Rd
2
2
BCLR Rn, @aa:8
2
2
BIAND #xx:3, Rd
1
BIAND #xx:3, @Rd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD #xx:3, @Rd
2
1
BILD #xx:3, @aa:8
2
1
BIOR #xx:3, Rd
1
BIOR #xx:3, @Rd
2
1
BIOR #xx:3, @aa:8
2
1
BCLR
BIAND
BILD
BIOR
Rev. 6.00 Mar 15, 2005 page 460 of 502
REJ09B0024-0600
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
BIST
BIST #xx:3, Rd
1
BIST #xx:3, @Rd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @Rd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @Rd
2
1
BLD #xx:3, @aa:8
2
1
BIXOR
BLD
BNOT
BOR
BSET
BNOT #xx:3, Rd
1
BNOT #xx:3, @Rd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @Rd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @Rd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @Rd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @Rd
2
2
BSET Rn, @aa:8
2
2
BSR
BSR d:8
2
BST
BST #xx:3, Rd
1
BST #xx:3, @Rd
2
2
BST #xx:3, @aa:8
2
2
1
Rev. 6.00 Mar 15, 2005 page 461 of 502
REJ09B0024-0600
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
BTST
BTST #xx:3, Rd
1
BTST #xx:3, @Rd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @Rd
2
1
BTST Rn, @aa:8
2
1
BXOR #xx:3, Rd
1
BXOR #xx:3, @Rd
2
1
BXOR #xx:3, @aa:8
2
1
CMP.B #xx:8, Rd
1
CMP.B Rs, Rd
1
CMP.W Rs, Rd
1
DAA
DAA.B Rd
1
DAS
DAS.B Rd
1
DEC
DEC.B Rd
1
DIVXU
DIVXU.B Rs, Rd
1
EEPMOV
EEPMOV
2
INC
INC.B Rd
1
JMP
JMP @Rn
2
JMP @aa:16
2
JMP @@aa:8
2
JSR @Rn
2
1
JSR @aa:16
2
1
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
BXOR
CMP
JSR
LDC
Rev. 6.00 Mar 15, 2005 page 462 of 502
REJ09B0024-0600
12
2n+2*
1
2
1
1
2
1
2
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
MOV
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @Rs, Rd
1
1
MOV.B @(d:16, Rs), Rd
2
1
MOV.B @Rs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B Rs, @Rd
1
1
MOV.B Rs, @(d:16, Rd)
2
1
MOV.B Rs, @-Rd
1
1
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @Rs, Rd
1
1
MOV.W @(d:16, Rs), Rd 2
1
MOV.W @Rs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W Rs, @Rd
1
1
MOV.W Rs, @(d:16, Rd) 2
1
MOV.W Rs, @-Rd
1
1
MOV.W Rs, @aa:16
2
1
MULXU
MULXU.B Rs, Rd
1
NEG
NEG.B Rd
1
NOP
NOP
1
NOT
NOT.B Rd
1
OR
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
ORC
ORC #xx:8, CCR
1
ROTL
ROTL.B Rd
1
ROTR
ROTR.B Rd
1
ROTXL
ROTXL.B Rd
1
2
2
2
2
12
Rev. 6.00 Mar 15, 2005 page 463 of 502
REJ09B0024-0600
Appendix A Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
ROTXR
ROTXR.B Rd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAR
SHAR.B Rd
1
SHLL
SHLL.B Rd
1
SHLR
SHLR.B Rd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
SUB
SUB.B Rs, Rd
1
SUB.W Rs, Rd
1
SUBS.W #1, Rd
1
SUBS.W #2, Rd
1
POP
POP Rd
1
1
2
PUSH
PUSH Rs
1
1
2
SUBX
SUBX.B #xx:8, Rd
1
SUBX.B Rs, Rd
1
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XORC #xx:8, CCR
1
SUBS
XOR
XORC
Note: n: Specified value in R4L. The source and destination operands are accessed n+1 times
respectively.
Rev. 6.00 Mar 15, 2005 page 464 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
Appendix B I/O Port Block Diagrams
B.1
Port 3 Block Diagrams
SBY
PUCR3
VCC
VCC
P3n
PDR3
VSS
PCR3
Internal data bus
PMR3
AEC module
AEVH(P36)
AEVL(P37)
Legend:
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
n = 7 or 6
Figure B.1(a) Port 3 Block Diagram (Pins P37 and P36)
Rev. 6.00 Mar 15, 2005 page 465 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
SBY
PUCR3
VCC
VCC
P35
PDR3
VSS
PCR3
Legend:
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR2:
Port mode register 2
PUCR3: Port pull-up control register 3
Figure B.1(b) Port 3 Block Diagram (Pin P35)
Rev. 6.00 Mar 15, 2005 page 466 of 502
REJ09B0024-0600
Internal data bus
PMR2
Appendix B I/O Port Block Diagrams
SBY
PUCR3
VCC
P3n
PDR3
Internal data bus
VCC
PCR3
VSS
Legend:
PUCR3: Port pull-up control register 3
PDR3:
Port data register 3
PCR3:
Port control register 3
n = 4 or 3
Figure B.1(c) Port 3 Block Diagram (Pins P34 and P33)
Rev. 6.00 Mar 15, 2005 page 467 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
SBY
TMOFH (P32)
TMOFL (P31)
PUCR3
VCC
VCC
P3n
PDR3
VSS
PCR3
Legend:
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
n = 2 or 1
Figure B.1(d) Port 3 Block Diagram (Pins P32 and P31)
Rev. 6.00 Mar 15, 2005 page 468 of 502
REJ09B0024-0600
Internal data bus
PMR3
Appendix B I/O Port Block Diagrams
Port 4 Block Diagrams
PMR2
Internal data bus
B.2
P43
IRQ0
Legend:
PMR2: Port mode register 2
Figure B.2(a) Port 4 Block Diagram (Pin P43)
Rev. 6.00 Mar 15, 2005 page 469 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
SBY
SCINV3
VCC
SPC32
SCI3 module
P42
PDR4
PCR4
VSS
Legend:
PDR4: Port data register 4
PCR4: Port control register 4
Figure B.2(b) Port 4 Block Diagram (Pin P42)
Rev. 6.00 Mar 15, 2005 page 470 of 502
REJ09B0024-0600
Internal data bus
TXD32
Appendix B I/O Port Block Diagrams
SBY
VCC
SCI3 module
RE32
RXD32
P41
PCR4
VSS
Internal data bus
PDR4
Legend:
PDR4: Port data register 4
SCINV2
PCR4: Port control register 4
Figure B.2(c) Port 4 Block Diagram (Pin P41)
Rev. 6.00 Mar 15, 2005 page 471 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
SBY
SCI3 module
SCKIE32
SCKOE32
VCC
SCKO32
SCKI32
P40
PCR4
VSS
Legend:
PDR4: Port data register 4
PCR4: Port control register 4
Figure B.2(d) Port 4 Block Diagram (Pin P40)
Rev. 6.00 Mar 15, 2005 page 472 of 502
REJ09B0024-0600
Internal data bus
PDR4
Appendix B I/O Port Block Diagrams
B.3
Port 5 Block Diagram
SBY
PUCR5
VCC
VCC
P5n
PDR5
VSS
PCR5
Internal data bus
PMR5
WKPn
Legend:
PDR5:
Port data register 5
PCR5:
Port control register 5
PMR5:
Port mode register 5
PUCR5: Port pull-up control register 5
n = 7 to 0
Figure B.3 Port 5 Block Diagram
Rev. 6.00 Mar 15, 2005 page 473 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
B.4
Port 6 Block Diagram
SBY
PUCR6
PDR6
PCR6
P6n
VSS
Legend:
PDR6:
Port data register 6
PCR6:
Port control register 6
PUCR6: Port pull-up control register 6
n = 7 to 0
Figure B.4 Port 6 Block Diagram
Rev. 6.00 Mar 15, 2005 page 474 of 502
REJ09B0024-0600
Internal data bus
VCC
VCC
Appendix B I/O Port Block Diagrams
Port 7 Block Diagram
SBY
VCC
PDR7
PCR7
P7n
Internal data bus
B.5
VSS
Legend:
PDR7: Port data register 7
PCR7: Port control register 7
n = 7 to 0
Figure B.5 Port 7 Block Diagram
Rev. 6.00 Mar 15, 2005 page 475 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
B.6
Port 8 Block Diagram
SBY
PDR8
PCR8
P80
VSS
Legend:
PDR8: Port data register 8
PCR8: Port control register 8
Figure B.6 Port 8 Block Diagram (Pin P80)
Rev. 6.00 Mar 15, 2005 page 476 of 502
REJ09B0024-0600
Internal data bus
VCC
Appendix B I/O Port Block Diagrams
B.7
Port 9 Block Diagrams
PWM module
PWMn + 1
Internal data bus
SBY
PMR9
P9n
PDR9
VSS
Legend:
PMR9: Port mode register 9
PDR9: Port data register 9
n = 1 or 0
Figure B.7(a) Port 9 Block Diagram (Pins P91 and P90)
P9n
PDR9
Internal data bus
SBY
VSS
Legend:
PDR9: Port data register 9
n = 5 to 2
Figure B.7(b) Port 9 Block Diagram (Pins P95 to P92)
Rev. 6.00 Mar 15, 2005 page 477 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
Internal data bus
SBY
P93
PDR93
VSS
LVD module
VREFSEL
Vref
PDR9: Port data register 9
Figure B.7(c) Port 9 Block Diagram (Pin P93, H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page 478 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
Port A Block Diagram
SBY
VCC
PDRA
PCRA
PAn
Internal data bus
B.8
VSS
Legend:
PDRA: Port data register A
PCRA: Port control register A
n = 3 to 0
Figure B.8 Port A Block Diagram
Rev. 6.00 Mar 15, 2005 page 479 of 502
REJ09B0024-0600
Appendix B I/O Port Block Diagrams
Port B Block Diagrams
Internal data bus
B.9
PBn
A/D module
DEC
AMR3 to AMR0
VIN
n = 3 to 0
Figure B.9(a) Port B Block Diagram
Rev. 6.00 Mar 15, 2005 page 480 of 502
REJ09B0024-0600
Internal data bus
Appendix B I/O Port Block Diagrams
PB0
A/D module
DEC
AMR3 to AMR0
VIN
LVD module
VINTDSEL
extD
Figure B.9(b) Port B Block Diagram (Pin PB0, H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page 481 of 502
REJ09B0024-0600
Internal data bus
Appendix B I/O Port Block Diagrams
PB1
A/D module
DEC
AMR3 to AMR0
VIN
LVD module
VINTUSEL
extU
Figure B.9(c) Port B Block Diagram (Pin PB1, H8/38104 Group Only)
Rev. 6.00 Mar 15, 2005 page 482 of 502
REJ09B0024-0600
Appendix C Port States in Each Operating State
Appendix C Port States in Each Operating State
Table C.1
Port
Port States
Reset
Sleep
Subsleep
Standby
P37 to P31 High
Retained
impedance
Retained
High
Retained
impedance*
Functioning Functioning
P43 to P40 High
Retained
impedance
Retained
High
impedance
Retained
Functioning Functioning
P57 to P50 High
Retained
impedance
Retained
Retained
High
impedance*
Functioning Functioning
P67 to P60 High
Retained
impedance
Retained
Retained
High
impedance*
Functioning Functioning
P77 to P70 High
Retained
impedance
Retained
High
impedance
Retained
Functioning Functioning
P80
High
Retained
impedance
Retained
High
impedance
Retained
Functioning Functioning
P95 to P90 High
Retained
impedance
Retained
High
impedance
Retained
Functioning Functioning
PA3 to PA0 High
Retained
impedance
Retained
High
impedance
Retained
Functioning Functioning
PB3 to PB0 High
High
High
High
impedance impedance impedance impedance
Note:
*
Watch
Subactive Active
High
High
High
impedance impedance impedance
High level output when the pull-up MOS is in on state.
Rev. 6.00 Mar 15, 2005 page 483 of 502
REJ09B0024-0600
Appendix D Product Code Lineup
Appendix D Product Code Lineup
Table D.1
Product Code Lineup of H8/3802 Group
Product Type
H8/3802
PROM
version
Mask ROM
version
H8/3801
H8/3800
Mask ROM
version
Mask ROM
version
Product Code
Regular
product
Model Marking
Package
(Package Code)
HD6473802H
HD6473802H
64-pin QFP (FP-64A)
HD6473802FP
HD6473802FP
64-pin LQFP (FP-64E)
HD6473802P
HD6473802P
64-pin DILP (DP-64S)
Product with
wide-range
temperature
specifications
HD6473802D
HD6473802H
64-pin QFP (FP-64A)
HD6473802FPI
HD6473802FP
64-pin LQFP (FP-64E)
HD6473802Q
HD6473802P
64-pin DILP (DP-64S)
Regular
product
HD6433802H
HD6433802 (***) H
64-pin QFP (FP-64A)
HD6433802FP
HD6433802 (***) FP
64-pin LQFP (FP-64E)
HD6433802P
HD6433802 (***) P
64-pin DILP (DP-64S)
HCD6433802

Die
Product with
wide-range
temperature
specifications
HD6433802D
HD6433802 (***) H
64-pin QFP (FP-64A)
HD6433802FPI
HD6433802 (***) FP
64-pin LQFP (FP-64E)
HD6433802Q
HD6433802 (***) P
64-pin DILP (DP-64S)
Regular
product
HD6433801H
HD6433801 (***) H
64-pin QFP (FP-64A)
HD6433801FP
HD6433801 (***) FP
64-pin LQFP (FP-64E)
HD6433801P
HD6433801 (***) P
64-pin DILP (DP-64S)
HCD6433801

Die
Product with
wide-range
temperature
specifications
HD6433801D
HD6433801 (***) H
64-pin QFP (FP-64A)
HD6433801FPI
HD6433801 (***) FP
64-pin LQFP (FP-64E)
HD6433801Q
HD6433801 (***) P
64-pin DILP (DP-64S)
Regular
product
HD6433800H
HD6433800 (***) H
64-pin QFP (FP-64A)
HD6433800FP
HD6433800 (***) FP
64-pin LQFP (FP-64E)
HD6433800P
HD6433800 (***) P
64-pin DILP (DP-64S)
HCD6433800

Die
HD6433800D
HD6433800 (***) H
64-pin QFP (FP-64A)
HD6433800FPI
HD6433800 (***) FP
64-pin LQFP (FP-64E)
HD6433800Q
HD6433800 (***) P
64-pin DILP (DP-64S)
Product with
wide-range
temperature
specifications
Legend:
(***): ROM code
Rev. 6.00 Mar 15, 2005 page 484 of 502
REJ09B0024-0600
Appendix D Product Code Lineup
Table D.2
Product Code Lineup of H8/38004 Group
Product Type
H8/38004
Flash
memory
version
Regular
product
(2.7 V)
Regular
product
(2.2 V)
Mask ROM
version
H8/38003
Mask ROM
version
Product Code
Model Marking
Package
(Package Code)
HD64F38004H10
64F38004H10
64-pin QFP (FP-64A)
HD64F38004FP10
F38004FP10
64-pin LQFP (FP-64E)
HCD64F38004

Die
HD64F38004H4
64F38004H4
64-pin QFP (FP-64A)
HD64F38004FP4
F38004FP4
64-pin LQFP (FP-64E)
HCD64F38004C4

Die
Product with
wide-range
temperature
specifications
(2.7 V)
HD64F38004H10W 64F38004H10
64-pin QFP (FP-64A)
HD64F38004FP10W F38004FP10
64-pin LQFP (FP-64E)
Regular
product
HD64338004H
HD64338004H
64-pin QFP (FP-64A)
HD64338004FP
38004 (***) FP
64-pin LQFP (FP-64E)
HCD64338004

Die
Product with
wide-range
temperature
specifications
HD64338004HW
HD64338004H
64-pin QFP (FP-64A)
HD64338004FPW
38004 (***) FP
64-pin LQFP (FP-64E)
Regular
product
HD64338003H
HD64338003H
64-pin QFP (FP-64A)
HD64338003FP
38003 (***) FP
64-pin LQFP (FP-64E)
HCD64338003

Die
Product with
wide-range
temperature
specifications
HD64338003HW
HD64338003H
64-pin QFP (FP-64A)
HD64338003FPW
38003 (***) FP
64-pin LQFP (FP-64E)
Rev. 6.00 Mar 15, 2005 page 485 of 502
REJ09B0024-0600
Appendix D Product Code Lineup
Product Code
Model Marking
Package
(Package Code)
Regular
product
(2.7 V)
HD64F38002H10
64F38002H10
64-pin QFP (FP-64A)
HD64F38002FP10
F38002FP10
64-pin LQFP (FP-64E)
HCD64F38002

Die
Regular
product
(2.2 V)
HD64F38002H4
64F38002H4
64-pin QFP (FP-64A)
HD64F38002FP4
F38002FP4
64-pin LQFP (FP-64E)
HCD64F38002C4

Die
Product Type
H8/38002
Flash
memory
version
Mask ROM
version
H8/38001
H8/38000
Mask ROM
version
Mask ROM
version
Product with
wide-range
temperature
specifications
(2.7 V)
HD64F38002H10W 64F38002H10
64-pin QFP (FP-64A)
HD64F38002FP10W F38002FP10
64-pin LQFP (FP-64E)
Regular
product
HD64338002H
HD64338002H
64-pin QFP (FP-64A)
HD64338002FP
38002 (***) FP
64-pin LQFP (FP-64E)
HCD64338002

Die
Product with
wide-range
temperature
specifications
HD64338002HW
HD64338002H
64-pin QFP (FP-64A)
HD64338002FPW
38002 (***) FP
64-pin LQFP (FP-64E)
Regular
product
HD64338001H
HD64338001H
64-pin QFP (FP-64A)
HD64338001FP
38001 (***) FP
64-pin LQFP (FP-64E)
HCD64338001

Die
Product with
wide-range
temperature
specifications
HD64338001HW
HD64338001H
64-pin QFP (FP-64A)
HD64338001FPW
38001 (***) FP
64-pin LQFP (FP-64E)
Regular
product
HD64338000H
HD64338000H
64-pin QFP (FP-64A)
HD64338000FP
38000 (***) FP
64-pin LQFP (FP-64E)
HCD64338000

Die
HD64338000HW
HD64338000H
64-pin QFP (FP-64A)
HD64338000FPW
38000 (***) FP
64-pin LQFP (FP-64E)
Product with
wide-range
temperature
specifications
Legend:
(***): ROM code
Rev. 6.00 Mar 15, 2005 page 486 of 502
REJ09B0024-0600
Appendix D Product Code Lineup
Table D.3
Product Code Lineup of H8/38002S Group
Product Code
Model Marking
Package
(Package Code)
Regular
product
HD64338002SH
38002 (***) H
64-pin QFP (FP-64A)
HD64338002SFZ
38002 (***)
64-pin LQFP (FP-64K)
Product with
wide-range
temperature
specifications
HD64338002SHW
38002 (***) H
64-pin QFP (FP-64A)
HD64338002SFZW 38002 (***)
64-pin LQFP (FP-64K)
Regular
product
HD64338001SH
38001 (***) H
64-pin QFP (FP-64A)
HD64338001SFZ
38001 (***)
64-pin LQFP (FP-64K)
Product with
wide-range
temperature
specifications
HD64338001SHW
38001 (***) H
64-pin QFP (FP-64A)
HD64338001SFZW 38001 (***)
64-pin LQFP (FP-64K)
Regular
product
HD64338000SH
38000 (***) H
64-pin QFP (FP-64A)
HD64338000SFZ
38000 (***)
64-pin LQFP (FP-64K)
Product with
wide-range
temperature
specifications
HD64338000SHW
38000 (***) H
64-pin QFP (FP-64A)
Product Type
H8/38002S
H8/38001S
H8/38000S
Mask ROM
version
Mask ROM
version
Mask ROM
version
HD64338000SFZW 38000 (***)
64-pin LQFP (FP-64K)
Legend:
(***): ROM code
Rev. 6.00 Mar 15, 2005 page 487 of 502
REJ09B0024-0600
Appendix D Product Code Lineup
Table D.4
Product Code Lineup of H8/38104 Group
Product Code
Model Marking
Package
(Package Code)
HD64F38104H
F38104H
64-pin QFP (FP-64A)
HD64F38104FP
F38104FP
64-pin LQFP (FP-64E)
Product with
wide-range
temperature
specifications
HD64F38104HW
F38104H
64-pin QFP (FP-64A)
HD64F38104FPW
F38104FP
64-pin LQFP (FP-64E)
Regular
product
HD64338104H
38104(***)H
64-pin QFP (FP-64A)
HD64338104FP
38104(***)
64-pin LQFP (FP-64E)
Product with
wide-range
temperature
specifications
HD64338104HW
38104(***)H
64-pin QFP (FP-64A)
HD64338104FPW
38104(***)
64-pin LQFP (FP-64E)
Regular
product
HD64338103H
38103(***)H
64-pin QFP (FP-64A)
HD64338103FP
38103(***)
64-pin LQFP (FP-64E)
HD64338103HW
38103(***)H
64-pin QFP (FP-64A)
HD64338103FPW
38103(***)
64-pin LQFP (FP-64E)
Product Type
H8/38104
Flash
memory
version
Mask ROM
version
H8/38103
Mask ROM
version
Regular
product
Product with
wide-range
temperature
specifications
H8/38102
Flash
memory
version
Mask ROM
version
H8/38101
Mask ROM
version
Regular
product
HD64F38102H
F38102H
64-pin QFP (FP-64A)
HD64F38102FP
F38102FP
64-pin LQFP (FP-64E)
Product with
wide-range
temperature
specifications
HD64F38102HW
F38102H
64-pin QFP (FP-64A)
HD64F38102FPW
F38102FP
64-pin LQFP (FP-64E)
Regular
product
HD64338102H
38102(***)H
64-pin QFP (FP-64A)
HD64338102FP
38102(***)
64-pin LQFP (FP-64E)
Product with
wide-range
temperature
specifications
HD64338102HW
38102(***)H
64-pin QFP (FP-64A)
HD64338102FPW
38102(***)
64-pin LQFP (FP-64E)
Regular
product
HD64338101H
38101(***)H
64-pin QFP (FP-64A)
HD64338101FP
38101(***)
64-pin LQFP (FP-64E)
HD64338101HW
38101(***)H
64-pin QFP (FP-64A)
HD64338101FPW
38101(***)
64-pin LQFP (FP-64E)
Product with
wide-range
temperature
specifications
Rev. 6.00 Mar 15, 2005 page 488 of 502
REJ09B0024-0600
Appendix D Product Code Lineup
Product Type
H8/38100
Mask ROM
version
Regular
product
Product with
wide-range
temperature
specifications
Product Code
Model Marking
Package
(Package Code)
HD64338100H
38100(***)H
64-pin QFP (FP-64A)
HD64338100FP
38100(***)
64-pin LQFP (FP-64E)
HD64338100HW
38100(***)H
64-pin QFP (FP-64A)
HD64338100FPW
38100(***)
64-pin LQFP (FP-64E)
Legend:
(***): ROM code
Rev. 6.00 Mar 15, 2005 page 489 of 502
REJ09B0024-0600
Appendix E Package Dimensions
Appendix E Package Dimensions
The package dimensions are shown in figure E.1 (FP-64A), figure E.2 (FP-64E), figure E.3 (FP64K), and figure E.4 (DP-64S).
JEITA Package Code
P-QFP64-14x14-0.80
RENESAS Code
PRQP0064GB-A
Previous Code
FP-64A/FP-64AV
MASS[Typ.]
1.2g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
48
33
32
49
bp
Reference
Symbol
D
c
c1
HE
Dimension in Millimeters
Min
Nom
Max
14
E
14
A2
2.70
*2
E
b1
ZE
Terminal cross section
17
17.2
17.5
16.9
17.2
17.5
A1
0.00
0.10
0.25
bp
0.29
0.37
0.45
θ
A1
L
L1
Detail F
y
bp
0.35
x
M
θ
0.22
8˚
0˚
0.8
0.15
x
0.10
y
1.0
ZD
1.0
ZE
L1
Rev. 6.00 Mar 15, 2005 page 490 of 502
REJ09B0024-0600
0.17
0.15
e
L
Figure E.1 Package Dimensions (FP-64A)
0.12
c1
c
A
A2
c
F
*3
3.05
b1
16
ZD
e
16.9
HE
A
64
1
HD
0.5
0.8
1.6
1.1
Appendix E Package Dimensions
JEITA Package Code
P-LQFP64-10x10-0.50
RENESAS Code
PLQP0064KC-A
Previous Code
FP-64E/FP-64EV
MASS[Typ.]
0.4g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
48
33
49
32
bp
Reference
Symbol
c
c1
HE
Terminal cross section
17
1
16
Index mark
10
A2
1.45
HD
11.8
12.0
12.2
HE
11.8
12.0
12.2
A1
0.00
0.10
0.20
bp
0.17
0.22
0.27
1.70
0.20
c
A2
A1
L
L1
*3
Detail F
bp
x
M
0.12
θ
0˚
e
0.22
8˚
0.5
x
0.08
y
0.10
1.25
ZD
ZE
y
0.17
0.15
c1
θ
e
E
c
F
Max
10
b1
A
ZD
Nom
A
ZE
64
Dimension in Millimeters
Min
D
*2
E
b1
L
L1
1.25
0.3
0.5
0.7
1.0
Figure E.2 Package Dimensions (FP-64E)
Rev. 6.00 Mar 15, 2005 page 491 of 502
REJ09B0024-0600
Appendix E Package Dimensions
JEITA Package Code
RENESAS Code
P-LQFP64-10x10-0.50
PLQP0064KB-A
Previous Code
64P6Q-A / FP-64K / FP-64KV
MASS[Typ.]
0.3g
HD
*1
D
48
33
49
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
32
bp
64
1
1
c1
Terminal cross section
ZE
17
Reference
Symbol
c
E
*2
HE
b1
Dimension in Millimeters
Min
Nom
Max
D
9.9
10.0
10.1
E
9.9
10.0
10.1
HD
11.8
12.0
HE
11.8
12.0
12.2
A1
0.05
0.1
0.15
bp
0.15
0.20
0.25
A2
6
Index mark
1.4
A
ZD
F
1.7
c
A
A2
b1
c
0.18
0.09
c1
0.145
*3
A1
y
bp
L
x
L1
e
8˚
0.5
0.08
x
y
Detail F
0.08
ZD
1.25
ZE
L
L1
Figure E.3 Package Dimensions (FP-64K)
Rev. 6.00 Mar 15, 2005 page 492 of 502
REJ09B0024-0600
0.20
0.125
0˚
e
12.2
1.25
0.35
0.5
1.0
0.65
Appendix E Package Dimensions
JEITA Package Code
P-SDIP64-17x57.6-1.78
RENESAS Code
PRDP0064BB-A
Previous Code
DP-64S/DP-64SV
MASS[Typ.]
8.8g
D
33
E
64
1
32
b3
Z
Dimension in Millimeters
Min
Nom
19.05
D
57.6
58.5
E
17.0
18.6
A
e
bp
Max
e1
A
L
A1
Reference
Symbol
θ
c
e1
5.08
A1
0.51
bp
0.38
c
0.20
θ
0˚
e
1.53
0.58
0.25
0.36
15˚
1.78
2.03
1.46
Z
L
0.48
1.0
b3
2.54
Figure E.4 Package Dimensions (DP-64S)
Rev. 6.00 Mar 15, 2005 page 493 of 502
REJ09B0024-0600
Appendix F Chip Form Specifications
Appendix F Chip Form Specifications
Maximum dimensions
in chip's plane
X direction 3.60 ± 0.25
Y direction 3.73 ± 0.25
Max 0.03
0.28 ± 0.02
X direction 3.60 ± 0.05
Y direction 3.73 ± 0.05
Unit: mm
Figure F.1 Cross-Sectional View of Chip (HCD6433802, HCD6433801, and HCD6433800)
Maximum dimensions
in chip's plane
X direction 2.73 ± 0.25
Y direction 3.27 ± 0.25
Max 0.03
0.28 ± 0.02
X direction 2.73 ± 0.05
Y direction 3.27 ± 0.05
Unit: mm
Figure F.2 Cross-Sectional View of Chip (HCD64338004, HCD64338003, HCD64338002,
HCD64338001, and HCD64338000)
Rev. 6.00 Mar 15, 2005 page 494 of 502
REJ09B0024-0600
Appendix F Chip Form Specifications
Maximum dimensions
in chip's plane
X direction 4.09 ± 0.25
Y direction 3.82 ± 0.25
max 0.03
0.28 ± 0.02
X direction 4.09 ± 0.05
Y direction 3.82 ± 0.05
Unit: mm
Figure F.3 Cross-Sectional View of Chip (HCD64F38004 and HCD64F38002)
Rev. 6.00 Mar 15, 2005 page 495 of 502
REJ09B0024-0600
Appendix A Instruction Set
Appendix G Bonding Pad Form
5µm
72µm
Bonding area
Metallic film is visible
from here
72µm
5µm
Figure G.1 Bonding Pad Form (HCD6433802, HCD6433801, HCD6433800, HCD64338004,
HCD64338003, HCD64338002, HCD64338001, HCD64338000, HCD64F38004,
and HCD64F38002)
Rev. 6.00 Mar 15, 2005 page 496 of 502
REJ09B0024-0600
Appendix H Chip Tray Specifications
Appendix H Chip Tray Specifications
51
Chip orientation
3.73
Product
name
Chip
51
3.60
4.9 ± 0.1
5.9 ± 0.1
1.8 ± 0.1
0.6 ± 0.1
4.0 ± 0.05
4.9 ± 0.1
5.9 ± 0.1
X'
4.0 ± 0.1
X
4.0 ± 0.05
Chip tray code
Manufactured by DAINIPPON INK
AND CHEMICALS, INCORPORATED
Product code: CT065
Characteristic engraving: TCT4040-060
Unit: mm
Cross-sectional view: X to X'
Figure H.1 Chip Tray Specifications (HCD6433802, HCD6433801, and HCD6433800)
Rev. 6.00 Mar 15, 2005 page 497 of 502
REJ09B0024-0600
Appendix H Chip Tray Specifications
51
Chip orientation
3.27
Product
name
Chip
51
2.73
4.48 ± 0.1
5.34 ± 0.1
1.8 ± 0.1
0.6 ± 0.1
3.6 ± 0.05
4.48 ± 0.1
5.34 ± 0.1
X'
4.0 ± 0.1
X
3.6 ± 0.05
Chip tray code
Manufactured by DAINIPPON INK
AND CHEMICALS, INCORPORATED
Product code: CT022
Characteristic engraving: TCT036036-060
Unit: mm
Cross-sectional view: X to X'
Figure H.2 Chip Tray Specifications (HCD64338004, HCD64338003, HCD64338002,
HCD64338001, and HCD64338000)
Rev. 6.00 Mar 15, 2005 page 498 of 502
REJ09B0024-0600
Appendix H Chip Tray Specifications
51
Chip orientation
3.82
Product
name
Chip
51
4.09
6.2 ± 0.1
6.9 ± 0.1
1.8 ± 0.1
0.6 ± 0.1
4.5 ± 0.05
6.2 ± 0.1
6.9 ± 0.15
X'
4.0 ± 0.1
X
4.5 ± 0.05
Chip tray code
Manufactured by DAINIPPON INK
AND CHEMICALS, INCORPORATED
Product code: CT015
Characteristic engraving: TCT45-060P
Unit: mm
Cross-sectional view: X to X'
Figure H.3 Chip Tray Specifications (HCD64F38004 and HCD64F38002)
Rev. 6.00 Mar 15, 2005 page 499 of 502
REJ09B0024-0600
Appendix H Chip Tray Specifications
Rev. 6.00 Mar 15, 2005 page 500 of 502
REJ09B0024-0600
Index
Index
10-bit PWM ............................................ 309
A/D converter ......................................... 317
Clock pulse generators
Prescaler S .......................................... 102
Prescaler W......................................... 102
Subclock generator ............................. 100
System clock generator......................... 96
Interrupt mask bit (I)................................. 35
LCD controller/driver ............................. 329
LCD display........................................ 339
LCD RAM .......................................... 341
Package ....................................................... 3
Pin arrangement .......................................... 7
Exception handling ................................... 73
Reset exception handling...................... 83
Stack status ........................................... 87
Flash memory ......................................... 141
Auto-erase mode................................. 169
Auto-program mode ........................... 167
Boot mode .......................................... 148
Boot program...................................... 148
Erase/erase-verify ............................... 157
Erasing units ....................................... 143
Error protection .................................. 159
Hardware protection ........................... 159
Memory read mode............................. 164
On-board programming modes........... 148
Power-down state ............................... 174
Program/program-verify..................... 153
Programmer mode .............................. 160
Programming units ............................. 143
Socket adapter .................................... 160
Software protection ............................ 159
Status polling ...................................... 172
Status read mode................................. 170
Interrupt
Internal interrupts ................................. 85
Interrupt response time ......................... 87
IRQ interrupts....................................... 84
WKP interrupts..................................... 84
Power-down modes................................. 109
Module standby function .................... 128
Sleep mode.......................................... 120
Standby mode ..................................... 121
Subactive mode................................... 122
Subsleep mode .................................... 122
Register
ADRR ......................... 319, 367, 371, 374
ADSR.......................... 321, 367, 371, 374
AEGSR ....................... 239, 366, 370, 373
AMR ........................... 320, 367, 371, 374
BRR ............................ 269, 366, 370, 373
CKSTPR1 ................... 114, 368, 372, 375
CKSTPR2 ................... 114, 368, 372, 375
EBR............................. 146, 366, 370, 373
ECCR.......................... 240, 366, 370, 373
ECCSR........................ 241, 366, 370, 373
ECPWCR.................... 237, 366, 370, 373
ECPWDR.................... 238, 366, 370, 373
FENR .......................... 147, 366, 370, 373
FLMCR1..................... 145, 366, 370, 373
FLMCR2..................... 146, 366, 370, 373
FLPWCR .................... 147, 366, 370, 373
IEGR ............................. 77, 368, 372, 375
IENR ............................. 78, 368, 372, 375
IRR................................ 80, 368, 372, 375
IWPR ............................ 82, 368, 372, 375
Rev. 6.00 Mar 15, 2005 page 501 of 502
REJ09B0024-0600
Index
LCR .............................336, 367, 371, 374
LCR2 ...........................338, 367, 371, 374
LPCR ...........................333, 367, 371, 374
OCR.............................222, 367, 371, 374
PCR3 ...........................180, 368, 372, 375
PCR4 ...........................187, 368, 372, 375
PCR5 ...........................191, 368, 372, 375
PCR6 ...........................195, 368, 372, 375
PCR7 ...........................199, 368, 372, 375
PCR8 ...........................201, 368, 372, 375
PCRA...........................206, 368, 372, 375
PDR3 ...........................180, 367, 371, 374
PDR4 ...........................186, 367, 371, 374
PDR5 ...........................191, 368, 371, 374
PDR6 ...........................195, 368, 371, 374
PDR7 ...........................198, 368, 371, 374
PDR8 ...........................201, 368, 371, 374
PDR9 ...........................203, 368, 371, 374
PDRA ..........................206, 368, 371, 374
PDRB ..........................209, 368, 371, 374
PMR2 ..........................183, 367, 371, 374
PMR3 ..........................182, 367, 371, 374
PMR5 ..........................192, 367, 371, 374
PMR9 ..........................204, 368, 372, 375
PMRB..........................209, 368, 372, 375
PUCR3 ........................181, 368, 372, 375
PUCR5 ........................192, 368, 372, 375
PUCR6 ........................196, 368, 372, 375
PWCR..........................312, 367, 371, 374
PWDR .........................314, 367, 371, 374
RDR.............................260, 367, 370, 373
RSR .................................................... 259
SCR3 ...........................264, 366, 370, 373
SMR.............................261, 366, 370, 373
SPCR ...........................187, 366, 370, 373
Rev. 6.00 Mar 15, 2005 page 502 of 502
REJ09B0024-0600
SSR ............................. 266, 367, 370, 373
SYSCR1...................... 110, 368, 372, 375
SYSCR2...................... 113, 368, 372, 375
TCA ............................ 217, 367, 370, 373
TCR ............................ 223, 367, 371, 374
TCSR .......................... 224, 367, 371, 374
TCSRW....................... 251, 367, 370, 373
TCW ........................... 253, 367, 370, 373
TDR ............................ 260, 367, 370, 373
TMA ........................... 216, 367, 370, 373
TSR..................................................... 260
WEGR........................... 83, 366, 370, 373
Serial communication interface 3 (SCI3) 257
Asynchronous mode ........................... 275
Bit rate ................................................ 269
Break................................................... 303
Clocked synchronous mode ................ 287
Framing error ...................................... 283
Mark state ........................................... 303
Multiprocessor communication function
........................................................ 295
Overrun error ...................................... 283
Parity error .......................................... 283
Timer A................................................... 215
Timer F ................................................... 219
16-bit timer mode ............................... 227
8-bit timer mode ................................. 228
Vector address .......................................... 76
Watchdog timer ...................................... 250
Renesas 8-Bit Single-Chip Microcomputer
Hardware Manual
H8/3802, H8/38004, H8/38002S, H8/38104 Group
Publication Date: 1st Edition, November, 1999
Rev.6.00, March 15, 2005
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Technical Documentation & Information Department
Renesas Kodaira Semiconductor Co., Ltd.
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
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7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
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10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
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Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
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1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Colophon 2.0
H8/3802, H8/38004,
H8/38002S, H8/38104 Group