ICST ICS839893I Low skew, 1-to-13 lvcmos/lvttl buffer divider Datasheet

ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
GENERAL DESCRIPTION
FEATURES
The ICS839893I is a high-performance one to
thirteen LVCMOS/LVTTL buffer/divider and is
HiPerClockS™ a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
device has two selectable LVCMOS/LVTTL
clock inputs and it generates 13 new LVCMOS/LVTTL clock
outputs. The first bank of six outputs offers divide-by-1, 2, 4,
8 or 16. The second bank of six outputs can be configured to
the same divide ratio as the first bank, or with an additional
divide-by-two. The first two banks can be placed into a highimpedance output state with the assertion of a LOW on the
nOE/MR input. One additional output can be configured
to divide-by-4, 6, 8 or 16. This device is functional with full
3.3V or full 2.5V supplies.
• 13 LVCMOS/LVTTL outputs: 3 banks (6, 6, 1 outputs per
bank respectively)
ICS
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
• CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Output skew: 40ps (maximum), within bank
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free compliant
packages
SIMPLIFIED BLOCK DIAGRAM
PIN ASSIGNMENT
V DD
nc
REF_SEL
nc
GND
FSEL0
FSEL1
GND
FSEL2
FSEL3
nOE/MR
V DD
nOE/MR
FSEL0
FSEL0 FSEL1
FSEL1 FSEL2
FSEL2QAQA
0
0
0
÷1
CLK0
0
CLK1
1
REF_SEL
0
0
0
÷1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷2
÷2
÷4
÷2
÷16
÷8
÷4
GND
QA0:QA5 QA0
QA1
VDDO_A
GND
QA2
QB0:QB5 QA3
VDDO_A
GND
QA4
QA5
VDDO_A
QC
D Q
0
÷2
1
D Q
FSEL0 FSEL1 FSEL2 QC
0
0
÷8
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷8
÷6
÷8
÷4
÷16
÷8
÷4
D Q
ICS839893I
GND
QB0
QB1
VDDO_B
GND
QB2
QB3
VDDO_B
GND
QB4
QB5
VDDO_B
GND
QC
nc
nc
VDDO _C
CLK0
CLK1
V DD
nc
nc
nc
GND
0
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
41
20
48-Pin LQFP
42
7mm x 7mm x 1.4mm 19
43
18
body package
17
44
Y Package
45
16
46
15
Top View
14
47
48
13
1 2 3 4 5 6 7 8 9 10 11 12
FSEL[0:2]
FSEL3
839893AYI
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1
REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
TABLE 1. PIN DESCRIPTIONS
Number
1, 12, 16, 20, 24, 29,
32, 37, 41, 45
2
Name
3, 4, 9, 10, 11, 33, 35
Type
Description
GND
Power
Supply ground.
QC
Output
Bank C output. LVCMOS / LVTTL interface levels.
nc
Unused
No connect.
5
VDDO_C
Power
6, 7
CLK0, CLK1
Input
8, 25, 36
VDD
Power
Core supply pins.
13, 17, 21
14, 15,
18, 19,
22, 23
VDDO_B
QB5, QB4
QB3, QB2
QB1, QB0
Power
Output supply pins for Bank B outputs.
Output
Bank B outputs. LVCMOS / LVTTL interface levels.
Output supply pin for Bank C output.
Pulldown LVCMOS / LVTTL clock inputs.
26
nOE/MR
Input
Active High Master Reset. Active Low Output Enable.
When logic LOW, the internal dividers and the outputs are
Pulldown enabled. When logic HIGH, the internal dividers are reset and
the outputs are tri-stated (HiZ). LVCMOS / LVTTL interface
levels.
27,
28,
30,
31
FSEL3,
FSEL2,
FSEL1,
FSEL0
Input
Pulldown
34
REF_SEL
Input
Selects the primar y reference clock. When LOW, selects CLK0
Pulldown as the primar y clock source. When HIGH, selects CLK1 as the
primar y clock source. LVCMOS / LVTTL interface levels.
38, 39
42, 43,
46, 47
QA0, QA1,
QA2, QA3,
QA4, QA5
Output
Bank A outputs. LVCMOS / LVTTL interface levels.
40, 44, 48
VDDO_A
Power
Output supply pins for Bank A outputs.
Clock frequency selection and configuration of clock divider
modes. LVCMOS / LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CPD
Power Dissipation Capacitance
(per output)
9
pF
9
pF
ROUT
Ouput Impedance
14
Ω
VDD = VDDA = VDDO_x = 3.465V
VDD = VDDA = VDDO_x = 2.625V
NOTE: VDDO_X denotes VDDO_A, VDDO_B, VDDO_C.
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REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
TABLE 3. CLOCK FREQUENCY FUNCTION TABLE
Inputs
Outputs
FSEL0
FSEL1
FSEL2
FSEL3
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
839893AYI
fREF Range
(MHz)
QAx
QBx
QC
fQAx (MHz)
fQBx (MHz)
fQC0 (MHz)
DC - 250
fREF ÷ 1
DC - 250
fREF ÷ 2
DC - 250
fREF ÷ 2
DC - 250
fREF ÷ 4
DC - 250
fREF ÷ 2
DC - 250
fREF ÷ 16
DC - 250
fREF ÷ 8
DC - 250
fREF ÷ 4
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fREF ÷ 1
fREF ÷ 2
fREF ÷ 2
fREF ÷ 4
fREF ÷ 2
fREF ÷ 4
fREF ÷ 4
fREF ÷ 8
fREF ÷ 2
fREF ÷ 4
fREF ÷ 16
fREF ÷ 32
fREF ÷ 8
fREF ÷ 16
fREF ÷ 4
fREF ÷ 8
fREF ÷ 8
fREF ÷ 8
fREF ÷ 6
fREF ÷ 8
fREF ÷ 4
fREF ÷ 16
fREF ÷ 8
fREF ÷ 4
REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO_X + 0.5V
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
V
3.135
3. 3
3.465
V
VDDO_A,
VDDO_B,
VDDO_C
Output Supply Voltage
IDD
Power Supply Current
155
mA
IDDO_A,
IDDO_B,
IDDO_C
Output Supply Current
20
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5±5%, TA = -40°C TO 85°C
Symbol Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
2.375
2. 5
2.625
V
VDDO_A,
VDDO_B,
VDDO_C
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
150
mA
IDDO_A,
IDDO_B,
IDDO_C
Output Supply Current
20
mA
839893AYI
Test Conditions
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REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum
Units
VIH
Input High Voltage
VDD = 3.3V
2
VDD + 0.3
V
VIL
Input Low Voltage
VDD = 3.3V
-0.3
0.8
V
IIH
Input High Current
20 0
µA
IIL
VOH
CLK0, CLK1,
nOE/MR, REF_SEL
FSEL0:FSEL3
CLK0, CLK1,
Input Low Current nOE/MR, REF_SEL
FSEL0:FSEL3
Output High Voltage; NOTE 1
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
-5
µA
2.6
VOL
Output Low Voltage; NOTE 1
Note 1: Outputs terminated with 50Ω to VDDO_x/2. See Parameter Measurement Information,
3.3V Output Load Test Circuit diagram.
V
0.5
V
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Maximum
Units
VIH
Input High Voltage
Test Conditions
1.7
VDD + 0.3
V
VIL
Input Low Voltage
-0.3
0.7
V
20 0
µA
VOH
CLK0, CLK1,
Input High Current nOE/MR, REF_SEL
FSEL0:FSEL3
CLK0, CLK1,
Input Low Current nOE/MR, REF_SEL
FSEL0:FSEL3
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
IIH
IIL
Minimum Typical
VDD = VIN = 2.625V
VDD = 2.625V, VIN = 0V
-5
µA
1.8
V
0.5
V
Note 1: Outputs terminated with 50Ω to VDDO_x/2. See Parameter Measurement Information,
2.5V Output Load Test Circuit diagram.
839893AYI
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REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Maximum
Units
DC
250
MHz
Input Frequency
DC
250
MHz
Propagation Delay;NOTE 1
4.5
6.5
ns
40
ps
fOUT
Output Frequency
fREF
tPD
Minimum
Typical
within bank
tsk(o)
Output Skew; NOTE 2 bank-to-bank
Excludes QC
any output to QC
20% to 80%
ps
ps
tR/tF
Output Rise/Fall Time
600
ps
tPZL, tPZH
Output Enable Time
10
ns
tPLZ, tPHZ
Output Disable Time
10
ns
53
%
Maximum
Units
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 output crossing point.
250
115
465
47
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
fOUT
Output Frequency
DC
25 0
MHz
DC
250
MHz
5
7
ns
fREF
Input Frequency
tPD
Propagation Delay; NOTE 1
tsk(o)
Output Skew;
NOTE 2
within bank
bank-to-bank
Excludes QC
any output to QC
40
ps
11 0
ps
410
ps
tR/tF
Output Rise/Fall Time
600
ps
tPZL, tPZH
Output Enable Time
10
ns
tPLZ, tPHZ
Output Disable Time
10
ns
53
%
20% to 80%
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 output crossing point.
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250
47
REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
1.25V±5%
SCOPE
VDD,
VDDO_A,
VDDO_B, VDDO_C
Qx
LVCMOS
SCOPE
VDD,
VDDO_A,
VDDO_B, VDDO_C
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDDOX
2
V
DDOX
Qx
QX0:QX5
2
VDDOX
2
V
DDOX
Qy
QX0:QX5
2
tsk(o)
tsk(b)
OUTPUT SKEW
BANK SKEW (where X denotes outputs in the same bank)
Sn
(Low-level
enabling)
V
2.5V
1.25V
DDOX
1.25V
0V
2
QA0:5,
QB0:5, QC
t PW
t
PERIOD
tPZH
odc =
t PW
x 100%
tPHZ
Output nDPx
(See Note)
t PERIOD
1.25V
VOL
VOH
VOH - 0.15V
VOL
NOTE: The output is high except when disabled by the Sn control.
OUTPUT ENABLE/DISABLE TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
Clock
Outputs
80%
20%
20%
tR
QA0:QA5,
QB0:QB5,
QC
tF
VDDOX
2
t
PD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
839893AYI
VDD
2
CLK0,
CLK1
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REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT
INPUTS:
AND
OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
CLK INPUT:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
CONTROL PINS:
All control pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resister can be used.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
48 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS839893I is: 4615
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REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
FOR
48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
BBC
MINIMUM
NOMINAL
MAXIMUM
48
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.17
0.22
0.27
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.50 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.50 Ref.
0.50 BASIC
e
0.60
0.75
L
0.45
θ
0°
--
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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REV. A AUGUST 8, 2005
ICS839893I
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS839893AYI
ICS839893AYI
48 Lead LQFP
tray
-40°C to 85°C
ICS839893AYIT
ICS839893AYI
48 Lead LQFP
1000 tape & reel
-40°C to 85°C
ICS839893AYILF
TBD
48 Lead "Lead-Free" LQFP
tray
-40°C to 85°C
ICS839893AYILFT
TBD
48 Lead "Lead-Free" LQFP
1000 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A AUGUST 8, 2005
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