FS8107E Low Power Phase-Locked Loop IC Princeton Technology Corp. reserves the right to change the product described in this datasheet. All information contained in this datasheet is subject to change without prior notice. Princeton Technology Corp. assumes no responsibility for the use of any circuits shown in this datasheet. Description The FS8107E is a serial data input, phase-locked loop IC with programmable input and reference frequency dividers. When combined with a VCO, the FS8107E becomes the core of a very low power frequency synthesizer well-suited for mobile communication applications such as paging systems. Compared to the FS8100, the FS8107E is housed in a smaller package and also implements a separate pin for stand-by control. Features High maximum input operating frequency — 100 MHz at VDD1 = 1.0 V Up to 22 MHz internal crystal oscillator reference frequency at VDD1 = 1.0 V Extremely low current consumption (IDD,total typically 0.4 mA at fFIN = 90 MHz) 16-bit programmable input frequency divider (including a ÷ 32/33 prescaler) with divide ratio range from 992 to 65535 13-bit programmable reference frequency divider (including a ÷ 8 prescaler) with divide ratio range from 40 to 65528 Optional lock detector output Charge pump output for passive low-pass filter Quick-lock signal output for faster locking Separate pin for stand-by control TSSOP 16L package (0.65mm pitch) Applications Pager Wireless communication system Page 1 April 2003 FS8107E Package and Pin Assignment: 16L, TSSOP Symbols Dimensions in mm 1 16 2 15 HiMARK FS8107E XIN XOUT VDD2 DB DO VSS FIN VDD1 3 4 5 6 7 8 14 13 12 11 10 9 TEST NC OPR LE DATA CLK LD NC Dimensions in inch MIN. NOM. MAX. MIN. NOM. MAX. A --- --- 1.20 --- --- 0.048 A1 0.05 --- 0.15 0.002 --- 0.006 A2 0.80 1.00 1.05 0.031 0.039 0.041 b 0.19 --- 0.30 0.007 --- 0.012 C 0.09 --- 0.20 0.004 --- 0.008 D 4.90 5.00 5.10 0.193 0.197 0.201 E --- 6.40 --- --- 0.252 --- E1 4.30 4.40 4.50 0.169 0.173 0.177 e --- 0.65 --- --- 0.026 --- L 0.45 0.60 0.75 0.018 0.024 0.030 y --- --- 0.10 --- --- 0.004 θ 0° --- 8° 0° --- 8° Note: Tolerance + 0.1mm unless otherwise specified Page 2 April 2003 FS8107E Pin Descriptions Number Name I/O Description 1 XIN I Reference crystal oscillator or external clock input with internally biased amplifier (any external input to XIN must be ac-coupled) 2 XOUT O Reference crystal oscillator or external clock output 3 VDD2 POWER 4 DB O Single-ended quick-lock output for faster locking 5 DO O Single-ended charge pump output for passive low pass filter 6 VSS GND 7 FIN I 8 VDD1 POWER 9 NC NC 10 LD O Lock detector output (high when PLL is locked) 11 CLK I Shift register clock input 12 DATA I Serial data input 13 LE I Latch enable input 14 OPR I Battery-save control input; normal operation when high, stand-by mode when low 15 NC NC 16 TEST I Nominal 3.0 V supply voltage Ground VCO frequency input with internally biased input amplifier (any external input to FIN must be ac-coupled) Nominal 1.0 V supply voltage No connection No connection Test mode control input with internal pull-down resistor Block Diagram FIN DATA CLK LE TEST OPR XIN ÷ 32/33 N-COUNTER LOCK DETECTOR N-LATCH CONTROL LOGIC SHIFT REGISTER PFD R-LATCH ÷8 LD CHARGE PUMP DO QUICKLOCK DB R-COUNTER WINDOW GENERATOR XOUT Page 3 April 2003 FS8107E Absolute Maximum Ratings VSS = 0 V Parameter Symbol Rating Unit VDD1 VSS – 0.3 to VSS + 2.0 V VDD2 VSS – 0.3 to VSS + 7.0 V Input voltage range VFIN VSS – 0.3 to VDD + 0.3 V Operating temperature range TOPR –10 to 60 o C Storage temperature range TSTG –40 to 125 o C Soldering temperature range TSLD 255 o C Soldering time range tSLD 10 Supply voltage s Recommended Operating Conditions VSS = 0 V Parameter Symbol Value Unit min. typ. max. VDD1 0.95 1.0 2.0 V VDD2 2.0 3.0 3.3 V TA –10 25 60 o Supply voltage range Operating temperature Page 4 C April 2003 FS8107E Electrical Characteristics (VDD1 = 0.95 to 2.0 V, VDD2 = 2.7 to 3.3 V, VSS = 0 V, TA = 0 to 60°C unless otherwise noted) Parameter Symbol Condition IDD,total VDD1 = 1.0 V, OPR=”H”, VFIN = 0.3 Vpk-pk sinusoid, fFIN = 100 MHz, VXIN = 0.3 Vpk-pk sinusoid, fXIN = 12.8 MHz IDD,standby VDD1 = 0 V, OPR=”L” FIN max. operating frequency fFIN,max VFIN = 0.3 Vpk-pk sinusoid FIN min. operating frequency fFIN,min VFIN = 0.3 Vpk-pk sinusoid XIN max. operating frequency fXIN,max VXIN = 0.3 Vpk-pk sinusoid XIN min. operating frequency fXIN,min VXIN = 0.3 Vpk-pk sinusoid Current consumption Standby current consumption (IDD2) Value min. Unit typ. max. 0.40 1.10 mA 10 µA 100 MHz 40 22 MHz MHz 7 MHz FIN input voltage swing VFIN 0.3 Vpk-pk XIN input voltage swing VXIN 0.3 Vpk-pk CLK, DATA, LE logic LOW input voltage VIL CLK, DATA, LE logic HIGH input voltage VIH 0.3 1.5 V V XIN logic LOW input current IIL,XIN VIL = 0 V 10 µA XIN logic HIGH input current IIH,XIN VIH = VDD1 10 µA FIN logic LOW input current IIL,FIN VIL = 0 V 60 µA FIN logic HIGH input current IIH,FIN VIH = VDD1 60 µA DO logic LOW output current IOL,DOP VOL = 0.4 V 1.0 mA DO logic HIGH output current IOH,DOP VOH = VDD2 – 0.4 V 1.0 mA LD, FV, FR logic LOW output current IOL VOL = 0.4 V 0.1 mA LD, FV, FR logic HIGH output current IOH VOH = VDD2 – 0.4 V 0.1 mA DATA to CLK setup time tSU1 2 µs CLK to LE setup time tSU2 2 µs tHOLD 2 µs Hold time Page 5 April 2003 FS8107E Functional Description Programmable Input Frequency Divider The VCO input to the FIN pin is divided by the programmable divider and then internally output to the phase/frequency detector (PFD) as fV. The programmable input frequency divider consists of a ÷ 32/33 (P/P+1) dual-modulus prescaler and a 16-bit (N) counter, which is further comprised of a 5-bit swallow (A) counter, and a 11-bit main (B) counter. The total divide ratio, M, is related to values for P, A, and B through the relation M = (P + 1) × A + P × (B – A) = P × B + A, with B ≥ A . The minimum programmable divisor for continuous counting is given by P × ( P – 1 ) = 32 × 31 = 992, and the valid total divide ratio range for the input divider isM = 992 to 65535. Programmable Reference Frequency Divider The crystal oscillator output is divided by the programmable divider and then internally output to the PFD as fR. The programmable reference frequency divider consists of a fixed ÷ 8 (S) prescaler and a 13-bit reference (R) counter. The total divide ratio, T, is related to values for S and R through the relation T = S × R = 8 × R. The usable divisor range of reference counter is R = 5 to 8191, and therefore, the valid total divide ratio range for the reference divider isT = 40 to 65528 (in steps of 8.) Serial Input Data Format The divide ratios for the input and reference dividers are input using a 17-bit serial interface consisting of separate clock (CLK), data (DATA), and latch enable (LE) lines. The format of the serial data is shown in Fig. 1. The data on the DATA line is written to the shift register on the rising edge of the CLK signal and is input with MSB first, and the last (17th) bit is used as the latch select control bit. The data on the DATA line should be changed on the falling edge of CLK, and LE should be held low while data is being written to the shift register. Data is transferred from the shift register to one of the frequency divider latches when LE being set high. When the 17th bit is set low, data is loaded to the 16-bit N-counter latch, and when the 17th bit is set high, the 13 MSBs are loaded to the Page 6 April 2003 FS8107E 13-bit R-counter latch and the remaining 3 LSBs are used to control testing modes and should be set as follows for normal operation: R14 = high, R15 = low, R16 = low. To disable LD output (i.e. set LD low), R14 should be set low. Serial input data timing waveforms are shown in Fig. 2. Fig. 1 – Serial input data format MSB 13-bit data for R-counter R14 R15 R16 CONTROL BIT LSB 16-bit data for N-counter Fig. 2 – Serial input data timing waveforms DATA tHOLD tSU1 CLK tSU2 DATA 1 2 3 4 5 6 7 8 CONTROL BIT LSB MSB LE 9 10 11 12 13 14 15 16 17 CLK LE Page 7 April 2003 FS8107E Phase/Frequency Detector (PFD) The PFD compares an internal input frequency divider output signal, fV, with an internal reference frequency divider output signal, fR, and generates an error signal, DO, which is proportional to the phase error between fV and fR. The DO output is intended for use with a passive filter as shown in Fig. 3. The input/output waveforms for the PFD are shown in Fig. 4. Fig. 3 – Passive low-pass filter circuit R1 DO to VCO R2 C Fig. 4 – PFD input/output waveforms fR fV high-Z high-Z DO high-Z LD Page 8 April 2003 FS8107E Quick-lock Signal (DB) The quick-lock output signal, DB, is provided so that the PLL may achieve higher speed locking. When connected, the DB output effectively doubles the charge pump current output to the loop filter during the initial start-up of the PLL (when OPR first goes high). Once the PLL phase error is within a specific tolerance, the quick-lock circuitry sets the DB output to a high impedance state and the PLL continues toward lock with its normal charge pump current. Stand-by Mode The stand-by mode for the PLL is entered by setting the OPR pin low and VDD1 to 0 V while the circuit is in operation. In the stand-by mode, the XIN and FIN amplifiers, Ncounter, and R-counter are stopped, the N- and R-counters are also reset, and the DO and DB outputs are set to the high impedance state. As long as voltage is supplied to VDD2, data loaded to the latches is kept. To exit from stand-by mode to normal operation, the OPR pin must be set high and voltage must again be supplied to VDD1. Page 9 April 2003 FS8107E Application Circuit LNA 1st mixer 1st IF amplifier 2nd mixer 2nd IF amplifier Discriminator Wave shaper LPF Frequency multiplier (×2,3) 2nd LO 1st LO XIN TEST NC VDD2 OPR DB DO VSS FIN VDD1 HiMARK FS8107E XOUT RAM ROM CPU Decoder LE DATA CLK LD NC LCD driver Driver LCD DC/DC converter Page 10 April 2003