STMicroelectronics M95256-WCS3G/K 256 kbit serial spi bus eeprom with high-speed clock Datasheet

M95256-DR
M95256 M95256-W M95256-R
256 Kbit serial SPI bus EEPROM
with high-speed clock
Features
■
Compatible with the Serial Peripheral Interface
(SPI) bus
■
Memory array
– 256 Kb (32 Kbytes) of EEPROM
– Page size: 64 bytes
SO8 (MN)
150 mil width
■
Additional Write lockable Page (Identification
page)
■
Write
– Byte Write within 5 ms
– Page Write within 5 ms
■
Write Protect: quarter, half or whole memory
array
■
High-speed clock frequency (20 MHz)
■
Single supply voltage: 1.8 V to 5.5 V
■
More than 1 Million Write cycles
■
More than 40-year data retention
■
Enhanced ESD Protection
■
Packages
– ECOPACK2® (RoHS compliant and
Halogen-free)
SO8 (MW)
200 mil width
TSSOP8 (DW)
169 mil width
WLCSP (CS)
September 2010
Doc ID 12276 Rev 11
1/48
www.st.com
1
Contents
M95256-DR, M95256, M95256-W, M95256-R
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
5
2/48
3.1
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8
Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8.1
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8.2
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8.3
Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.2
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.2
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.3
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5
Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.6
Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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5.6.1
Contents
ECC (error correction code) and Write cycling . . . . . . . . . . . . . . . . . . . 22
5.7
Read Identification Page (available only in M95256-DR devices) . . . . . . 23
5.8
Write Identification Page (available only in M95256-DR devices) . . . . . . 24
5.9
Read Lock Status (available only in M95256-DR devices) . . . . . . . . . . . . 25
5.10
Lock ID (available only in M95256-DR devices) . . . . . . . . . . . . . . . . . . . . 25
6
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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3/48
List of tables
M95256-DR, M95256, M95256-W, M95256-R
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
4/48
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
M95256-R instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating conditions (M95256) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating conditions (M95256-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Operating conditions (M95256-R and M95256-DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC characteristics (M95256, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC characteristics (M95256-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DC characteristics (M95256-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC characteristics (M95256-R, M95256-DR, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 33
AC characteristics (M95256, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC characteristics, new M95256-W, device grade 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
AC characteristics (M95256-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC characteristics (M95256-DR, M95256-R device grade 6). . . . . . . . . . . . . . . . . . . . . . . 37
SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 39
SO8 wide – 8 lead plastic small outline, 200 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 41
M95256-DR WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . 42
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Available M95256x products (package, voltage range, temperature grade) . . . . . . . . . . . 44
Available M95256-DR products (package, voltage range, temperature grade) . . . . . . . . . 44
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 39
SO8 wide – 8 lead plastic small outline, 200 mils body width, package outline . . . . . . . . . 40
TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 41
M95256-DR WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Doc ID 12276 Rev 11
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Description
1
M95256-DR, M95256, M95256-W, M95256-R
Description
The M95256, M95256-W, M95256-R and M95256-DR are electrically erasable
programmable memory (EEPROM) devices. They are accessed by a high speed SPIcompatible bus. Their memory array is organized as 32768 × 8 bits.
The M95256-DR also offers an additional page, named the Identification Page (64 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as the Identification Page can
be used to store unique identification parameters and/or parameters specific to the
production line.
The device is accessed by a simple serial interface that is SPI-compatible.
Figure 1.
Logic diagram
VCC
D
Q
C
S
M95256
W
HOLD
VSS
AI12361
The bus signals are C, D and Q, as shown in Table 1 and Figure 1.
The device is selected when Chip Select (S) is taken low. Communications with the device
can be interrupted using Hold (HOLD).
Figure 2.
8-pin package connections
M95256
S
Q
W
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
C
D
AI12362
1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
Caution:
6/48
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
ST Microelectronics must never be exposed to UV light.
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Figure 3.
Description
WLCSP connections (top view, marking side, with balls on the underside)
VCC
Q
S
HOLD
W
D
C
VSS
ai14707
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
D
Serial Data input
Input
Q
Serial Data output
Output
S
Chip Select
Input
W
Write Protect
Input
HOLD
Hold
Input
VCC
Supply voltage
VSS
Ground
Doc ID 12276 Rev 11
7/48
Memory organization
2
M95256-DR, M95256, M95256-W, M95256-R
Memory organization
The memory is organized as shown in Figure 4.
Figure 4.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
I/O Shift Register
Q
Address Register
and Counter
Data
Register
Size of the
Read only
EEPROM
area
Y Decoder
Status
Register
1 Page
X Decoder
AI01272C
8/48
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
3
Signal description
Signal description
See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals
connected to this device.
3.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
3.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).
3.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
3.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Write cycle is in progress, the device will be in the Standby
Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power
mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
3.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
3.6
M95256-DR, M95256, M95256-W, M95256-R
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all write instructions.
3.7
VSS ground
VSS is the reference for the VCC supply voltage.
3.8
Operating supply voltage (VCC)
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9,
Table 10).
This voltage must remain stable and valid until the end of the transmission of the
instructionand, for a Write instruction, until the completion of the internal write cycle (tW).
In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line
with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS
package pins.
3.8.1
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches the internal Reset threshold voltage (this threshold is defined in DC tables as
VRES). (this threshold is lower than the minimum VCC operating voltage defined in Table 8,
Table 9 and Table 10).
When VCC passes over the POR threshold, the device is reset and in the following state:
●
in Standby Power mode,
●
deselected (note that a further instruction must be preceded by a falling edge on Chip
Select (S) to be executed),
●
Status Register value:
–
the Write Enable Latch (WEL) is reset to 0,
–
Write In Progress (WIP) is reset to 0,
–
The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode, however, the device must not be accessed until VCC reaches a valid and
stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 8, Table 9
and Table 10).
3.8.2
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage, it is
10/48
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Operating features
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 17).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been High, prior to going Low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 8, Table 9 and Table 10 and the rise time must not vary faster than 1 V/µs.
3.8.3
Power-down
During Power-down (continuous decrease of VCC supply voltage below the minimum VCC
operating voltage defined in Table 8, Table 9 and Table 10), the device must be:
●
deselected (Chip Select S should be allowed to follow the voltage applied on VCC)
●
in Standby Power mode (there should not be an internal Write cycle in progress).
4
Operating features
4.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition, has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.
Doc ID 12276 Rev 11
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Operating features
Figure 5.
M95256-DR, M95256, M95256-W, M95256-R
Hold condition activation
C
HOLD
Hold
Condition
Hold
Condition
AI02029D
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M95256-DR, M95256, M95256-W, M95256-R
4.2
Operating features
Status Register
Figure 4 shows the position of the Status Register in the control logic of the device. The
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 5.3: Read Status Register (RDSR).
4.3
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
●
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
Power-up
–
Write Disable (WRDI) instruction completion
–
Write Status Register (WRSR) instruction completion
–
Write (WRITE) instruction completion
●
The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be
configured as read-only.
●
The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits of the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
●
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
●
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
Table 2.
Write-protected block size
Status Register bits
Protected array addresse
Protected block
BP1
BP0
M95256, M95256-W, M95256-R
0
0
none
none
0
1
Upper quarter
6000h - 7FFFh
1
0
Upper half
4000h - 7FFFh
1
1
Whole memory
0000h - 7FFFh
Doc ID 12276 Rev 11
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Instructions
5
M95256-DR, M95256, M95256-W, M95256-R
Instructions
Each instruction starts with a single-byte code, as summarized in Table 3.
If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.
Table 3.
Instruction set
Instruction
Description
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Table 4.
M95256-R instruction set
Instruction
Description
Instruction
format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
Read Identification
Reads the page dedicated to identification.
Page
1000 0011(1)
Write Identification
Writes the page dedicated to identification.
Page
1000 0010(1)
Read Lock Status
Reads the lock status of the Identification Page.
1000 0011(2)
Lock ID
Locks the Identification page in read-only mode.
1000 0010(2)
1. Address bit A10 must be 0, all other address bits are Don't Care.
2. Address bit A10 must be 1, all other address bits are Don't Care.
14/48
Instruction format
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
5.1
Instructions
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 6, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data input (D). The device then
enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven
high.
Figure 6.
Write Enable (WREN) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
5.2
AI02281E
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
Power-up
●
WRDI instruction execution
●
WRSR instruction completion
●
WRITE instruction completion
Figure 7.
Write Disable (WRDI) sequence
S
0
1
2
3
4
5
6
7
C
Instruction
D
High Impedance
Q
AI03750D
Doc ID 12276 Rev 11
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Instructions
5.3
M95256-DR, M95256, M95256-W, M95256-R
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 8.
The status and control bits of the Status Register are as follows:
5.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
5.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
5.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 5) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
5.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 5.
Status Register format
b7
SRWD
b0
0
0
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Figure 8.
Instructions
Read Status Register (RDSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
D
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
MSB
2
1
0
7
6
5
4
3
2
1
0
7
MSB
AI02031E
Doc ID 12276 Rev 11
17/48
Instructions
5.4
M95256-DR, M95256, M95256-W, M95256-R
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, the data byte on Serial Data Input (D) and the Chip Select
(S) driven High. Chip Select (S) must be driven High after the rising edge of Serial Clock (C)
that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock
(C). Otherwise, the Write Status Register (WRSR) instruction is not properly executed.
The instruction sequence is shown in Figure 9.
Driving the Select (S) High at a byte boundary of the input data triggers the self timed Write
cycle, and continues for a period tW (as specified in Table 17, Table 18, Table 19 and
Table 20). While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit: the WIP bit is 1 during the selftimed Write cycle tW, and is 0 when the Write cycle is completed. The WEL bit (Write Enable
Latch) is also reset when the Write cycle tW is completed.
The Write Status Register (WRSR) instruction allows the user to change the values of the
BP1, BP0 bits and the SRWD bit:
●
The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read only, as defined in Table 2.
●
The SRWD bit (Status Register Write Disable bit), in accordance with the signal read
on the Write Protect pin (W), allows the user to set or reset the Write protection mode
of the Status Register itself, as defined in Table 6 When in Write Protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on bits b6, b5, b4, b1, b0 of the
Status Register. Bits b6, b5, b4 are always read as 0.
Table 6.
Protection modes
W signal
SRWD
bit
1
0
0
0
1
0
1
1
Mode
Write protection of the
Status Register
Memory content
Protected area(1)
Unprotected area(1)
Write-protected
Ready to accept Write
instructions
Status Register is
Hardware write
Hardware protected
Protected
Write-protected
(HPM) The values in the BP1
and BP0 bits cannot be
changed
Ready to accept Write
instructions
Status Register is
Writable (if the WREN
Software instruction has set the
Protected WEL bit)
(SPM) The values in the BP1
and BP0 bits can be
changed
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 6.
18/48
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Instructions
The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W) input pin:
●
If Write Protect (W) input pin is driven high, it is possible to write to the Status Register
(provided that the WEL bit has previously been set by a WREN instruction.
●
If Write Protect (W) input pin is driven low, it is not possible to write to the Status
Register even if the WEL bit has previously been set by a WREN instruction. (Attempts
to write to the Status Register are rejected, and are not accepted for execution). As a
consequence, all the data bytes in the memory area that are software protected (SPM)
by the Block Protect (BP1, BP0) bits of the Status Register, are also hardware
protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
either by setting the SRWD bit after driving Write Protect (W) input pin low,
●
or by driving Write Protect (W) input pin low after setting the SRWD bit.
Once entered in the Hardware Protected mode (HPM), the only way to exit the HPM mode is
to pull high the Write Protect (W) input pin.
If Write Protect (W) input pin is permanently tied high, the Hardware Protected mode (HPM)
can never be activated, and only the Software Protected mode (SPM), using the Block
Protect (BP1, BP0) bits of the Status Register, can be used.
Figure 9.
Write Status Register (WRSR) sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
Instruction
Status
Register In
7
D
High Impedance
6
5
4
3
2
1
0
MSB
Q
AI02282D
Doc ID 12276 Rev 11
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Instructions
5.5
M95256-DR, M95256, M95256-W, M95256-R
Read from Memory Array (READ)
As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data output (Q).
If Chip Select (S) continues to be driven low, the internal address register is automatically
incremented, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The first byte addressed can be any byte within any page.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 10. Read from Memory Array (READ) sequence
S
0
1
2
3
4
5
6
7
8
9 10
20 21 22 23 24 25 26 27 28 29 30 31
C
Instruction
16-Bit Address
15 14 13
D
3
2
1
0
MSB
Data Out 1
High Impedance
7
Q
6
5
4
3
2
Data Out 2
1
0
7
MSB
AI01793D
1. The most significant address bit (b15) is Don’t Care.
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
5.6
Instructions
Write to Memory Array (WRITE)
As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address bytes, and at least one data byte are then
shifted in, on Serial Data input (D). The instruction is terminated by driving Chip Select (S)
high at a byte boundary of the input data. The self-timed Write cycle, triggered by the rising
edge of Chip Select (S), continues for a period tWC (as specified in Table 17, Table 18,
Table 19 and Table 20.), at the end of which the Write in Progress (WIP) bit is reset to 0.
In the case of Figure 11, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in Figure 12, the next byte of
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 64 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
Note:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
●
if a Write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
●
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
The self-timed Write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 11. Byte Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
20 21 22 23 24 25 26 27 28 29 30 31
9 10
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte
1
0
7
6
5
4
3
2
1
0
High Impedance
Q
AI01795D
1. The most significant address bit (b15) is Don’t Care.
Doc ID 12276 Rev 11
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
Figure 12. Page Write (WRITE) sequence
S
0
1
2
3
4
5
6
7
8
20 21 22 23 24 25 26 27 28 29 30 31
9 10
C
Instruction
16-Bit Address
15 14 13
D
3
2
Data Byte 1
1
0
7
6
5
4
3
2
0
1
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Data Byte 2
D
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte N
1
0
6
5
4
3
2
1
0
AI01796D
1. The most significant address bit (b15) is Don’t Care.
5.6.1
ECC (error correction code) and Write cycling
The M95256 and M95256-D devices offer an ECC (error correction code) logic which
compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a
single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC
detects it and replaces it by the correct value. The read reliability is therefore much improved
by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write data in words (4 bytes) in order to
optimize the number of Write cycles.
The M95256 and M95256-D devices are qualified at 1 million (1 000 000) Write cycles,
using a cycling routine that writes to the device in multiples of 4-byte words.
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M95256-DR, M95256, M95256-W, M95256-R
5.7
Instructions
Read Identification Page (available only in M95256-DR
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Reading this page is achieved with the Read Identification Page instruction (see Table 4).
The Chip Select signal (S) is first driven low, the bits of the instruction byte and address
bytes are then shifted in, on Serial Data input (D). Address bit A10 must be 0, address bits
[A17:A11] and [A9:A8] are Don't Care, and the data byte pointed to by [A7:A0] is shifted out
on Serial Data output (Q). If Chip Select (S) continues to be driven low, the internal address
register is automatically incremented, and the byte of data at the new address is shifted out.
The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the ID page from location 24d, the number of bytes should be less than or equal to
40d, as the ID page boundary is 64 bytes).
The read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle. The first byte addressed can be any
byte within any page.
The instruction is not accepted, and is not executed, if a write cycle is currently in progress.
Figure 13. Read Identification Page sequence
3
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)NSTRUCTION
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$ATA /UT (IGH IMPEDANCE
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$ATA /UT -3"
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Instructions
5.8
M95256-DR, M95256, M95256-W, M95256-R
Write Identification Page (available only in M95256-DR
devices)
The Identification Page (64 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
Writing this page is achieved with the Write Identification Page instruction (see Table 4), the
Chip Select signal (S) is first driven low. The bits of the instruction byte, address byte, and at
least one data byte are then shifted in on Serial Data input (D). Address bit A10 must be 0,
address bits [A23:A11] and [A9:A8] are Don't Care, the [A7:A0] address bits define the byte
address inside the identification page. The instruction is terminated by driving Chip Select
(S) high at a byte boundary of the input data. The self-timed write cycle triggered by the
rising edge of Chip Select (S) continues for a period tW (as specified in Table 20), at the end
of which the Write in Progress (WIP) bit is reset to 0.
In the case of Figure 14, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 14, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle. Each time
a new data byte is shifted in, the least significant bits of the internal address counter are
incremented. If the number of data bytes sent to the device exceeds the page boundary, the
internal address counter rolls over to the beginning of the page, and the previous data there
are overwritten with the incoming data. (The page size of these devices is 64 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a
Write Enable instruction)
●
if Status register bits (BP1, BP0) = (1, 1)
●
if a write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that was latched in)
●
if the Identification page is locked by the Lock Status bit
Figure 14. Write Identification Page sequence
3
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)NSTRUCTION
$
BIT ADDRESS
$ATA BYTE
(IGH IMPEDANCE
1
!I
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Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
5.9
Instructions
Read Lock Status (available only in M95256-DR devices)
The Read Lock Status instruction (see Table 4) allows to check if the Identification Page is
locked (or not) in read-only mode. The Read Lock Status sequence is defined with the Chip
Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted
in on Serial Data input (D). Address bit A10 must be 1, all other address bits are Don't Care.
The Lock bit is the LSB (least significant bit) of the byte read on Serial Data output (Q). It is
at ‘1’ when the lock is active and at ‘0’ when the lock is not active. If Chip Select (S)
continues to be driven low, the same data byte is shifted out. The read cycle is terminated by
driving Chip Select (S) high.
The instruction sequence is shown in Figure 15.
Figure 15. Read Lock Status sequence
3
#
)NSTRUCTION
BIT ADDRESS
$
-3"
$ATA /UT (IGH IMPEDANCE
1
$ATA /UT -3"
!I
5.10
Lock ID (available only in M95256-DR devices)
The Lock ID instruction permanently locks the Identification Page in read-only mode. Before
this instruction can be accepted, a Write Enable (WREN) instruction must have been
executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the
instruction code, the address and a data byte on Serial Data input (D), and driving Chip
Select (S) high. In the address sent, A10 must be equal to 1, all other address bits are Don't
Care. The data byte sent must be equal to the binary value xxxx xx1x, where x = Don't Care.
Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Lock ID instruction is not executed.
Driving Chip Select (S) high at a byte boundary of the input data triggers the self-timed write
cycle whose duration is tW (specified in Table 20). The instruction sequence is shown in
Figure 16.
Doc ID 12276 Rev 11
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Instructions
M95256-DR, M95256, M95256-W, M95256-R
The instruction is not accepted, and so not executed, under the following conditions:
●
if the Write Enable Latch (WEL) bit has not been set to 1 (by previously executing a
Write Enable instruction)
●
if Status register bits (BP1,BP0) = (1,1)
●
if a write cycle is already in progress
●
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that was latched in)
●
if the Identification page is locked by the Lock Status bit
Figure 16. Lock ID sequence
3
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$
BIT ADDRESS
$ATA BYTE
(IGH IMPEDANCE
1
!I
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M95256-DR, M95256, M95256-W, M95256-R
6
Delivery state
Delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
7
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such
as the Read from Memory Array and Read Status Register instructions) have been clocked
into the device.
Figure 17 shows an example of three memory devices connected to an MCU, on an SPI
bus. Only one memory device is selected at a time, so only one memory device drives the
Serial Data output (Q) line at a time, the other memory devices are high impedance.
Figure 17. Bus master and memory devices on the SPI bus
VSS
VCC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
VCC
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
R
CS3
CS2
VCC
C Q D
VSS
VCC
C Q D
VSS
SPI Memory
Device
R
VSS
SPI Memory
Device
R
CS1
S
W
HOLD
S
W
HOLD
S
W
HOLD
AI12304b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
The pull-up resistor R (represented in Figure 17) ensures that a device is not selected if the
bus master leaves the S line in the high-impedance state.
In applications where the bus master might enter a state where all SPI bus inputs/outputs
would be in high impedance at the same time (for example, if the bus master is reset during
Doc ID 12276 Rev 11
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Connecting to the SPI bus
M95256-DR, M95256, M95256-W, M95256-R
the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low
(while the S line is pulled high): this ensures that S and C do not become high at the same
time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.
7.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
●
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 18, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
●
C remains at 1 for (CPOL=1, CPHA=1)
Figure 18. SPI modes supported
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
28/48
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
8
Maximum rating
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 7.
Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient temperature with power applied
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
Lead temperature during soldering
see note
VO
Output voltage
–0.50
VCC+0.6
V
VI
Input voltage
–0.50
6.5
V
IOL
DC output current (Q = 0)
-
5
mA
IOH
DC output current (Q = 1)
–5
-
mA
VCC
Supply voltage
–0.50
6.5
V
–4000
4000
V
VESD
Electrostatic discharge voltage (human body
model)(2)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100pF, R1=1500 , R2=500 )
Doc ID 12276 Rev 11
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DC and AC parameters
9
M95256-DR, M95256, M95256-W, M95256-R
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (M95256)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
4.5
5.5
V
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (M95256-W)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (M95256-R and M95256-DR)
Symbol
VCC
TA
Table 11.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
Min.
Max.
Unit
AC measurement conditions(1)
Symbol
CL
Parameter
30 or 100(2)
Load capacitance
Input rise and fall times
25
pF
ns
Input pulse voltages
0.2VCC to 0.8VCC
V
Input and output timing reference voltages
0.3VCC to 0.7VCC
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
2. 100 pF when the clock frequency fC is less than 10 MHz, 30 pF when the clock frequency fC is equal to or
greater than 10 MHz.
30/48
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
DC and AC parameters
Figure 19. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
AI00825B
Table 12.
Capacitance(1)
Symbol
COUT
Parameter
Test condition
Max.
Unit
VOUT = 0 V
8
pF
Input capacitance (D)
VIN = 0 V
8
pF
Input capacitance (other pins)
VIN = 0 V
6
pF
Output capacitance (Q)
CIN
1. Sampled only, not 100% tested.
Table 13.
Symbol
DC characteristics (M95256, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
ILI
Input leakage current
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current
C = 0.1VCC/0.9VCC at 5 MHz,
VCC = 5 V, Q = open
4
mA
ICC1
Supply current
(Standby Power mode)
S = VCC, VCC = 5 V,
VIN = VSS or VCC
5
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
0.4
V
VOL
(1)
Output low voltage
IOL = 2 mA, VCC = 5 V
(1)
Output high voltage
IOH = –2 mA, VCC = 5 V
VOH
0.8 VCC
V
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards.
Doc ID 12276 Rev 11
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DC and AC parameters
Table 14.
Symbol
M95256-DR, M95256, M95256-W, M95256-R
DC characteristics (M95256-W, device grade 6)
Parameter
Test condition
ILI
Input leakage current
ILO
Output leakage current
ICC
ICC0(3)
ICC1
Max.
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
VCC= 2.5 V, C = 0.1VCC/0.9VCC
at 5 MHz, Q = open
3
mA
VCC= 2.5 V, C = 0.1VCC/0.9VCC
at 10 MHz, Q = open
4(1)
mA
VCC= 5.5 V, C = 0.1VCC/0.9VCC
at 5 MHz, Q = open
5
mA
VCC= 5.5 V, C = 0.1VCC/0.9VCC
at 20 MHz, Q = open
5(2)
mA
During tW, S = VCC,
2.5 V < VCC < 5.5 V
5
mA
S = VCC, VCC = 5.5 V,
VIN = VSS or VCC,
5(4)
µA
S = VCC, VCC = 2.5 V,
VIN = VSS or VCC,
5(5)
µA
Supply current (Read)
Supply current (Write)
Supply current
(Standby Power mode)
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
VCC = 2.5 V and IOL = 1.5 mA or
VCC = 5 V and IOL = 2 mA
0.4
V
VOH
Output high voltage
VCC = 2.5 V and IOH = –0.4 mA or
0.8 VCC
VCC = 5 V and IOH = –2 mA
1. Preliminary data: 2mA with the new product identified with process letter K.
2. For new product identified with process letter K (preliminary data)
3. Characterized value, not tested in production.
4. 3 µA with the new product identified with process letter K (Preliminary data)
5. 2 µA with the new product identified with process letter K (Preliminary data)
32/48
Min.
Doc ID 12276 Rev 11
V
M95256-DR, M95256, M95256-W, M95256-R
Table 15.
Symbol
DC and AC parameters
DC characteristics (M95256-W, device grade 3)
Parameter
Test condition
Min.
Max.
Unit
VIN = VSS or VCC
±2
µA
ILI
Input leakage current
ILO
Output leakage current
S = VCC, VOUT = VSS or VCC
±2
µA
ICC
Supply current (Read)
C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V,
Q = open
3
mA
ICC0(1)
Supply current (Write)
During tW, S = VCC,
2.5 V < VCC < 5.5 V
6
mA
ICC1
Supply current
(Standby Power mode)
S = VCC, VIN = VSS or VCC
2.5 V < VCC < 5.5 V,
5
µA
VIL
Input low voltage
–0.45
0.3 VCC
V
VIH
Input high voltage
0.7 VCC
VCC+1
V
VOL
Output low voltage
IOL = 1.5 mA, VCC = 2.5 V
0.4
V
VOH
Output high voltage
IOH = –0.4 mA, VCC = 2.5 V
0.8 VCC
V
1. Characterized value, not tested in production.
Table 16.
Symbol
DC characteristics (M95256-R, M95256-DR, device grade 6)(1)
Test condition(2)
Parameter
ILI
Input leakage current
ILO
Output leakage current
Min
Max
Unit
VIN = VSS or VCC
±2
µA
S = VCC, VOUT = VSS or VCC
±2
µA
VCC = 1.8 V, C = 0.1VCC/0.9VCC at 2 MHz, Q = open
1 (3)
VCC = 1.8 V, C = 0.1VCC/0.9VCC at 5 MHz, Q = open
2(4)
ICC
Supply current (Read)
ICC0(5)
Supply current (Write)
VCC = 1.8 V, during tW, S = VCC
3
mA
ICC1
Supply current
(Standby Power mode)
VCC = 1.8 V, S = VCC, VIN = VSS or VCC
3
µA
VIL
Input low voltage
1.8 V  VCC < 2.5 V
–0.45
0.25 VCC
V
VIH
Input high voltage
1.8 V  VCC < 2.5 V
0.75 VCC
VCC+1
V
VOL
Output low voltage
IOL = 0.15 mA, VCC = 1.8 V
0.3
V
VOH
Output high voltage
IOH = –0.1 mA, VCC = 1.8 V
mA
0.8 VCC
V
1. New product identified with process letter K.
2.
If the application uses the M95256-R, M95256-DR device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer
to Table 14: DC characteristics (M95256-W, device grade 6) instead of the above table.
3. 2 mA for the new product identified with the process letter K (Preliminary data).
4. Only the new product identified with the process letter K can run at 5 MHz (Preliminary data)
5. Characterized value, not tested in production.
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DC and AC parameters
Table 17.
M95256-DR, M95256, M95256-W, M95256-R
AC characteristics (M95256, device grade 3)
Test conditions specified in Table 11: AC measurement conditions and Table 8: Operating
conditions (M95256)
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
ns
tSHCH
tCSS2
S not active setup time
90
ns
tSHSL
tCS
S deselect time
100
ns
tCHSH
tCSH
S active hold time
90
ns
S not active hold time
90
ns
tCHSL
Parameter
Min.
Max.
Unit
D.C.
5
MHz
(1)
tCLH
Clock high time
90
ns
tCL (1)
90
ns
tCH
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
1
µs
tCHCL
(2)
tFC
Clock fall time
1
µs
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
30
ns
tHHCH
Clock low hold time after HOLD not active
70
ns
tHLCH
Clock low hold time after HOLD active
40
ns
tCLHL
Clock low setup time before HOLD active
0
ns
tCLHH
Clock low setup time before HOLD not active
0
ns
tSHQZ
(2)
tDIS
Output disable time
100
ns
Clock low to output valid
60
ns
tCLQV
tV
tCLQX
tHO
Output hold time
tQLQH (2)
tRO
Output rise time
50
ns
(2)
tFO
Output fall time
50
ns
tLZ
HOLD high to output valid
50
ns
tHZ
HOLD low to output High-Z
100
ns
tWC
Write time
5
ms
tQHQL
tHHQV
tHLQZ
tW
(2)
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not tested in production.
34/48
Doc ID 12276 Rev 11
0
ns
M95256-DR, M95256, M95256-W, M95256-R
Table 18.
DC and AC parameters
AC characteristics, new M95256-W, device grade 6
Test conditions: VCC = 2.5 to 5.5 V,
TA = -40 to 85 °C
Symbol
Alt.
CL = 100 pF
New products (process K,
preliminary information)
Unit
CL = 30 pF
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
D.C.
5
D.C.
10
D.C.
20
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
30
15
ns
tSHCH
tCSS2
S not active setup time
90
30
15
ns
tSHSL
tCS
S deselect time
100
40
20
ns
tCHSH
tCSH
S active hold time
90
30
15
ns
S not active hold time
90
30
15
ns
tCHSL
MHz
tCH (1)
tCLH
Clock high time
90
45
20
ns
tCL (1)
tCLL
Clock low time
90
45
20
ns
tCLCH (2)
tRC
Clock rise time
1
2
2
µs
tCHCL (2)
tFC
Clock fall time
1
2
2
µs
tDVCH
tDSU
Data in setup time
20
10
5
ns
tCHDX
tDH
Data in hold time
30
10
10
ns
tHHCH
Clock low hold time after HOLD not
active
70
30
15
ns
tHLCH
Clock low hold time after HOLD active
40
30
15
ns
tCLHL
Clock low setup time before HOLD active
0
0
0
ns
tCLHH
Clock low setup time before HOLD not
active
0
0
0
ns
tSHQZ (2)
tDIS
Output disable time
100
40
20
ns
tCLQV
tV
Clock low to output valid
60
40
20
ns
tCLQX
tHO
Output hold time
tQLQH (2)
tRO
Output rise time
50
40
20
ns
tQHQL (2)
tFO
Output fall time
50
40
20
ns
tHHQV
tLZ
HOLD high to output valid
50
40
20
ns
tHLQZ (2)
tHZ
HOLD low to output High-Z
100
40
20
ns
tW
tWC
Write time
5
5
5
ms
0
0
0
ns
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not tested in production.
Doc ID 12276 Rev 11
35/48
DC and AC parameters
Table 19.
M95256-DR, M95256, M95256-W, M95256-R
AC characteristics (M95256-W, device grade 3)
Test conditions specified in Table 11: AC measurement conditions and Table 9: Operating
conditions (M95256-W)
Symbol
Alt.
fC
fSCK
Clock frequency
tSLCH
tCSS1
S active setup time
90
ns
tSHCH
tCSS2
S not active setup time
90
ns
tSHSL
tCS
S deselect time
100
ns
tCHSH
tCSH
S active hold time
90
ns
S not active hold time
90
ns
tCHSL
Parameter
Max.
Unit
D.C.
5
MHz
(1)
tCLH
Clock high time
90
ns
tCL (1)
90
ns
tCH
tCLL
Clock low time
tCLCH
(2)
tRC
Clock rise time
1
µs
tCHCL
(2)
tFC
Clock fall time
1
µs
tDVCH
tDSU
Data in setup time
20
ns
tCHDX
tDH
Data in hold time
30
ns
tHHCH
Clock low hold time after HOLD not active
70
ns
tHLCH
Clock low hold time after HOLD active
40
ns
tCLHL
Clock low setup time before HOLD active
0
ns
tCLHH
Clock low setup time before HOLD not active
0
ns
tSHQZ
(2)
tDIS
Output disable time
100
ns
Clock low to output valid
60
ns
tCLQV
tV
tCLQX
tHO
Output hold time
tQLQH (2)
tRO
Output rise time
50
ns
(2)
tFO
Output fall time
50
ns
tLZ
HOLD high to output valid
50
ns
tHZ
HOLD low to output High-Z
100
ns
tWC
Write time
5
ms
tQHQL
tHHQV
tHLQZ
tW
(2)
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Value guaranteed by characterization, not tested in production.
36/48
Min.
Doc ID 12276 Rev 11
0
ns
M95256-DR, M95256, M95256-W, M95256-R
Table 20.
DC and AC parameters
AC characteristics (M95256-DR, M95256-R device grade 6)
Test conditions: VCC = 1.8 to 5.5 V, TA = –40 to 85 °C
Min.
Min.
Max.
New
products(2)
(Preliminary
information)
Symbol
Alt.
fC
fSCK
Clock frequency
D.C.
tSLCH
tCSS1
S active setup time
200
60
ns
tSHCH
tCSS2
S not active setup time
200
60
ns
tSHSL
tCS
S deselect time
200
90
ns
tCHSH
tCSH
S active hold time
200
60
ns
S not active hold time
200
60
ns
tCHSL
Parameter
Max.
Current(1)
products
2
D.C.
5
Unit
MHz
tCH
(3)
tCLH
Clock high time
200
80
ns
tCL
(3)
tCLL
Clock low time
200
80
ns
tCLCH (4)
tRC
Clock rise time
1
2
µs
(4)
tFC
Clock fall time
1
2
µs
tCHCL
tDVCH
tDSU
Data in setup time
40
20
ns
tCHDX
tDH
Data in hold time
50
20
ns
tHHCH
Clock low hold time after HOLD not active
140
60
ns
tHLCH
Clock low hold time after HOLD active
90
60
ns
tCLHL
Clock low setup time before HOLD active
0
0
ns
tCLHH
Clock low setup time before HOLD not active
0
0
ns
tSHQZ (4)
tDIS
tCLQV
tV
tCLQX
Output disable time
250
80
ns
Clock low to output valid
150
80
ns
tHO
Output hold time
(4)
tRO
Output rise time
100
20
ns
tQHQL (4)
tFO
Output fall time
100
20
ns
tHHQV
tLZ
HOLD high to output valid
100
80
ns
tHZ
HOLD low to output High-Z
250
80
ns
tWC
Write time
5
5
ms
tQLQH
tHLQZ
tW
(4)
0
0
ns
1. Current products are identified by process letters “AB”.
2. New products are identified by process letter K. For these new products, the test flow guarantees the AC parameter values
defined in this table (when VCC = 1.8 V) and the AC parameter values defined in Table 18 (when VCC= 2.5 V or VCC=
5.0 V). The M95256-DR is available as only "new product" type.
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
4. Value guaranteed by characterization, not 100% tested in production.
Doc ID 12276 Rev 11
37/48
DC and AC parameters
M95256-DR, M95256, M95256-W, M95256-R
Figure 20. Serial input timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
LSB IN
MSB IN
D
High Impedance
Q
AI01447C
Figure 21. Hold timing
S
tHLCH
tCLHL
tHHCH
C
tCLHH
tHLQZ
tHHQV
Q
HOLD
AI01448c
Figure 22. Output timing
S
tCH
C
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
tCLQX
LSB OUT
Q
tQLQH
tQHQL
D
ADDR.LSB IN
AI01449e
38/48
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
10
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers the M95256 in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at www.st.com.
Figure 23. SO8N – 8 lead plastic small outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
A1
L
L1
SO-A
1. Drawing is not to scale.
Table 21.
SO8N – 8 lead plastic small outline, 150 mils body width, package data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
Min
1.75
Max
0.0689
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.1
0.0039
D
4.9
4.8
5
0.1929
0.189
0.1969
E
6
5.8
6.2
0.2362
0.2283
0.2441
E1
3.9
3.8
4
0.1535
0.1496
0.1575
e
1.27
-
-
0.05
-
-
h
0.25
0.5
0.0098
0.0197
k
0°
8°
0°
8°
L
0.4
1.27
0.0157
0.05
L1
1.04
0.0409
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95256-DR, M95256, M95256-W, M95256-R
Figure 24. SO8 wide – 8 lead plastic small outline, 200 mils body width, package
outline
A2
A
c
b
CP
e
D
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 22.
SO8 wide – 8 lead plastic small outline, 200 mils body width, package
mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
2.5
Max
0.0984
A1
0
0.25
0
0.0098
A2
1.51
2
0.0594
0.0787
b
0.4
0.35
0.51
0.0157
0.0138
0.0201
c
0.2
0.1
0.35
0.0079
0.0039
0.0138
CP
0.1
0.0039
D
6.05
0.2382
E
5.02
6.22
0.1976
0.2449
E1
7.62
8.89
0.3
0.35
-
-
-
-
k
0°
10°
0°
10°
L
0.5
0.8
0.0197
0.0315
N
8
e
1.27
0.05
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Min
Doc ID 12276 Rev 11
8
M95256-DR, M95256, M95256-W, M95256-R
Package mechanical data
Figure 25. TSSOP8 – 8 lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 23.
TSSOP8 – 8 lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Min
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ
1.000
CP
Max
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
0.0394

0°
N
8
8°
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95256-DR, M95256, M95256-W, M95256-R
Figure 26. M95256-DR WLCSP, 0.5 mm pitch, package outline
Orientation reference
D
2
3
1
A
e2
e
B
C
E
D
B
G
E
e3
F
e1
A2
A1
A
1. Drawing is not to scale.
Table 24.
M95256-DR WLCSP, 0.5 mm pitch, package mechanical data
Inches(1)
Millimeters
Symbol
Typ
Min
Max
Typ
Max
A
0.60
0.55
0.65
0.0236
0.0217
0.0256
A1
0.245
0.22
0.27
0.0096
0.0087
0.0106
A2
0.355
0.330
0.380
0.0140
0.0130
0.0150
B
Ø 0.311
Ø 0.0122
D
1.97
1.95
1.99
0.0776
0.0768
0.0783
E
1.785
1.765
1.805
0.0703
0.0695
0.0711
e
0.5
0.0197
e1
0.866
0.0341
e2
0.25
0.0098
e3
0.433
0.0170
F
0.552
0.502
0.602
0.0217
0.0198
0.0237
G
0.392
0.342
0.442
0.0154
0.0135
0.0174
N(2)
8
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. N is the total number of terminals.
42/48
Min
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8
M95256-DR, M95256, M95256-W, M95256-R
11
Part numbering
Part numbering
Table 25.
Ordering information scheme
Example:
M95256
–
W MN 6
T
P
/A
Device type
M95 = SPI serial access EEPROM
Device function
256 = 256 Kbit
256-D = 256 Kbit plus Identification page
Operating voltage
blank = VCC = 4.5 to 5.5 V
W = VCC = 2.5 to 5.5 V
R = VCC = 1.8 to 5.5 V
Package
MN = SO8 (150 mils width)
MW = SO8 (200 mils width)
DW = TSSOP8 (169 mils width)
CS = WLCSP
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 = Device tested with High Reliability Certified Flow(1)
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHs compliant)
Process
A or AB = F8L(2)
K= F8H
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.
The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your
nearest ST sales office for a copy.
2. Used only for device grade 3 and WLCSP packages.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST Sales Office.
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Part numbering
M95256-DR, M95256, M95256-W, M95256-R
The category of second-level interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
Table 26.
Available M95256x products (package, voltage range, temperature grade)
Package
M95256
(4.5 V to 5.5 V)
M95256-W
(2.5 V to 5.5 V)
M95256-R
(1.8 V to 5.5 V)
SO8N (MN)
Range 3
Range 6, Range 3
Range 6
SO8W (MW)
-
Range 6
-
TSSOP (DW)
-
Range 6, Range 3
Range 6
WLCSP
-
-
Range 6
Table 27.
Available M95256-DR products (package, voltage range, temperature
grade)
M95256-DR
1.8 V to 5.5 V
Package
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SO8 (MN)
Range 6
TSSOP (DW)
Range 6
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
12
Revision history
Revision history
Table 28.
Document revision history
Date
Revision
Changes
17-Nov-1999
2.1
New -V voltage range added (including the tables for DC characteristics,
AC characteristics, and ordering information).
07-Feb-2000
2.2
New -V voltage range extended to M95256 (including AC characteristics,
and ordering information).
22-Feb-2000
2.3
tCLCH and tCHCL, for the M95xxx-V, changed from 1s to 100ns
15-Mar-2000
2.4
-V voltage range changed to 2.7-3.6V
29-Jan-2001
2.5
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Illustrations and Package Mechanical data updated
12-Jun-2001
2.6
Correction to header of Table 12B
TSSOP14 Illustrations and Package Mechanical data updated
Document promoted from Preliminary Data to Full Data Sheet
08-Feb-2002
2.7
Announcement made of planned upgrade to 10 MHz clock for the 5V, –40
to 85°C, range.
09-Aug-2002
2.8
M95128 split off to its own datasheet. Data added for new and forthcoming
products, including availability of the SO8 narrow package.
24-Feb-2003
2.9
Omission of SO8 narrow package mechanical data remedied
26-Jun-2003
2.10
-V voltage range removed
21-Nov-2003
3.0
Table of contents, and Pb-free options added. -S voltage range extended
to -R. VIL(min) improved to –0.45V
17-Mar-2004
4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering
temperature information clarified for RoHS compliant devices. Device
grade information clarified
21-Oct-2004
5.0
M95128 datasheet merged back in. Product List summary table added.
AEC-Q100-002 compliance. Device Grade information clarified. tHHQX
corrected to tHHQV. 10MHz product becomes standard
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Revision history
Table 28.
Date
Document revision history (continued)
Revision
Changes
6
M95128 part numbers removed from document. PDIP8 package removed.
Delivery state paragraph added.
Section 3.8: Operating supply voltage (VCC) added and information
removed below Section 4: Operating features.
Power up state removed below Section 6: Delivery state.
Figure 18: SPI modes supported modified and Note 2 added.
Note 1 added to Table 8.
ICC1 specified over the whole VCC range and ICC0 added in Table 14,
Table 15 and Table 16. ICC specified over the whole VCC range in Table 14.
Table 17: AC Characteristics (M95256, Device Grade 6) added.
tCHHL and tCHHH replaced by tCLHL and tCLHH, respectively.
Figure 21: Hold timing modified. Process added to Table 25: Ordering
information scheme. Note 1 added to Table 25.
Note 1 removed from Table 20: AC characteristics (M95256-DR, M95256R device grade 6).
TA added to Table 7: Absolute maximum ratings.
Order of sections modified.
7
M95256 with device grade 6 temperature range removed.
Section 3.7: VSS ground added, Section 3.8: Operating supply voltage
(VCC) modified. Small text changes.
Section 5.4: Write Status Register (WRSR), Section 5.5: Read from
Memory Array (READ) and Section 6: Delivery state updated.
Note 2 below Figure 17: Bus master and memory devices on the SPI bus
removed, replaced by explanatory paragraph.
TLEAD added to Table 7: Absolute maximum ratings.
Test conditions modified for ICC0 and ICC1, and VIH min modified in
Table 17: AC characteristics (M95256, device grade 3).
tW modified and “preliminary data” note removed in Table 20: AC
characteristics (M95256-DR, M95256-R device grade 6).
Blank option removed below Plating technology, process A modified and
process V removed in Table 25: Ordering information scheme.
Table 26: Available M95256x products (package, voltage range,
temperature grade) added.
SO8N and SO8W package specifications updated (see Section 10:
Package mechanical data). Package mechanical data: inches calculated
from mm and rounded to 3 decimal digits.
27-Mar-2008
8
Section 3.8: Operating supply voltage (VCC) modified. Small text changes.
Frequency corrected on page 1.
VIL and VIH modified in Table 16: DC characteristics (M95256-R, M95256DR, device grade 6).
AB Process added to Table 25: Ordering information scheme.
15-Jul-2008
9
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 10: Package
mechanical data).
13-Apr-2006
15-Oct-2007
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M95256-DR, M95256, M95256-W, M95256-R
Doc ID 12276 Rev 11
M95256-DR, M95256, M95256-W, M95256-R
Table 28.
Date
24-Jun-2010
07-Sep-2010
Revision history
Document revision history (continued)
Revision
Changes
10
M95256-DR part number added.
Updated Section 3.8: Operating supply voltage (VCC)
Updated Section 4.3: Data protection and protocol control
Updated Section 5.4: Write Status Register (WRSR)
Added note in Section 5.6: Write to Memory Array (WRITE)
Updated Table 7: Absolute maximum ratings
Added Table 20: AC characteristics (M95256-DR, M95256-R device grade
6)
Updated Table 20: AC characteristics (M95256-DR, M95256-R device
grade 6)
11
Updated Section 1: Description.
Updated Section 5.7: Read Identification Page (available only in M95256DR devices).
Updated Section 5.8: Write Identification Page (available only in M95256DR devices).
Updated Section 5.9: Read Lock Status (available only in M95256-DR
devices).
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M95256-DR, M95256, M95256-W, M95256-R
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