Mitsubishi M38B43E7H-XXXXFP Single-chip 8-bit cmos microcomputerã ã ã Datasheet

MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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DESCRIPTION
The 38B4 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38B4 group has six 8-bit timers, a 16-bit timer, a fluorescent
display automatic display circuit, 12-channel 10-bit A-D converter, a
serial I/O with automatic transfer function, which are available for
controlling musical instruments and household appliances.
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FEATURES
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Basic machine-language instructions ....................................... 71
Minimum instruction execution time ................................. 0.48 µs
(at 4.2 MHz oscillation frequency)
Memory size
ROM ............................................. 48K to 60K bytes
RAM .......................................... 1024 to 2048 bytes
Programmable input/output ports ............................................. 51
High-breakdown-voltage output ports ...................................... 36
Software pull-up resistors (Ports P5, P61 to P65 , P7, P8 4 to P87 ,
P9)
Interrupts .................................................. 21 sources, 16 vectors
Timers ........................................................... 8-bit ✕ 6, 16-bit ✕ 1
Serial I/O1 (Clock-synchronized) ................................... 8-bit ✕ 1
...................... (max. 256-byte automatic transfer function)
Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ✕ 1
PWM ............................................................................ 14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
A-D converter .............................................. 10-bit ✕ 12 channels
Fluorescent display function ......................... Total 40 control pins
Interrupt interval determination function ..................................... 1
Watchdog timer ............................................................ 20-bit ✕ 1
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Buzzer output ............................................................................. 1
Clock generating circuit ...................................... Built-in 2 circuits
(connect to external ceramic resonator or quartz-crystal
oscillator)
Power source voltage
In high-speed mode ................................................... 4.0 to 5.5 V
(at 4.2 MHz oscillation frequency)
2.7 to 5.5 V
(at 2.0 MHz oscillation frequency)
In middle-speed mode ................................................ 2.7 to 5.5 V
(at 4.2 MHz oscillation frequency)
In low-speed mode ..................................................... 2.7 to 5.5 V
(at 32 kHz oscillation frequency)
Power dissipation
In high-speed mode .......................................................... 35 mW
(at 4.2 MHz oscillation frequency)
In low-speed mode ............................................................. 60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
In stop mode ......................................................................... 1 µA
(at clock stop)
Operating temperature range ................................... –20 to 85 °C
APPLICATION
Musical instruments, VCR, household appliances, etc.
50
49
48
47
46
45
44
43
42
41
61
60
59
58
57
56
55
54
53
52
51
65
66
67
40
39
38
68
69
37
70
71
35
36
72
M38B4xMxH-XXXXFP
73
74
34
33
32
31
P75/AN5
P74/AN4
P73/AN3
P72/AN2
P71/AN1
P70/AN0
P61/CNTR0/CNTR2
(Note) P60/CNTR1
P47/INT2
RESET
P91/XCOUT
P90/XCIN
VSS
XIN
XOUT
VCC
P46/T3OUT
P45/T1OUT
P44/PWM1
P43/BUZ01
(Note) P42/INT3
P41/INT1
P40/INT0
P87/PWM0/FLD39
21
22
23
24
26
25
13
14
15
16
17
18
19
20
28
27
79
80
11
12
29
77
78
4
5
6
7
8
9
10
30
76
2
3
75
1
P57/SRDY2/SCLK22
P56/SCLK21
P55/TxD
P54/RxD
P53/SCLK12
P52/SCLK11
P51/SOUT1
P50/SIN1
AVSS
VREF
P65/SSTB1/AN11
P64/INT4/SBUSY1/AN10
P63/AN9
P62/SRDY1/AN8
P77/AN7
P76/AN6
62
64
63
P20/BUZ02/FLD0
P21/FLD1
P22/FLD2
P23/FLD3
P24/FLD4
P25/FLD5
P26/FLD6
P27/FLD7
P00/FLD8
P01/FLD9
P02/FLD10
P03/FLD11
P04/FLD12
P05/FLD13
P06/FLD14
P07/FLD15
P10/FLD16
P11/FLD17
P12/FLD18
P13/FLD19
P14/FLD20
P15/FLD21
P16/FLD22
P17/FLD23
PIN CONFIGURATION (TOP VIEW)
Note: In the mask option type P, INT3 and CNTR1 cannot be used.
Package type : 80P6N-A
80-pin plastic-molded QFP
Fig. 1 Pin configuration of M38B4xMxH-XXXXFP
P30/FLD24
P31/FLD25
P32/FLD26
P33/FLD27
P34/FLD28
P35/FLD29
P36/FLD30
P37/FLD31
P80/FLD32
P81/FLD33
P82/FLD34
P83/FLD35
VEE
P84/FLD36
P85/RTP0/FLD37
P86/RTP1/FLD38
2
Port P0(8)
8
Fig. 2 Functional block diagram
A-D converter
Port P6(6)
6
Port P5(8)
8
(36 high-breakdown
voltage ports)
40 control pins
FLD display function
Buzzer output
PWM0(14-bit)
PWM1(8-bit)
Serial I/O2
(Clock-synchronized or UART)
Serial I/O1(Clock-synchronized)
(256 byte automatic transfer)
Serial I/O
(10-bit 5 12 channel)
8
CPU core
Timer X(16-bit)
Timer 1(8-bit)
Timer 2(8-bit)
Timer 3(8-bit)
Timer 4(8-bit)
Timer 5(8-bit)
Timer 6(8-bit)
Timers
8
Port P2(8)
8
Port P7(8)
Interrupt interval
determination function
Watchdog timer
Port P1(8)
Build-in peripheral functions
I/O ports
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A)
Port P9(2)
2
8
Port P4(8)
1
Port P8(8)
RAM
ROM
Memory
XIN-XOUT
(main-clock)
XCIN-XCOUT
(sub-clock)
System clock generation
Port P3(8)
8
7
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL BLOCK
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
Power source
• Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS.
VEE
• Apply voltage supplied to pull-down resistors of ports P0, P1, and P3.
AVSS
Pull-down
power source
Reference
voltage
Analog power
RESET
XIN
source
Reset input
Clock input
XOUT
Clock output
• Connect to VSS.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
P00/FLD8–
P07/FLD15
I/O port P0
VREF
• Reference voltage input pin for A-D converter.
• Analog power source input pin for A-D converter.
oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
• 8-bit I/O port.
• FLD automatic display
• I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• A pull-down resistor is built in between port P0 and the VEE pin.
• CMOS compatible input level.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
P10/FLD16– Output port P1
P17/FLD23
P20/BUZ02 /
I/O port P2
FLD0–
P27/FLD7
P30/FLD24– Output port P3
P37/FLD31
P40/INT 0,
P41/INT 1,
P42/INT 3
P43/BUZ01
P44/PWM1
P45/T 1OUT,
P46/T 3OUT
P47/INT2
I/O port P4
• 8-bit output port.
• A pull-down resistor is built in between port P1 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
• At reset, this port is set to VEE level.
• 8-bit I/O port with the same function as port P0.
• FLD automatic display
pins
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• 8-bit output port.
• A pull-down resistor is built in between port P3 and the VEE pin.
• High-breakdown-voltage P-channel open-drain output structure.
pins
• Buzzer output pin (P20)
• FLD automatic display
pins
• At reset, this port is set to VEE level.
• 7-bit I/O port with the same function as port P0.
• CMOS compatible input level
• N-channel open-drain output structure.
• FLD automatic display
• Interrupt input pins
In the mask option type P,
INT3 cannot be used.
• Buzzer output pin
• PWM output pin
(Timer output pin)
• Timer output pin
Input port P4
• 1-bit input port.
• CMOS compatible input level.
• Interrupt input pin
3
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
P50/SIN1,
Name
I/O port P5
P51/SOUT1,
P52/SCLK11,
P53/SCLK12
P54/RXD,
P55/TXD,
P56/SCLK21,
Function
• 8-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Serial I/O2 function pins
P57/SRDY2/
SCLK22
P60/CNTR1 I/O port P6
P61/CNTR0/
CNTR2
P62/SRDY1/
AN 8
P63/AN9
• 1-bit I/O port with the same function as port P0.
• CMOS compatible input level.
• N-channel open-drain output structure.
• Timer input pin
In the mask option type P,
CNTR 1 cannot be used.
• 5-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Timer I/O pin
P64/INT4/
SBUSY1 /AN10,
P65/SSTB1/
AN11
P70/AN0–
P77/AN7
I/O port P7
P84/FLD36
P85/RTP0/
FLD 37,
P86/RTP1/
FLD38
P87/PWM0/
FLD 39
4
• Serial I/O1 function pin
• A-D conversion input pin
• A-D conversion input pin
• Dimmer signal output pin
• Serial I/O1 function pin
• A-D conversion input pin
• Interrupt input pin (P64)
P80/FLD32 – I/O port P8
P83/FLD35
P90/XCIN,
P91/XCOUT
Function except a port function
• Serial I/O1 function pins
• 8-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• A-D conversion input pin
• 4-bit I/O port with the same function as port P0.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• 4-bit CMOS I/O port with the same function as port P0.
• Low-voltage input level.
• CMOS 3-state output structure
• FLD automatic display pins
• FLD automatic display pins
• Real time port output
• FLD automatic display pins
• 14-bit PWM output
I/O port P9
• 2-bit CMOS I/O port with the same function as port P0.
• CMOS compatible input level.
• CMOS 3-state output structure.
• I/O pins for sub-clock generating
circuit (connect a ceramic resonator or a quarts-crystal oscillator)
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product M38B4 9 M F H - XXXX FP
Package type
FP : 80P6N-A package
ROM number
High-breakdown voltage pull-down option
Regarding option contents, refer to section
“MASK OPTION OF PULL-DOWN
RESISTOR”.
ROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
D : 53248 bytes
E : 57344 bytes
F : 61440 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used for
users.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
5
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 38B4 group as follows:
Memory Type
Support for Mask ROM version.
Memory Size
Mask ROM size ..................................................... 48K to 60K bytes
RAM size ............................................................ 1024 to 2048 bytes
Package
80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
ROM size (bytes)
Under development
60K
M38B49MFH
56K
52K
Under development
48K
M38B47MC
44K
40K
36K
32K
28K
24K
20K
16K
12K
8K
4K
256
512
768
1,024
1,536
2,048
RAM size (bytes)
Note : Products under development or planning : the development schedule and specifications may be revised without notice.
Fig. 4 Memory expansion plan
Currently supported products are listed below.
Table 3 List of supported products
Product
M38B49MFH-XXXXFP
M38B47MCH-XXXXFP
6
ROM size (bytes)
ROM size for User ( )
61440
(61310)
49152
(49022)
As of Mar. 2000
Remarks
RAM size (bytes)
Package
2048
80P6N-A
Mask ROM version
1024
80P6N-A
Mask ROM version
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016 ”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine
calls (see Table 4).
The 38B4 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PC L. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b0
b7
Y
b7
Index register Y
b0
S
b15
b7
Stack pointer
b0
PCL
PCH
b7
Program counter
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 5 740 Family CPU register structure
7
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Interrupt request
(Note)
M (S)
Execute JSR
Push return address
on stack
M (S)
(PCH)
(S)
(S) – 1
M (S)
(PCL)
(S)
(S)– 1
(S)
M (S)
(S)
M (S)
(S)
Subroutine
POP return
address from stack
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
(S) – 1
(PCL)
Push return address
on stack
(S) – 1
(PS)
Push contents of processor
status register on stack
(S) – 1
Interrupt
Service Routine
Execute RTS
(S)
(PCH)
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTI
Note: Condition for acceptance of an interrupt
(S)
(S) + 1
(PS)
M (S)
(S)
(S) + 1
(PCL)
M (S)
(S)
(S) + 1
(PCH)
M (S)
POP contents of
processor status
register from stack
POP return
address
from stack
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 6 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
8
Push instruction to stack
Pop instruction from stack
PHA
PHP
PLA
PLP
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Processor Status Register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
C flag
Set instruction
Clear instruction
SEC
CLC
Z flag
_
_
I flag
D flag
SEI
CLI
SED
CLD
B flag
_
_
T flag
V flag
SET
CLT
_
CLV
N flag
_
_
9
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B 16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit etc.
The CPU mode register is allocated at address 003B 16 .
b7
b0
CPU mode register
(CPUM: address 003B16)
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1:
1 0 : Not available
1 1:
Stack page selection bit
0: Page 0
1: Page 1
Not available
Port XC switch bit
0: I/O port function
1: XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0: Oscillating
1: Stopped
Main clock division ratio selection bit
0: f(XIN) (high-speed mode)
1: f(XIN)/4 (middle-speed mode)
Internal system clock selection bit
0: XIN-XOUT selection (middle-/high-speed mode)
1: XCIN-XCOUT selection (low-speed mode)
Fig. 7 Structure of CPU mode register
10
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains
control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero
page area. The internal RAM and the special function registers (SFR)
are allocated to this area.
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing programs.
The 256 bytes from addresses FF0016 to FFFF 16 are called the special page area. The special page addressing mode can be used to
specify memory addresses in the special page area. Access to this
area with only 2 bytes is possible in the special page addressing
mode.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM size
(byte)
192
256
384
512
640
768
896
1024
1536
2048
Address
XXXX16
000016
RAM
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
SFR area 1
Zero page
004016
010016
XXXX16
Reserved area
044016
Not used (Note)
0EF016
0EFF16
0F0016
ROM area
ROM size
(byte)
Address
YYYY16
Address
ZZZZ16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
ROM
0FFF16
YYYY16
SFR area 2
RAM area for Serial I/O automatic
transfer
RAM area for FLD automatic display
Reserved ROM area
(common ROM area,128 byte)
ZZZZ16
FF0016
FFDC16
FFFE16
FFFF16
Special page
Interrupt vector area
Reserved ROM area
Note: When 1024 bytes or more are used as RAM area, this area can be used.
Fig. 8 Memory map diagram
11
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
Port P0 (P0)
002016
Timer 1 (T1)
000116
Port P0 direction register (P0D)
002116
Timer 2 (T2)
000216
Port P1 (P1)
002216
Timer 3 (T3)
002316
Timer 4 (T4)
000416
Port P2 (P2)
002416
Timer 5 (T5)
000516
Port P2 direction register (P2D)
002516
Timer 6 (T6)
000616
Port P3 (P3)
002616
PWM control register (PWMCON)
000316
002716
Timer 6 PWM register (T6PWM)
000816
Port P4 (P4)
002816
Timer 12 mode register (T12M)
000916
Port P4 direction register (P4D)
002916
Timer 34 mode register (T34M)
000A16
Port P5 (P5)
002A16
Timer 56 mode register (T56M)
000B16
Port P5 direction register (P5D)
002B16
Watchdog timer control register (WDTCON)
000C16
Port P6 (P6)
002C16
Timer X (low-order) (TXL)
000D16
Port P6 direction register (P6D)
002D16
Timer X (high-order) (TXH)
000E16
Port P7 (P7)
002E16
Timer X mode register 1 (TXM1)
000F16
Port P7 direction register (P7D)
002F16
Timer X mode register 2 (TXM2)
001016
Port P8 (P8)
003016
Interrupt interval determination register (IID)
001116
Port P8 direction register (P8D)
003116
Interrupt interval determination control register (IIDCON)
001216
Port P9 (P9)
003216
A-D control register (ADCON)
001316
Port P9 direction register (P9D)
003316
A-D conversion register (low-order) (ADL)
001416
PWM register (high-order) (PWMH)
003416
A-D conversion register (high-order) (ADH)
001516
PWM register (low-order) (PWM L)
003516
001616
Baud rate generator (BRG)
003616
001716
UART control register (UARTCON)
003716
001816
Serial I/O1 automatic transfer data pointer (SIO1DP)
003816
001916
Serial I/O1 control register 1 (SIO1CON1)
003916
Interrupt source switch register (IFR)
001A16
Serial I/O1 control register 2 (SIO1CON2)
003A16
Interrupt edge selection register (INTEDGE)
001B16
Serial I/O1 register/Transfer counter (SIO1)
003B16
CPU mode register (CPUM)
001C16
Serial I/O1 control register 3 (SIO1CON3)
003C16
Interrupt request register 1(IREQ1)
001D16
Serial I/O2 control register (SIO2CON)
003D16
Interrupt request register 2(IREQ2)
001E16
Serial I/O2 status register (SIO2STS)
003E16
Interrupt control register 1(ICON1)
001F16
Serial I/O2 transmit/receive buffer register (TB/RB)
003F16
Interrupt control register 2(ICON2)
0EF016
Pull-up control register 1 (PULL1)
0EF816
FLD data pointer (FLDDP)
0EF116
Pull-up control register 2 (PULL2)
0EF916
Port P0FLD/port switch register (P0FPR)
0EF216
0EFA16
Port P2FLD/port switch register (P2FPR)
0EF316
0EFB16
Port P8FLD/port switch register (P8FPR)
000716
0EF416
FLDC mode register (FLDM)
0EFC16 Port P8FLD output control register (P8FLDCON)
0EF516
Tdisp time set register (TDISP)
0EFD16 Buzzer output control register (BUZCON)
0EF616
Toff1 time set register (TOFF1)
0EFE16
0EF716
Toff2 time set register (TOFF2)
0EFF16
Fig. 9 Memory map of special function register (SFR)
12
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
[Direction Registers] PiD
The 38B4 group has 51 programmable I/O pins arranged in eight
individual I/O ports (P0, P2, P40–P4 6, and P5–P9). The I/O ports
have direction registers which determine the input/output direction of
each individual pin. Each bit in a direction register corresponds to
one pin, and each pin can be set to be input port or output port. When
“0” is written to the bit corresponding to a pin, that pin becomes an
input pin. When “1” is written to that pin, that pin becomes an output
pin. If data is read from a pin set to output, the value of the port
output latch is read, not the value of the pin itself. Pins set to input
(the bit corresponding to that pin must be set to “0”) are floating and
the value of that pin can be read. If a pin set to input is written to, only
the port output latch is written to and the pin remains floating.
b7
b0
Pull-up control register 1
(PULL1 : address 0EF016)
P50, P51 pull-up control bit
P52, P53 pull-up control bit
P54, P55 pull-up control bit
P56, P57 pull-up control bit
P61 pull-up control bit
0: No pull-up
1: Pull-up
P62, P63 pull-up control bit
P64, P65 pull-up control bit
Not used
(returns “0” when read)
[High-Breakdown-Voltage Output Ports]
The 38B4 group has 5 ports with high-breakdown-voltage pins (ports
P0–P3 and P8 0–P83). The high-breakdown-voltage ports have Pchannel open-drain output with Vcc- 45 V of breakdown voltage. Each
pin in ports P0, P1, and P3 has an internal pull-down resistor connected to V EE. At reset, the P-channel output transistor of each port
latch is turned off, so that it goes to VEE level (“L”) by the pull-down
resistor.
Writing “1” (weak drivability) to bit 7 of the FLDC mode register (address 0EF416 ) shows the rising transition of the output transistors for
reducing transient noise. At reset, bit 7 of the FLDC mode register is
set to “0” (strong drivability).
[Pull-up Control Register] PULL
Ports P5, P61–P65, P7, P84–P87 and P9 have built-in programmable
pull-up resistors. The pull-up resistors are valid only in the case that
the each control bit is set to “1” and the corresponding port direction
registers are set to input mode.
b7
b0
Pull-up control register 2
(PULL2 : address 0EF116)
P70, P71 pull-up control bit
P72, P73 pull-up control bit
P74, P75 pull-up control bit
P76, P77 pull-up control bit
P84, P85 pull-up control bit
0: No pull-up
1: Pull-up
P86, P87 pull-up control bit
P90, P91 pull-up control bit
Not used
(returns “0” when read)
Fig. 10 Structure of pull-up control registers (PULL1 and
PULL2)
13
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 List of I/O port functions (1)
zPin
Name
Input/Output
Port P0
Input/output,
individual bits
CMOS compatible input level FLD automatic display function FLDC mode register
High-breakdown voltage PPort P0FLD/port switch register
P10/FLD16– Port P1
P17/FLD23
Output
channel open-drain output
with pull-down resistor
High-breakdown voltage Pchannel open-drain output
with pull-down resistor
P20/BUZ02/ Port P2
FLD0
P21/FLD1–
P27/FLD7
P30/FLD24– Port P3
Input/output,
individual bits
P00/FLD8–
P07/FLD15
Output
P37/FLD31
P40/INT0,
P41/INT1
P42/INT3
Port P4
P43/BUZ01
P44/PWM1
P45/T1OUT
P46/T3OUT
P47/INT2
Input
P50/SIN1
Port P5
P51/SOUT1,
P52/SCLK11,
P53/SCLK12
P54/RXD
P55/TXD,
P56/SCLK21
P57/SRDY2/
SCLK22
P60/CNTR1 Port P6
P61/CNTR0/
CNTR2
P62/SRDY1/
AN8
P63/AN9
P64/INT4/
SBUSY1/AN10
P65/SSTB1/
AN11
P70/AN0–
P77/AN7
14
Input/output,
individual bits
Port P7
Input/output,
individual bits
I/O Format
Low-voltage input level
High-breakdown voltage Pchannel open-drain output
Non-Port Function
Related SFRs
FLDC mode register
Buzzer output (P20)
FLDC mode register
FLD automatic display function Port P2FLD/port switch register
FLD automatic display function Buzzer output control register
High-breakdown voltage P-
FLDC mode register
Ref.No.
(1)
(2)
(3)
(1)
(2)
channel open-drain output
with pull-down resistor
CMOS compatible input level External interrupt input
Interrupt edge selection register
(5)
N-channel open-drain output In the mask option type P, INT3
cannot be used.
(7-1) (7-2)
Buzzer output
Buzzer output control register
(4)
PWM output
Timer 56 mode register
(6)
Timer output
Timer 12 mode register
(8-1)
Timer output
Timer 34 mode register
(8-2)
CMOS compatible input level External interrput input
Interrupt edge selection register
(9)
Interrupt interval determination
control register
CMOS compatible input level Serial I/O1 function I/O
CMOS 3-state output
Serial I/O2 function I/O
Serial I/O1 control register 1, 2
(10)
(11)
Serial I/O2 control register
UART control register
(10)
(11)
(12)
CMOS compatible input level External count input
N-channel open-drain output In the mask option type P,
CMOS compatible input level CNTR1 cannot be used.
CMOS 3-state output
Serial I/O1 function I/O
A-D conversion input
A-D conversion input
Dimmer signal output
Serial I/O1 function I/O
A-D conversion input
External interrupt input
Serial I/O1 function I/O
A-D conversion input
A-D conversion input
Interrupt edge selection register
(7-1)
(7-2)
(13)
Serial I/O1 control register 1, 2
A-D control register
(14)
A-D control register
P8FLD output control bit
Serial I/O1 control register 1, 2
A-D control register
Interrupt edge selection register
Serial I/O1 control register 1, 2
A-D control register
A-D control register
(15)
(16)
(17)
(15)
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 List of I/O port functions (2)
Name
Input/Output
I/O Format
P80/FLD32 – Port P8
P83/FLD35
Pin
Input/output,
individual bits
Low-voltage input level
High-breakdown voltage Pchannel open-drain output
Low-voltage input level
CMOS 3-state output
P84/FLD36
P85/RTP0/
FLD 37,
P86/RTP1/
FLD38
P87/PWM0/
FLD 39
P90/XCIN
P91/XCOUT
Non-Port Function
Related SFRs
FLD automatic display function FLDC mode register
Port P8FLD/port switch register
FLD automatic display function FLDC mode register
Real time port output
(1)
(18)
(19)
Port P8FLD/port switch register
Timer X mode register 2
FLD automatic display function FLDC mode register
PWM output
Port P8FLD/port switch register
PWM control register
Port P9
Ref.No.
CMOS compatible input level Sub-clock generating circuit I/O CPU mode register
CMOS 3-state output
(20)
(21)
(22)
Notes 1 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
2 : How to use double-function ports as function I/O ports, refer to the applicable sections.
15
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P21–P27, P80–P83
(2) Ports P1, P3
FLD/Port
switch register
Dimmer signal (Note 1)
*
Port latch
Data bus
Dimmer signal (Note 1)
Local data
bus
Direction register
Local data
bus
*
Port latch
Data bus
read
VEE
(Note 2)
VE E
(3) Port P20
(4) Port P43
FLD/Port
switch register
Buzzer control signal
Buzzer signal output
Buzzer control signal
Buzzer signal output
Dimmer signal (Note 1)
Local data
bus
Direction register
Data bus
Port latch
Direction register
Data bus
*
#
Port latch
read
read
(Note 2)
VEE
(5) Ports P40, P41
(6) Port P44
Timer 6 output selection bit
Direction register
Data bus
Port latch
Direction register
Data bus
#
Port latch
read
INT0,INT1 interrupt input
Timer 6 output
* High-breakdown-voltage P-channel transistor
# Middle-breakdown-voltage N-channel transistor
Notes 1: The dimmer signal sets the Toff timing.
2: A pull-down resistor is not built in to ports P2 and P8.
Fig. 11 Port block diagram (1)
16
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(7-2) Ports P42, P60 (mask option type P)
(7-1) Ports P42, P60
Direction register
Direction register
Data bus
Port latch
#
Data bus
#
Port latch
read
INT3 interrupt input
CNTR1 input
(8-2) Ports P45, P46 (mask option type P)
(8-1) Ports P45, P46
Timer 1 output bit
Timer 3 output bit
Timer 1 output bit
Timer 3 output bit
Direction register
Direction register
Data bus
Port latch
#
Data bus
#
Port latch
read
Timer 1 output
Timer 3 output
Timer 1 output
Timer 3 output
(9) Port P47
(10) Ports P50, P54
Pull-up control
Data bus
INT2 interrupt
input
Direction register
Data bus
Port latch
Serial I/O input
# Middle-breakdown-voltage N-channel transistor
Fig. 12 Port block diagram (2)
17
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(11) Ports P51–P53, P55, P56
(12) Port P57
Pull-up control
P-channel output disable signal (P51,P55)
Output OFF control signal
Serial I/O2 mode selection bit
Pull-up control
SRDY2 output enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
TXD, SOUT or SCLK
Port latch
Serial ready output
Serial clock input
Serial clock input
P52,P53,P56
(13) Port P61
(14) Port P62
Pull-up control
Pull-up control
P62/SRDY1•P64/SBUSY1
pin control bit
Timer X operating mode bit
Direction register
Direction register
Port latch
Data bus
Data bus
Timer X output
CNTR0,CNTR2 input
Timer 2, Timer X external clock input
(15) Ports P63, P7
Port latch
Serial ready output
Serial ready input
A-D conversion input
Analog input pin selection bit
(16) Port P64
Pull-up control
P62/SRDY1•P64/SBUSY1
pin control bit
Pull-up control
Dimmer output control bit (P63)
Direction register
Direction register
Data bus
Data bus
Port latch
Port latch
SBUSY1 output
INT4 interrupt input, SBUSY1 input
Dimmer signal output (P63)
A-D conversion input
Analog input pin selection bit
Fig. 13 Port block diagram (3)
18
A-D conversion input
Analog input
pin selection
bit
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Port P65
(18) Port P84
Pull-up control
P65/SSTB1 pin control bit
Dimmer signal
(Note)
Direction register
Direction register
Port latch
Data bus
Pull-up control
FLD/Port
switch register
Local data
bus
Port latch
Data bus
SSTB1 output
A-D conversion input
(19) Ports P85, P86
(20) Port P87
Dimmer signal
(Note)
Pull-up control
Dimmer signal
(Note)
FLD/Port
switch register
FLD/Port
switch register
Real time port
control bit
Direction register
Local data
bus
Data bus
Local data
bus
Port latch
Direction register
Port latch
Data bus
RTP output
PWM0 output
(21) Port P90
(22) Port P91
Pull-up control
Pull-up control
Port Xc switch bit
Port Xc switch bit
Direction register
Data bus
Pull-up control
P87/PWM
output enable
bit
Port latch
Direction register
Data bus
Port latch
Oscillator
Port P90
Sub-clock generating circuit input
Port Xc switch bit
* High-breakdown-voltage P-channel transistor
Note: The dimmer signal sets the Toff timing.
Fig. 14 Port block diagram (4)
19
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by twenty one sources: five external, fifteen internal,
and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an
interrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are “1” and the interrupt disable flag
is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by
software. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occurs
at the same time the interrupt with highest priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are automatically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Use
When the active edge of an external interrupt (INT0–INT4) is set or
when switching interrupt sources in the same vector address, the
corresponding interrupt request bit may also be set. Therefore, please
take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(3) Clear the set interrupt request bit to “0”.
(4) Enable the external interrupt which is selected.
20
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 8 Interrupt vector addresses and priority
Interrupt Source Priority
Vector Addresses (Note 1)
High
Low
Reset (Note 2)
INT0
1
2
FFFD16
FFFB16
FFFC16
FFFA16
INT1
3
FFF916
FFF816
INT2
4
FFF716
Remote control/
counter overflow
Serial I/O1
5
FFF516
Interrupt Request
At reset
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
FFF616
At detection of either rising or falling edge of
INT2 input
At 8-bit counter overflow
FFF416
At completion of data transfer
External interrupt
(active edge selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O ordinary
Serial I/O automatic transfer
Timer X
Timer 1
6
7
FFF316
FFF116
FFF216
FFF016
At timer X underflow
At timer 1 underflow
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
8
9
10
11
12
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFEE16
FFEC16
FFEA16
FFE816
FFE616
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
Serial I/O2 receive
INT3
13
14
FFE516
FFE316
FFE416
FFE216
Serial I/O2 transmit
INT4
15
FFE116
FFE016
At completion of serial I/O2 data receive
At detection of either rising or falling edge of
INT3 input
At completion of serial I/O2 data transmit
At detection of either rising or falling edge of
At completion of the last data transfer
INT4 input
A-D conversion
FLD blanking
16
FFDF16
Remarks
Generating Conditions
FFDE16
At completion of A-D conversion
At falling edge of the last timing immediately
before blanking period starts
mode is selected
Valid when serial I/O automatic
transfer mode is selected
STP release timer underflow
(Note 3)
External interrupt (Note 4)
(active edge selectable)
External interrupt
(active edge selectable)
Valid when INT4 interrupt is selected
Valid when A-D conversion is selected
Valid when FLD blanking
interrupt is selected
FLD digit
At rising edge of digit (each timing)
Valid when FLD digit interrupt is selected
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
3 : In the mask option type P, timer 4 interrupt whose count source is CNTR1 input cannot be used.
4 : In the mask option type P, INT3 interrupt cannot be used.
21
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag I
Interrupt request
BRK instruction
Reset
Fig. 15 Interrupt control
b7
b0 Interrupt source switch register
(IFR : address 003916)
INT3/serial I/O2 transmit interrupt switch bit (Note 1)
0 : INT3 interrupt
1 : Serial I/O2 transmit interrupt
INT4/AD conversion interrupt switch bit
0 : INT4 interrupt
1 : A-D conversion interrupt
Not used (return “0” when read)
(Do not write “1” to these bits.)
b7
b0 Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
0 : Falling edge active
INT2 interrupt edge selection bit
1 : Rising edge active
INT3 interrupt edge selection bit (Note 1)
INT4 interrupt edge selection bit
Not used (return “0” when read)
0 : Rising edge count
CNTR0 pin edge switch bit
1 : Falling edge count
CNTR1 pin edge switch bit (Note 1)
b7
b0 Interrupt request register 1
(IREQ1 : address 003C16)
b7
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Remote controller/counter overflow interrupt
request bit
Serial I/O1 interrupt request bit
Timer 4 interrupt request bit (Note 2)
Timer 5 interrupt request bit
Timer 6 interrupt request bit
Serial I/O2 receive interrupt request bit
INT3/serial I/O2 transmit interrupt request bit (Note 2)
INT4 interrupt request bit
AD conversion interrupt request bit
FLD blanking interrupt request bit
FLD digit interrupt request bit
Not used (returns “0” when read)
Serial I/O automatic transfer interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
b7
b0 Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Remote controller/counter overflow interrupt
enable bit
Serial I/O1 interrupt enable bit
Serial I/O automatic transfer interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
b0 Interrupt request register 2
(IREQ2 : address 003D16)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 2
(ICON2 : address 003F16)
Timer 4 interrupt enable bit (Note 3)
Timer 5 interrupt enable bit
Timer 6 interrupt enable bit
Serial I/O2 receive interrupt enable bit
INT3/serial I/O2 transmit interrupt enable bit (Note 3)
INT4 interrupt enable bit
AD conversion interrupt enable bit
FLD blanking interrupt enable bit
FLD digit interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupt disabled
1 : Interrupt enabled
Notes 1: In the mask option type P, these bits are not available because CNTR1 function and INT3 function cannot be used.
2: In the mask option type P, if timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are selected, these bits do not become “1”.
3: In the mask option type P, timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are not available.
Fig. 16 Structure of interrupt related registers
22
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
8-Bit Timer
b7
b0
Timer 12 mode register
(T12M: address 002816)
The 38B4 group has six built-in timers : Timer 1, Timer 2, Timer 3,
Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “00 16”, an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is
set to “1”.
The count can be stopped by setting the stop bit of each timer to “1”.
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
timer internal count source is switched to either f(X IN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 can be output from the P4 5/T1OUT pin. The
active edge of the external clock CNTR 0 can be switched with the bit
6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0”, timer 1 is set to “FF 16”, and timer 2
is set to “0116”.
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : f(XCIN)
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 2 count source selection bits
00 : Underflow of Timer 1
01 : f(XCIN)
10 : External count input CNTR0
11 : Not available
Timer 1 output selection bit (P45)
0 : I/O port
1 : Timer 1 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
Timer 34 mode register
(T34M: address 002916)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 2
10 : f(XIN)/16 or f(XCIN)/32
11 : f(XIN)/64 or f(XCIN)/128
Timer 4 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 3
10 : External count input CNTR1 (Note)
11 : Not available
Timer 3 output selection bit (P46)
0 : I/O port
1 : Timer 3 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 can be output from the P4 6/T3OUT pin. The
active edge of the external clock CNTR 1 (Note) can be switched with
the bit 7 of the interrupt edge selection register.
Note: In the mask option type P, CNTR 1 function cannot be used.
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 can be output from the P4 4/PWM1 pin.
(1) Timer 6 PWM 1 mode
Timer 6 can output a PWM rectangular waveform with “H” duty cycle
n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode register (refer to Figure 19). The n is the value set in timer 6 latch (address
0025 16) and m is the value in the timer 6 PWM register (address
0027 16). If n is “0”, the PWM output is “L”, if m is “0”, the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
b7
b0
Timer 56 mode register
(T56M: address 002A16)
Timer 5 count stop bit
0 : Count operation
1 : Count stop
Timer 6 count stop bit
0 : Count operation
1 : Count stop
Timer 5 count source selection bit
0 : f(XIN)/8 or f(XCIN)/16
1 : Underflow of Timer 4
Timer 6 operation mode selection bit
0 : Timer mode
1 : PWM mode
Timer 6 count source selection bits
00 : f(XIN)/8 or f(XCIN)/16
01 : Underflow of Timer 5
10 : Underflow of Timer 4
11 : Not available
Timer 6 (PWM) output selection bit (P44)
0 : I/O port
1 : Timer 6 output
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Note: In the mask option type P, CNTR1 function cannot be used.
Fig. 17 Structure of timer related register
23
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
XCIN
Timer 1 latch (8)
1/2
Timer 1 count source
“1”
Internal system clock
selection bit
1/8
XIN
“0”
“01” selection bits
Timer 1 (8)
“00”
1/16
FF16
“10”
RESET
STP instruction
Timer 1 interrupt request
Timer 1 count
stop bit
1/64
P45/T1OUT
“11”
P45 latch
1/2
Timer 1 output selection bit
Timer 2 latch (8)
“00”
Timer 2 count source
selection bits
0 116
Timer 2 (8)
P45 direction register
“10”
P61/CNTR0/CNTR2
Timer 2 interrupt request
“01”
Timer 2 count
stop bit
Rising/Falling
active edge switch
Timer 3 latch (8)
“01”
“00”
P46/T3OUT
Timer 3 count source
selection bits
Timer 3 (8)
Timer 3 interrupt request
Timer 3 count
stop bit
“10”
P46 latch
“11”
1/2
Timer 3 output selection bit
Timer 4 latch (8)
“01”
P46 direction register
Timer 4 count source
selection bits
Timer 4 (8)
“00”
P60/CNTR1
(Note)
Timer 4 interrupt request
Timer 4 count
stop bit
“10”
Rising/Falling
active edge switch
Timer 5 latch (8)
“1”
Timer 5 count source
selection bit
Timer 5 (8)
“0”
Timer 5 interrupt request
Timer 5 count
stop bit
Timer 6 latch (8)
“01”
Timer 6 count source
selection bits
Timer 6 (8)
“00”
Timer 6 interrupt request
Timer 6 count
stop bit
“10”
Timer 6 PWM register (8)
P44/PWM1
P44 latch
“1”
“0”
PWM
1/2
Timer 6 output selection bit
Timer 6 operation
mode selection bit
P44 direction register
Fig. 18 Block diagram of timer
24
Note: In the mask option type P, CNTR1 function cannot be used.
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts
Timer 6
count source
Timer 6 PWM
mode
n ✕ ts
m ✕ ts
(n+m) ✕ ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: PWM waveform (duty : n/(n + m) and period: (n + m) ✕ ts) is output.
n : setting value of Timer 6
m: setting value of Timer 6 PWM register
ts: period of Timer 6 count source
Fig. 19 Timing chart of timer 6 PWM1 mode
25
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
16-Bit Timer
■ Note
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode registers 1, 2 and can be controlled the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
•Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
●Timer X
Timer X is a down-counter. When the timer reaches “000016”, an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues downcounting. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR2 active edge switch bit is “0”, the timer counts while the input
signal of the CNTR2 pin is at “H”. When it is “1”, the timer counts
while the input signal of the CNTR2 pin is at “L”. When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
26
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P85 and P86 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1”,
data are output without the timer X.) When the data for the real time
port is changed while the real time port function is valid, the changed
data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction registers to output mode.
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Real time port
control bit “1”
Data bus
Q D
P85
P85 data for real time port
“0 ”
Latch
P85 direction
register
P85 latch
Real time port
control bit “1”
Q D
Real time port
control bit (P85) “0”
“0 ”
Latch
P86 direction
register
P86 latch
Real time port
control bit (P86) “0”
“1 ”
Timer X mode register
write signal
P86 data for real time port
P86
XCIN
1/2
“1 ”
Timer X mode register
write signal
Internal system clock
selection bit
1/2
XIN
Count source selection bit
1/8
“0 ”
1/64
Timer X stop
Timer X write
control bit
control bit
Timer X operating
mode bits
CNTR2 active
h
o
r
der) (8)
T
i
m
e
r
X
l
a
t
c
h
(
h
i
g
Timer X latch (low-order) (8)
edge switch bit
“00”,“01”,“11”
“0 ”
P61/CNTR0/CNTR2
Timer X (low-order) (8)
Timer X (high-order) (8)
“10”
“1 ”
Pulse width
measurement mode
Pulse output mode
CNTR2 active
edge switch bit “0”
S
Q
T
“1 ”
Q
P61 direction
register
P61 latch
Divider
“1 ”
Timer X
interrupt request
Pulse output mode
CNTR0
Fig. 20 Block diagram of timer X
b7
b7
b0
b0
Timer X mode register 1
(TXM1 : address 002E16)
Timer X mode register 2
(TXM2 : address 002F16)
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bits
b2 b1
0 0 : f(XIN)/2 or f(XCIN)/4
0 1 : f(XIN)/8 or f(XCIN)/16
1 0 : f(XIN)/64 or f(XCIN)/128
1 1 : Not available
Not used (returns “0” when read)
Timer X operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
CNTR2 active edge switch bit
0 : • Event counter mode ; counts rising edges
• Pulse output mode ; output starts with “H” level
• Pulse width measurement mode ; measures “H” periods
1 : • Event counter mode ; counts falling edges
• Pulse output mode ; output starts with “L” level
• Pulse width measurement mode ; measures “L” periods
Timer X stop control bit
0 : Count operating
1 : Count stop
Real time port control bit (P85)
0 : Real time port function is invalid
1 : Real time port function is valid
Real time port control bit (P86)
0 : Real time port function is invalid
1 : Real time port function is valid
P85 data for real time port
P86 data for real time port
Not used (returns “0” when read)
Fig. 21 Structure of timer X related registers
27
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
Serial I/O1
FLD automatic display RAM).
The P62/SRDY1 /AN8, P64/INT4/S BUSY1/AN10, and P65/S STB1/AN11
pins each have a handshake I/O signal function and can select
either “H” active or “L” active for active logic.
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
0F0016 to 0FFF16 : addresses 0F6016 to 0FFF16 are also used as
Main address
bus
Local address
bus
Serial I/O automatic
transfer RAM
(0F0016—0FFF16)
Main
Local
data bus data bus
Serial I/O1
automatic transfer
data pointer
Address decoder
Serial I/O1
automatic transfer
controller
XCIN
1/2
Serial I/O1
control register 3
Internal system
clock selection bit
“1 ”
“0 ”
P65 latch
“0 ”
P65/SSTB1
Divider
XIN
(P65/SSTB1 pin control bit)
“1 ”
P62/SRDY1•P64/SBUSY1
pin control bit
P64 latch
“0 ”
Serial I/O1
synchronous clock
selection bit
“0”
P64/SBUSY1
“1 ”
P62/SRDY1•P64/SBUSY1
P62 latch
pin control bit
1/4
1/8
1/16
1/32
1/64
1/128
1/256
Internal synchronous
clock selection bits
Synchronous
circuit
“1”
SCLK1
“0 ”
P62/SRDY1
“1 ”
Serial I/O1 clock
pin selection bit
“0 ”
“1 ”
Serial transfer
status flag
P52 latch
“0 ”
P52/SCLK11
“0 ”
“1 ”
“1 ”
Serial I/O1 counter
“1 ”
P53/SCLK12
Serial I/O1 clock
pin selection bits
“0 ”
P53 latch
“0 ”
P51/SOUT1
P51 latch
“1” Serial transfer selection bits
P50/SIN1
Fig. 22 Block diagram of serial I/O1
28
Serial I/O1 register (8)
Serial I/O1
interrupt request
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 control register 1
(SIO1CON1 (SC11):address 001916)
Serial transfer selection bits
00: Serial I/O disabled (pins P62,P64,P65,and P50—P53 are I/O ports)
01: 8-bit serial I/O
10: Not available
11: Automatic transfer serial I/O (8-bits)
Serial I/O1 synchronous clock selection bits (P65/SSTB1 pin control bits)
00: Internal synchronous clock (P65 pin is an I/O port.)
01: External synchronous clock (P65 pin is an I/O port.)
10: Internal synchronous clock (P65 pin is an SSTB1 output.)
11: Internal synchronous clock (P65 pin is an SSTB1 output.)
Serial I/O initialization bit
0: Serial I/O initialization
1: Serial I/O enabled
Transfer mode selection bit
0: Full duplex (transmit and receive) mode (P50 pin is an SIN1 input.)
1: Transmit-only mode (P50 pin is an I/O port.)
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O1 clock pin selection bit
0:SCLK11 (P53/SCLK12 pin is an I/O port.)
1:SCLK12 (P52/SCLK11 pin is an I/O port.)
b7
b0
Serial I/O1 control register 2
(SIO1CON2 (SC12): address 001A16)
P62/SRDY1 • P64/SBUSY1 pin control bits
0000: Pins P62 and P64 are I/O ports
0001: Not used
0010: P62 pin is an SRDY1 output, P64 pin is an I/O port.
0011: P62 pin is an SRDY1 output, P64 pin is an I/O port.
0100: P62 pin is an I/O port, P64 pin is an SBUSY1 input.
0101: P62 pin is an I/O port, P64 pin is an SBUSY1 input.
0110: P62 pin is an I/O port, P64 pin is an SBUSY1 output.
0111: P62 pin is an I/O port, P64 pin is an SBUSY1 output.
1000: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1001: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1010: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1011: P62 pin is an SRDY1 input, P64 pin is an SBUSY1 output.
1100: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
1101: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
1110: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
1111: P62 pin is an SRDY1 output, P64 pin is an SBUSY1 input.
SBUSY1 output • SSTB1 output function selection bit
(Valid in automatic transfer mode)
0: Functions as each 1-byte signal
1: Functions as signal for all transfer data
Serial transfer status flag
0: Serial transfer completion
1: Serial transferring
SOUT1 pin control bit (at no-transfer serial data)
0: Output active
1: Output high-impedance
P51/SOUT1 P-channel output disable bit
0: CMOS 3-state (P-channel output is valid.)
1: N-channel open-drain (P-channel output is invalid.)
Fig. 23 Structure of serial I/O1 control registers 1, 2
29
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●Serial I/O1 operation
Either the internal synchronous clock or external synchronous clock
can be selected by the serial I/O1 synchronous clock selection bits
(b2 and b3 of address 001916 ) of serial I/O1 control register 1 as
synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider where
7 different clocks are selected by the internal synchronous clock
selection bits (b5, b6 and b7 of address 001C16) of serial I/O1
control register 3.
The P62/SRDY1 /AN8, P64/INT4/SBUSY1/AN 10, and P65/S STB1/AN11
pins each select either I/O port or handshake I/O signal by the
serial I/O1 synchronous clock selection bits (b2 and b3 of address
001916) of serial I/O1 control register 1 as well as the P62/SRDY1 •
P64/SBUSY1 pin control bits (b0 to b3 of address 001A16 ) of serial
I/O1 control register 2.
For the SOUT1 being used as an output pin, either CMOS output or
N-channel open-drain output is selected by the P5 1/S OUT1
P-channel output disable bit (b7 of address 001A16) of serial I/O1
control register 2.
Either output active or high-impedance can be selected as a SOUT1
pin state at serial non-transfer by the SOUT1 pin control bit (b6 of
address 001A16 ) of serial I/O1 control register 2. However, when
the external synchronous clock is selected, perform the following
setup to put the SOUT1 pin into a high-impedance state.
b7
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1”.
When the SCLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the transmit-only mode are available for serial transfer, one of which is selected by the transfer mode selection bit (b5 of address 001916 ) of
serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6 of
address 001916) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or automatic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 001916) of serial I/O1 control register 1, after completion of the above bit setup. Next, set the serial I/O initialization bit
(b4 of address 001916) of serial I/O1 control register 1 to “1” (Serial
I/O enable) .
When stopping serial transfer while data is being transferred, regardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0”.
b0
Serial I/O1 control register 3
(SIO1CON3 (SC13): address 001C16)
Automatic transfer interval set bits
00000: 2 cycles of transfer clocks
00001: 3 cycles of transfer clocks
:
11110: 32 cycles of transfer clocks
11111: 33 cycles of transfer clocks
Data is written to a latch and read from a decrement counter.
Internal synchronous clock selection bits
000: f(XIN)/4 or f(XCIN)/8
001: f(XIN)/8 or f(XCIN)/16
010: f(XIN)/16 or f(XCIN)/32
011: f(XIN)/32 or f(XCIN)/64
100: f(XIN)/64 or f(XCIN)/128
101: f(XIN)/128 or f(XCIN)/256
110: f(XIN)/256 or f(XCIN)/512
Fig. 24 Structure of serial I/O1 control register 3
30
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) 8-bit serial I/O mode
Address 001B16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B16).
The serial transfer status flag (b5 of address 001A16) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by writing into the serial I/O1 register, which becomes a transfer start trigger and reset to “0” after completion of 8bit transfer. At the same time, a serial I/O1 interrupt request occurs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer clocks
are input to SCLK1. Therefore, the clock needs to be controlled externally.
(2) Automatic transfer serial I/O mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so the function of address 001B16 is used as a transfer counter (1-byte units).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16 ), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
Input the low-order 8 bits of the first data store address to be serially transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer interval for each 1-byte data can be set by the automatic transfer interval set bits (b0 to b4 of address 001C16) of serial I/O1 control register 3 in the following cases:
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or a
combination of SBUSY1 output and SSTB1 output of the handshake
signal
It is possible to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the SBUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16) of serial
I/O1 control register 2 as the signal for all transfer data, provided
b7
that the automatic transfer interval setting is valid, a transfer interval is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the SBUSY1 output •
SSTB1 output function selection bit (b4), the transfer interval for each
1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of SBUSY1 output and SSTB1
output as a signal for all transfer data, the transfer interval after the
end of transmission/reception of the last data is longer than the set
value by 2 cycles.
When the external synchronous clock is selected, automatic transfer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes - 1” into the transfer counter
(address 001B16 ).
When the external synchronous clock is selected, write the value of
“number of transfer bytes - 1” into the transfer counter and input an
internal system clock interval of 5 cycles or more. After that, input
transfer clock to SCLK1.
As a transfer interval for each 1-byte data transfer, input an internal
system clock interval of 5 cycles or more from the clock rise time of
the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The serial transfer
status flag (b5 of address 001A16 ) is set to “1” by writing data into
the transfer counter. Writing data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data is
written into the automatic transfer RAM. At the same time, a serial
I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816 ) and the automatic transfer interval set
bits (b0 to b4 of address 001C 16) are held in the latch.
When data is written into the transfer counter, the values latched in
the automatic transfer data pointer set bits (b0 to b7) and the automatic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
b0
Serial I/O1 automatic transfer data pointer
(SIO1DP: address 001816)
Automatic transfer data pointer set bits
Specify the low-order 8 bits of the first data store address on the serial I/O automatic
transfer RAM. Data is written into the latch and read from the decrement counter.
Fig. 25 Structure of serial I/O1 automatic transfer data pointer
31
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Automatic transfer RAM
FFF16
Automatic transfer
data pointer
5216
F5216
F5116
F5016
F4F16
F4E16
Transfer counter
0416
F0016
SIN1
SOUT1
Serial I/O1 register
Fig. 26 Automatic transfer serial I/O operation
32
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
●Handshake signal
1. SSTB1 output signal
The SSTB1 output is a signal to inform an end of transmission/reception to the serial transfer destination. The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O
initialization bit (b4) is reset to “0”, the SSTB1 output goes to “L”, or
the SSTB1 output goes to “H”.
At the end of transmit/receive operation, when the data of the serial
I/O1 register is all output from SOUT1 , pulses are output in the period of 1 cycle of the transfer clock so as to cause the SSTB1 output
to go “H” or the SSTB1 output to go “L.” After that, each pulse is
returned to the initial status in which SSTB1 output goes to “L” or the
SSTB1 output goes to “H”.
Furthermore, after 1 cycle, the serial transfer status flag (b5) is reset to “0”.
In the automatic transfer serial I/O mode, whether the SSTB1 output
is to be active at an end of each 1-byte data or after completion of
transfer of all data can be selected by the SBUSY1 output • SSTB1
output function selection bit (b4 of address 001A16) of serial I/O1
control register 2.
SSTB1
Serial transfer
status flag
SCLK1
SBUSY1
SCLK1
SOUT1
Fig. 28 SBUSY1 input operation (internal synchronous clock)
When the external synchronous clock is selected, input an “H” level
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped. At this time,
the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 become valid, enabling a transmit/receive operation, while an “L” level
signal is input into the S BUSY1 input and an “H” level signal is input
into the SBUSY1 input.
When changing the input values in the SBUSY1 input and the SBUSY1
input at these operations, change them when the SCLK1 input is in a
high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, enabling serial transfer by inputting a transfer clock to SCLK1, while an
“L” level signal is input into the S BUSY1 input and an “H” level signal
is input into the SBUSY1 input.
SOUT1
SBUSY1
Fig. 27 S STB1 output operation
2. SBUSY1 input signal
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H” level
signal into the SBUSY1 input and an “L” level signal into the SBUSY1
input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level signal
into the SBUSY1 input and an “H” level signal into the SBUSY1 input in
the period of 1.5 cycles or more of the transfer clock. Then, transfer
clocks are output from the SCLK1 output.
When an “H” level signal is input into the SBUSY1 input and an “L”
level signal into the SBUSY1 input after a transmit/receive operation
is started, this transmit/receive operation are not stopped immediately and the transfer clocks from the SCLK1 output is not stopped
until the specified number of bits are transmitted and received.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
SCLK1
Invalid
SOUT1
(Output high-impedance)
Fig. 29 SBUSY1 input operation (external synchronous clock)
3. S BUSY1 output signal
The S BUSY1 output is a signal which requests a stop of transmission/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external synchronous clock, whether the SBUSY1 output is to be active at transfer of each 1-byte data or during transfer of all data can be selected
by the SBUSY1 output • S STB1 output function selection bit (b4).
In the initial status, the status in which the serial I/O initialization bit
(b4) is reset to “0”, the SBUSY1 output goes to “H” and the S BUSY1
output goes to “L”.
33
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the S BUSY1 output goes to “L”
and the SBUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the SCLK1 output goes
to “L” at a start of transmit/receive operation.
In the automatic transfer serial I/O mode (the SBUSY1 output function outputs all transfer data), the SBUSY1 output goes to “L” and the
SBUSY1 output goes to “H” when the first transmit data is written into
the serial I/O1 register (address 001B16).
When the external synchronous clock is selected, the SBUSY1 output goes to “L” and the SBUSY1 output goes to “H” when transmit
data is written into the serial I/O1 register to start a transmit operation, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY1 output returns to “H” and the SBUSY1 output returns to “L”, the initial status,
when the serial transfer status flag is set to “0”, regardless of whether
the internal or external synchronous clock is selected.
Furthermore, in the automatic transfer serial I/O mode (SBUSY1 output function outputs in 1-byte units), the SBUSY1 output goes to “H”
and the SBUSY1 output goes to “L” each time 1-byte of receive data
is written into the automatic transfer RAM.
SBUSY1
SBUSY1
Serial transfer
status flag
Serial transfer
status flag
SCLK1
SCLK1
SOUT1
Write to Serial
I/O1 register
Fig. 30 SBUSY1 output operation
(internal synchronous clock, 8-bits serial I/O)
Fig. 31 SBUSY1 output operation
(external synchronous clock, 8-bits serial I/O)
Automatic transfer
interval
SCL K1
Serial I/O1 register
→Automatic transfer RAM
Automatic transfer RAM
→Serial I/O1 register
SBUSY1
Serial transfer
status flag
SOUT1
Fig. 32 SBUSY1 output operation in automatic transfer serial I/O mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
34
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which informs
the serial transfer destination that transmit/receive is ready. In the
initial status, when the serial I/O initialization bit (b4) is reset to “0”,
the SRDY1 output goes to “L” and the SRDY1 output goes to “H”. After
transmitted data is stored in the serial I/O1 register (address 001B16)
and a transmit/receive operation becomes ready, the SRDY1 output
goes to “H” and the SRDY1 output goes to “L”. When a transmit/
receive operation is started and the transfer clock goes to “L”, the
SRDY1 output goes to “L” and the SRDY1 output goes to “H”.
5. SRDY1 input signal
The SRDY1 input signal becomes valid only when the SRDY1 input
and the SBUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the serial
transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the SRDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the SRDY1 input and an “L”
level signal is input into the SRDY1 input for a period of 1.5 cycles or
more of transfer clock, transfer clocks are output from the SCLK1
output and a transmit/receive operation is started.
After the transmit/receive operation is started and an “L” level signal is input into the SRDY1 input and an “H” level signal into the
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received, the
transfer clocks from the SCLK1 output is stopped. The handshake
unit of the 8-bit serial I/O and that of the automatic transfer serial
I/O are of 8 bits.
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
To start a transmit/receive operation (SBUSY1 output: “L”, S BUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an “L”
level signal into the SRDY1 input, and also write transmit data into
the serial I/O1 register.
SRDY1
SCLK1
Write to serial
I/O1 register
Fig. 33 SRDY1 output operation
SRDY1
SCLK1
SOUT1
Fig. 34 SRDY1 input operation (internal synchronous clock)
35
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A:
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
Internal synchronous
clock selection
SCLK1
B:
External synchronous
clock selection
B:
Write to serial
I/O1 register
Fig. 35 Handshake operation at serial I/O1 mutual connecting (1)
A:
SCLK1
SCLK1
SRDY1
SRDY1
SBUSY1
Write to serial
I/O1 register
SRDY1
SBUSY1
SBUSY1
A:
Internal synchronous
clock selection
External synchronous
clock selection
Fig. 36 Handshake operation at serial I/O1 mutual connecting (2)
36
SCLK1
B:
B:
Write to serial
I/O1 register
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
ister (address 001D16) to “1”. For clock synchronous serial I/O, the
transmitter and the receiver must use the same clock for serial I/O2
operation. If an internal clock is used, transmit/receive is started by
a write signal to the serial I/O2 transmit/receive buffer register (TB/
RB) (address 001F 16).
When P5 7 (SCLK22) is selected as a clock I/O pin, SRDY2 output
function is invalid, and P5 6 (S CLK21) is used as an I/O port.
Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 operation.
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control reg-
Data bus
Serial I/O2 control register
Address 001F16
Receive buffer register
Shift clock
“0 ”
P56/SCLK21
P57/SRDY2/SCLK22
XIN
Serial I/O2 clock I/O pin selection bit
P57/SRDY2/SCLK22
P55/TXD
Clock control circuit
“1 ”
“0 ”
Internal system clock selection bit
Serial I/O2 synchronous clock selection bit
“0 ”
“1 ”
XCIN
Receive interrupt request (RI)
Receive shift register
P54/RXD
Address 001D16
Receive buffer full flag (RBF)
“1 ”
1/2
F/F
BRG count source selection bit Division ratio 1/(n+1)
Baud rate generator
BRG clock
Address 001616
1/4
switch bit
Falling edge detector
Serial I/O2
clock I/O pin
selection bit
1/4
Clock control circuit
Shift clock
Transmit shift register
Transmit buffer register
Address 001F16
Transmit shift register shift
completion flag (TSC)
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O2 status register
Address 001E16
Data bus
Fig. 37 Block diagram of clock synchronous serial I/O2
Transmit/Receive shift clock
(1/2—1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
D0
D1
D2
D3
D4
D5
D6
D7
Serial I/O2 input RxD
D0
D1
D2
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F16)
TBE = 0
TBE = 1
TSC = 0
RBF = 1
TSC = 1
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Fig. 38 Operation of clock synchronous serial I/O2 function
37
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous serial I/O (UART) mode
The asynchronous serial I/O (UART) mode can be selected by clearing the serial I/O2 mode selection bit (b6) of the serial I/O2 control
register (address 001D16 ) to “0”. Eight serial data transfer formats
can be selected and the transfer formats used by the transmitter
and receiver must be identical.
The transmit and receive shift registers each have a buffer (the two
buffers have the same address in memory). Since the shift register
cannot be written to or read from directly, transmit data is written to
the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can receive 2-byte data continuously.
Data bus
Serial I/O2 control register Address 001D16
Address 001F16
P54/RXD
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Receive buffer register
OE
Character length selection bit
7 bit
ST detector
Receive shift register
1/16
8 bit
PE FE
P56/SCLK21
P57/SRDY2/SCLK22
XIN
“0 ”
Clock control circuit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 clock I/O pin
selection bit
UART control register
Address 001716
“1 ”
Internal system clock selection bit
“0 ”
“1 ”
XCIN
SP detector
1/2
BRG count source
selection bit
Division ratio 1/(n+1)
Baud rate generator
Address 001616
“1 ”
BRG clock
switch bit
1/4
ST/SP/PA generator
Transmit shift register shift
completion flag (TSC)
1/16
Transmit shift register
P55/TXD
Transmit interrupt source selection bit
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Address 001E16
Serial I/O2 status register
Transmit buffer register
Address 001F16
Data bus
Fig. 39 Block diagram of UART serial I/O2
Transmit or receive clock
Write-in signal to
transmit buffer register
TBE=0
TSC=0
TBE=1
Serial I/O2 output TXD
TBE=0
TBE=1
ST
D0
D1
SP
TSC=1*
ST
D0
D1
Read-out signal from receive
buffer register
SP
* Generated at 2nd bit in 2-stop
bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
RBF=0
RBF=1
Serial I/O2 input RXD
ST
Fig. 40 Operation of UART serial I/O2 function
38
D0
D1
SP
RBF=1
ST
D0
D1
SP
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Serial I/O2 Control Register] SIO2CON (001D16)
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (001716)
This is a 7 bit register containing four control bits, which are valid
when UART is selected, two control bits, which are valid when using
serial I/O2, and one control bit, which is always valid.
Data format of serial data receive/transfer and the output structure of
the P5 5/TxD pin, etc. are set by this register.
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O2 function
and various errors. Three of the flags (b4 to b6) are only valid in the
UART mode. The receive buffer full flag (b1) is cleared to “0” when
the receive buffer is read.
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O2 status regis-
b7
b0
Serial I/O2 status register
(SIO2STS : address 001E16)
ter clears error flags OE, PE, FE, and SE (b3 to b6, respectively).
Writing “0” to the serial I/O2 enable bit (SIOE : b7 of the serial I/O2
control register) also clears all the status flags, including the error
flags.
All bits of the serial I/O2 status register are initialized to “0” at reset,
but if the transmit enable bit (b4) of the serial I/O2 control register
has been set to “1”, the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become “1”.
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is “0”.
[Baud Rate Generator] BRG (001616)
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register, the baud rate generator divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
b7
b0
UART control register
(UARTCON : address 001716)
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
BRG count source selection bit (CSS)
0: f(XIN) or f(XCIN)/2 or f(XCIN)
1: f(XIN)/4 or f(XCIN)/8 or f(XCIN)/4
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
SRDY2 output enable bit (SRDY)
0: P57 pin operates as ordinary I/O pin
1: P57 pin operates as SRDY2 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P54 to P57 operate as ordinary I/O pins)
1: Serial I/O2 enabled
(pins P54 to P57 operate as serial I/O pins)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P55/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: XIN or XCIN/2 (depends on internal system clock)
1: XCIN
Serial I/O2 clock I/O pin selection bit
0: SCLK21 (P57/SCLK22 pin is used as I/O port or SRDY2 output pin.)
1: SCLK22 (P56/SCLK21 pin is used as I/O port.)
Not used (return “1” when read)
Fig. 41 Structure of serial I/O2 related register
39
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD CONTROLLER
The 38B4 group has fluorescent display (FLD) drive and control circuits.
The FLD controller consists of the following components:
•40 pins for FLD control pins
•FLDC mode register
•FLD data pointer
•FLD data pointer reload register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•Port P8 FLD output control register
•FLD automatic display RAM (max. 160 bytes)
A gradation display mode can be used for bright/dark display as a
display function.
Main
data bus
Main address bus
FLD automatic display RAM
0F6016
Local address bus
0FFF16
Local
data bus
FLD/P P20/FLD0
FLD/P P21/FLD1
FLD/P P22/FLD2
8
FLD/P P23/FLD3
FLD/P P24/FLD4
FLD/P P25/FLD5
FLD/P P26/FLD6
FLD/P P27/FLD7
000416
0EFA16
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
FLD/P
0EF916
P00/FLD8
P01/FLD9
P02/FLD10
8
P03/FLD11
P04/FLD12
P05/FLD13
P06/FLD14
P07/FLD15
000016
P10/FLD16
P11/FLD17
P12/FLD18
8
P13/FLD19
P14/FLD20
P15/FLD21
P16/FLD22
P17/FLD23
000216
FLDC mode register
(0EF416)
FLD data pointer
reload register
(0EF816)
Address
decoder
FLD data pointer
(0EF816)
Timing generator
Fig. 42 Block diagram for FLD control circuit
40
P30/FLD24
P31/FLD25
P32/FLD26
8
P33/FLD27
P34/FLD28
P35/FLD29
P36/FLD30
P37/FLD31
000616
FLD/P P80/FLD32
FLD/P P81/FLD33
FLD/P P82/FLD34
FLD/P P83/FLD35 8
FLD/P P84/FLD36
FLD/P P85/FLD37
FLD/P P86/FLD38
FLD/P P87/FLD39
001016
0EFB16
FLD blanking interrupt
FLD digit interrupt
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[FLDC Mode Register] FLDM
The FLDC mode register is a 8-bit register respectively which is used
to control the FLD automatic display and to set the blanking time
Tscan for key-scan.
b7
b0
FLDC mode register
(FLDM: address 0EF416)
Automatic display control bit (P0, P1, P2, P3, P8)
0 : General-purpose mode
1 : Automatic display mode
Display start bit
0 : Stop display
1 : Display
(start to display by switching “0” to “1”)
Tscan control bits
00 : FLD digit interrupt (at rising edge of each digit)
01 : 1 ✕ Tdisp
FLD blanking interrupt
10 : 2 ✕ Tdisp
(at falling edge of the last digit)
11 : 3 ✕ Tdisp
Timing number control bit
0 : 16 timing mode
1 : 32 timing mode
Gradation display mode selection control bit
0 : Not selecting
1 : Selecting (Note 1)
Tdisp counter count source selection bit
0 : f(XIN)/16 or f(XCIN)/32
1 : f(XIN)/64 or f(XCIN)/128
High-breakdown voltage port drivability selection bit
0 : Drivability strong
1 : Drivability weak
Notes 1: When a gradation display mode is selected, a number of timing is max. 16
timing. (Set the timing number control bit to “0”.)
2: When changing bit 4 (timing number control bit) or bit 5 (gradation display
mode selection control bit), set “0” to bit 1 (display start bit) to perform at
display stop state.
Fig. 43 Structure of FLDC mode register
41
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD Automatic Display Pins
This setting is performed by writing a value into the FLD/port switch
register (addresses 0EF916 to 0EFB16 ) of each port.
This setting can be performed in units of bit. When “0” is set, the port
is set to the general-purpose port. When “1” is set, the port is set to
the FLD pin. There is no restriction on whether the FLD pin is to be
used as a segment pin or a digit pin.
When the automatic display control bits of the FLDC mode register
(address 0EF416 ) are set to “1,” the ports of P0, P1, P2, P3 and P8
are used as FLD automatic display pins.
When using the FLD automatic display mode, set each port to the
FLD pin or the general-purpose port using the respective switch register in accordance with the number of segments and the number of
digits.
Table 9 Pins in FLD automatic display mode
Port Name
P0, P2,
P80–P83
P1, P3
P84–P87
Automatic Display Pins
FLD0–FLD15
FLD32–FLD35
FLD16–FLD31
FLD36–FLD39
Setting Method
The individual bits of the FLD/port switch register (addresses 0EF916–0EFB16 ) can be set each pin
either FLD port (“1”) or general-purpose port (“0”).
None (FLD only)
The individual bits of the FLD/port switch register (address 0EFB16) can be set each pin to either
FLD port (“1”) or general-purpose port (“0”).
The output can be reversed by the port P8 FLD output control register (address 0EFC16).
The port output format is the CMOS output format. When using the port as a display pin, a driver
must be installed externally.
Setting example 2
Setting example 1
15
8
Number of segments
Number of digits
Port P2
Port P0
0
0
0
0
0
0
0
0
FLD0(SEG1)
FLD1(SEG2)
FLD2(SEG3)
FLD3(SEG4)
FLD4(SEG5)
FLD5(SEG6)
1 FLD6(SEG7)
1 FLD7(SEG8)
FLD8(SEG1)
P01
P02
P03
P04
P05
FLD14(SEG2)
1 FLD15(SEG3)
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
16
10
FLD8(SEG9)
FLD9(SEG10)
FLD10(SEG11)
FLD11(SEG12)
FLD12(SEG13)
FLD13(SEG14)
FLD14(SEG15)
FLD15(SEG16)
0
0
1
1
1
1
1
1
P20
P21
FLD2(SEG1)
FLD3(SEG2)
FLD4(SEG3)
FLD5(SEG4)
FLD6(SEG5)
FLD7(SEG6)
0
0
0
0
0
0
1
1
P20
P21
P22
P23
P24
P25
FLD4(SEG1)
FLD5(SEG2)
1
1
1
1
1
1
1
1
FLD8(DIG1)
FLD9(DIG2)
FLD10(DIG3)
FLD11(DIG4)
1
1
1
1
1
1
1
1
FLD6(SEG3)
FLD7(SEG4)
FLD8(SEG5)
FLD9(SEG6)
FLD10(SEG7)
FLD11(SEG8)
FLD12(SEG9)
FLD13(SEG10)
FLD12(DIG5)
FLD13(DIG6)
FLD14(DIG7)
FLD15(DIG8)
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(DIG5)
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
1
1
1
1
1
1
1
1
FLD16(DIG9)
FLD17(DIG10)
FLD18(DIG11)
FLD19(DIG12)
FLD20(DIG13)
FLD21(DIG14)
FLD22(DIG15)
FLD23(DIG16)
1
1
1
1
1
1
1
1
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(DIG5)
FLD24(SEG8)
FLD25(SEG9)
FLD26(SEG10)
FLD27(SEG11)
FLD28(DIG5)
FLD29(DIG6)
FLD30(DIG7)
FLD31(DIG8)
0
0
0
0
1
1
1
1
FLD24(DIG9)
FLD25(DIG10)
FLD26(DIG11)
FLD27(DIG12)
FLD28(DIG13)
FLD29(DIG14)
FLD30(DIG15)
FLD31(SEG17)
1
1
1
1
1
1
1
0
FLD24(DIG17)
FLD25(DIG18)
FLD26(DIG19)
FLD27(DIG20)
FLD28(SEG7)
FLD29(SEG8)
FLD30(SEG9)
FLD31(SEG10)
1
1
1
FLD24(DIG9)
FLD25(DIG10) 1
FLD14(SEG11) 0
FLD32(SEG12)
FLD33(SEG13)
FLD34(SEG14)
FLD35(SEG15)
P84
P85
P86
P87
Value of FLD/port switch register
Fig. 44 Segment/Digit setting example
42
Setting example 4
18
20
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(SEG4)
FLD21(SEG5)
FLD22(SEG6)
FLD23(SEG7)
FLD16(DIG1)
Port P3
Port P8
1
1
1
1
1
1
P20
P21
P22
P23
P24
P25
P26
P27
1
0
0
0
0
0
1
Port P1
Setting example 3
25
15
1
1
1
1
1
1
1
1
FLD32(SEG18)
FLD33(SEG19)
FLD34(SEG20)
FLD35(SEG21)
FLD36(SEG22)
FLD37(SEG23)
FLD38(SEG24)
FLD39(SEG25)
FLD32(SEG11)
FLD33(SEG12)
FLD34(SEG13)
FLD35(SEG14)
FLD36(SEG15)
FLD37(SEG16)
FLD38(SEG17)
1 FLD39(SEG18)
1
1
1
1
1
1
1
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
1
1
0
0
FLD15(SEG12)
FLD26(SEG13)
FLD27(SEG14)
FLD28(SEG15)
FLD29(SEG16)
0
0
0
0
0
0
0
0
0
0
P80
P81
P82
P83
P84
P85
P86
P87
0
0
0
0
0
Value of FLDRAM write disable register
If data is set to “1”, data is protected.
This setting does not decide the FLD
port function (SEG/DIG).
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD Automatic Display RAM
[FLD Data Pointer and FLD Data Pointer Reload Register]
The FLD automatic display RAM uses the 160 bytes of addresses
0F6016 to 0FFF16 . For FLD, the 3 modes of 16-timing ordinary mode,
16-timing•gradation display mode and 32-timing mode are available
depending on the number of timings and the presence/absence of
gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•ordinary mode
The 80 bytes of addresses 0FB016 to 0FFF16 are used as a FLD
display data store area. Because addresses 0F6016 to 0FAF 16
are not used as the automatic display RAM, they can be the ordinary RAM or serial I/O automatic transfer RAM.
(2) 16-timing•gradation display mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used. The 80
bytes of addresses 0FB016 to 0FFF 16 are used as an FLD display data store area, while the 80 bytes of addresses 0F6016 to
0FAF16 are used as a gradation display control data store area.
(3) 32-timing mode
The 160 bytes of addresses 0F6016 to 0FFF16 are used as an
FLD display data store area.
FLDDP (0EF816)
16-timing•gradation display mode
16-timing•ordinary mode
0F6016
0F6016
0FB016
32-timing mode
0F6016
Gradation display
control data stored
area
Not used
1 to 32 timing display
data stored area
0FB016
1 to 16 timing display
data stored area
0FFF16
Both the FLD data pointer and FLD data pointer reload register are
8-bit registers assigned at address 0EF816. When writing data to this
address, the data is written to the FLD data pointer reload register;
when reading data from this address, the value in the FLD data pointer
is read.
1 to 16 timing display
data stored area
0FFF16
0FFF16
Fig. 45 FLD automatic display RAM assignment
43
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Setup
(1) 16-timing•ordinary mode
The area of addresses 0FB0 16 to 0FFF16 are used as a
FLD automatic display RAM.
When data is stored in the FLD automatic display RAM,
the last data of FLD port P2 is stored at address 0FB0 16 ,
the last data of FLD port P0 is stored at address 0FC0 16 ,
the last data of FLD port P1 is stored at address 0FD0 16 ,
the last data of FLD port P3 is stored at address 0FE0 16 ,
and the last data of FLD port P8 is stored at address 0FF0 16,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored at
an address which adds the value of (the timing number – 1) to the
corresponding address 0FB0 16, 0FC0 16 , 0FD016 , 0FE016, and
0FF016 .
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when reading.
(2) 16-timing•gradation display mode
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is arranged at an address resulting from subtracting 0050 16 from
the display data store address of each timing and pin. Bright display is performed by setting “0”, and dark display is performed by
setting “1”.
Set the FLD data pointer reload register to the value given by the
timing number – 1. “1” is always written to bits 7, 6, and 5. Note
that “0” is always read from bits 7, 6, and 5 when reading. “1” is
always set to bit 4, but this bit become written value when reading.
(3) 32-timing mode
The area of addresses 0F6016 to 0FFF16 are used as a FLD automatic display RAM. When data is stored in the FLD automatic
display RAM, the last data of FLD port P2 is stored at address
0F6016 , the last data of FLD port P0 is stored at address 0F8016 ,
the last data of FLD port P1 is stored at address 0FA0 16 ,
the last data of FLD port P3 is stored at address 0FC0 16 ,
and the last data of FLD port P8 is stored at address 0FE0 16,
to assign in sequence from the last data respectively.
The first data of the FLD port P2, P0, P1, P3, and P8 is stored
at an address which adds the value of (the timing number – 1)
to the corresponding address 0F6016 , 0F8016, 0FA016 , 0FC016,
and 0FE0 16.
Set the FLD data pointer reload register to the value given by
the timing number –1. “1” is always written to bits 7, 6, and 5.
Note that “0” is always read from bits 7, 6, and 5 when reading.
Number of FLD segments: 15
Number of timing: 8
(FLD data pointer reload register = 7)
B it
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
Timing for start
(The first data of FLDP2)
FLDP2 data area
The last timing
(The last data of FLDP0)
Timing for start
(The first data of FLDP0)
FLDP0 data area
The last timing
(The last data of FLDP1)
Timing for start
(The first data of FLDP1)
FLDP1 data area
The last timing
(The last data of FLDP3)
Timing for start
(The first data of FLDP3)
FLDP3 data area
The last timing
(The last data of FLDP8)
Timing for start
(The first data of FLDP8)
FLDP8 data area
shaded area is used for segment.
shaded area is used for digit.
Fig. 46 Example of using FLD automatic display RAM in
16-timing•ordinary mode
44
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Number of FLD segments: 25
Number of timing: 15
(FLD data pointer reload register = 14)
B it
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
B it
0
Address
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
shaded area is used for segment.
shaded area is used for digit.
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
Note:
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
FLDP2 gradation
display data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 gradation
display data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 gradation
display data area
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 gradation
display data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 gradation
display data area
Timing for start
(The first data of FLDP8)
shaded area is used for gradation display data.
Fig. 47 Example of using FLD automatic display RAM in 16-timing•gradation display mode
45
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Number of FLD segments: 18
Number of timing: 20
(FLD data pointer reload register = 19)
B it
Address
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
B it
0
Address
Timing for start
(The first data of FLDP1)
The last timing
(The last data of FLDP3)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
0F6016
0F6116
0F6216
0F6316
0F6416
0F6516
0F6616
0F6716
0F6816
0F6916
0F6A16
0F6B16
0F6C16
0F6D16
0F6E16
0F6F16
0F7016
0F7116
0F7216
0F7316
0F7416
0F7516
0F7616
0F7716
0F7816
0F7916
0F7A16
0F7B16
0F7C16
0F7D16
0F7E16
0F7F16
0F8016
0F8116
0F8216
0F8316
0F8416
0F8516
0F8616
0F8716
0F8816
0F8916
0F8A16
0F8B16
0F8C16
0F8D16
0F8E16
0F8F16
0F9016
0F9116
0F9216
0F9316
0F9416
0F9516
0F9616
0F9716
0F9816
0F9916
0F9A16
0F9B16
0F9C16
0F9D16
0F9E16
0F9F16
0FA016
0FA116
0FA216
0FA316
0FA416
0FA516
0FA616
0FA716
0FA816
0FA916
0FAA16
0FAB16
0FAC16
0FAD16
0FAE16
0FAF16
shaded area is used for segment.
shaded area is used for digit.
Fig. 48 Example of using FLD automatic display RAM in 32-timing mode
46
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
The last timing
(The last data of FLDP1)
FLDP1 data area
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Setting Method When Using Grid Scan Type FLD
When using the grid scan type FLD, set “1” in the RAM area corresponding to the digit ports that output “1” at each timing. Set “0” in
the RAM area corresponding to the other digit ports.
Number of FLD segments: 16
Number of timing: 10
(FLD data pointer reload register = 9)
B it
Address
Number of timing: 10
The first second
third.......................9th
10th
DIG10 (P31)
DIG9 (P30)
DIG8 (P17)
DIG2 (P11)
DIG1 (P10)
Segment output
Fig. 49 Example of digit timing using grid scan type
0FB016
0FB116
0FB216
0FB316
0FB416
0FB516
0FB616
0FB716
0FB816
0FB916
0FBA16
0FBB16
0FBC16
0FBD16
0FBE16
0FBF16
0FC016
0FC116
0FC216
0FC316
0FC416
0FC516
0FC616
0FC716
0FC816
0FC916
0FCA16
0FCB16
0FCC16
0FCD16
0FCE16
0FCF16
0FD016
0FD116
0FD216
0FD316
0FD416
0FD516
0FD616
0FD716
0FD816
0FD916
0FDA16
0FDB16
0FDC16
0FDD16
0FDE16
0FDF16
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FE816
0FE916
0FEA16
0FEB16
0FEC16
0FED16
0FEE16
0FEF16
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FFA16
0FFB16
0FFC16
0FFD16
0FFE16
0FFF16
Note:
7
6
5
4
3
2
1
0
The last timing
(The last data of FLDP2)
FLDP2 data area
Timing for start
(The first data of FLDP2)
The last timing
(The last data of FLDP0)
FLDP0 data area
Timing for start
(The first data of FLDP0)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
The last timing
(The last data of FLDP1)
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
The last timing
(The last data of FLDP3)
FLDP1 data area
Timing for start
(The first data of FLDP1)
FLDP3 data area
Timing for start
(The first data of FLDP3)
The last timing
(The last data of FLDP8)
FLDP8 data area
Timing for start
(The first data of FLDP8)
shaded area is used for segment.
shaded area is used for digit.
Fig. 50 Example of using FLD automatic display RAM
using grid scan type
47
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Setting
Key-scan
Each timing is set by the FLDC mode register, Tdisp time set register, Toff1 time set register, and Toff2 time set register.
●Tdisp time setting
Set the Tdisp time by the Tdisp counter count source selection bit of
the FLDC mode register and the Tdisp time set register.
Supposing that the value of the Tdisp time set register is n, the
Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count source
synchronization).
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Tdisp time set register is 200
(C816), the Tdisp time is: Tdisp = (200+1) ✕ 4 (at XIN= 4 MHz) = 804
µs. When reading the Tdisp time set register, the value in the
counter is read out.
●Toff1 time setting
Set the Toff1 time by the Toff1 time set register.
Supposing that the value of the Toff1 time set register is n1, the
Toff1 time is represented as Toff1 = n1 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff1 time set register is 30
(1E16 ), Toff1 = 30 ✕ 4 (at XIN = 4 MHz) = 120 µs.
Set a value of 0316 or more to the Toff1 time set register (address
0EF6 16).
●Toff2 time setting
Set the Toff2 time by the Toff2 time set register.
Supposing that the value of the Toff2 time set register is n2, the
Toff2 time is represented as Toff2 = n2 ✕ t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff2 time set register is 180
(B416 ), Toff2 = 180 ✕ 4 (at XIN = 4 MHz) = 720 µs.
This Toff2 time setting is valid only for FLD ports which are in the
gradation display mode and whose gradation display control RAM
value is “1”.
When setting “1” to bit 7 of the P8FLD output control register (address 0EFC 16), set a value of 03 16 or more to the Toff2 time set
register (address 0EF716).
When a key-scan is performed with the segment during key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 0EF416 ).
2. Set the port corresponding to the segment for key-scan to the
output port.
3. Perform the key-scan.
4. After the key-scan is performed, write “1” to bit 0 of FLDC mode
register (address 0EF416).
FLD Automatic Display Start
To perform FLD automatic display, set the following registers.
•Port P0FLD/port switch register
•Port P2FLD/port switch register
•Port P8FLD/port switch register
•FLDC mode register
•Tdisp time set register
•Toff1 time set register
•Toff2 time set register
•FLD data pointer
FLD automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register (address 0EF416 ), and the automatic display is started by writing “1” to bit 1. During FLD automatic display,
bit 1 of the FLDC mode register (address 0EF416) always keeps “1”,
and FLD automatic display can be interrupted by writing “0” to bit 1.
48
■ Note
When performing a key-scan according to the above step 1 to 4, take
the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 0EF4 16).
2. Do not set “1” in the ports corresponding to digits.
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Repeat synchronous
Tdisp
Segment
Digit output
Tn
Tscan
Tn-1 Tn-2
T4
T3
FLD digit interrupt request occurs at the rising
edge of digit (each timing).
T2
T1
Segment setting by software
FLD blanking interrupt request occurs
at the falling edge of the last timing.
Segment
Digit
Toff1
Tdisp
Segment
Digit
When a gradation display mode is selected
Toff1
Toff2
Tdisp
Pin under the condition that bit 5 of the
FLDC mode register is “1”, and the
corresponding gradation display control
data value is “1”.
n: Number of timing
Fig. 51 FLDC timing
49
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
P84 to P87 FLD Output Reverse Function
P84 to P87 are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
The output polarity can be reversed by setting “1” to bit 0 of the port
P8 FLD output control register.
P84 to P87 Toff Invalid Function
P84 to P87 can output waveform in which Toff is invalid, when P84 to
P87 is selected FLD ports (See Figure 52).
The function is useful when using a 4 bits →16 bits decoder. The Toff
can be invalid by setting “1” to bit 2 of the port P8FLD output control
register (address 0EFC16).
Segment
Digit
At Toff2 control bit = “0” in
gradation display mode
(at gradation display
control data= “1”)
At Toff2 control bit = “1” in
gradation display mode
(at gradation display
control data= “1”)
Toff1
Toff2
Tdisp
Dimmer signal
P84 to P87 Output Delay Function
P84 to P87 can output waveform in which is delayed for 16 µs, when
selecting FLD port and selecting Toff invalid function (See Figure
52). When using a 4 bits →16 bits decoder, the function can be useful for prevention of leak radiation caused by phase discrepancy between segment output waveform and digit output waveform. This function can be set by setting “1” to bit 3 of the port P8FLD output control
register (address 0EFC16).
P84–P87
Toff invalid
P84–P87
Toff invalid
Delay
16 µs
Fig. 52 P84 to P87 FLD output waveform
Dimmer Signal Output Function
P63 can output the dimmer signal. When using a 4 bits →16 bits
decoder, the dimmer signal can be used as a control signal for a 4
bits →16 bits decoder. When using M35501FP, the dimmer signal
can be used as the CLK signal. The dimmer signal can be output by
setting “1” to bit 4 of the port P8FLD output control register (address
0EFC16).
b7
Toff2 Control Bit
The value of the Toff2 time set register is valid when gradation display mode is selected. The FLD ports output (set) the data of display
RAM at the end of the Toff1 time and output “0” (reset) at the end of
the Toff2 time, when bit 7 of the port P8FLD output control register is
“0”.
The FLD ports output (set) the data of display RAM at the end of the
Toff2 time and output “0” (reset) at the end of Tdisp time, when bit 7
of the port P8FLD output control register is “1”.
b0
Port P8FLD output control register
(P8FLDCON: address 0EFC16)
P84–P87 FLD output reverse bit
0: Output normally
1: Reverse output
Not used (“0” at reading)
P84–P87 Toff invalid bit
0: Operating normally
1: Toff invalid
P84–P87 delay control bit (Note)
0: No delay
1: Delay
P63/AN9 dimmer output control bit
0: Ordinary port
1: Dimmer output
Not used (“0” at reading)
Toff2 control bit
0: Gradation display data is reset at Toff2
(set at Toff1)
1: Gradation display data is set at Toff2
(reset at Tdisp)
Note: Valid only when selecting FLD port and P84–P87 Toff invalid function
Fig. 53 Structure of port P8 FLD output control register
50
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The 38B4 group has a 10-bit A-D converter. The A-D converter performs successive approximation conversion.
conversion interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so set
f(XIN) to at least 250 kHz during A-D conversion. Use a CPU system
clock dividing the main clock XIN as the internal system clock.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a loworder register. The high-order 8 bits of a conversion result is stored
in the A-D conversion register (high-order) (address 0034 16), and
the low-order 2 bits of the same result are stored in bit 7 and bit 6 of
the A-D conversion register (low-order) (address 0033 16 ).
During A-D conversion, do not read these registers.
b7
b0
A-D control register
(ADCON: address 003216)
Analog input pin selection bits
0000: P70/AN0
0001: P71/AN1
0010: P72/AN2
0011: P73/AN3
0100: P74/AN4
0101: P75/AN5
0110: P76/AN6
0111: P77/AN7
1000: P62/SRDY1/AN8
1001: P63/AN9
1010: P64/INT4/SBUSY1/AN10
1011: P65/SSTB1/AN11
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conversion.
A-D conversion is started by setting “0” in this bit.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
[Comparison Voltage Generator]
Not used (returns “0” when read)
The comparison voltage generator divides the voltage between AV SS
and VREF, and outputs the divided voltages.
b7
[Channel Selector]
b0
A-D conversion register (high-order)
(ADH: address 003416)
The channel selector selects one of the input ports P77/AN 7–P70/
AN 0, and P65/SSTB1/AN11–P62/SRDY1/AN8 and inputs it to the comparator.
When port P6 4 is selected as an analog input pin, an external interrupt function (INT4) is invalid.
AD conversion result stored bits
b7
b0
A-D conversion register (low-order)
(ADL: address 003316)
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
Not used (returns “0” when read)
AD conversion result stored bits
Fig. 54 Structure of A-D control register
Data bus
b7
b0
A-D control register
4
A-D control circuit
Channel selector
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P62/SRDY1/AN8
P63/AN9
P64/INT4/SBUSY1/AN10
P65/SSTB1/AN11
Comparator
A-D interrupt request
A-D conversion register (H) A-D conversion register (L)
(Address 003416)
(Address 003316)
Resistor ladder
AVSS
VREF
Fig. 55 Block diagram of A-D converter
51
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
The 38B4 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the XIN clock.
The explanation in the rest assumes XIN = 4 MHz.
Data bus
It is set to “1”
when write.
bit7
PWM register (low-order)
(address 001516)
bit7
bit5
bit0
bit0
PWM register (high-order)
(address 001416)
PWM latch (14-bit)
MSB
LSB
14
P87 latch
P87/PWM0
14-bit PWM circuit
When an internal
XCIN
1/2
system clock
selection bit is set
(64 µs cycle)
Timing
“1”
to “0”
generating
XI N
unit for PWM (4096 µs cycle)
(4MHz) “0”
Fig. 56 PWM block diagram
52
PWM
P87/PWM output
selection bit
P87/PWM output
selection bit
P87 direction
register
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data Setup
Transfer From Register To Latch
The PWM output pin also function as port P8 7. Set port P87 to be the
PWM output pin by setting bit 0 of the PWM control register (address
0026 16) to “1”. The high-order 8 bits of output data are set in the
high-order PWM register PWMH (address 0014 16) and the low-order
6 bits are set in the low-order PWM register PWML (address 0015 16).
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each subperiod (every 64 µs). When the PWML register is read, the contents
of the latch are read. However, bit 7 of the PWML register indicates
whether the transfer to the PWM latch is completed; the transfer is
completed when bit 7 is “0”.
PWM Operation
The timing of the 14-bit PWM function is shown in Figure 57.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an “H” level signal
is output during each sub-period. There are 64 sub-periods in each
period, and each sub-period t is 256 ✕ τ (= 64 µs) long. The signal’s
“H” has a length equal to N times τ, and its minimum resolution = 250
ns.
The last bit of the sub-period becomes the ADD bit which is specified
either “H” or “L”, by the contents of PWML. As shown in Table 10, the
ADD bit is decided either “H” or “L”.
That is, only in the sub-period tm shown in Table 10 in the PWM
cycle period T = 64t, the “H” duration is lengthened during the minimum resolution width τ period in comparison with the other period.
For example, if the high-order eight bits of the 14-bit data are “0316”
and the low-order six bits are “05 16”, the length of the “H” level output
in sub-periods t 8, t24 , t32, t 40 and t56 is 4 τ, and its length 3 τ in all
other sub-periods.
Time at the “H” level of each sub-period almost becomes equal because the time becomes length set in the high-order 8 bits or becomes the value plus τ, and this sub-period t (= 64 µs, approximate
15.6 kHz) becomes cycle period approximately.
Table 10 Relationship between low-order 6-bit data and setting
period of ADD bit
Low-order
Sub-periods tm lengthened (m = 0 to 63)
6-bit data
LSB
000000
None
000001
000010
000100
001000
010000
100000
m = 32
m = 16, 48
m = 8, 24, 40, 56
m = 4, 12, 20, 28, 36, 44, 52, 60
m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
4096 µs
64 µs
64 µs
m=0
15.75 µs
m=7
15.75 µs
15.75 µs
64 µs
m=8
16.0 µs
64 µs
64 µs
m=9
15.75 µs
m = 63
15.75 µs
15.75 µs
Pulse width modulation register H: 00111111
Pulse width modulation register L: 000101
Sub-periods where “H” pulse width is 16.0 µs: m = 8, 24, 32, 40, 56
Sub-periods where “H” pulse width is 15.75 µs: m = all other values
Fig. 57 PWM timing
53
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
PWM control register
(PWMCON: address 002616)
P87/PWM output selection bit
0: I/O port
1: PWM output
Not used (return “0” when read)
Fig. 58 Structure of PWM control register
Data 7B16 stored at address 001416
Data 6A16 stored at address 001416
PWM register
(high-order)
5916
6A16
7B16
Data 2416 stored at address 001516
PWM register
(low-order)
1316
Bit 7 cleared after transfer
A416
Data 3516 stored at address 001516
2416
3516
Transfer from register to latch
PWM latch
(14-bit)
165316
1A9316
Transfer from register to latch
B516
1AA416
1AA416
1EE416
1EF516
When bit 7 of PWML is “0”, transfer
from register to latch is disabled.
T = 4096 µs
(64 ✕ 64 µs)
t = 64 µs
6A
(Example 1)
6B
6A
6B
6A
6B
6A
6B
6A
6B
6B
5
2
5
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
6B
6A
PWM output
1
Low-order 6-bits
output
H = 6A16
L = 2416
5
6A
(Example 2)
5
5
5
6B16............36 times
(107)
6A
6A
6A
6B
6A
5
5
6A16............28 times
(106)
6B
6A
6B
6A
6A
6A
5
106 ✕ 64
6B
6A
6B
6A
6B
5
5
5
5
5
36
6A
6A
6A
6B
6A
6B
6A
6B
6A
6A
PWM output
Low-order 6 bits
output
H = 6A16
L = 1816
4
3
4
6B16............24 times
4
3
4
6A16............40 times
4
106 ✕ 64
3
4
24
t = 64 µs
(256 ✕ 0.25 µs)
Minimum bit width
PWM output
6B
τ = 0.25 µs
6A
69
68
67
.........
02
01
6A
69
68
67
.........
02
01
FF
FE
FD
FC
.........
97
96
2
ADD
8-bit counter
02
01
The ADD portions with
additional τ are determined
either “H” or “L” by low-order
6-bit data.
00
ADD
FF
FE
FD
FC
.........
54
96
95
“H” period length specified by PWMH
256
Fig. 59 14-bit PWM timing
97
τ (64 µs), fixed
.........
02
01
00
95
.........
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPT INTERVAL DETERMINATION
FUNCTION
The 38B4 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a duration of time from the
rising edge (falling edge) of an input signal pulse on the P47/INT2 pin
to the rising edge (falling edge) of the signal pulse that is input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E 16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A 16).
2. Set bit 0 of the interrupt interval determination control register
(address 0031 16) to “1” (interrupt interval determination operating).
3. Select the sampling clock of 8-bit binary up counter by setting bit
1 of the interrupt interval determination control register. When
writing “0”, f(XIN)/128 is selected (the sampling interval: 32 µs at
f(X IN) = 4.19 MHz); when “1”, f(XIN)/256 is selected (the sampling
interval: 64 µs at f(X IN) = 4.19 MHz).
4. When the signal of polarity which is set on the INT 2 pin (rising or
falling edge) is input, the 8-bit binary up counter starts counting up
of the selected counter sampling clock.
5. When the signal of polarity above 4 is input again, the value of the
8-bit binary up counter is transferred to the interrupt interval
determination register (address 0030 16), and the remote control
interrupt request occurs. Immediately after that, the 8-bit binary
up counter continues to count up again from “0016 ”.
6. When count value reaches “FF16 ”, the 8-bit binary up counter stops
counting up. Then, simultaneously when the next counter sampling clock is input, the counter sets value “FF 16 ” to the interrupt
interval determination register to generate the counter overflow
interrupt request.
Counter sampling
clock selection bit
f(XIN)/128
f(XIN)/256
Noise filter
INT2 interrupt input
Noise Filter
The P47/INT 2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt interval determination control register. When not
using the noise filter, set “00”.
2. The P47/INT2 input signal is sampled in synchronization with the
selected clock. When sampling the same level signal in a series
of three sampling, the signal is recognized as the interrupt signal,
and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control
register to “1”, the interrupt request can occur at both rising and
falling edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
Note: In the low-speed mode (CM7 = 1), the interrupt interval determination function cannot operate.
8-bit binary up
counter
Counter overflow
interrupt request
or remote control
interrupt request
Interrupt interval
determination register
address 003016
One-sided/both-sided
detection selection bit
Noise filter sampling
clock selection bit
1/128
1/32 1/64
Data bus
Divider
f(XIN)
Fig. 60 Interrupt interval determination circuit block diagram
55
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt interval determination control register
(IIDCON: address 003116)
Interrupt interval determination circuit operating selection bit
0 : Stopped
1 : Operating
Counter sampling clock selection bit
0 : f(XIN)/128
1 : f(XIN)/256
Noise filter sampling clock selection bits (INT2)
00 : Filter stop
01 : f(XIN)/32
10 : f(XIN)/64
11 : f(XIN)/128
One-sided/both-sided edge detection selection bit
0 : One-sided edge detection
1 : Both-sided edge detection (can be used when using a noise filter)
Not used (return “0” when read)
Fig. 61 Structure of interrupt interval determination control register
(When IIDCON4 = “0”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
N
8-bit binary up
counter value
0
1
3
2
5
4
0
1
FF
3
2
FF
N
FF
6
Counter overflow
interrupt request
Remote control
interrupt request
Remote control
interrupt request
1
0
6
N
Interrupt interval
determination
register value
FE
6
Fig. 62 Interrupt interval determination operation example (at rising edge active)
(When IIDCON4 = “1”)
Noise filter
sampling clock
INT2 pin
Acceptance of
interrupt
Counter sampling
clock
FE
N
8-bit binary up
counter value
0
1
N
Interrupt interval
determination
register value
2
0
2
N
Remote control
interrupt request
2
1
0
1
3
2
Remote control
interrupt request
3
2
0
2
2
Remote control
interrupt request
Remote control
interrupt request
0
FF
2
3
Fig. 63 Interrupt interval determination operation example (at both-sided edge active)
56
1
FF
FF
Counter overflow
interrupt request
1
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
“0”, the underflow signal of watchdog timer L becomes the count
source. The detection time is set then to f(XIN ) = 2.1 s at 4 MHz
frequency and f(XCIN) = 512 s at 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal
divided by 8 for f(XIN) (or divided by 16 for f(X CIN)). The detection
time in this case is set to f(XIN) = 8.2 ms at 4 MHz frequency and
f(XCIN) = 2 s at 32 KHz frequency. This bit is cleared to “0” after
resetting.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software runaway). The watchdog timer consists of an 8-bit watchdog timer L and a 12-bit watchdog timer H.
Standard Operation Of Watchdog Timer
When any data is not written into the watchdog timer control register
(address 002B 16) after resetting, the watchdog timer is in the stop
state. The watchdog timer starts to count down by writing an optional
value into the watchdog timer control register (address 002B16) and
an internal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to the
watchdog timer control register (address 002B16) may be started
before an underflow. When the watchdog timer control register
(address 002B16 ) is read, the values of the high-order 6 bits of the
watchdog timer H, STP instruction disable bit, and watchdog timer H
count source selection bit are read.
●Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 002B16) permits
disabling the STP instruction when the watchdog timer is in operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
Once the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after resetting.
■ Note
●Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
002B 16), a watchdog timer H is set to “FFF16” and a watchdog timer
L to “FF16 ”.
When releasing the stop mode, the watchdog timer performs its count
operation even in the stop release waiting time. Be careful not to
cause the watchdog timer H to underflow in the stop release waiting
time, for example, by writing data in the watchdog timer control register (address 002B16) before executing the STP instruction.
●Watchdog timer H count source selection bit operation
Bit 7 of the watchdog timer control register (address 002B16) permits
selecting a watchdog timer H count source. When this bit is set to
XCIN
“FF16” is set when
watchdog timer
control register is
written to.
1/2
“FFF16” is set
when watchdog
timer control
register is written
to.
“0 ”
“1 ”
Internal system clock
selection bit
(Note)
Data bus
Watchdog timer L (8)
1/8
“1 ”
“0 ”
Watchdog timer H (12)
Watchdog timer H count
source selection bit
XIN
STP instruction disable bit
STP instruction
Reset
circuit
RESET
Internal reset
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
Fig. 64 Block diagram of watchdog timer
b7
b0
Watchdog timer control register
(WDTCON : address 002B16)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/8 or f(XCIN)/16
Fig. 65 Structure of watchdog timer control register
57
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
BUZZER OUTPUT CIRCUIT
The 38B4 group has a buzzer output circuit. One of 1 kHz, 2 kHz and
4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the buzzer
output control register (address 0EFD16). Either P4 3/B UZ01 or P20/
BUZ02/FLD 0 can be selected as a buzzer output port by the output
port selection bits (b2 and b3 of address 0EFD16).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Port latch
f(XIN)
Divider
1/1024
1/2048
1/4096
Buzzer output
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Fig. 66 Block diagram of buzzer output circuit
b7
b0
Buzzer output control register
(BUZCON: address 0EFD16)
Output frequency selection bits (XIN = 4.19 MHz)
00 : 1 kHz (f(XIN)/4096)
01 : 2 kHz (f(XIN)/2048)
10 : 4 kHz (f(XIN)/1024)
11 : Not available
Output port selection bits
00 : P20 and P43 function as ordinary ports.
01 : P43/BUZ01 functions as a buzzer output.
10 : P20/BUZ02/FLD0 functions as a buzzer output.
11 : Not available
Buzzer output ON/OFF bit
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (return “0” when read)
Fig. 67 Structure of buzzer output control register
58
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
______
To reset the microcomputer, RESET
pin should be held at an “L”
______
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between 2.7 V and 5.5 V, and
the oscillation should be stable), reset is released. After the reset is
completed, the program starts from the address contained in address
FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make
sure that the reset input voltage is less than 0.5 V for V CC of 2.7 V
(switching to the high-speed mode, a power source voltage must be
between 4.0 V and 5.5 V).
Poweron
RESET
Power source
voltage
0V
VCC
Reset input
voltage
0V
(Note)
0.2VCC
Note : Reset release voltage ; Vcc=2.7 V
RESET
VCC
Power source
voltage detection
circuit
Fig. 68 Reset circuit example
XIN
φ
RESET
Internal
reset
Address
?
?
?
?
FFFC
F FFD
ADL
Data
ADH, ADL
ADH
SYNC
XIN: about 4000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN)=4 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 69 Reset sequence
59
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
(1) Port P0
000016
(2) Port P0 direction register
000116
(3) Port P1
(33) Timer 34 mode register
002916
0016
0016
(34) Timer 56 mode register
002A16
0016
000216
0016
(35) Watchdog timer control register
002B16
3F16
(4) Port P2
000416
0016
(36) Timer X (low-order)
002C16
FF16
(5) Port P2 direction register
000516
0016
(37) Timer X (high-order)
002D16
FF16
(6) Port P3
000616
0016
(38) Timer X mode register 1
002E16
0016
(7) Port P4
000816
0016
(39) Timer X mode register 2
002F16
0016
(8) Port P4 direction register
000916
0016
003116
0016
(9) Port P5
000A16
0016
(40) Interrupt interval determination
control register
(41) A-D control register
003216
1016
(10) Port P5 direction register
000B16
0016
(42) Interrupt source switch register
003916
0016
(11) Port P6
000C16
0016
(43) Interrupt edge selection register
003A16
0016
(12) Port P6 direction register
000D16
0016
(44) CPU mode register
003B16 0 1 0 0 1 0 0 0
(13) Port P7
000E16
0016
(45) Interrupt request register 1
003C16
0016
(14) Port P7 direction register
000F16
0016
(46) Interrupt request register 2
003D16
0016
(15) Port P8
001016
0016
(47) Interrupt control register 1
003E16
0016
(16) Port P8 direction register
001116
0016
(48) Interrupt control register 2
003F16
0016
(17) Port P9
001216
0016
(49) Pull-up control register 1
0EF016
0016
(18) Port P9 direction register
001316
0016
(50) Pull-up control register 2
0EF116
0016
(19) UART control register
001716
8016
(51) FLDC mode register
0EF416
0016
(20) Serial I/O1 control register 1
001916
0016
(52) Tdisp time set register
0EF516
0016
(21) Serial I/O1 control register 2
001A16
0016
(53) Toff1 time set register
0EF616
FF16
(22) Serial I/O1 control register 3
001C16
0016
(54) Toff2 time set register
0EF716
FF16
(23) Serial I/O2 control register
001D16
0016
(55) Port P0FLD/port switch register
0EF916
0016
(24) Serial I/O2 status register
001E16
8016
(56) Port P2FLD/port switch register
0EFA16
0016
(25) Timer 1
002016
FF16
(57) Port P8FLD/port switch register
0EFB16
0016
(26) Timer 2
002116
0116
(58) Port P8FLD output control register
0EFC16
0016
(27) Timer 3
002216
FF16
(59) Buzzer output control register
0EFD16
0016
(28) Timer 4
002316
FF16
(60) Processor status register
(29) Timer 5
002416
FF16
(61) Program counter
(30) Timer 6
002516
FF16
(31) PWM control register
002616
0016
(32) Timer 12 mode register
002816
0016
0016
(PS) ✕ ✕ ✕ ✕ ✕ 1 ✕ ✕
(PCH)
FFFD16 contents
(PCL)
FFFC16 contents
✕: Not fixed
Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
Fig. 70 Internal status at reset
60
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 38B4 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance with
the resonator manufacturer’s recommended values. No
external resistor is needed between XIN and X OUT since a feedback
resistor exists on-chip. However, an external feedback resistor is
needed between X CIN and XCOUT.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
(1) Stop mode
If the STP instruction is executed, the internal system clock stops at
an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16”
and timer 2 is set to “0116 ”.
Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2. The
bits of the timer 12 mode register are cleared to “0”. Set the interrupt
enable bits of the timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts when an external interrupt
is received or reset, but the internal system clock is not supplied to
the CPU until timer 1 underflows. This allows time for the clock circuit oscillation to stabilize.
Frequency Control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. After
reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of XIN.
(3) Low-speed mode
The internal system clock is the frequency of XCIN divided by 2.
■Note
If you switch the mode between middle/high-speed and low-speed,
stabilize both XIN and XCIN oscillations. The sufficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between
middle/high-speed and low-speed, set the frequency on condition
that f(XIN) > 3f(XCIN).
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set bit
5 of the CPU mode register to “1”. When the main clock X IN is restarted (by setting the main clock stop bit to “0”), set enough time for
oscillation to stabilize.
By clearing furthermore the XCOUT drivability selection bit (b3) of CPU
mode register to “0”, low power consumption operation of less than
200 µA (f(XCIN) = 32 kHz) can be realized by reducing the drivability
between XCIN and X COUT. At reset or during STP instruction execution this bit is set to “1” and a strong drivability that has an easy
oscillation start is set.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops at
an “H” level. The states of X IN and XCIN are the same as the state
before executing the WIT instruction. The internal system clock restarts at reset or when an interrupt is received. Since the oscillator
does not stop, normal operation can be started immediately after the
clock is restarted.
XCIN
XCOUT
Rf
CCIN
XIN
XOUT
Rd
CCOUT
CI N
COUT
Fig. 71 Ceramic resonator circuit
XCIN
XCOUT
XIN
XOUT
open
open
External oscillation circuit
External oscillation circuit
or external pulse
VCC
VCC
VSS
VSS
Fig. 72 External clock input circuit
61
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCOUT
XCIN
“0”
“1”
Port XC
switch bit (Note 3)
1/2
XOUT
XI N
Timer 2 count source
selection bit (Note 2)
Timer 1 count source
selection bit (Note 2)
Internal system clock
selection bit (Notes 1, 3)
“1”
Low-speed mode
Timer 1
“1”
1/4
1/2
“0”
Timer 2
“0”
“0”
“1”
High-speed or
middle-speed
mode
Main clock division ratio
selection bit (Note 3)
Middle-speed mode
“1”
Timing φ (internal clock)
“0”
Main clock stop bit
(Note 3)
Q
High-speed or
low-speed mode
S
R
S Q
STP instruction
WIT instruction
R
Q S
R
Reset
Interrupt disable flag l
Interrupt request
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1”.
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
Fig. 73 Clock generating circuit block diagram
62
STP instruction
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
C M4
CM
“1”
”
“1
4
C
”
“1
”
“0
M
6
“1
”
”
“0
Middle-speed mode
(φ =1 MHz)
“0”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
“0 C
”
M
4
CM
“1
6
”
“0
”
High-speed mode
(φ =4 MHz)
C M6
“1”
“0”
C M7
“1”
“1”
C M7
“0”
CM7=0(4 MHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
“0”
“0”
CM7=0(4 MHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=0(32 kHz stopped)
High-speed mode
(φ =4 MHz)
C M4
C M6
“1”
“1”
Middle-speed mode
(φ =1 MHz)
5
C
M
“0
”
”
“0
6
CM
”
1
“
“1
”
”
“0
CM
CM
6
“0
”
Low-power dissipation mode
(φ =16 kHz)
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
5
“1
”
Low-power dissipation mode
(φ =16 kHz)
C M6
“1”
“0”
“0”
“1”
”
“1
“0”
C M5
“1”
CM7=1(32 kHz selected)
CM6=1(middle-speed)
CM5=0(XIN oscillating)
CM4=1(32 kHz oscillating)
C M5
Low-speed mode
(φ =16 kHz)
C M6
“1”
Low-speed mode
(φ =16 kHz)
“0”
CM7=1(32 kHz selected)
CM6=0(high-speed)
CM5=1(XIN stopped)
CM4=1(32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16)
CM4 : Port Xc switch bit
0: I/O port function
1: XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0: Oscillating
1: Stopped
CM6: Main clock division ratio selection bit
0: f(XIN) (High-speed mode)
1: f(XIN)/4 (Middle-speed mode)
CM7: Internal system clock selection bit
0: XIN–XOUT selected (Middle-/High-speed mode)
1: XCIN–XCOUT selected (Low-speed mode)
Notes 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait
mode is ended.
3: Timer operates in the wait mode.
4: When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 in middle-/high-speed mode.
5: When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 in low-speed mode.
6: The example assumes that 4 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal system clock.
Fig. 74 State transitions of system clock
63
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Automatic Transfer Serial I/O
When using the automatic transfer serial I/O mode of the serial I/O1,
set an automatic transfer interval as the following.
Otherwise the serial data might be incorrectly transmitted/received.
•Set an automatic transfer interval for each 1-byte data transfer as
the following:
(1) Not using FLD controller
Keep the interval for 5 cycles or more of internal system clock
from clock rising of the last bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for 12 cycles or more of internal system clock
from clock rising of the last bit of 1-byte data.
(b) Using gradation display
Keep the interval for 18 cycles or more of internal system clock
from clock rising of the last bit of 1-byte data.
A-D Converter
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an A-D
conversion.
Do not execute the STP or WIT instruction during an A-D conversion.
Multiplication and Division Instructions
Instruction Execution Time
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents of
the processor status register.
The instruction execution time is obtained by multiplying the frequency
of the internal system clock by the number of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in
the list of machine instructions.
The frequency of the internal system clock is the same of the XIN
frequency in high-speed mode.
Timers
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the internal clock, then clear the serial I/O interrupt request bit before executing a serial I/O transfer and serial I/O automatic transfer.
64
At STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register
are cleared.
The XCOUT drivability selection bit (the CPU mode register) is set to
“1” (high drive) in order to start oscillating.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production:
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical copies)
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MASK OPTION OF PULL-DOWN RESISTOR
(object product: M38B4XMXH-XXXXFP)
Power Dissipation Calculating Example 1
Whether built-in pull-down resistors are connected or not to highbreakdown voltage ports P20 to P27 and P80 to P83 can be specified
in ordering mask ROM. The option type can be specified from among
8 types; A to G, P as shown Table 11.
●Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
Table 11 Mask option type of pull-down resistor
Option
type
A ($41)
B ($42)
C ($43)
D ($44)
E ($45)
F ($46)
G ($47)
P ($50)
Connective port of pull-down resistor
(connected at “1” writing)
Restriction
P20 P2 1 P22 P23 P24 P25 P2 6 P2 7 P80 P8 1 P82 P83
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(Note 4)
Notes 1: The electrical characteristics of high-breakdown voltage ports
P20 to P27 and P80 to P83 ’s built-in pull-down resistors are the
same as that of high-breakdown voltage ports P00 to P0 7.
2: The absolute maximum ratings of power dissipation may be
exceed owing to the number of built-in pull-down resistor. After
calculating the power dissipation, specify the option type.
3: One time PROM version and EPROM version cannot be
specified whether built-in pull-down resistors are connected or not
likewise option type A.
4: INT 3 function and CNTR1 function cannot be used in the option
type P.
Power Dissipation Calculating Method
●Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
●Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment number during repeat cycle: 340 (= 17 ✕ 20)
• Total number of built-in resistor: for digit; 16, for segment; 20
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 16 ✕ (1–1/16) ✕ 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 ✕ 31 ✕ (1–1/16) ✕ 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
(45 – 2)2 /48 ✕ (16 ✕ 16/16) ✕ (1 – 1/16) / 17 = 33.99 mW
(4) Pull-down resistor power dissipation (segment)
(45 – 2)2 /48 ✕ (31 ✕ 20/20) ✕ (1 – 1/16) / 17 = 65.86 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
(1) + (2)+ (3) + (4) + (5) = 217 mW
DIG0
DIG1
DIG2
●Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a ✕ c)
• Total number of built-in resistor: for digit; f, for segment; g
• Digit pin current value h (mA)
• Segment pin current value i (mA)
DIG3
DIG14
DIG15
DIG16
Timing number
(1) Digit pin power dissipation
{h ✕ b ✕ (1–Toff/Tdisp) ✕ voltage} / a
(2) Segment pin power dissipation
{i ✕ d ✕ (1–Toff/Tdisp) ✕ voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit ✕ (b ✕ f / b) ✕ (1–Toff/Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment ✕ (d ✕ g / c) ✕ (1–Toff/Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
1
2
3
14
15
16
17
Repeat cycle
Tscan
Fig. 75 Digit timing waveform (1)
(1) + (2)+ (3) + (4) + (5) = X mW
65
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Power Dissipation Calculating Example 2
(when 2 or more digit is turned ON at same
time)
●Fixed number depending on microcomputer’s standard
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µA = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.) = 5 V ✕
15 mA = 75 mW
●Fixed number depending on use condition
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 ✕ 24)
• Total number of built-in resistor: for digit; 10, for segment; 22
• Digit pin current value: 18 (mA)
• Segment pin current value: 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 12 ✕ (1–1/16) ✕ 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 ✕ 114 ✕ (1–1/16) ✕ 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
(45 – 2)2 /48 ✕ (12 ✕ 10/12) ✕ (1 – 1/16) / 11 = 32.84 mW
(4) Pull-down resistor power dissipation (segment)
(45 – 2)2 /48 ✕ (114 ✕ 22/24) ✕ (1 – 1/16) / 11 = 343.08 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.) = 75 mW
(1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0
DIG1
DIG2
DIG3
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
Timing number
1
2
3
4
5
6
7
8
9
10
11
Repeat cycle
Tscan
Fig. 76 Digit timing waveform (2)
66
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Table 12 Absolute maximum ratings
Parameter
Symbol
VCC
VEE
Pull-down power source voltage
VI
Input voltage
P47, P50–P5 7, P6 1–P65, P7 0–
P77, P84–P8 7, P90 , P91
VI
Input voltage
P40–P46, P6 0
VI
VI
Conditions
Power source voltage
Input voltage
Input voltage
P00–P07, P2 0–P2 7, P80–P8 3
RESET, XIN
All voltages are
based on VSS.
Output transistors
are cut off.
Ratings
Unit
–0.3 to 6.5
V
VCC – 45 to V CC +0.3 (Note 1)
V
VCC – 42 to V CC +0.3 (Note 2)
V
–0.3 to VCC +0.3
V
–0.3 to 13
V
VCC – 45 to V CC +0.3 (Note 1)
V
VCC – 42 to V CC +0.3 (Note 2)
V
–0.3 to VCC +0.3
V
–0.3 to VCC +0.3
V
VI
Input voltage
XCIN
VO
Output voltage
P00–P07, P1 0–P17 , P20–P2 7,
VCC – 45 to V CC +0.3 (Note 1)
V
P30–P37, P8 0–P8 3
VCC – 42 to V CC +0.3 (Note 2)
V
–0.3 to VCC +0.3
V
VO
Output voltage
P50–P57, P6 1–P65 , P70–P7 7,
P84–P87, P9 0, P91 , XOUT,
XCOUT
VO
Output voltage
P40–P46, P6 0
Pd
Power dissipation
–0.3 to 13
V
Ta = –20 to 65 °C
800
mW
Ta = 65 to 85 °C
800 – 12.5 ✕ (Ta – 65)
mW
Topr
Operating temperature
–20 to 85
°C
Tstg
Storage temperature
–40 to 125
°C
Notes 1: When Vcc is 4.0 to 5.5 V.
2: When Vcc is 2.7 to 4.0 V.
67
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS
Table 13 Recommended operating conditions (1)
(Vcc = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
VCC
Parameter
Power source voltage
In high-speed mode
In middle-/low-speed mode, 2 MHz or less in high-speed mode
VSS
VEE
VIH
VIH
Power source voltage
Pull-down power source voltage VCC = 4.0 to 5.5 V
VCC = 2.7 to 4.0 V
Analog reference voltage (when A-D conver ter is used)
Analog power source voltage
Analog input voltage
AN0–AN11
“H” input voltage
P40 –P47, P50–P57 , P60–P65, VCC = 4.0 to 5.5 V
P70 –P77, P90, P91
VCC = 2.7 to 4.0 V
“H” input voltage
P84 –P87
VCC = 4.0 to 5.5 V
VCC = 2.7 to 4.0 V
“H” input voltage
P00 –P07
“H” input voltage
P20 –P27, P80–P83
VCC = 4.0 to 5.5 V
VIH
VIH
VIL
“H” input voltage
“H” input voltage
“L” input voltage
VIL
VIL
VIL
VIL
“L” input voltage
“L” input voltage
“L” input voltage
“L” input voltage
VREF
AVSS
VIA
VIH
VIH
68
VCC = 2.7 to 4.0 V
RESET
XIN, X CIN
P40 –P47, P50–P57 , P60–P65, VCC = 4.0 to 5.5 V
P70 –P77, P90, P91
VCC = 2.7 to 4.0 V
P84 –P87
P00 –P07, P20–P27, P8 0–P83
RESET
XIN, X CIN
Min.
4.0
2.7
Limits
Typ.
5.0
5.0
0
VCC–43
VCC–40
2.0
Max.
5.5
5.5
VCC
VCC
VCC
0
0
0.75V CC
0.8V CC
0.4V CC
0.5Vcc
0.8V CC
0.52V CC
0.75V CC
0.8V CC
0.8V CC
0
0
0
0
0
0
VCC
VCC
VCC
VCC
Vcc
VCC
VCC
VCC
VCC
VCC
0.25V CC
0.2VCC
0.16V CC
0.2VCC
0.2VCC
0.2VCC
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 14 Recommended operating conditions (2)
(Vcc = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
ΣI OH(peak)
Parameter
f(CNTR 0)
f(CNTR 1)
f(XIN )
H” total peak output current (Note 1)
P00 –P07, P10–P17, P2 0–P27, P30–P37 , P80–P83
“H” total peak output current (Note 1)
P50 –P57, P61–P65, P7 0–P77, P90, P9 1
“L” total peak output current (Note 1)
P50 –P57, P60–P65, P7 0–P77, P90, P9 1
“L” total peak output current (Note 1)
P40 –P46, P84–P87
“H” total average output current (Note 1)
P00 –P07, P10–P17, P2 0–P27, P30–P37 , P80–P87
“H” total average output current (Note 1)
P50 –P57, P61–P65, P7 0–P77, P90, P9 1
“L” total average output current (Note 1)
P50 –P57, P60–P65, P7 0–P77, P90, P9 1
“L” total average output current (Note 1)
P40 –P46, P84–P87
“H” peak output current (Note 2)
P00 –P07, P10–P17, P2 0–P27, P30–P37 , P80–P83
“H” peak output current (Note 2)
P50 –P57, P61–P65, P7 0–P77, P84–P87 , P90, P91
“L” peak output current (Note 2)
P50 –P57, P61–P65, P7 0–P77, P84–P87 , P90, P91
“L” peak output current (Note 2)
P40 –P46, P60
“H” average output current (Note 3)
P00 –P07, P10–P17, P2 0–P27, P30–P37 , P80–P83
“H” average output current (Note 3)
P50 –P57, P60–P65, P7 0–P77, P84–P87 , P90, P91
“L” average output current (Note 3)
P50 –P57, P61–P65, P7 0–P77, P84–P87 , P90, P91
“L” average output current (Note 3)
P40 –P46, P60
Clock input frequency for timers 2, 4, and X
(duty cycle 50 %)
Main clock input oscillation frequency (Note 4)
f(XCIN )
Sub-clock input oscillation frequency (Notes 4, 5)
ΣI OH(peak)
ΣI OL(peak)
ΣI OL(peak)
ΣI OH(avg)
ΣI OH(avg)
ΣI OL(avg)
ΣI OL(avg)
I OH(peak)
I OH(peak)
I OL(peak)
I OL(peak)
I OH(avg)
I OH(avg)
I OL(avg)
I OL(avg)
Min.
VCC
VCC
VCC
VCC
Limits
Typ.
= 4.0 to 5.5 V
= 2.7 to 4.0 V
= 4.0 to 5.5 V
= 2.7 to 4.0 V
32.768
Max.
–240
Unit
mA
–60
mA
100
mA
60
mA
–120
mA
–30
mA
50
mA
30
mA
–40
mA
–10
mA
10
mA
30
mA
–18
mA
–5
mA
5
mA
15
mA
250
100
4.2
2
50
kHz
kHz
MHz
MHz
kHz
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an
average value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN ) < f(XIN)/3.
69
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Table 15 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Parameter
Symbol
VOH
VOH
VOL
VOL
VT+ –VT–
VT+ –VT–
VT+ –VT–
I IH
I IH
I IH
I IH
I IH
I IL
I IL
VCC = 4.0 to 5.5 V
VCC = 2.7 to 4.0 V
VCC = 4.0 to 5.5 V
“H” output voltage
VCC = 2.7 to 4.0 V
VCC = 4.0 to 5.5 V
“L” output voltage
VCC = 2.7 to 4.0 V
VCC = 4.0 to 5.5 V
“L” output voltage
VCC = 2.7 to 4.0 V
Hysteresis
P40 –P42, P45–P47, P5, P6 0, P61,P6 4 (Note 1)
Hysteresis
RESET, XIN
Hysteresis
XCIN
“H” input current
P47, P50 –P57, P61–P65, P7 0–P77, P84–P87
“H” input current
P40–P46, P6 0
“H” input current
P00–P07 , P20–P27, P80 –P83 (Note 2)
“H” input current
RESET, X CIN
“H” input current
XIN
“L” input current
P40–P47, P6 0
“L” input current
P50–P57 , P61–P65, P70 –P77 , P84–P87, P90 ,
P91
“H” output voltage
P00–P07, P1 0–P17, P20–
P27, P30 –P37, P80–P83
P50–P57, P6 0–P65, P70–
P77, P84 –P87, P90, P91
P50–P57, P6 1–P65, P84–
P87, P90, P91
P40–P46, P6 0
Test conditions
IOH = –18 mA
IOH = –10 mA
IOH = –10 mA
IOH = –10 mA
IOL = 10 mA
IOL = 1.6 mA
IOL = 15 mA
IOL = 5 mA
VI = V CC
VI = 12 V
VI = V CC
VI = V CC
VI = V CC
VI = V SS
VI = V SS
Pull-up “off”
VCC = 5 V, VI = VSS
Pull-up “on”
VCC = 3 V, VI = VSS
Pull-up “on”
VI = V SS
I IL
“L” input current
P00–P07 , P20–P27, P80 –P83 (Note 2)
VI = V SS
I IL
“L” input current
RESET, X CIN
VI = V SS
I IL
“L” input current
XIN
VEE = VCC–43 V,
RPULLD
Pull-down resistor
P00–P07 , P10–P17, P30–P37
VOL =VCC
(P2 0–P27, P80–P83 at option)
Output transistors “off”
VEE = VCC–43 V,
I LEAK
Output leak current P00–P07 , P10–P17, P20–P27 , P30–P37,
VOL =VCC–43 V
P80–P83
Output transistors “off”
VI = 5 V
I READH
“H” read current
P00–P07 , P20–P27, P80–P83
When clock is stopped
VRAM
RAM hold voltage
Notes 1: P42, P45 , P46, and P60 of the mask option type P do not have hysteresis characteristics.
2: Except when reading ports P0, P2, or P8.
70
Limits
Min.
VCC–2.0
VCC–1.5
VCC–2.0
VCC–1.0
Typ.
0.6
0.3
0.4
0.5
0.5
Max.
2.0
0.4
2.0
1.0
5.0
10.0
5.0
5.0
4.0
–5.0
–5.0
µA
–25
µA
–4.0
72
47
µA
µA
µA
kΩ
–10
µA
Vcc
µA
V
1
2
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
–70
–5.0
–5.0
143
Unit
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 Electrical characteristics (2)
(V CC =2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Power source current
ICC
Limits
Test conditions
Min.
High-speed mode
f(X IN) = 4.2 MHz
f(X CIN) = 32 kHz
Output transistors “off”
Typ.
Max.
Unit
7.5
mA
High-speed mode
f(X IN) = 4.2 MHz (in WIT state)
f(X CIN) = 32 kHz
Output transistors “off”
1
mA
Middle-speed mode
f(X IN) = 4.2 MHz
f(X CIN) = stopped
Output transistors “off”
3
mA
Middle-speed mode
f(X IN) = 4.2 MHz (in WIT state)
f(X CIN) = stopped
Output transistors “off”
1
mA
Low-speed mode
f(X IN) = stopped
f(X CIN) = 32 kHz
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
60
µA
Low-speed mode
f(X IN) = stopped
f(X CIN) = 32 kHz (in WIT state)
Low-power dissipation mode (CM 3 = 0)
Output transistors “off”
20
µA
Increment when A-D conversion is executed
0.6
mA
All oscillation stopped (in STP state)
Output transistors “off”
0.1
Ta = 25 °C
Ta = 85 °C
1
µA
10
µA
A-D converter characteristics
Table 17 A-D converter characteristics (1)
(V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, f(XIN ) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Symbol
Parameter
—
Resolution
—
Absolute accuracy (excluding quantization error)
Test conditions
Min.
VCC = VREF = 5.12 V
Limits
Typ.
Max.
10
Bits
±1
±2.5
LSB
62
tc(φ)
150
200
µA
5.0
µA
TCONV
Conversion time
61
IVREF
Reference input current
IIA
Analog port input current
0.5
RLADDER
Ladder resistor
35
VREF = 5.0 V
50
Unit
kΩ
Table 18 A-D converter characteristics (2)
(V CC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, f(X IN) = 250 kHz to 2 MHz in high-speed mode, unless otherwise noted)
Symbol
Parameter
—
Resolution
—
Absolute accuracy (excluding quantization error)
Test conditions
Limits
Min.
VCC = VREF = 3.3 V
Typ.
10
Bits
±6
LSB
62
tc(φ)
95
120
µA
5.0
µA
Conversion time
IVREF
Reference input current
IIA
Analog port input current
0.5
RLADDER
Ladder resistor
35
61
30
Unit
±3
TCONV
VREF = 3.3 V
Max.
kΩ
71
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 19 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
____________
Limits
Min.
Typ.
Max.
Unit
tW (RESET)
Reset input “L” pulse width
2.0
µs
tC (XIN)
Main clock input cycle time (XIN input)
238
ns
tWH (XIN)
Main clock input “H” pulse width
60
ns
tWL (XIN)
Main clock input “L” pulse width
60
ns
tC (XCIN)
Sub-clock input cycle time (XCIN input)
20
µs
tWH (XCIN)
Sub-clock input “H” pulse width
5.0
µs
tWL (XCIN)
Sub-clock input “L” pulse width
5.0
µs
tC (CNTR)
CNTR0, CNTR 1 input cycle time
4.0
µs
tWH (CNTR)
CNTR0, CNTR 1 input “H” pulse width
1.6
µs
tWL (CNTR)
CNTR0, CNTR 1 input “L” pulse width
1.6
µs
tWH (INT)
INT0 to INT4 input “H” pulse width
80
ns
tWL (INT)
INT0 to INT4 input “L” pulse width
80
ns
tC (SCLK)
Serial I/O clock input cycle time
0.95
µs
tWH (SCLK)
Serial I/O clock input “H” pulse width
400
ns
tWL (SCLK)
Serial I/O clock input “L” pulse width
400
ns
tsu (SCLK–SIN)
Serial I/O input set up time
200
ns
th (SCLK–SIN)
Serial I/O input hold time
200
ns
Table 20 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
____________
Limits
Min.
Typ.
Max.
Unit
tW (RESET)
Reset input “L” pulse width
2.0
µs
tC (XIN)
Main clock input cycle time (XIN input)
500
ns
tWH (XIN)
Main clock input “H” pulse width
120
ns
tWL (XIN)
Main clock input “L” pulse width
120
ns
tC (XCIN)
Sub-clock input cycle time (X CIN input)
20
µs
tWH (XCIN)
Sub-clock input “H” pulse width
5.0
µs
tWL (XCIN)
Sub-clock input “L” pulse width
5.0
µs
tC (CNTR)
CNTR 0, CNTR1 input cycle time
10
µs
tWH (CNTR)
CNTR 0, CNTR1 input “H” pulse width
4.0
µs
tWL (CNTR)
CNTR 0, CNTR1 input “L” pulse width
4.0
µs
tWH (INT)
INT0 to INT4 input “H” pulse width
230
ns
tWL (INT)
INT0 to INT4 input “L” pulse width
230
ns
tC (SCLK)
Serial I/O clock input cycle time
2.0
µs
tWH (SCLK)
Serial I/O clock input “H” pulse width
950
ns
tWL (SCLK)
Serial I/O clock input “L” pulse width
950
ns
tsu (SCLK–SIN)
Serial I/O input set up time
400
ns
th (SCLK–SIN)
Serial I/O input hold time
300
ns
72
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS
Table 21 Switching characteristics (1)
(V CC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
Unit
tWH(SCLK)
Serial I/O clock output “H” pulse width
CL = 100 pF
tC(SCLK)/2–160
tWL(SCLK)
Serial I/O clock output “L” pulse width
CL = 100 pF
tC(SCLK)/2–160
ns
td(SCLK–SOUT)
Serial I/O output delay time
tv (SCLK–SOUT)
Serial I/O output valid time
tr(SCLK)
Serial I/O clock output rising time
CL = 100 pF
40
ns
tf(SCLK)
Serial I/O clock output falling time
CL = 100 pF
40
ns
tr(Pch–strg)
P-channel high-breakdown voltage
output rising time (Note 1)
CL = 100 pF
VEE = V CC–43 V
55
ns
tr(Pch–weak)
P-channel high-breakdown voltage
output rising time (Note 2)
CL = 100 pF
VEE = V CC–43 V
1.8
µs
ns
0.2 tc
0
ns
ns
Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.
2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.
Table 22 Switching characteristics (2)
(V CC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
tWH(SCLK)
Serial I/O clock output “H” pulse width
CL = 100 pF
tC(SCLK)/2–240
tWL(SCLK)
Serial I/O clock output “L” pulse width
CL = 100 pF
tC(SCLK)/2–240
td(SCLK–SOUT)
Serial I/O output delay time
tv (SCLK–SOUT)
Serial I/O output valid time
Typ.
Max.
Unit
ns
ns
0.4 tc
0
ns
ns
tr(SCLK)
Serial I/O clock output rising time
CL = 100 pF
60
ns
tf(SCLK)
Serial I/O clock output falling time
CL = 100 pF
60
ns
tr(Pch–strg)
P-channel high-breakdown voltage
output rising time (Note 1)
CL = 100 pF
VEE = V CC–40 V
140
ns
tr(Pch–weak)
P-channel high-breakdown voltage
output rising time (Note 2)
CL = 100 pF
VEE = V CC–40 V
3.6
µs
Notes 1: When bit 7 of the FLDC mode register (address 0EF416) is at “0”.
2: When bit 7 of the FLDC mode register (address 0EF416) is at “1”.
73
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O clock
output port
P52/SCLK11,
P53/SCLK12,
P56/SCLK21,
P57/SCLK22
CL
P0,P1,P2,
P3,P80–P83
High-breakdown
P-channel opendrain output port
CL
(Note)
VEE
Note: Ports P2 and P8 need external resistors.
Fig. 77 Circuit for measuring output switching characteristics
74
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing Diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
CNTR0,CNTR1
0.8VCC
0.2VCC
tWL(INT)
tWH(INT)
INT0–INT4
0.8VCC
0.2VCC
tW(RESET)
RESET
0.8VCC
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
XI N
0.8VCC
0.2VCC
tC(XCIN)
tWL(XCIN)
tWH(XCIN)
XCIN
0.8VCC
0.2VCC
tC(SCLK)
tf(SCLK)
SCLK
tWL(SCLK)
tr
tWH(SCLK)
0.8VCC
0.2VCC
tsu(SIN-SCLK)
th(SCLK-SIN)
0.8VCC
0.2VCC
SI N
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
Fig. 78 Timing diagram
75
MITSUBISHI MICROCOMPUTERS
38B4 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
QFP80-P-1420-0.80
Weight(g)
1.58
Lead Material
Alloy 42
MD
e
JEDEC Code
–
65
b2
80
ME
HD
D
1
64
I2
24
Symbol
HE
E
Recommended Mount Pad
41
25
A
40
c
A2
L1
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
x
y
y
76
b
x
M
A1
F
e
L
Detail F
b2
I2
MD
ME
Dimension in Millimeters
Min
Nom
Max
3.05
–
–
0.1
0.2
0
2.8
–
–
0.3
0.35
0.45
0.13
0.15
0.2
13.8
14.0
14.2
19.8
20.0
20.2
0.8
–
–
16.5
16.8
17.1
22.5
22.8
23.1
0.4
0.6
0.8
1.4
–
–
–
–
0.2
0.1
–
–
0°
10°
–
–
–
0.5
1.3
–
–
14.6
–
–
–
–
20.6
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
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Notes regarding these materials
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© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective MAY 2000.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
1.0
38B4 GROUP DATA SHEET
Revision Description
First Edition
Rev.
date
000510
(1/1)