ON NCP1379 Quasi-resonant current-mode controller for high-power universal off-line supply Datasheet

NCP1379
Product Preview
Quasi-Resonant
Current-Mode Controller for
High-Power Universal
Off-line Supplies
The NCP1379 hosts a high−performance circuitry aimed to
powering quasi−resonant converters. Capitalizing on a proprietary
valley−lockout system, the controller shifts gears and reduces the
switching frequency as the power loading becomes lighter. This
results in a stable operation despite switching events always occurring
in the drain−source valley. This system works down to the 4th valley
and toggles to a variable frequency mode beyond, ensuring an
excellent standby power performance.
The controller includes an Over Power Protection circuit which
clamps the delivered power at high−line. Safety−wise, a fixed internal
timer relies on the feedback voltage to detect a fault. Once the timer
elapses, the controller stops and enters auto−recovery mode, ensuring
a low duty−cycle burst operation. To further improve the safety of the
power supply, the NCP1379 features a pin to implement a combined
brown−out/overvoltage protection.
Particularly well suited for TVs power supply applications, the
controller features a low startup voltage allowing the use of an
auxiliary power supply to power the device.
Features
• Quasi−Resonant Peak Current−Mode Control Operation
• Valley Switching Operation with Valley−Lockout for Noise−Immune
•
•
•
•
•
•
•
•
•
•
•
•
Operation
Frequency Foldback at Light Load to Improve the Light Load
Efficiency
Adjustable Over Power Protection
Auto−Recovery Output Short−Circuit Protection
Fixed Internal 80 ms Timer for Short−Circuit Protection
Combined Overvoltage Protection and Brown−out
+500 mA / −800 mA Peak Current Source/Sink Capability
Internal Temperature Shutdown
Direct Optocoupler Connection
Low VCC(on) Allowing to Use a Standby Power Supply to Power the
Device
Extremely Low No−Load Standby Power
SO8 Package
These Devices are Pb−Free and are RoHS Compliant
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QUASI−RESONANT PWM
CONTROLLER FOR HIGH
POWER AC−DC WALL
ADAPTERS
MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
1379
A
L
Y
W
G
1379
ALYW
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
ZCD 1
8 CT
FB 2
7 FAULT
CS 3
6 VCC
GND 4
5 DRV
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
Typical Applications
• High Power ac−dc Converters for TVs, Set−Top Boxes etc.
• Offline Adapters for Notebooks
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. P0
1
Publication Order Number:
NCP1379/D
NCP1379
TYPICAL APPLICATION EXAMPLE
HV −bulk
.
.
Vout
.
ZCD / OPP
NCP 1 3 7 9
GND
1
8
2
7
3
6
4
5
VCC
GND
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION
Pin N5
Pin Name
Function
Pin Description
1
ZCD
Zero Crossing Detection
Adjust the over power protection
2
FB
Feedback pin
Hooking an optocoupler collector to this pin will allow regulation.
3
CS
Current sense
This pin monitors the primary peak.
4
GND
−
5
DRV
Driver output
6
VCC
Supplies the controller
This pin is connected to an external auxiliary voltage.
7
Fault
Overvoltage protection
Brown−out
This pin observes the HV rail and protects the circuit in case of low
main conditions. It also offers a way to latch the circuit in case of over
voltage event.
8
CT
Timing capacitor
A capacitor connected to this pin acts as the timing capacitor in foldback mode.
Connected to the auxiliary winding, this pin detects the core reset
event.
Also, injecting a negative voltage smaller than 0.3 V on this pin will
perform over power protection.
The controller ground
The driver’s output to an external MOSFET
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2
NCP1379
INTERNAL CIRCUIT ARCHITECTURE
VDD
BO r e se t
Vcc
latch
VCC management
VDD
VDD
fa ul t
Rpullup
V cc aux
V CCstop
gr a nd
reset
FB
LOGIC BLOCK
VDD
clamp
ICt
DRV
Ct
+
ga te
gr a nd
reset
DRV
−
C t s e tpoint
R
Q
Q
Ct
Discharge
ZC D
+
10 V
ESD
DRV
S
GN D
de ma g
−
CsS top
Vth
S
3 ms blanking
La ux
SS end
TIMER
Reset
R
40 ms
Time Out
/4
Q
Q
noi s e de l a y
5 ms
Time Out
+
LEB 1
+
Rsense
VCC HV
VOVP
−
CS
PW Mreset
−
PW Mreset
Ipeak(VCO) = 17.5 % VILIMIT
IpFlag
gr a nd
reset
The 40 ms Time Out is active
only during s oft−s ta r t
SS end
Up
Down
VDD
I pFl a g
IBO
OPP
VILIMIT
LEB 2
LE B 2 is shorter than LE B 1
noise delay
+
Soft-start
−
VBO
+
−
Soft-start end ? then 1
else 0
Cs S top
SS end
+
BO r e se t
−
VCS(stop )
Figure 2. Internal Circuit Architecture
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3
Rclamp
Vclamp
OVP/BO
NCP1379
MAXIMUM RATINGS TABLE(S)
Value
Unit
VCC(MAX)
ICC(MAX)
Symbol
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
−0.3 to 28
$30
V
mA
VDRV(MAX)
IDRV(MAX)
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
−0.3 to 20
$1000
V
mA
Maximum voltage on low power pins (except pins DRV and VCC)
Current range for low power pins (except pins ZCD, DRV and VCC)
−0.3 to 10
$10
V
mA
+3 / −2
mA
Thermal Resistance Junction−to−Air
120
°C/W
Maximum Junction Temperature
150
°C
Operating Temperature Range
−40 to +125
°C
Storage Temperature Range
−60 to +150
°C
ESD Capability, Human Body Model (HBM) model (Note 1)
4
kV
ESD Capability, CDM model (Note 1)
2
kV
VMAX
IMAX
IZCD(MAX)
RqJA
TJ(MAX)
Rating
Maximum current for ZCD pin
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.
Charged Device Model 2000 V per JEDEC Standard JESD22−C101D
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,
VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Parameter
Conditions
Min
Typ
Max
VCC increasing
VCC decreasing
10.5
8.3
2.0
6
11.4
9.0
2.4
7
12.3
9.4
−
8
VCC(off) noise filter
−
5
−
ms
VCC(reset) noise filter
−
20
−
ms
FB pin open
VCC = VCC(on) − 0.5 V
−
0.7
1.2
mA
VCC > VCC(off)
Fsw = 10 kHz
CDRV = 1 nF, Fsw = 65 kHz
CDRV = 1 nF, VFB = 1.25 V
−
−
−
−
1.7
1.7
2.65
2.0
2.0
2.0
3.00
−
VFB = 4 V, VCS increasing
0.76
0.80
0.84
V
Minimum on time minus
tILIM
210
275
330
ns
DRV high
−2
−
2
mA
VCS > VILIM to DRV
turn−off
−
125
175
ns
VFB = 0.4 V, VCS
increasing
15.4
17.5
19.6
%
Symbol
Unit
SUPPLY SECTION − STARTUP AND SUPPLY CIRCUITS
VCC(on)
VCC(off)
VCC(hyst)
VCC(reset)
tVCC(off)
tVCC(reset)
ICC(start)
ICC1
ICC2
ICC3A
ICC3B
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis VCC(on) − VCC(off)
Internal logic reset
VCC decreasing
Startup current
Supply Current
Device Disabled/Fault (Note 3)
Device Enabled/No output load on pin 5
Device Switching (Fsw = 65 kHz)
Device Switching (Fsw around 12 kHz)
V
mA
CURRENT COMPARATOR − CURRENT SENSE
VILIM
Current Sense Voltage Threshold
tLEB
Leading Edge Blanking Duration for VILIM
Ibias
Input Bias Current (Note 3)
tILIM
Propagation Delay
Ipeak(VCO)
3.
4.
5.
6.
Percentage of maximum peak current level at which
VCO takes over (Note 4)
Guaranteed by design
The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)
If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
Minimum value for TJ = 125°C
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NCP1379
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,
VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VZCD = −300 mV, VFB =
4 V, VCS increasing
35.0
37.5
40.0
%
1.125
1.200
1.275
V
−
120
−
ns
CURRENT COMPARATOR − CURRENT SENSE
VOPP(MAX)
VCS(stop)
tBCS
Setpoint decrease for VZCD = −300 mV (Note 5)
Threshold for immediate fault protection activation
Leading Edge Blanking Duration for VCS(stop)
DRIVE OUTPUT − GATE DRIVE
RSNK
RSRC
Drive Resistance
DRV Sink
DRV Source
VDRV = 10 V
VDRV = 2 V
−
−
12.5
20
−
−
ISNK
ISRC
Drive current capability
DRV Sink
DRV Source
VDRV = 10 V
VDRV = 2 V
−
−
800
500
−
−
W
mA
tr
Rise Time (10 % to 90 %)
CDRV = 1 nF, VDRV from 0
to 12 V
−
40
75
ns
tf
Fall Time (90 % to 10 %)
CDRV = 1 nF, VDRV from 0
to 12 V
−
25
60
ns
VDRV(low)
DRV Low Voltage
VCC = VCC(off) + 0.2 V
CDRV = 1 nF, RDRV=33 kW
8.4
9.1
−
V
VDRV(high)
DRV High Voltage (Note 6)
VCC = VCC(MAX)
CDRV = 1 nF
10.5
13.0
15.5
V
DEMAGNETIZATION INPUT − ZERO VOLTAGE DETECTION CIRCUIT
VZCD(TH)
ZCD threshold voltage
VZCD decreasing
35
55
90
mV
VZCD(HYS)
ZCD hysteresis
VZCD increasing
15
35
55
mV
VCH
VCL
Input clamp voltage
High state
Low state
Ipin1 = 3.0 mA
Ipin1 = −2.0 mA
8
−0.9
10
−0.7
12
−0.3
tDEM
Propagation Delay
VZCD decreasing from 4 V
to −0.3 V
−
150
250
ns
CPAR
Internal input capacitance
tBLANK
Blanking delay after on−time
toutSS
tout
Timeout after last demag transition
RZCD(pdown)
V
−
10
−
pF
2.30
3.15
4.00
ms
28
5.0
41
5.9
54
6.7
ms
140
320
500
kW
VFB < VFB(TH)
5.15
5.40
5.65
V
VCT = 0 V
18
20
22
mA
−
−
90
mV
During soft−start
After the end of soft−start
Pulldown resistor (Note 3)
TIMING CAPACITOR − TIMING CAPACITOR
VCT(MAX)
ICT
VCT(MIN)
CT
Maximum voltage on CT pin
Source current
Minimum voltage on CT pin, discharge switch
activated
Recommended timing capacitor value
220
pF
FEEDBACK SECTION − FEEDBACK
RFB(pullup)
Iratio
VFB(TH)
3.
4.
5.
6.
Internal pullup resistor
15
18
22
Pin FB to current setpoint division ratio
3.8
4.0
4.2
FB pin threshold under which CT is clamped to
VCT(MAX)
0.26
0.30
0.34
kW
Guaranteed by design
The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)
If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
Minimum value for TJ = 125°C
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5
V
NCP1379
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VFB = 3 V,
VCS = 0 V, Vfault = 1.5 V, CT = 680 pF) For min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
FEEDBACK SECTION − FEEDBACK
VFB decreases
1.316
1.4
1.484
VFB decreases
1.128
1.2
1.272
VFB decreases
0.846
0.9
0.954
VHVCOD
Valley threshold
FB voltage where 1st valley ends and 2nd valley
starts
FB voltage where 2nd valley ends and 3rd valley
starts
FB voltage where 3rd valley ends and 4th valley
starts
FB voltage where 4th valley ends and VCO starts
VFB decreases
0.732
0.8
0.828
VHVCOI
FB voltage where VCO ends and 4th valley starts
VFB increases
1.316
1.4
1.484
VH4I
FB voltage where 4th valley ends and 3rd valley
starts
FB voltage where 3rd valley ends and 2nd valley
starts
FB voltage where 2nd valley ends and 1st valley
starts
VFB increases
1.504
1.6
1.696
VFB increases
1.692
1.8
1.908
VFB increases
1.880
2.0
2.120
Device switching (FSW
around 65 kHz)
140
−
170
°C
−
40
−
°C
75
85
95
ms
1.0
1.2
1.4
s
VFB = 4 V, VCS ramping
up, measured from 1st
DRV pulse to VCS(peak) =
90% of VILIM
2.8
3.8
4.8
ms
VFault decreasing
0.744
0.800
0.856
V
VFault = VBO + 0.2 V
9
10
11
mA
22.5
30.0
37.5
ms
2.35
2.5
2.65
V
22.5
30
37.5
ms
VH2D
VH3D
VH4D
VH3I
VH2I
V
PROTECTIONS − FAULT PROTECTION
TSHDN
TSHDN(HYS)
tOVLD
Thermal Shutdown
Thermal Shutdown Hysteresis
Overload Timer
tOVLD(off)
OFF phase in auto−recovery fault mode
tSSTART
Soft−start duration
VBO
Brown−Out level
IBO
Sourced hysteresis current VFault > VBO
tBO(delay)
Delay before entering and exiting Brown−out
VOVP
Internal Fault detection level for OVP
tlatch(delay)
Delay before latch confirmation (OVP)
VFault(clamp)
Clamped voltage (Fault pin left open)
RFault(clamp)
Clamping resistor (Note 3)
3.
4.
5.
6.
VFB = 4 V, VCS > VILIM
VFault increasing
Fault pin open
1.0
1.2
1.4
V
1.30
1.55
1.80
kW
Guaranteed by design
The peak current setpoint goes down as the load decreases. It is frozen below Ipeak(VCO) (Ipeak = cst)
If negative voltage in excess to −300 mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
Minimum value for TJ = 125°C
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NCP1379
11.40
8.96
8.94
11.35
8.92
VCC(off), (V)
VCC(on), (V)
11.30
11.25
11.20
8.90
8.88
8.86
8.84
11.15
11.10
−40
8.82
−20
0
20
40
60
80
100
8.80
−40
120
TJ, JUNCTION TEMPERATURE (°C)
1.8
2.8
1.7
2.7
ICC3A, (mA)
ICC2, (mA)
2.9
1.6
1.5
40
60
80
100
120
2.6
2.5
2.4
1.4
−20
0
20
40
60
80
100
2.3
−40
120
−20
TJ, JUNCTION TEMPERATURE (°C)
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. ICC2 vs. Junction Temperature
Figure 6. ICC3A vs. Junction Temperature
2.6
1.2
2.5
1.1
2.4
1.0
ICC(start), (mA)
2.3
ICC3B, (mA)
20
Figure 4. VCC(off) vs. Junction Temperature
1.9
2.2
2.1
2.0
1.9
0.9
0.8
0.7
0.6
1.8
0.5
1.7
1.6
−40
0
TJ, JUNCTION TEMPERATURE (°C)
Figure 3. VCC(on) vs. Junction Temperature
1.3
−40
−20
−20
0
20
40
60
80
100
120
0.4
−40
TJ, JUNCTION TEMPERATURE (°C)
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 7. ICC3B vs. Junction Temperature
Figure 8. ICC(start) vs. Junction Temperature
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120
NCP1379
290
810
808
280
806
270
802
TLEB, (ns)
VILIM, (mV)
804
800
798
796
794
260
250
240
792
790
−40
−20
0
20
40
60
80
100
230
−40
120
TJ, JUNCTION TEMPERATURE (°C)
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 9. VILIM vs. Junction Temperature
Figure 10. TLEB vs. Junction Temperature
38.00
1.24
37.80
1.23
VOPP(max), (%)
VCS(stop), (V)
37.60
1.22
1.21
1.20
37.40
37.20
37.00
36.80
1.19
36.60
1.18
−40
−20
0
20
40
60
80
100
36.40
−40
120
−20
TJ, JUNCTION TEMPERATURE (°C)
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VCS(stop) vs. Junction Temperature
Figure 12. VOPP(MAX) vs. Junction Temperature
14.5
9.4
14.0
9.3
VDRV(high), (V)
VDRV(low), (V)
13.5
9.2
9.1
9.0
13.0
12.5
12.0
11.5
8.9
8.8
−40
11.0
−20
0
20
40
60
80
100
10.5
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 13. VDRV(low) vs. Junction Temperature
Figure 14. VDRV(high) vs. Junction Temperature
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90.0
50.0
80.0
45.0
40.0
70.0
VZCD(hys), (V)
VZCD(th), (V)
NCP1379
60.0
50.0
35.0
30.0
25.0
40.0
20.0
30.0
−40
−20
0
20
40
60
80
100
15.0
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. VZCD(th) vs. Junction Temperature
Figure 16. VZCD(hys) vs. Junction Temperature
46
3.30
45
3.25
ToutSS, (ms)
TBLANK, (ms)
44
3.20
3.15
3.10
43
42
41
40
3.05
39
3.00
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
38
−40
120
6.4
810
6.2
805
6.0
800
5.8
5.6
120
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
120
795
790
785
5.4
5.2
−40
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 18. ToutSS vs. Junction Temperature
VBO, (mV)
Tout, (ms)
Figure 17. TBLANK vs. Junction Temperature
−20
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
780
−40
120
Figure 19. Tout vs. Junction Temperature
−20
Figure 20. VBO vs. Junction Temperature
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NCP1379
10.4
10.2
IBO, (mA)
10.0
9.8
9.6
9.4
9.2
−40
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
Figure 21. IBO vs. Junction Temperature
APPLICATION INFORMATION
• Overpower protection (OPP): When the voltage on
NCP1379 implements a standard current−mode
architecture operating in quasi−resonant mode. Thanks to a
proprietary
circuitry,
the
controller
prevents
valley−jumping instability and steadily locks out in selected
valley as the power demand goes down. Once the fourth
valley is reached, the controller continues to reduce the
frequency further down, offering excellent efficiency over
a wide operating range. Due to a fault timer combined to an
OPP circuitry, the controller is able to efficiently limit the
output power at high−line.
• Quasi−Resonance Current−mode operation:
implementing quasi−resonance operation in peak
current−mode control, the NCP1379 optimizes the
efficiency by switching in the valley of the MOSFET
drain−source voltage. Due to a proprietary circuitry, the
controller locks−out in a selected valley and remains
locked until the output loading significantly changes.
This behavior is obtained by monitoring the feedback
voltage. When the load becomes lighter, the feedback
setpoint changes and the controller jumps into the next
valley. It can go down to the 4th valley if necessary.
Beyond this point, the controller reduces its switching
frequency by freezing the peak current setpoint. During
quasi−resonance operation, in case of very damped
valleys, a 5.9 ms timer adds the missing valleys.
• Frequency reduction in light−load conditions: when the
4th valley is left, the controller reduces the switching
frequency which naturally improves the standby power
by a reduction of all switching losses.
•
•
•
ZCD pin swings in flyback polarity, a direct image of
the input voltage is applied on ZCD pin. We can thus
reduce the peak current depending of the ZCD pin
voltage level during the on−time.
Internal soft−start: a soft−start precludes the main
power switch from being stressed upon start−up. Its
duration is fixed and equal to 3.8 ms.
Fault input: the NCP1379 and D versions include a
brown−out circuit which safely stops the controller in
case the input voltage is too low. Restart occurs via a
complete startup sequence (latch reset and soft−start).
During normal operation, the voltage on this pin is
clamped to 1.2 V to give enough room for OVP
detection. If the voltage on this pin increases above
2.5 V, the part latches−off.
Short−circuit protection: short−circuit and especially
over−load protections are difficult to implement when a
strong leakage inductance between auxiliary and power
windings affects the transformer (where the auxiliary
winding level does not properly collapse in presence of
an output short). Here, when the internal 0.8 V
maximum peak current limit is activated, the timer
starts counting up. If the fault disappears, the timer
counts down. If the timer reaches completion while the
error flag is still present, the controller stops the pulses
and goes into auto−recovery mode.
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NCP1379
NCP1379 OPERATING MODES
• During VCO mode, the peak current decreases down to
NCP1379 has two operating mode: quasi−resonant
operation and VCO operation for the frequency foldback.
The operating mode is fixed by the FB voltage as
portrayed by Figure 22:
• Quasi−resonant operation occurs for FB voltage higher
than 0.8 V (FB decreasing) or higher than 1.4 V (FB
increasing) which correspond to high output power and
medium output power. The peak current is variable and
is set by the FB voltage divided by 4.
• Frequency foldback or VCO mode occurs for FB
voltage lower than 0.8 V (FB decreasing) or lower than
1.4 V (FB increasing). This corresponds to low output
power.
•
17.5% of its maximum value and is then frozen. The
switching frequency is variable and decreases as the
output load decreases.
The switching frequency is set by the end of charge of
the capacitor connected to the CT pin. This capacitor is
charged with a constant current source and the
capacitor voltage is compared to an internal threshold
fixed by FB voltage. When this capacitor voltage
reaches the threshold the capacitor is rapidly discharged
down to 0 V and a new period start.
Figure 22. Operating Valley According to FB Voltage
VALLEY DETECTION AND SELECTION
The valley detection is done by monitoring the voltage of
the auxiliary winding of the transformer. A valley is detected
when the voltage on pin 1 crosses down the 55 mV internal
threshold. When a valley is detected, an internal counter is
incremented. The operating valley (1st, 2nd, 3rd or 4th) is
determined by the FB voltage as shown by Figure 22.
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NCP1379
VDD
VDD
Rpullup
FB
VFB
Ct
LOGIC BLOCK
VFBth
Vdd
S
ICt
DRV
Q
+
Ct setpoint
Q
−
R
Time Out CS comparator
Ct
Discharge
ZCD
+
10 V
ESD
DRV
demag
−
Vth
leakage
blanking
3 us puls e
Laux
Figure 23. Valley Detection Circuit
necessary output power. This allows achieving very low
standby power consumption.
The Figure 24 shows a simulation case where the output
current of a 19 V / 60 W decreases from 2.8 A to 0.1 A. No
instability is seen during the valley transitions
(Figures 25, 26, 27 and 28)
As the output load decreases (FB voltage decreases the
valleys are incremented from the first to the fourth. When
the fourth valley is reached, if FB voltage further decreases
below 0.8 V, the controller enters VCO mode.
During VCO operation, the peak current continues to
decrease until it reaches 17.5% of the maximum peak
current: the switching frequency expands to deliver the
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NCP1379
Figure 24. Output Load is Decreased from 2.4 A to 0.5 A at 120 Vdc Input Voltage
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NCP1379
Figure 25. Zoom 1: 1st to 2nd Valley Transition
Figure 26. Zoom 2: 2nd to 3rd Valley Transition
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NCP1379
Figure 27. Zoom 3: 3rd to 4th Valley Transition
Figure 28. Zoom 4: 4th Valley to VCO Mode Transition
Time Out
introduced by the Over Power Compensation diode
(Figure 35), the voltage on the ZCD pin is very low and the
ZCD comparator might be unable to detect the valleys. In
this condition, setting the DRV Latch with the 5.9 ms
time−out leads to a continuous conduction mode operation
(CCM) at the beginning of the soft−start. This CCM
operation only last a few cycles until the voltage on ZCD pin
becomes high enough to be detected by the ZCD
comparator.
To avoid this, the time−out duration is extended to 40 ms
during the soft−start in order to ensure that the transformer
is fully demagnetized before the MOSFET is turned−on.
In case of extremely damped free oscillations, the ZCD
comparator can be unable to detect the valleys. To avoid
such situation, NCP1379 integrates a Time Out function that
acts as a substitute clock for the decimal counter inside the
logic bloc. The controller thus continues its normal
operation. To avoid having a too big step in frequency, the
time out duration is set to 5.9 ms. Figures 30 and 31 detail the
time out operation.
The NCP1379 also features an extended time out during
the soft−start.
Indeed, at startup, the output voltage reflected on the
auxiliary winding is low. Because of the voltage drop
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NCP1379
VDD
ZC D
+
demag
−
10 V
ES D
LOGI C BLOCK
Vth
leakage blanking
3 us pulse
Ti meOut
DRV
VDD
5. 9 us ti m e −out
SS e nd
+
−
100 ns
VDD
40 us ti m e −out
SS end
+
−
100 ns
Figure 29. Time Out Circuit
Figure 30. Time Out Case n51: the 3rd Valley is Missing
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NCP1379
Figure 31. Time Out Case n52: the 3rd and 4th Valley are Missing
VCO MODE
VCO operation occurs for FB voltage lower than 0.8 V
(FB decreasing), or lower than 1.4 V (FB increasing). This
corresponds to low output power.
During VCO operation, the switching frequency is
variable and expands as the output power decreases. The
peak current is fixed to 17.5% of his maximum value when
VFB < 0.56 V.
The frequency is set by the end of charge of the capacitor
connected to the CT pin. This capacitor is charged with a
constant current source and its voltage is compared to an
internal threshold (VFBth) fixed by FB voltage (see
Figure 23). When this capacitor voltage reaches the
threshold, the capacitor is rapidly discharged down to 0 V
and a new period start. The internal threshold is inversely
proportional to FB voltage. The relationship between VFB
and VFBth is given by Equation 1.
V FBth + 6.5 * (10ń3)V FB
(eq. 1)
When VFB is lower than 0.3 V, VCT is clamped to
VCT(MAX) which is typically 5.5 V. Figure 32 shows the
VCO mode at works.
Figure 32. In VCO Mode, as the Power Output Decreases the Frequency Expands
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NCP1379
SHORT−CIRCUIT OR OVERLOAD MODE
Figure 33 shows the implementation of the fault timer.
S
Q
Q
VDD
DRV
au x
R
VCC
management
VC C sto p
Vcc
latch
grand
reset
CsStop
CS
LEB1
R sen se
+
ZCD/OPP
fau l t
PW Mr eset
−
FB/4
Down
Up TIMER
IpFlag
OPP
VCCstop
Reset
+
−
VIL IM IT
SS en d
Soft −s t art end ?
t hen 1
else 0
Soft−start
Laux
LEB2
+
CsStop
−
grand
reset
VCS(stop)
Figure 33. Fault Detection Schematic
When the timers reaches its completion, the circuit enter
auto−recovery mode: the circuit stops all operations during
1.2 s typically and re−start. This ensures a low duty−cycle
burst operation in fault mode (around 6.7%).
In parallel to the cycle−by−cycle sensing of the CS pin,
another comparator with a reduced LEB (tBCS) and a
threshold of 1.2 V is able to sense winding short−circuit and
immediately stop the controller. This additional protection
is also auto−recovery.
When the current in the MOSFET is higher than VILIM
/Rsense, “Max Ip” comparator trips and the digital timer
starts counting: the timer count is incremented each 10 ms.
When the current comes back within safe limits, “Max Ip”
comparator becomes silent and the timer count down: the
timer count is decremented each 10 ms. In normal overload
conditions the timer reaches its completion when it has
counted up 8 times 10 ms.
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NCP1379
Figure 34. Auto−Recovery Overload Protection Chronograms
OVER POWER COMPENSATION
the input voltage. As the auxiliary winding is already
connected to ZCD pin for the valley detection, by selecting
the right values for Ropu and Ropl, we can easily perform
over power compensation.
The over power compensation is achieved by monitoring
the signal on ZCD pin (pin 1). Indeed, a negative voltage
applied on this pin directly affects the internal voltage
reference setting the maximum peak current (Figure 35).
When the power MOSFET is turned−on, the auxiliary
winding voltage becomes a negative voltage proportional to
Rz cd
Ropu
CS
ZC D / O P P
OPP
IpFlag
1
Au x
Ropl
ESD
pr ot ect ion
V IL IMIT
+
−
Demag
Vth
leakage blanking
Tblank
DRV
Figure 35. Over Power Compensation Circuit
To ensure optimal zero−crossing detection, a diode is
needed to bypass Ropu during the off−time.
If we apply the resistor divider law on pin 1 during the
on−time, we obtain the following relationship:
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NCP1379
R zcd ) R opu
R opl
+−
N p,auxV IN * V OPP
V OPP
• Vaux = 18 V
• Vd = 0.6 V
• Np,aux = 0.18
(eq. 2)
Where:
Np,aux is the auxiliary to primary turn ration: Np,aux = Naux
/ Np
VIN is the DC input voltage
VOPP is the negative OPP voltage
By selecting a value for Ropl, we can easily deduce Ropu
using Equation 2. While selecting the value for Ropl, we
must be careful not choosing a too low value for this resistor
in order to have enough voltage for zero−crossing detection
during the off−time. We recommend having at least 8 V on
ZCD pin, the maximum voltage being 10 V.
During the off−time, ZCD pin voltage can be expressed as
follows:
V ZCD +
R opl
R ZCD ) Ropl
ǒV auz * V dǓ
If we want at least 8 V on ZCD pin, we have:
R ZCD
R opl
R opl
+
V aux * V d * V ZCD
V ZCD
V OPP + 0.375
+
18 * 0.6 * 8
+ 1.2
8
(eq. 5)
V ILIM + −300 mV
(eq. 6)
Using Equation 2, we have:
R ZCD ) R opu
R opl
(eq. 3)
+−
+
N p,auxV IN * V OPP
V OPP
−0.18
370 * (−0.3)
(−0.3)
(eq. 7)
+ 221
Thus,
R opu + 221 Ropl * R ZCD + 221
(eq. 4)
V ZCD
V aux * V d * V ZCD
We can choose: Rzcd = 1 kW and Ropl = 1 kW.
For the over power compensation, we need to decrease the
peak current by 37.5% at high line (370 Vdc). The
corresponding OPP voltage is:
We can thus deduce the relationship between Ropl and
Rzcd:
R ZCD
+
1k * 1k + 220 kW
(eq. 8)
Design example:
OVERVOLTAGE PROTECTION / BROWN−OUT
NCP1379 combine brown−out and overvoltage detection
on the pin Fault.
HV−BULK VCC
+
noi s e de l a y
S
−
Dz
S
VOVP
Rbou
Q
Q
7
Q
La tc h
Q
OVP/BO
DRV
R
VDD
R
IBO
Rbol
noi s e de l a y
grand
reset
−
+
Vclamp
VBO
Clamp
Rc l a mp
CS c omp
BO reset
Figure 36. Brown−out and Overvoltage Protection
In order to protect the power supply against low input
voltage condition, the pin 7 permanently monitors a fraction
of the bulk voltage through a voltage divider. When this
image of bulk voltage is below the VBO threshold, the
controller stops switching. When the bulk voltage comes
back within safe limits, the circuit restarts pulsing. The
hysteresis for the brown−out function is implemented with
a high side current source sinking 10 mA when the
brown−out comparator is high (Vbulk > Vbulk(on))
In order to avoid having a too high voltage on pin 7 if the
bulk voltage is high, an internal clamp limits the voltage.
In case of over voltage, the zener diode will start to
conduct and inject current inside the internal clamp resistor
Rclamp thus causing pin 7 voltage to increase. When this
voltage reaches VOVP, the controller latches−off and stays
latched. The controller will be reset if VCC falls bellow
VCC(reset) or if a brown−out occurs (Figure 37).
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NCP1379
Figure 37. Operating Chronograms in Case of Overvoltage with NCP1379 Supplied by an Auxiliary Power Supply
The following equations show how to calculate the
brown−out resistors.
First of all, select the bulk voltage value at which the
controller must start switching (Vbulk(on)) and the bulk
voltage for shutdown (Vbulk(off)). Then use the following
equation to calculate Rbou and Rbol.
R bol +
V BOǒV bulk(on) * V bulk(off)Ǔ
R bou +
I BOǒV bulk(on) * V BOǓ
R bolǒV bulk(on) * V BOǓ
(eq. 9)
(eq. 10)
V BO
DESIGN EXAMPLE
VBO = 0.8 V
IBO = 10 mA
R bou +
We select: Vbulk(on) = 120 V, Vbulk(off) = 60 V
R bol +
+
V BOǒV bulk(on) * V bulk(off)Ǔ
I BOǒV bulk(on) * V BOǓ
0.8(120 * 60)
10x10 −6(120 * 0.8)
+
R bolǒV bulk(on) * V BOǓ
V BO
40.3x10 3(120 * 0.8)
0.8
(eq. 12)
+ 6 MW
(eq. 11)
+ 40.3 kW
ORDERING INFORMATION
Device
NCP1379DR2G
Package Type
Shipping†
SOIC−8
(Pb free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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21
NCP1379
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The products described herein (NCP1379), may be covered by one or more of the following U.S. patents; 6,362,067 and 5,073,850. There may be other
patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative
NCP1379/D