Datasheet
Serial EEPROM Series Standard EEPROM
WLCSP EEPROM
BU9889GUL-W
(8Kbit)
●General Description
BU9889GUL-W is a serial EEPROM of I2C BUS interface method.
●Features
■ Completely conforming to the world standard I2C BUS.
All controls available by 2 ports of serial clock (SCL) and serial data
(SDA)
■ 1k words×8 bits architecture 8kbit serial EEPROM.
■ Other devices than EEPROM can be connected to the same port,
saving microcontroller port.
■ 1.7V to 5.5V single power source action most suitable for battery use.
■ FAST MODE 400kHz at 1.7V to 5.5V
■ Page write mode useful for initial value write at factory shipment.
■ Auto erase and auto end function at data rewrite.
■ Low current consumption
¾ At write operation (5V)
: 0.5mA (Typ.)
¾ At read operation (5V)
: 0.2mA (Typ.)
¾ At standby operation (5V) : 0.1µA (Typ.)
■ Write mistake prevention function
¾ Write (write protect) function added
¾ Write mistake prevention function at low voltage
■ Data rewrite up to 100,000 times
■ Data kept for 40 years
■ Noise filter built in SCL / SDA terminal
■ Shipment data all address FFh
●Absolute Maximum Ratings (Ta=25℃)
Parameter
symbol
Limits
Unit
Impressed voltage
VCC
-0.3 to +6.5
V
Permissible dissipation
Pd
220
mW
Storage temperature range
Tstg
-65 to +125
℃
Action temperature range
Topr
-40 to +85
℃
-
-0.3 to VCC+1.0
V
Terminal voltage
●Memory cell characteristics (Ta=25℃, Vcc=1.7V to 5.5V)
Limits
Parameter
Min.
Typ.
Number of data rewrite times *1
Data hold years *1
●Package W(Typ.) x D(Typ.) x H(Max.)
VCSP50L1 1.60mm x 1.00mm x 0.55mm
Max.
Remarks
When using at Ta=25℃ or higher, 2.2mW to be reduced per 1℃
Unit
100,000
-
-
Times
40
-
-
Years
Shipment data all address FFh
*1 Not 100% TESTED
●Recommended Operating Ratings
Parameter
Symbol
Limits
Power source voltage
VCC
1.7 to 5.5
Input voltage
VIN
0 to VCC
○Product structure：Silicon monolithic integrated circuit
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TSZ22111・14・001
Unit
V
○This product is not designed protection against radioactive rays
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Datasheet
BU9889GUL-W (8Kbit)
●Electrical Characteristics
Parameter
(Unless otherwise specified Ta=-40℃ to +85℃, Vcc=1.7V to 5.5V)
Limits
Symbol
Unit
Min
Typ.
Max.
Condition
"H" Input Voltage1
VIH1
0.7VCC
-
VCC+1.0
V
"L" Input Voltage1
VIL1
-0.3
-
0.3VCC
V
"L" Output Voltage1
VOL1
-
-
0.4
V
IOL=3.0mA , 2.5V≦VCC≦5.5V (SDA)
"L" Output Voltage2
VOL2
-
-
0.2
V
IOL=0.7mA , 1.7V≦VCC≦2.5V (SDA)
Input Leakage Current
ILI
-1
-
1
μA
VIN=0 to VCC
Output Leakage Current
ILO
-1
-
1
μA
VOUT=0 to VCC (SDA)
ICC1
-
-
2.0
mA
ICC2
-
-
0.5
mA
ISB
-
-
2.0
μA
VCC=5.5V, fSCL =400kHz, tWR=5ms
Byte Write, Page Write
VCC=5.5V, fSCL =400kHz
Random read, Current read, Sequential read
Current consumption at action
Standby Current
VCC=5.5V, SDA・SCL=VCC
A2=GND, WP=GND
●Action timing characteristics
(Unless otherwise specified Ta=-40℃ to +85℃, Vcc=1.7V to 5.5V)
Limits
Parameter
Symbol
Min.
Typ.
Max.
Unit
SCL Frequency
fSCL
-
-
400
kHz
Data clock "High" time
tHIGH
0.6
-
-
μs
tLOW
1.2
-
-
μs
tR
-
-
0.3
μs
Data clock "Low" time
SDA, SCL rise time
*1
tF
-
-
0.3
μs
Start condition hold time
tHD:STA
0.6
-
-
μs
Start condition setup time
tSU:STA
0.6
-
-
μs
Input data hold time
tHD:DAT
0
-
-
ns
Input data setup time
tSU:DAT
100
-
-
ns
Output data delay time
tPD
0.1
-
0.9
μs
Output data hold time
tDH
0.1
-
-
μs
tSU:STO
0.6
-
-
μs
Bus release time before transfer start
tBUF
1.2
-
-
μs
Internal write cycle time
tWR
-
-
5
ms
SDA, SCL fall time
*1
Stop condition data setup time
tI
-
-
0.1
μs
WP hold time
tHD:WP
0
-
-
ns
WP setup time
tSU:WP
0.1
-
-
μs
WP valid time
tHIGH:WP
1.0
-
-
μs
Noise removal valid period (SDA,SCL terminal)
*1 : Not 100% TESTED
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Datasheet
BU9889GUL-W (8Kbit)
●Sync Data Input / Output Timing
tR
tF
tHIGH
SCL
SCL
tSU:DAT
tHD:STA
tLOW
DATA(1)
tHD:DAT
D1
SDA
SDA
DATA(n)
D0
ACK
ACK
(Input)
(入力)
ｔWR
tPD
tBUF
tDH
Stop
condition
ストップコンディション
WP
SDA
(Output)
(出力)
ｔHD：WP
tSU：WP
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
Figure 1-(d) WP timing at write execution
Figure 1-(a) Sync data input / output timing
SCL
SCL
tSU:STA
tHD:STA
DATA(n)
DATA(1)
tSU:STO
SDA
SDA
D1
D0
ACK
ACK
tHIGH:WP
START BIT
STOP BIT
tWR
WP
○At write execution, in the area from the D0 taken clock rise of the first DATA(1),
to tWR, set WP= 'LOW'.
○By setting WP "HIGH" in the area, write can be cancelled.
When it is set WP = 'HIGH' during tWR, write is forcibly ended, and data of address under
access is not guaranteed, therefore write it once again.
Figure 1-(b) Start - stop bit timing
Figure 1-(e) WP timing at write cancel
SCL
SDA
D0
ACK
WRITE DATA(n)
tWR
STOP
CONDITION
START
CONDITION
Figure 1-(c) Write cycle timing
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Datasheet
BU9889GUL-W (8Kbit)
●Block Diagram
Vcc
8Kｂｉｔ ＥＥＰＲＯＭ ARRAY
GND
8bit
10bit
ADDRESS
DECODER
SLAVE、WORD
10bit
DATA
ADDRESS REGISTER
START
REGISTER
STOP
SCL
CONTROL LOGIC
A2
WP
ACK
SDA
Vcc LEVEL DETECT
HIGH VOLTAGE GEN.
●Pin Configuration
(BOTTOM VIEW)
B
A
○ ○ ○
○ ○ ○
B1
B2
B3
SDA
GND
A2
A2
A3
SCL
WP
VCC
1
2
3
A1
●Pin Descriptions
Terminal name
Input/ Output
A2
Input
GND
-
SDA
Input / Output
SCL
Input
Serial clock input
WP
Input
Write protect terminal
Vcc
-
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Function
Slave address setting
Reference voltage of all input / output, 0V.
Slave and word address,
Serial data input serial data output
Connect the power source.
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Datasheet
BU9889GUL-W (8Kbit)
●Typical Performance Curves
(The following values are Typ. ones.)
Figure 2. ‘H’ input voltage VIH
(A2, SCL, SDA, WP)
Figure 3. ‘L’ input voltage VIL
(A2, SCL, SDA, WP)
Figure 5. ‘L’ output voltage VOL-IOL
(Vcc=2.5V)
Figure 4. ‘L’ output voltage VOL-IOL
(Vcc=1.7V)
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Datasheet
BU9889GUL-W (8Kbit)
●Typical Performance Curves‐Continued
Figure 6. Input leak current ILI
(A2, SCL, WP)
Figure 7. Output leak current IL0(SDA)
Figure 9. Current consumption at READ operation ICC2
(fscl=400kHz)
Figure 8. Current consumption at WRITE operation ICC1
(fscl=400kHz)
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Datasheet
BU9889GUL-W (8Kbit)
●Typical Performance Curves‐Continued
Figure 10. Standby operation ISB
Figure 11. SCL frequency fSCL
Figure 13. Data clock Low Period tLOW
Figure 12. Data clock High Period tHIGH
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Datasheet
BU9889GUL-W (8Kbit)
●Typical Performance Curves‐Continued
Figure 15. Start Condition Setup Time tSU:STA
tHD:DAT(ns)
Figure 14. Start Condition Hold Time tHD:STA
Figure 16. Input Data Hold Time
tHD:DAT(HIGH)
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Figure 17. Input Data Hold Time
tHD:DAT(LOW)
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Datasheet
BU9889GUL-W (8Kbit)
●Typical Performance Curves‐Continued
Figure 18. Input Data Setup Time
TSU:DAT(HIGH)
Figure 19. Input Data Setup Time
TSU:DAT(LOW)
Figure 21. ‘H’ Data output delay time tPD1
Figure 20. ‘L’ Data output delay time tPD0
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Datasheet
BU9889GUL-W (8Kbit)
●Typical Performance Curves‐Continued
Figure 23. Internal writing cycle time tWR
EFFECTIVE
EFFECTIVE
Figure 22. BUS open time before transmission tBUF
Figure 24. Noise reduction effective time t1 (SCL H)
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Figure 25. Noise reduction effective time tI(SCL L)
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Datasheet
BU9889GUL-W (8Kbit)
SDA
●Typical Performance Curves‐Continued
Figure 26. Noise reduction effective time tI (SDAH)
Figure 27. Noise reduction effective time tI(SDA L)
Figure 28. WP setup time tSU:WP
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Figure 29. WP effective time tHIGH:WP
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Datasheet
BU9889GUL-W (8Kbit)
●I2C BUS communication
2
○I C BUS data communication
2
I C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
and acknowledge is always required after each byte.
I2C BUS carries out data transmission with plural devices connected by 2 communication lines of serial data (SDA) and
serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by addresses peculiar to devices.
EEPROM becomes “slave”. And the device that outputs data to bus during data communication is called “transmitter”,
and the device that receives data is called “receiver”.
SDA
1-7
SCL
S
START ADDRESS
condition
8
9
R/W
ACK
1-7
DATA
8
1-7
9
ACK
DATA
Figure 30. Data transfer timing
8
9
ACK
P
STOP
condition
○Start condition (start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this condition is
satisfied, any command is executed.
○Stop condition (stop bit recognition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In master
and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data output of
read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal) (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and recognizes
stop condition (stop bit), and ends read action. And this IC gets in standby status.
○Device addressing
・Following a START condition, the master output the slave address to be accessed.
・The most significant four bits of the slave address are the “device type indentifier,” for this device it is fixed as “1010”.
・The next bit (device address) identify the specified device on the bus. The device address is defined by the state of A2
input pin. This IC works only when the device address inputted from SDA pin correspond to the state of A2 input pin.
Using this address scheme, up to two devices may be connected to the bus.
・The next two bits (P1, P0) are used by the master to select four 256 word page of memory.
P1, P0 set to “0” “0” ･･･ 1page (000 to 0FF)
P1, P0 set to “0” “1” ･･･ 1page (100 to 1FF)
P1, P0 set to “1” “0” ･･･ 1page (200 to 2FF)
P1, P0 set to “1” “1” ･･･ 1page (300 to 3FF)
・The last bit of the stream (R/W … READ/WRITE) determines the operation to be performed. When set to “1”, a read
operation is selected ; when set to “0”, a write operation is selected.
R/W set to “0” ･･･ WRITE (including word address input of Random Read)
R/W set to “1” ･･･ READ
1 0 1
0
A2
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Datasheet
BU9889GUL-W (8Kbit)
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle.
S
T
A
R
T
SDA
LINE
W
R
I
T
E
SLAVE
ADDRESS
WORD
ADDRESS
WA
7
1 0 1 0 A2 P1 P0
S
T
O
P
DATA
WA
0
D7
D0
A
C
K
R A
/ C
W K
A
C
K
Figure 31. Byte write cycle
S
W
T
R
A
I
SLAVE
R
T
WORD
T
ADDRESS
T
S
O
DATA(n)
ADDRESS(n)
E
DATA(n+15)
P
SDA
LINE
1
0 1
0 A2 P1 P0
WA
WA
7
0
D7
D0
D0
R A
A
A
A
/
C
C
C
C
W K
K
K
K
Figure 32. Page write cycle
・Data is written to the address designated by word address (n-th address).
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk: Up to 16 bytes
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment " in Pape14.)
・As for page write command, after page select bit(PS) of slave address is designated arbitrarily, by continuing data input of
2 bytes or more, the address of insignificant 4 bits is incremented internally, and data up to 16 bytes can be written.
○Notes on write cycle continuous input
At STOP (s top bit )
write starts.
S
T
A
R
T
SDA
LINE
SL AVE
ADDRESS
W
R
I
T
E
WORD
ADDRESS（ｎ）
WA
7
1 0 1 0 A2 P1 P0
R A
/ C
W K
DATA(n)
WA
0
D7
A
C
K
S
T
O
P
DATA(n+15)
D0
D0
A
C
K
S
T
A
R
T
1 0 1 0
A
C
K
Next command
tW R(maximum： 5ms)
Command is not accepted for this
period.
Figure 33. Page write cycle
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Datasheet
BU9889GUL-W (8Kbit)
○Notes on page write cycle
Maximum page number is 16 bytes for this IC.
Any bytes below these can be written.
The page write cycle write time is 5ms at maximum for 16byte bulk write.
It does not stand 5ms at maximum × 16byte = 80ms(Max.).
○Internal address increment
Page write mode
WA4
0
0
0
WA3
0
0
0
WA2
0
0
0
---------
0Eh
0
0
0
-------------
0
0
0
1
1
0
1
1
0
WA1
0
0
1
WA0
0
1
0
1
1
0
0
1
0
---------
WA7 ----0
----0
----0
-----
Increment
Significant bit is fixed.
No digit up
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･, which please note.
* 0Eh･･･16 in hexadecimal, therefore, 00001110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all address is prohibited. When it is set GND (L level), data rewrite
of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON/OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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Datasheet
BU9889GUL-W (8Kbit)
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can
be read in succession.
S
T
A
R
T
SD A
LINE
S LA VE
A DDRE SS
W
R
I
T
E
W O RD
ADD RES S(n)
WA
7
1 0 1 0 A2 P1P0
S
T
A
R
T
WA
0
R A
/ C
W K
SLA VE
A DDRE SS
R
E
A
D
DA TA (n)
D7
1 0 1 0 A 2 P1P0
A
C
K
S
T
O
P
It is necessary to input 'H'
to the last ACK.
D0
A
C
K
R A
/ C
W K
Figure 34. Random read cycle
S
T
A
R
T
SDA
LINE
S LAV E
AD DRES S
R
E
A
D
1 0 1 0 A 2P 1P 0
DA TA (n)
D7
It is necessary to input 'H'
to the last ACK.
S
T
O
P
D0
A
C
K
R A
/ C
W K
Figure 35. Current read cycle
S
T
A
R
T
SDA
LINE
SLAVE
ADDRESS
R
E
A
D
1 0 1 0 A2 P1P0
DATA(n)
D7
R A
/ C
W K
S
T
O
P
DATA(n+x)
D0
D7
A
C
K
A
C
K
D0
A
C
K
Figure 36. Sequential read cycle (in the case of current read cycle)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H'.
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
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Datasheet
BU9889GUL-W (8Kbit)
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kids of them are shown in the figure below. (Refer to Figure 37-(a), Figure 37-(b), Figure 37-(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
Start×2
Dummy clock×14
SCL
1
2
13
Normal command
14
SDA
Normal command
Figure 37-(a) The case of 14 Dummy clock + START + START+ command input
SCL
Start
Dummy clock×9
Start
1
2
8
Normal command
9
SDA
Normal command
Figure 37-(b) The case of START+9 Dummy clock + START + command input
Start×9
SCL
1
2
3
8
7
9
Normal command
Normal command
SDA
Figure 37-(c) START × 9 + command input
* Start command from START input.
●Acknowledge polling
During internal write, all input commands are ignored, therefore ACK is not sent back. During internal automatic write
execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then it
means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next command
can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data so forth.
During internal write,
First write command
S
T
A
R
T
Write command
ACK = HIGH is sent back.
S
T
O
P
S
T Slave
A address
R
T
A
C
K
H
tWR
S
T Slave
A
R address
T
A
C
K
H
…
Second write command
…
S
T Slave
A
R address
T
A
C
K
H
tWR
S
T Slave
A
R address
T
A
C
K
L
Word
address
A
C
K
L
Data
A
C
K
L
S
T
O
P
After completion of internal
write, ACK=LOW is sent back,
so input next word address and
data in succession.
Figure 38. Case to continuously write by acknowledge polling
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© 2012 ROHM Co., Ltd. All rights reserved.
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TSZ02201-0R2R0G100490-1-2
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Datasheet
BU9889GUL-W (8Kbit)
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of data
(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken 100ns or more. The area from the rise of
SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again.(Refer to Figure 39.)
After execution of forced end by WP standby status gets in, so there is no need to wait for tWR (5ms at maximum).
・Rise of D0 taken clock
SCL
SCL
・Rise of SDA
SDA
D0
D1
SDA
ACK
ACK
D0
Enlarged view
SDA
S
T Slave
A
R address
T
Enlarged view
A
A
C Word C D7 D6 D5 D4 D3 D2 D1 D0
K address K
L
L
WP cancel invalid area
A
C
K
L
Data
A
C
K
L
S
T
O
P
tWR
Write forced end
WP cancel valid area
WP
Data not guaranteed
Data is not written.
Figure 39. WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Figure 40.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0
1
0
Start condition
Stop condition
Figure 40. Case of cancel by start, stop condition during slave address input
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© 2012 ROHM Co., Ltd. All rights reserved.
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TSZ02201-0R2R0G100490-1-2
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Datasheet
BU9889GUL-W (8Kbit)
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (RPU), select an appropriate value to
this resistance value from microcontroller VIL, IL, and VOL-IOL characteristics of this IC. If RPU is large, action frequency is
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of RPU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by input leak total (IL) of device connected to bus output of 'H' to SDA
(2)The bus electric potential ○
bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended
noise margin 0.2Vcc.
Microcontroller
Vcc - ILRPU - 0.2Vcc ≧ VIH
∴
RPU ≦
BU9889GUL-W
0.8VCC－VIH
IL
RPU
SDA terminal
A
Ex.) When Vcc = 3V, IL=10μA, VIH = 0.7Vcc, from (2)
RPU ≦
IL
0.8×3－0.7×3
-6
10×10
IL
Bus line
Capacity
CBUS
≦ 300 ［kΩ］
Figure 41. I/O circuit diagram
○Minimum value of RPU
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that VOLMAX=0.4V and IOLMAX=3mA.
VCC－VOL
≦ IOL
RPU
∴ RPU ≧
VCC－VOL
IOL
(2)VOLMAX=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise
margin 0.1Vcc.
VOLMAX ≦ VIL-0.1 Vcc
Ex.) When Vcc= 3V, VOL0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3Vcc
from(1),
RPU
≧
3－0.4
3×10 -3
≧ 867 ［Ω］
And
VOL=0.4［V］
VIL=0.3×3
=0.9［V］
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ to several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A2, WP process
○Process of device address terminals (A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or Vcc or GND.
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or Vcc. In the case to use both READ and WRITE, control WP terminal or connect it
to pull down or GND.
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
18/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
Datasheet
BU9889GUL-W (8Kbit)
●Cautions on microcontroller connection
○Rs
In I2C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
ACK
SCL
RPU
RS
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
EEPROM
Over current flows to SDA line by 'H' output of microcontroller
and 'L' output of EEPROM.
Figure 42. I/O circuit diagram
Figure 43. Input/output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA shoulder be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
(2)The bus electric potential ○
should sufficiently secure the input 'L' level (VIL) of microcontroller including recommended noise margin 0.1Vcc.
VCC
RPU
RS
(VCC－VOL)×RS
RPU+RS
A
VOL
∴ RS ≦
IOL
Bus line
capacity CBUS
VIL
VIL－VOL－0.1VCC
1.1VCC－VIL
×
RPU
Example）When VCC=3V, VIL=0.3VCC, VOL=0.4V, RPU=20kΩ,
from(2),
EEPROM
Microcontroller
+ VOL+0.1VCC≦VIL
Figure 44. I/O circuit diagram
RS ≦
0.3×3－0.4－0.1×3
×
1.1×3－0.3×3
20×10
3
≦ 1.67［kΩ］
○Maximum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
VCC
≦
RS
RPU
I
'L' output
RS
∴ RS ≧
Over currentⅠ
VCC
I
Example）When VCC=3V, I=10mA
'H' output
RS
Microcontroller
≧
3
-3
10×10
EEPROM
≧ 300［Ω］
Figure 45. I/O circuit diagram
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
19/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
Datasheet
BU9889GUL-W (8Kbit)
●I2C BUS input / output circuit
○Input (A2, SCL, WP)
Figure 46. Input pin circuit diagram
○Input/Output (SDA)
Figure 47. Input /output pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following condition at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit.
tR
VCC
Recommended conditions of tR, tOFF, Vbot
tR
tOFF
tOFF
Vbot
0
Vbot
10ms or below
10ms or longer
0.3V or below
100ms or below
10ms or longer
0.2V or below
Figure 48. Rise waveform diagram
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above conditions 1 cannot be observed. When SDA becomes 'L' at power on.
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
VCC
tLOW
SCL
SDA
A ft er V cc bec omes st able
Af t er Vcc becom es stab le
tDH
tSU:DAT
tSU:DAT
Figure 50. When SCL='H' and SDA='L'
Figure 49. When SCL='H' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(Page 16).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
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TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
Datasheet
BU9889GUL-W (8Kbit)
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write.
At LVCC voltage (Typ. =1.2V) or below, it prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is recommended
to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
●Cautions on use
(1)Described numeric values and data are design representative values, and the values are not guaranteed.
(2)We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in
consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3)Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI
may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear
exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4)GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5)Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6)Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7)Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference
to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority.
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
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TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
Datasheet
BU9889GUL-W (8Kbit)
●Ordering Information
B
U
9
8
8
9
G
Part Number
U
L
-
W
E2
Package
Packaging and forming specification
E2: Embossed tape and reel
GUL: VCSP50L1(BU9889GUL-W)
●Physical Dimension Tape and Reel Information
1.60±0.05
0.55MAX
1PIN MARK
0.10±0.05
1.00±0.05
VCSP50L1
(BU9889GUL-W)
VCSP50L1
(BU9889GUL-W)
S
6-φ0.25±0.05
0.05 A B
0.25
0.06 S
(φ0.15)INDEX POST
A
0.5
B B
A
1
0.30
2
3
P=0.5×2
(Unit : mm)
<Tape and Reel information>
Tape
Embossed carrier tape (heat sealing method)
Quantity
3000pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
Direction of feed
1pin
Reel
)
∗ Order quantity needs to be multiple of the minimum quantity.
●Marking Diagram
VCSP50L1(BU9889GUL-W)
(TOP VIEW)
1PIN MARK
Part Number Marking
U 8 9
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© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
LOT Number
22/23
TSZ02201-0R2R0G100490-1-2
05.SEP.2012 Rev.001
Datasheet
BU9889GUL-W (8Kbit)
●Revision History
Date
Revision
05.Sep.2012
001
Changes
New Release
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05.SEP.2012 Rev.001
Datasheet
Notice
Precaution on using ROHM Products
1.
Our Products are designed and manufactured for application in ordinary electronic equipments (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
(Note 1)
, transport
intend to use our Products in devices requiring extremely high reliability (such as medical equipment
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅣ
CLASSⅢ
2.
ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3.
Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4.
The Products are not subject to radiation-proof design.
5.
Please verify and confirm characteristics of the final or mounted products in using the Products.
6.
In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7.
De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta). When used in sealed area, confirm the actual
ambient temperature.
8.
Confirm that operation temperature is within the specified range described in the product specification.
9.
ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1.
When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2.
In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
Precautions Regarding Application Examples and External Circuits
1.
If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2.
You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1.
Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2.
Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3.
Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4.
Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
QR code printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since our Products might fall under controlled goods prescribed by the applicable foreign exchange and foreign trade act,
please consult with ROHM representative in case of export.
Precaution Regarding Intellectual Property Rights
1.
All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data. ROHM shall not be in any way responsible or liable
for infringement of any intellectual property rights or other damages arising from use of such information or data.:
2.
No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the information contained in this document.
Other Precaution
1.
This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2.
The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3.
In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4.
The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice - GE
© 2014 ROHM Co., Ltd. All rights reserved.
Rev.002
Datasheet
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall n ot be in an y way responsible or liabl e for fa ilure, malfunction or acci dent arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3.
The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for an y damages, expenses or losses incurred b y you or third parties resulting from inaccur acy or errors of or
concerning such information.
Notice – WE
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Datasheet
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