Features ARM7TDMI® ARM® Thumb® Processor Core Two 16-bit Fixed-point OakDSPCore® Cores 256 x 32-bit Boot ROM 88K Bytes of Integrated Fast RAM for Each DSP Flexible External Bus Interface with Programmable Chip Selects Dual Codec Interface Multi-level Priority, Individually Maskable, Vectored Interrupt Controller Three 16-bit Timers/Counters Additional Watchdog Timer Two USARTs with FIFO and Modem Control Lines Industry -standard Serial Peripheral Interface (SPI) Up to 24 General-purpose I/O Pins On-chip SDRAM Controller for Embedded ARM7TDMI and OakDSPCore JTAG Debug Interface Software Development Tools Available for ARM7TDMI and OakDSPCore Supported by a Wide Range of Ready-to-use Application Software, including Multitasking Operating System, Networking, Modems and Voice Processing Functions • Available in 160-lead PQFP Package • 2.5V Power Supply for the core and the PLL Pins, 3.3V Power Supply for Other I/O Pins • • • • • • • • • • • • • • • • Description The Atmel AT75C320 Smart Internet Appliance Processor (SIAP™) is a high-performance processor specially designed for Internet appliance applications, such as Internet telephony (Voice-over-Internet Protocol – VoIP). The AT75C320 is a derivative version of the AT75C310. The device is built around an ARM7TDMI microcontroller core running at 40 MIPS with two DSP co-processors running at 60 MIPS each – all three processors delivering unmatched performance for low power consumption. Smart Internet Appliance Processor (SIAP™) AT75C320 Preliminary In a typical standalone VoIP phone, one DSP handles the voice processing functions (voice compression, acoustic echo cancellation, etc.), while the other one deals with the telephony functions (dialing, line echo cancellation, callerID detection, high-speed modem, etc.). In such an application, the power of the ARM7TDMI allows it to run the VoIP protocol stack as well as all the system control tasks. Atmel provides the AT75C320 with three levels of software modules: • a special port of the Linux® kernel as the proposed operating system; • a comprehensive set of tunable DSP algorithms for modems and voice processing, specially tailored to be run by the DSP subsystems; • a broad range of application level software modules such as H.323 telephony or POP-3/SMTP e-mail services. Rev. 1769A–07/01 1 AT75C320 Pin Configuration Table 1. AT75C320 Pinout in PQFP160 Package Pin 2 PQFP160 Pin PQFP160 Pin PQFP160 Pin PQFP160 1 NC 41 NC 81 PA12/NPCS1 121 NC 2 NC 42 PB6/NWDOVF 82 VDD2V5 122 NC 3 D10 43 PB5/NRIA 83 GND 123 A16 4 D11 44 PB4 84 A0 124 A17 5 NCE3 45 PB3/NCTSA 85 A1 125 A18 6 D12 46 DBW32 86 A2 126 A19 7 D13 47 GND 87 A3 127 A20 8 SRXB 48 VDD3V3 88 VDD3V3 128 A21 9 NWE0 49 RESET 89 BO208 129 VDD2V5 10 GND 50 IRQ0 90 NWR 130 GND 11 VDD3V3 51 PB2/TIOB1 91 NWAIT 131 VDD3V3 12 D14 52 PB9 92 NREQ 132 D0 13 D15 53 PB1/TIOA1 93 FIQ 133 DQM0 14 NC 54 PB8 94 NGNT 134 D1 15 NWE1 55 PB0/TCLK1 95 SCLKA 135 DQM1 16 NC 56 VDD2V5 96 FSA 136 D2 17 VDD2V5 57 GND 97 STXA 137 D3 18 GND 58 TST 98 SRXA 138 D4 19 VDD2V5 59 NTRST 99 A4 139 RAS 20 XTALIN 60 TCK 100 A5 140 CAS 21 XTALOUT 61 TMS 101 A6 141 CS0 22 GND 62 TDI 102 A7 142 CS1 23 PLL_GND 63 TDO 103 NPCSS 143 DCK 24 XREF240 64 PA0/OakAIN0 104 SPCK 144 WE 25 PLL_VDD2V5 65 PA1/OakAIN1 105 MISO 145 D5 26 GND 66 PA2/OakAOUT0 106 MOSI 146 STXB 27 VDD2V5 67 PA3/OakAOUT1 107 VDD3V3 147 FSB 28 RXDA 68 PA19/ACLK 108 GND 148 SCLKB 29 TXDA 69 PA4/OakBIN0 109 VDD2V5 149 D6 30 NRTSA 70 GND 110 GND 150 D7 31 NCTSA 71 VDD3V3 111 A8 151 GND 32 NDCDB 72 PA5/OakBIN1 112 A9 152 VDD3V3 33 NDTRA 73 PA6/OakBOUT0 113 A10 153 NCE0 34 NDSRA 74 PA7/OakBOUT1 114 A11 154 D8 35 GND 75 PA8/TCLK0 115 A12 155 D9 36 VDD3V3 76 PA9/TIOA0 116 VDD3V3 156 NSOE 37 NDCDA 77 PA10/TIOB0 117 GND 157 GND 38 TXDB 78 PA11/SCKA 118 A13 158 GND 39 RXDB 79 NC 119 A14 159 NC 40 PB7 80 NC 120 A15 160 NC AT75C320 1769A–07/01 AT75C320 AT75C320 Pin Description Table 2. AT75C320 Pin Description Block PQFP Pin Name Type Function A[21:0] O Address Bus D[15:0] I/O Data Bus NREQ I Bus Request NGNT O Bus Grant DCK O SDRAM Clock DQM[1:0] O Memory Data Byte Masks CS0 O SDRAM Chip Select CS1 O SDRAM Chip Select WE O SDRAM Write Enable RAS O Row Address Select CAS O Column Address Select NCE0, NCE3 O Chip Selects NWE[1:0] O Byte Select/Write NSOE O Enable Output NWR O Enable Memory Block Write NWAIT I Enable Enable Wait States Common Bus Synchronous Dynamic Memory Controller Static Memory Controller I/O Port A PA[12:0], PA19 I/O General Purpose I/O Lines. Multiplexed with Peripheral I/Os I/O Port B PB[9:0] I/O General Purpose I/O Lines. Multiplexed with Peripheral I/Os OakAIN[1:0] I OakDSPCore A User Inputs OakAOUT[1:0] O OakDSPCore A User Outputs OakBIN[1:0] I OakDSPCore B User Inputs OakBOUT[1:0] O OakDSPCore B User Outputs TCLK0 I Timer 0 External Clock TIOA0 I/O Timer 0 Signal A TIOB0 I/O Timer 0 Signal B TCLK1 I TIOA1 I/O Timer 1 Signal A TIOB1 I/O Timer 1 Signal B NWDOVF O Watchdog Overflow MISO I/O Master In/Slave Out MOSI I/O Master Out/Slave In SPCK I/O Serial Clock NPCSS I/O Chip Select/Slave Select DSP Subsystem A DSP Subsystem B Timer/Counter 0 Timer/Counter 1 Watchdog Serial Peripheral Interface Timer 1 External Clock 3 1769A–07/01 Table 2. AT75C320 Pin Description (Continued) Block PQFP Pin Name USART A Type Function RXDA I Receive Serial Data TXDA O Transmit Serial Data NRTSA O Request to Send NCTSA I Clear To Send NDTRA O Data Terminal Ready NDSRA I Data Set Ready NDCDA I Data Carrier Detect NRIA I Ring Indicator SCKA I/O RXDB I Receive Serial Data TXDB O Transmit Serial Data NTRST I TAP Reset TCK I TAP Clock TMS I JTAG Test Mode Select TDI I JTAG Test Data Input TDO O JTAG Test Data Output SCLKA I/O Codec Serial Clock FAS I/O Frame Pulse STXA O Transmit Data to Codec SRXA I Receive Data from Codec SCLKB I/O Codec Serial Clock FSB I/O Frame Pulse STXB O Transmit Data to Codec SRXB I Receive Data from Codec RESET I Master Reset FIQ/LOWP I Fast Interrupt/Low Power IRQ0 I External Interrupt request XREF I External 96 MHz PLL Reference XTALIN I External Crystal Input XTALOUT O External Crystal Output TST I Test Mode DBW32 I External Data Width for CS0 BO206 I Package Size Option Serial Clock USART B JTAG Interface Codec Interface A Codec Interface B Miscellaneous 4 AT75C320 1769A–07/01 AT75C320 Block Diagram Figure 1. AT75C320 Block Diagram ASB OakDSPCore A DSP Subsystem Reset Clocks OakDSPCore B DSP Subsystem SDRAM Controller JTAG External Bus Interface Embedded ICE SRAM Controller ARM7TDMI Core Peripheral Data Controller Boot ROM TM AMBA Bridge SPI IRQ Controller USART A PIO A USART B PIO B Timer/Counter 0 Timer/Counter 1 Watchdog Timer Timer/Counter 2 APB 5 1769A–07/01 Figure 2. DSP Subsystem Block Diagram Oak Program Bus Oak Data Bus 2K x 16 X-RAM Codec Interface 2K x 16 Y-RAM 24K x 16 Program RAM 16K x 16 Generalpurpose RAM OakDSPCore On-chip Emulation Module 256 x 16 Dual-port Mailbox Bus Interface Unit DSP Subsystem ASB Application Example Figure 3. Standalone Internet Telephone Keyboard Screen Line Line Interface Data Codec V.34 Modem SDRAM Controller SDRAM DSP Subsystem Speaker Microphone Handset Speaker Phone Interface VolP Protocol Stack Voice Codec SRAM Controller Voice Processing Analog Front-End DSP Subsystem External Bus Interface Flash ARM7TDMI Core AT75C320 6 AT75C320 1769A–07/01 AT75C320 Functional Description ARM7TDMI Core The ARM7TDMI is a three-stage pipeline, 32-bit RISC processor. The processor architecture is Von Neumann load/store architecture which is characterized by a single data and address bus for instructions and data. The CPU has two instruction sets: the ARM and the Thumb instruction set. The ARM instruction set has 32-bit wide instructions and provides maximum performance. Thumb instructions are 16 bits wide and give maximum code density. Instructions operate on 8-, 16- and 32-bit data types. The CPU has seven operating modes. Each operating mode has dedicated banked registers for fast exception handling. The processor has a total of 37 32-bit registers, including six status registers. DSP Subsystem The AT75C320 has two identical DSP subsystems. Each DSP subsystem is composed of: • An OakDSPCore running at 60 MIPS • 2K x 16 of X-RAM • 2K x 16 of Y-RAM • 16K x 16 of general purpose data RAM • 24K x 16 of loadable program RAM • One 256 x 16 dual-port mailbox • One codec interface The DSP subsystem is fully autonomous. The local X- and Y-RAM allow it to reach its maximum processing rate, and a local large data RAM enables complex DSP algorithms to be implemented. The large size of the loadable program RAM permits the use of functions as complex as a V.34 modem or a low bit-rate vocoder. During boot time, the ARM7TDMI core has the ability to maintain the OakDSPCore in reset state and to upload DSP boot code. When the OakDSPCore reverts to an active state, this boot code can be used to get the complete DSP application code from the ARM7TDMI through the mailbox. When the OakDSPCore is running, the dual-port mailbox is used as the communication channel between the ARM7TDMI and the OakDSPCore. One programmable codec interface is directly connected to each OakDSPCore. It allows the connection of most industrial voice, multimedia or data codecs. Boot ROM The ARM7TDMI has the ability to boot either from an external memory or from the onchip 256 x 32-bit boot ROM. Boot Code Operation The internal boot sequence allows programming of the ARM7TDMI program RAM through a serial port. When the download is complete, a branch is executed to the downloaded code. 7 1769A–07/01 EBI: External Bus Interface The EBI generates the signals that control access to external memory or memory-mapped peripherals. The EBI is fully programmable and can address up to 64M bytes. The interface to external devices is composed of common address and data buses and separate control lines to allow the connection of static or dynamic devices. The main features are: AIC: Advanced Interrupt Controller • External memory mapping • Up to four chip select lines • 32- or 16-bit data bus • Byte write or byte select lines • Remap of boot memory • Support for both static and dynamic memories • Two different read protocols for static memories • Support for early read/early write for dynamic memories • Programmable wait state generation • Programmable data float time The AT75C320 has an 8-level priority interrupt controller. The interrupt controller outputs are connected to the NFIQ (fast interrupt request) and the NIRQ (normal interrupt request) of the ARM7TDMI core. The processor’s NFIQ can only be asserted by the external fast interrupt request input (FIQ). The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals or by the external interrupt request line IRQ0. An 8-level priority encoder allows the application to define the priority between the different interrupt sources. Interrupt sources are programmed to be level sensitive or edge sensitive. External sources can be programmed to be positive- or negative-edge triggered, or low- or high-level sensitive. PIO: Parallel I/O Controller The AT75C320 has 24 programmable I/O lines. They can all be programmed as inputs or outputs. To optimize the use of available package pins, most of them are multiplexed with external signals of on-chip peripherals. The PIO lines are controlled by two separate and identical PIO controllers called PIOA and PIOB. The PIO controllers enable the generation of an interrupt on input change and insertion of a simple glitch filter on each PIO line. Some I/O lines have enough drive capability to power a LED. 8 AT75C320 1769A–07/01 AT75C320 USART: Universal Synchronous/ Asynchronous Receiver/ Transmitter The AT75C320 provides two identical full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the peripheral data controller. The main features are: • Programmable baud rate generator • Parity, framing and overrun error detection • Line break generation and detection • Automatic echo, local loopback and remote loopback • Multi-drop mode: address detection and generation • Interrupt generation • Dedicated peripheral data controller channels • 6-, 7-, 8- and 9-bit character length • In addition to the Tx and Rx signals, the USART A provides several modem control lines. SPI: Serial Peripheral Interface The AT75C320 includes an SPI that provides communication with external devices in master or slave mode. Timer/Counter The AT75C320 features three identical 16-bit timer/counters. They can be independently programmed to perform a wide range of functions, including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. The SPI has one external chip select that can be connected to two devices. The data length is programmable from 8- to 16-bit. The triple timer/counter block has three external clock inputs, five internal clock inputs and two multi-purpose signals that can be configured by the user. Each timer drives an internal interrupt signal that can be programmed to generate processor interrupts via the advanced interrupt controller. Watchdog Timer The AT75C320 has an internal watchdog timer that can be used to prevent system lock-up if the software becomes trapped in a deadlock. Special Functions The AT75C320 provides registers that implement the following special functions: Application Software • Chip identification • Reset status The AT75C320 is supported by a comprehensive range of software modules. As a result of the widespread use of the ARM7TDMI and the OakDSPCore, a wide range is available, either directly from Atmel or from third parties. The application software modules are in three categories: OS level, DSP level and application level. OS Level The AT75C320 is supplied with a customized port of the Linux kernel. It features device drivers for all the on-chip peripherals, including the DSP subsystems, and supports virtual file system usage. It also supports the native TCP/IP facilities that have made Linux a success in Internet applications. This kernel is available in source code under the terms of the Gnu Public License. Many other operating systems exist for the ARM7TDMI core. 9 1769A–07/01 DSP Level A wide range of DSP functions are available for the OakDSPCore. Among others, Atmel supplies modules for a V.34 modem, G723.1 and G729A voice codecs, silence compression and echo cancellation. Application Level A rich software toolkit is available with support for popular communication protocols (H.323, POP-3/SMTP, etc.), connection processes, multimedia applications, full-feature telephony and audio software suites. 10 AT75C320 1769A–07/01 AT75C320 Development Tools Both the ARM7TDMI and the OakDSPCore are industry-standard cores. They are supported by a comprehensive range of state-of-the-art development tools, including assemblers, C-compilers, source level debuggers and hardware emulators. Packaging The AT75C320 is supplied in a 160-lead PQFP package. This provides the best compromise between external connectivity and cost. Figure 4. PQFP Package Drawing For package data, see Table 3, Table 4 and Table 5 below. 11 1769A–07/01 Package Data Table 3. Common Dimensions (mm) Symbol Min Nom Max c 0.11 0.23 c1 0.11 0.17 L 0.65 0.88 L1 1.03 1.95 REF R2 0.13 R1 0.13 S 0.4 0.3 Tolerances of Form and Position aaa 0.25 bbb 0.20 ccc 0.10 Table 4. Dimensions Specific to 160-lead Package (mm) A A1 A2 b b1 Max Min Min Nom Max Min Max Min Nom 4.07 0.25 3.17 3.42 3.67 0.22 0.38 0.22 0.3 D D1 E E1 E ddd Max BSC BSC BSC BSC BSC BSC 0.33 31.90 28.00 31.90 28.00 0.65 0.12 Table 5. 160-lead PQFP Package Electrical Characteristics R (mΩ) Cs (pF) Cm (pF) Ls (nH) Lm (nH) Body Size Min Max Min Max Min Max Min Max Min Max 28 x 28 42 64 1.2 1.6 0.5 0.7 5.6 8.6 3.5 5.7 12 AT75C320 1769A–07/01 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 1150 E. Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL ® is the registered trademark of Atmel Corporation; SIAP is the trademark of Atmel Corporation. ARM ®, ARM7TDMI and Thumb ® are trademarks of ARM, Ltd.; OakDSPCore ® is the trademark of DSP Group, Inc.; Linux ® is the trademark of Linus Torvalds. Other terms and product names may be the trademark of others. Printed on recycled paper. 1769A–07/01