CY7C199C 32K x 8 Static RAM General Description1 Features • Fast access time: 12 ns, 15 ns, 20 ns, and 25 ns • Wide voltage range: 5.0V ± 10% (4.5V to 5.5V) • CMOS for optimum speed/power • TTL–compatible Inputs and Outputs • Available in 28 DIP, 28 SOJ, and 28 TSOP I. • 2.0V Data Retention The CY7C199C is a high–performance CMOS Asynchronous SRAM organized as 32K by 8 bits that supports an asynchronous memory interface. The device features an automatic power–down feature that significantly reduces power consumption when deselected. See the Truth Table in this datasheet for a complete description of read and write modes. The CY7C199C is available in 28 DIP, 28 SOJ, and 28 TSOP I package(s). • Low CMOS standby power • Automated Power–down when deselected Logic Block Diagram RAM Array Sense Amps Row Decoder Input Buffer I/Ox CE Column Decoder WE Power Down Circuit OE A X X Product Portfolio Maximum Access Time 12 ns 15 ns 20 ns 25 ns Unit 12 15 20 25 ns Maximum Operating Current 85 80 75 75 mA Maximum CMOS Standby Current (low power) 500 500 500 500 uA Notes: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05408 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 11, 2003 CY7C199C Pin Layout and Specifications 28 DIP (6.9 x 35.6 x 3.5 mm) – P21 OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11 Document #: 38-05408 Rev. *A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A5 1 28 A6 2 27 VCC WE A7 3 26 A4 A8 4 25 A3 A9 5 24 A2 A10 6 23 A1 A11 7 22 OE A12 8 21 A0 A13 9 20 CE A14 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 VSS 14 15 I/O3 28 TSOP I (8 x 13.4 x 1.2 mm) – Z28 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A14 A13 A12 Page 2 of 12 CY7C199C Pin Layout and Specifications (continued) 28 SOJ (8 x 18 x 3.5 mm) – V21 A5 1 28 A6 2 27 VCC WE A7 3 26 A4 A8 4 25 A3 A9 5 24 A2 A10 6 23 A1 A11 7 22 OE A12 8 21 A0 A13 9 20 CE A14 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 VSS 14 15 I/O3 Pin Description Pin Type Description DIP SOJ TSOP I 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 21, 23, 24, 25, 26 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 28 20 20 27 11, 12, 13, 15, 16, 17, 18, 19 11, 12, 13, 15, 16, 17, 18, 19 18, 19, 20, 22, 23, 24, 25, 26 Output Enable. 22 22 1 Power (5.0V). 28 28 7 Supply Ground. 14 14 21 Control Write Enable. 27 27 6 AX Input Address Inputs. CE Control Chip Enable. I/OX Input or Output Data Input/Outputs. OE Control VCC Supply VSS WE Truth Table CE OE WE I/Ox Mode Power H X X High Z Deselect / Power-Down Standby (ISB) L L H Data Out Read Active (ICC ) L X L Data In Write Active (ICC ) L H H High Z Selected, outputs disabled Active (ICC ) Document #: 38-05408 Rev. *A Page 3 of 12 CY7C199C Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Parameter Description Value Unit TSTG Storage Temperature –65 to +150 °C TAMB Ambient Temperature with Power Applied (i.e. case temperature) –55 to +125 °C VCC Core Supply Voltage Relative to VSS –0.5 to +7.0 V VIN, VOUT DC Voltage Applied to any Pin Relative to VSS –0.5 to VCC + 0.5 IOUT Output Short–Circuit Current 20 VESD Static Discharge Voltage (per MIL–STD–883, Method 3015) > 2001 V ILU Latch–up Current > 200 mA V mA Operating Range Range Ambient Temperature (TA) Voltage Range (VCC) 0°C to 70°C 5.0V ± 10% –40°C to 85°C 5.0V ± 10% Commercial Industrial DC Electrical Characteristics Over the Operating Range (–12, –15)2 12 ns Parameter Power Min. Max. Min. Max. Unit VIH Input HIGH Voltage – 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input LOW Voltage – –0.5 0.8 –0.5 0.8 V VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA – 2.4 – 2.4 – V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA – – 0.4 – 0.4 V ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = FMAX = 1/tRC – – 85 – 80 mA ISB1 Automatic CE Power–down Current TTL Inputs Max. VCC, CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = FMAX – – 30 – 30 mA L – 10 – 10 mA Automatic CE Power–down Current CMOS Inputs Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 – – 10 – 10 mA L – 500 – 500 uA IOZ Output Leakage Current GND ≤ Vi ≤ VCC, Output Disabled – –5 +5 –5 +5 uA IIX Input Load Current GND ≤ Vi ≤ VCC – –5 +5 –5 +5 uA ISB2 Description Condition 15 ns DC Electrical Characteristics Over the Operating Range (–20, –25)3 20 ns Parameter Description Condition 25 ns Power Min Max Min Max Unit VIH Input HIGH Voltage – 2.2 VCC + 0.3 2.2 VCC + 0.3 V VIL Input LOW Voltage – –0.5 0.8 –0.5 0.8 V VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA – 2.4 – 2.4 – V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA – – 0.4 – 0.4 V Notes: 2. VIL (min) = –2.0V for pulse durations of less than 20 ns. 3.VIL (min) = –2.0V for pulse durations of less than 20 ns. Document #: 38-05408 Rev. *A Page 4 of 12 CY7C199C 20 ns Parameter Description 25 ns Condition Power Min Max Min Max Unit ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = FMAX = 1/tRC – – 75 – 75 mA ISB1 Automatic CE Power–down Current TTL Inputs Max. VCC, CE ≥ VIH, VIN ≥ VIH or VIN ≤ VIL, f = FMAX – – 30 – 30 mA L – 10 – 10 mA Automatic CE Power–down Current CMOS Inputs Max. VCC, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V, or VIN ≤ 0.3V, f = 0 – – 10 – 10 mA L – 500 – 500 uA IOZ Output Leakage Current GND ≤ Vi ≤ VCC, Output Disabled – –5 +5 –5 +5 uA IIX Input Load Current GND ≤ Vi ≤ VCC – –5 +5 –5 +5 uA ISB2 Capacitance4 Max Parameter Description CIN Input Capacitance COUT Output Capacitance Conditions ALL – PACKAGES Unit TA = 25C, f = 1 MHz, VCC = 5.0V 8 pF 8 AC Test Loads Output Loads Output Loads for tHZOE, tHZCE & tHZWE R1 R3 VCC VCC Output C1 R2 C2 (A)* (B)* All Input Pulses Thevenin Equivalent Output Rth R4 VCC 90% 90% VT VSS 10% 10% Rise Time 1 V/ns Fall Time 1 V/ns * including scope and jig capacitance Notes: 4. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05408 Rev. *A Page 5 of 12 CY7C199C AC Test Conditions Parameter Description Nom. Unit 30 pF C1 Capacitor 1 C2 Capacitor 2 5 R1 Resistor 1 480 R2 Resistor 2 255 R3 Resistor 3 480 R4 Resistor 4 255 RTH Resistor Thevenin 167 VTH Voltage Thevenin 1.73 Ω V Thermal Resistance5 Parameter Description Conditions TSOP I SOJ DIP Unit ΘJA Thermal Resistance (Junction to Ambient) 88.6 79 TBD °C/W ΘJC Thermal Resistance (Junction to Case) Still Air, soldered on a 3 × 4.5 square inch, two–layer printed circuit board 21.94 41.42 TBD AC Electrical Characteristics6 7 8 12 ns Parameter Description 15 ns 20 ns 25 ns Min Max Min Max Min Max Min Max Unit tRC Read Cycle Time 12 – 15 – 20 – 25 – ns tAA Address to Data Valid – 12 – 15 – 20 – 25 ns tOHA Data Hold from Address Change 3 – 3 – 3 – 3 – ns tACE CE to Data Valid – 12 – 15 – 20 – 25 ns tDOE OE to Data Valid – 5 – 7 – 9 – 9 ns tLZOE OE to Low Z 0 – 0 – 0 – 0 – ns tHZOE OE to High Z – 5 – 7 – 9 – 9 ns tLZCE CE to Low Z 3 – 3 – 3 – 3 – ns tHZCE CE to High Z – 5 – 7 – 9 – 9 ns tPU CE to Power–Up 0 – 0 – 0 – 0 – ns tPD CE to Power–Down – 12 – 15 – 20 – 20 ns tWC Write Cycle Time 12 – 15 – 20 – 25 – ns tSCE CE to Write End 9 – 10 – 15 – 15 – ns tAW Address Set–Up to Write End 9 – 10 – 15 – 15 – ns tHA Address Hold from Write End 0 – 0 – 0 – 0 – ns Notes: 5. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage. Document #: 38-05408 Rev. *A Page 6 of 12 CY7C199C 12 ns Parameter Description 15 ns 20 ns 25 ns Min Max Min Max Min Max Min Max Unit tSA Address Set–Up to Write Start 0 – 0 – 0 – 0 – ns tPWE WE Pulse Width 8 – 9 – 15 – 15 – ns tSD Data Set–Up to Write End 8 – 9 – 10 – 10 – ns tHD Data Hold from Write End 0 – 0 – 0 – 0 – ns tHZWE WE LOW to High Z – 7 – 7 – 10 – 10 ns tLZWE WE HIGH to Low Z 3 – 3 – 3 – 3 – ns Data Retention Characteristics9 ALL Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Condition VCC = VDR=2.0V, CE ≥ VCC – 0.3V, VIN ≥ VCC – 0.3V or VIN ≤ 0.3V Min Max Unit 2.0 – V – 150 uA 0 – ns 200 – us Timing Waveforms Data Retention Waveform VCC DATA RETENTION MODE tCDR tR CE Read Cycle No. 1 10 11 tRC Address tAA tOHA Data Out Previous Data Valid Data Valid Notes: 9. L–version only. 10. Device is continuously selected. OE = VIL = CE. 11. WE is HIGH for Read Cycle. Document #: 38-05408 Rev. *A Page 7 of 12 CY7C199C Read Cycle No. 2 12 13 tRC Address CE tHZCE tACE OE tDOE tHZOE tLZOE High Z High Z Data Out VCC Current Data Valid tLZCE tPU ICC tPD 50% ISB 50% Write Cycle No. 1 (WE Controlled)14 15 16 tWC Address tSCE CE tAW tSA tHA tPWE WE OE tHD tHZOE Data In/Out Undefined see footnotes tSD Data-In Valid Notes: 12. This cycle is OE Controlled and WE is HIGH read cycle. 13. Address valid prior to or coincident with CE transition LOW. 14. This cycle is WE controlled, OE is HIGH during write. 15. Data In/Out is high impedance if OE = VIH. 16. During this period the I/Os are in output state and input signals should not be applied. Document #: 38-05408 Rev. *A Page 8 of 12 CY7C199C Write Cycle No. 2 (CE Controlled)17 18 19 tWC Address tSCE CE tSA tHA tAW WE tSD Data In/Out High Z tHD High Z Data-In Valid Write Cycle No. 3 (WE Controlled, OE Low)20 t WC Address tSCE CE tAW tHA tPWE tSA WE tSD Data In/Out Undefined tHD Undefined See Footnotes Data-In Valid see footnotes tHZWE tLZWE Notes: 17. This cycle is CE controlled. 18. Data In/Out is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high–impedance state. 20. The cycle is WE controlled, OE low. The minimum write cycle time is the sum of tHZWE and tSD. Document #: 38-05408 Rev. *A Page 9 of 12 CY7C199C Ordering Information Speed Ordering Code Package Name Package Type Power Option Operating Range 12 ns CY7C199C–12VC V21 28 SOJ (8 x 18 x 3.5 mm) Standard Commercial 12 ns CY7C199C–12ZC Z28 28 TSOP I (8 x 13.4 x 1.2 mm) Standard Commercial 12 ns CY7C199C–12VI V21 28 SOJ (8 x 18 x 3.5 mm) Standard Industrial 15 ns CY7C199C–15PC P21 28 DIP (6.9 x 35.6 x 3.5 mm) Standard Commercial 15 ns CY7C199C–15VC V21 28 SOJ (8 x 18 x 3.5 mm) Standard Commercial 15 ns CY7C199C–15ZC Z28 28 TSOP I (8 x 13.4 x 1.2 mm) Standard Commercial 15 ns CY7C199C–15VI V21 28 SOJ (8 x 18 x 3.5 mm) Standard Industrial 15 ns CY7C199CL–15VC V21 28 SOJ (8 x 18 x 3.5 mm) Low Power Commercial 15 ns CY7C199CL–15ZC Z28 28 TSOP I (8 x 13.4 x 1.2 mm) Low Power Commercial 15 ns CY7C199CL–15VI V21 28 SOJ (8 x 18 x 3.5 mm) Low Power Industrial 20 ns CY7C199C–20VC V21 28 SOJ (8 x 18 x 3.5 mm) Standard Commercial 20 ns CY7C199C–20ZI Z28 28 TSOP I (8 x 13.4 x 1.2 mm) Standard Industrial 25 ns CY7C199C–25PC P21 28 DIP (6.9 x 35.6 x 3.5 mm) Standard Commercial Package Diagram 28 TSOP I (8 × 13.4 × 1.2 mm) – Z28 51-85071-*G Document #: 38-05408 Rev. *A Page 10 of 12 CY7C199C Package Diagram (continued) 28 SOJ (8 × 18 × 3.5 mm) – V21 51-85031-*B 28ÐLead(300ÐMil)Molded DIP P21 51Ð85014Ð*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05408 Rev. *A Page 11 of 12 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C199C Document History Page Document Title: CY7C199C 32K x 8 Static RAM Document Number: 38-05408 REV. ECN No. Issue Date Orig. of Change ** 129233 09/11/03 HGK New Data Sheet *A 129697 09/15/03 KKV Minor change: Move Product Portfolio from page 4 to page 1 Move Truthtable from page 9 to page 3 Document #: 38-05408 Rev. *A Description of Change Page 12 of 12