HD404339 Series Rev. 7.0 Sept. 1999 Description The HD404339 Series is 4-bit HMCS400-Series microcomputer with large-capacity memory designed to increase program productivity. Each microcomputer has an A/D converter, input capture timer, and a 32kHz oscillator circuit for clock use all built in. They also come with high-voltage I/O pins that can directly drive a fluorescent display. The HD404339 Series includes six chips: the HD404339 with 16-kword ROM; the HD4043312 with 12kword ROM; the HD404338 with 8-kword ROM; the HD404336 with 6-kword ROM; the HD404334 with 4-kword ROM; the HD4074339 with 16-kword PROM. The HD4074339 is a PROM version ZTAT microcomputer. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd. Features • 54 I/O pins One input-only pin 53 input/output pins: 30 pins are high-voltage pins (40 V, max.) • On-chip A/D converter (8-bit × 12-channel) • Three timers One event counter input One timer output One input capture timer • 8-bit clock-synchronous serial interface (1 channel) • Alarm output • Built-in oscillators Ceramic or crystal oscillator External clock drive is also possible Subclock: 32.768-kHz crystal oscillator HD404339 Series • Seven interrupt sources Two by external sources Three by timers One each by the A/D converter and serial interface • Four low-power dissipation modes Standby mode Stop mode Watch mode Subactive mode • Instruction cycle time: 1 µs (fOSC = 4 MHz, 1/4 division ratio) 1/4, 1/8, 1/16, 1/32 system clock division ratio can be selected Ordering Information Type Product Name Model Name ROM (words) RAM (digit) Package Mask ROM HD404334 HD404334S 4,096 512 DP-64S HD404334FS HD404336 HD404336S FP-64B 6,144 HD404336FS HD404338 HD404338S FP-64B 8,912 HD404338FS HD4043312 HD4043312S HD404339S 12,288 HD4074339 HD4074339S DP-64S FP-64B 16,384 HD404339FS ZTAT DP-64S FP-64B HD4043312FS HD404339 DP-64S DP-64S FP-64B 16,384 HD4074339FS DP64S FP-64B Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacture Model Name Package Manufacture Model Name DATA I/O corp 121 B DP-64S Hitachi HS4339ESS01H FP-64B AVAL corp PKW-1000 DP-64S FP-64B 2 HS4339ESF01H Hitachi HS4339ESS01H HS4339ESF01H HD404339 Series 64 63 62 61 60 59 58 57 56 55 54 53 52 R71 R70 R63 R62 R61 R60 RA1/Vdisp R23 R22 R21 R20 R13 R12 Pin Arrangement FP-64B 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AVCC VCC D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5 R60 R61 R62 R63 R70 R71 R72 R00/SCK R01/SI R02/SO R03/TOC TEST RESET OSC1 OSC2 GND X1 X2 AVSS R30/AN0 R31/AN1 R32/AN2 R33/AN3 R40/AN4 R41/AN5 R42/AN6 R43/AN7 R50/AN8 R51/AN9 R52/AN10 R53/AN11 AV CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DP-64S 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA1/Vdisp R23 R22 R21 R20 R13 R12 R11 R10 R93 R92 R91 R90 R83 R82 R81 R80 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/STOPC D3/BUZZ D2/EVNB D1/INT1 D0/INT0 VCC 3 HD404339 Series Pin Description Pin Number Item Symbol DP-64S FP-64B Power supply VCC 33 27 I/O Function Applies power voltage GND 16 10 Connected to ground Vdisp 64 58 Used as a high-voltage output power supply pin when selected by the mask option (shared with RA1) Test TEST 12 6 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 13 7 I Resets the MCU Oscillator OSC 1 14 8 I Input/output pin for the internal oscillator. Connect these pins to the ceramic or crystal oscillator, or OSC1 to an external oscillator circuit. OSC 2 15 9 O X1 17 11 I X2 18 12 O D0–D 13 34–47 28–41 I/O Input/output pins addressed individually by bits; D0–D 13 are all high-voltage I/O pins. Each pin can be individually configured as selected by the mask option. RA 1 64 58 I One-bit high-voltage input port pin 1–5, I/O Four-bit input/output pins consisting of standard voltage pins 42–57 I/O Four-bit input/output pins consisting of high voltage pins Port R0 0–R0 3, 1–11, R3 –R7 20–31 0 2 14–25, Used with a 32.768-kHz crystal oscillator for clock purposes 59–64 R1 0–R2 3, 48–63 R8 0–R9 3 Interrupt INT0, INT1 34, 35 28, 29 I Input pins for external interrupts Stop clear STOPC 38 32 I Input pin for transition from stop mode to active mode 8 2 I/O Serial interface clock input/output pin SI 9 3 I Serial interface receive data input pin SO 10 4 O Serial interface transmit data output pin TOC 11 5 O Timer output pin EVNB 36 30 I Event count input pin BUZZ 37 31 O Square waveform output pin Serial interface SCK Timer Alarm 4 HD404339 Series Pin Number Item Symbol DP-64S FP-64B A/D converter AVCC 32 26 Power supply for the A/D converter. Connect this pin as close as possible to the VCC pin and at the same voltage as VCC. If the power supply voltage to be used for the A/D converter is not equal to V CC, connect a 0.1-µF bypass capacitor between the AV CC and AV SS pins. (However, this is not necessary when the AV CC pin is directly connected to the VCC pin.) AVSS 19 13 Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. AN 0–AN 11 20–31 14–25 I/O I Function Analog input pins for the A/D converter 5 HD404339 Series Pin Description in PROM Mode The HD4074339 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-64S FP-64B Pin I/O Pin I/O 1 59 R6 0 I/O O4 I/O 2 60 R6 1 I/O O3 I/O 3 61 R6 2 I/O O2 I/O 4 62 R6 3 I/O O1 I/O 5 63 R7 0 I/O O0 I/O 6 64 R7 1 I/O 7 1 R7 2 I/O 8 2 R0 0/SCK I/O VCC 9 3 R0 1/SI I/O VCC 10 4 R0 2/SO I/O 11 5 R0 3/TOC I/O 12 6 TEST I VPP 13 7 RESET I RESET 14 8 OSC 1 I VCC 15 9 OSC 2 O 16 10 GND — GND 17 11 X1 I GND 18 12 X2 O 19 13 AVSS — GND 20 14 R3 0/AN0 I/O O0 I/O 21 15 R3 1/AN1 I/O O1 I/O 22 16 R3 2/AN2 I/O O2 I/O 23 17 R3 3/AN3 I/O O3 I/O 24 18 R4 0/AN4 I/O O4 I/O 25 19 R4 1/AN5 I/O O5 I/O 26 20 R4 2/AN6 I/O O6 I/O 27 21 R4 3/AN7 I/O O7 I/O 28 22 R5 0/AN8 I/O 29 23 R5 1/AN9 I/O 30 24 R5 2/AN10 I/O 6 I HD404339 Series Pin Number MCU Mode PROM Mode DP-64S FP-64B Pin I/O Pin I/O 31 25 R5 3/AN11 I/O 32 26 AVCC — VCC 33 27 VCC — VCC 34 28 D0 /INT0 I/O M0 I 35 29 D1 /INT1 I/O M1 I 36 30 D2 /EVNB I/O A1 I 37 31 D3 /BUZZ I/O A2 I 38 32 D4 /STOPC I/O 39 33 D5 I/O A3 I 40 34 D6 I/O A4 I 41 35 D7 I/O A9 I 42 36 D8 I/O VCC 43 37 D9 I/O 44 38 D10 I/O 45 39 D11 I/O 46 40 D12 I/O 47 41 D13 I/O 48 42 R8 0 I/O CE 49 43 R8 1 I/O OE I 50 44 R8 2 I/O A13 I 51 45 R8 3 I/O A14 I 52 46 R9 0 I/O 53 47 R9 1 I/O 54 48 R9 2 I/O 55 49 R9 3 I/O 56 50 R1 0 I/O A5 I 57 51 R1 1 I/O A6 I 58 52 R1 2 I/O A7 I 59 53 R1 3 I/O A8 I 60 54 R2 0 I/O A0 I 61 55 R2 1 I/O A10 I 62 56 R2 2 I/O A11 I 63 57 R2 3 I/O A12 I 64 58 RA 1/V disp I I Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin 2. O0 to O 4 consist of two pins each. Tie each pair together before using them. 7 HD404339 Series GND VCC X2 X1 OSC2 OSC1 STOPC TEST RESET Block Diagram D0 INT0 D1 System control Interrupt control D2 INT1 D3 RAM (512 × 4 bits) D4 D port D5 W (4 bits) Timer A D6 D7 D8 D9 X (4 bits) D10 D11 D12 D13 R0 port SPX (4 bits) R1 port SCK ALU AV SS R2 port SPY (4 bits) R3 port Serial interface Internal data bus SI SO Internal data bus Timer C TOC Internal address bus Y (4 bits) R4 port Timer B EVNB CA (1 bit) R6 port A (4 bits) AVCC B (4 bits) BUZZ Buzzer SP (10 bits) Data bus High voltage pin Directional signal line 8 Instruction decoder PC (14 bits) ROM (16,384 × 10 bits) (6,144 × 10 bits) (12,288 × 10 bits) (4,096 × 10 bits) (8,192 × 10 bits) R7 port ST (1 bit) R8 port A/D converter R9 port • • • RA port • • • AN11 R5 port AN 0 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R50 R51 R52 R53 R60 R61 R62 R63 R70 R71 R72 R80 R81 R82 R83 R90 R91 R92 R93 RA1 HD404339 Series Memory Map ROM Memory Map Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000-$0FFF (HD404334), $0000-$17FF (HD404336), $0000–$1FFF (HD404338), $0000–$2FFF (HD4043312), $0000–$3FFF (HD404339, HD4074339)): The entire ROM area can be used for program coding. $0000 $000F Vector address (16 words) $0010 Zero-page subroutine (64 words) $003F $0040 $0FFF $1000 $17FF $1800 $1FFF Pattern (4,096 words) HD404334 Program (4,096 words) HD404336 Program (6,144 words) HD404338 Program (8,192 words) $0000 JMPL instruction $0001 (jump to RESET, STOPC routine) JMPL instruction $0002 (jump to INT 0 routine) $0003 JMPL instruction $0004 (jump to INT 1 routine) $0005 JMPL instruction $0006 (jump to timer A routine) $0007 $0008 JMPL instruction (jump to timer B routine) $0009 $000A JMPL instruction (jump to timer C routine) $000B $000C JMPL instruction $000D (jump to A/D converter routine) $000E JMPL instruction (jump to serial routine) $000F $2000 HD4043312 Program (12,288 words) $2FFF $3000 HD404339, HD4074339 Program (16,384 words) $3FFF Note: Since the ROM address areas between $0000–$0FFF overlap, the user can determine how these areas are to be used. Figure 1 ROM Memory Map 9 HD404339 Series RAM Memory Map Initial values after reset $000 RAM-mapped registers $040 Memory registers (MR) $050 Data (432 digits) $200 Not used $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) W W R/W R/W W W R/W R/W W W R/W R/W 0000 0000 Undefined Undefined 0000 0000 *2/0000 Undefined 0000 0000 *2/0000 Undefined Not used $3C0 Stack (64 digits) $3FF (ACR) (ADRL) (ADRU) (AMR1) (AMR2) W R R W W 0000 0000 1000 0000 -000 $020 Register flag area $023 $024 Port mode register B (PMRB) $025 Port mode register C (PMRC) $026 Timer mode register B2 (TMB2) $027 System clock selection register 1 (SSR1) System clock selection register 2 (SSR2) $028 W W W W W 0000 00-0 -000 000--00 (DCR0) W 0000 (DCR3) (DCR4) (DCR5) (DCR6) (DCR7) W W W W W 0000 0000 0000 0000 -000 $016 $017 $018 $019 $01A A/D channel register A/D data register lower A/D data register upper A/D mode register 1 A/D mode register 2 Not used Not used Notes: 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). $030 Port R0 DCR 2. Undefined. Not used R: Read only W: Write only R/W: Read/write $033 $034 $035 $036 $037 Port R3 DCR Port R4 DCR Port R5 DCR Port R6 DCR Port R7 DCR Not used $03F $00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W $00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W $00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W $00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W Figure 2 RAM Memory Map and Initial Values 10 *1 HD404339 Series Table 1 Initial Values of Flags after MCU Reset Item Initial Value Interrupt flags/mask Bit registers Interrupt enable flag (IE) 0 Interrupt request flag (IF) 0 Interrupt mask (IM) 1 Watchdog timer on flag (WDON) 0 A/D start flag (ADSF) 0 Input capture status flag (ICSF) 0 Input capture error flag (ICEF) 0 I AD off flag (IAOF) 0 RAM enable flag (RAME) 0 Low speed on flag (LSON) 0 Direct transfer on flag (DTON) 0 RAM Address Bit 3 Bit 2 Bit 1 Bit 0 $0000 IM0 (IM of INT0) IF0 (IF of INT0) RSP (Reset SP bit) IE (Interrupt enable flag) $0001 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM of INT1) IF1 (IF of INT1) $0002 IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) $0003 IMS (IM of serial) IFS (IF of serial) IMAD (IM of A/D) IFAD (IF of A/D) Interrupt control bits area Bit 2 Bit 1 Bit 0 $020 DTON (Direct transfer on flag) Bit 3 ADSF (A/D start flag) WDON (Watchdog on flag) LSON (Low speed on flag) $021 RAME (RAM enable flag) IAOF (IAD off flag) ICEF (Input capture error flag) ICSF (Input capture status flag) IF: Interrupt request flag $022 IM: Interrupt mask IE: Interrupt $023 enable flag SP: Stack pointer Not used Register flag area Figure 3 Interrupt Control Bits and Register Flag Areas Configuration 11 HD404339 Series SEM/SEMD IE REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed RSP Not executed Allowed Inhibited WDON Allowed Not executed Inhibited ADSF Allowed Inhibited Allowed DTON Not executed in active mode Allowed Allowed IM LSON IAOF IF ICSF ICEF RAME Used in subactive mode Not used Not executed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD instruction must not be executed for ADSF during A/D conversion. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions Memory registers $040 MR(0) $041 MR(1) $042 MR(2) $043 MR(3) $044 MR(4) $045 MR(5) $046 MR(6) $047 MR(7) $048 MR(8) $049 MR(9) $04A MR(10) $04B MR(11) $04C MR(12) $04D MR(13) $04E MR(14) $04F MR(15) Stack area Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 $3FF Level 1 $3C0 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC13 PC 12 PC11 $3FD PC 10 PC9 PC 8 PC7 $3FE CA PC6 PC 5 PC4 $3FF PC 3 PC2 PC 1 PC0 PC13 –PC0 : Program counter ST: Status flag CA: Carry flag Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position 12 HD404339 Series Registers and Flags 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W 0 (B) 1 W register Initial value: Undefined, R/W 0 (W) 3 X register Initial value: Undefined, R/W Y register Initial value: Undefined, R/W 0 (X) 3 0 (Y) 3 SPX register Initial value: Undefined, R/W 0 (SPX) 3 SPY register Initial value: Undefined, R/W 0 (SPY) 0 Carry Initial value: Undefined, R/W (CA) 0 Status Initial value: 1, no R/W Program counter Initial value: 0, no R/W (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 1 5 1 1 1 0 (SP) Figure 6 Registers and Flags 13 HD404339 Series Addressing Modes RAM Addressing Modes Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. 0 3 1 0 3 W 9 3 Y X 7 0 3 Instruction 0 9 0 RAM address 0 0 0 1 0 0 Register Indirect Addressing Memory Register Addressing Instruction 1st instruction word 0 9 2nd instruction word 0 Opcode 9 RAM address Direct Addressing Figure 7 RAM Addressing Modes 14 Opcode RAM address 9 0 0 HD404339 Series ROM Addressing Modes Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000–$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction. 2nd instruction word 1st instruction word 9 3 Opcode 09 0 Opcode 9 5 Operand 13 0 Operand 0 13 Program counter 0 Program counter 0 0 0 0 0 0 0 0 Direct Addressing Zero-Page Addressing Operand Opcode 9 7 0 Operand 13 9 3 Opcode 0 Program counter * * * * * * 0 7 0 B 13 A 0 Program counter 0 0 Current Page Addressing Table Data Addressing Figure 8 ROM Addressing Modes 15 HD404339 Series Instruction Set Table 2 Instruction Set Classification Instruction Type Function Number of Instructions Immediate Transferring constants to the accumulator, B register, and RAM. 4 Register-to-register Transferring contents of the B, Y, SPX, SPY, or memory registers to 8 the accumulator. RAM addressing Available when accessing RAM in register indirect addressing mode. 13 RAM register Transferring data between the accumulator and memory. 10 Arithmetic Performing arithmetic operations with the contents of the accumulator, B register, or memory. 25 Compare Comparing contents of the accumulator or memory with a constant. 12 RAM bit manipulation Bit set, bit reset, and bit test. 6 ROM addressing Branching and jump instructions based on the status condition. 8 Input/output Controlling the input/output of the R and D ports; ROM data reference with the P instruction. 11 Control Controlling the serial communication interface and low-power dissipation modes. 4 Total: 101 instructions 16 HD404339 Series Interrupts $000,0 IE Interrupt request (RESET, STOPC) $000,2 INT0 interrupt IF0 $000,3 IM0 $001,0 INT1 interrupt IF1 $001,1 IM1 Priority Controller Priority Order Vector Address $0000 1 $0002 2 $0004 3 $0006 4 $0008 5 $000A 6 $000C 7 $000E $001,2 Timer A interrupt IFTA $001,3 IMTA $002,0 Timer B interrupt IFTB $002,1 IMTB $002,2 Timer C interrupt IFTC $002,3 IMTC $003,0 A/D interrupt IFAD $003,1 IMAD $003,2 Serial interrupt IFS $003,3 IMS Figure 9 Interrupt Control Circuit 17 HD404339 Series Instruction cycles 1 2 3 4 5 6 Instruction execution* Stacking Interrupt acceptance IE reset Vector address generation Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Note: * The stack is accessed and the interrupt enable flag is reset after the instruction is executed, even if it is a two-cycle instruction. Figure 10 Interrupt Processing Sequence 18 HD404339 Series Operating Modes The MCU has five operating modes as shown in table 3. Transitions between operating modes are shown in figure 11. Table 3 Operations in Each Operating Mode Function Active Mode Subactive Mode Standby Mode Watch Mode Stop Mode System oscillator OP Stopped OP Stopped Stopped Subsystem oscillator OP OP OP OP * OP CPU OP OP Retained Retained Reset RAM OP OP Retained Retained Retained Timer A OP OP OP OP Reset Timers B, C OP OP OP Stopped Reset Serial OP OP OP Stopped Reset A/D OP Stopped OP Stopped Reset I/O OP OP Retained Retained Reset Notes: OP implies in operation. * Oscillation can be switched on or off with bit 3 of system clock selection register 1 (SSR1: $027). 19 HD404339 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR13 = 0) RAME = 0 RESET 1 RAME = 1 RESET 2 STOPC STOPC Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: ø CPU: ø CLK: ø PER: fOSC: fX: ø CPU: ø CLK: ø PER: SBY instruction Interrupt fOSC: fX: ø CPU: ø CLK: ø PER: Oscillate Oscillate fcyc fcyc fcyc STOP instruction STOP instruction (TMA3 = 0, SSR13 = 1) fOSC: fX: ø CPU: ø CLK: ø PER: Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode fOSC: fX: ø CPU: ø CLK: ø PER: Oscillate Oscillate Stop fW fcyc SBY instruction Interrupt (TMA3 = 1) fOSC: fX: ø CPU: ø CLK: ø PER: Oscillate Oscillate fcyc fW fcyc STOP instruction INT0, timer A (TMA3 = 1, LSON = 0) fOSC: fX: ø CPU: ø CLK: ø PER: Stop Oscillate Stop fW Stop *2 fOSC: fX: Main oscillation frequency Subsystem oscillation frequency for time base fcyc: fOSC/4, fOSC/8, fOSC/16, or fOSC/32 (software selectable) fSUB: fX/8 or fX/4 (software selectable) fW: fX/8 ø CPU: System clock ø CLK: Clock for timer A ø PER: Clock for other peripheral functions (except timer A) LSON: Low speed on flag DTON: Direct transfer on flag *1 STOP instruction Subactive mode fOSC: fX: ø CPU: ø CLK: ø PER: Stop Oscillate fSUB fW fSUB *3 INT0, timer A fOSC: fX: ø CPU: ø CLK: ø PER: Stop Oscillate Stop fW Stop Notes: 1. STOP/SBY (DTON = 1, LSON = 0) 2. STOP/SBY (DTON = 0, LSON = 0) 3. STOP/SBY (DTON = Don’t care, LSON = 1) Figure 11 MCU Status Transitions 20 (TMA3 = 1, LSON = 1) , , HD404339 Series In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least tRC when clearing stop mode, execute the cancellation according to the timing chart in figure 12. In watch and subactive modes, a timer A or INT0 interrupt can be accepted during the interrupt frame period T (see figure 13). Note: In watch and subactive modes, an interrupt will not be properly detected if the INT0 high or low level period is shorter than the interrupt frame period T. Thus, when operating in watch and subactive modes, maintain the INT0 high or low level period longer than period T to ensure interrupt detection. Stop mode Oscillator Internal clock RESET or STOPC tres tres ≥ tRC (stabilization period) STOP instruction execution Figure 12 Timing of Stop Mode Cancellation Active mode Oscillation stabilization period Watch mode Active mode Interrupt strobe INT0 Interrupt request generation (During the transition from watch mode to active mode only) T t RC T Tx T + tRC ≤ TX ≤ 2T + tRC T: Interrupt frame length t RC : Oscillation stabilization period Figure 13 Interrupt Frame 21 HD404339 Series The MCU automatically provides an oscillation stabilization period tRC when operation switches from watch mode to active mode. The interrupt frame period T and one of three values for t RC can be selected with the miscellaneous register (MIS: $00C), as listed in figure 14. Operation can switch directly from subactive mode to active mode, as illustrated in figure 15. In this case, the transition time TD obeys the following relationship. t RC < TD < T + t RC Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 Bit name MIS3 MIS2 Buffer control. Refer to figure 24. MIS1 MIS0 0 0 T*1 tRC*1 0.24414 ms 0.12207 ms 0.24414 0 1 15.625 ms 1 0 125 ms 1 1 Not used Oscillation Circuit Conditions External clock input ms*2 7.8125 ms 62.5 ms Ceramic oscillator Crystal oscillator — Notes: 1. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used. 2. The value is applied only when direct transfer operation is used. Figure 14 Miscellaneous Register 22 HD404339 Series STOP/SBY instruction execution Subactive mode MCU internal processing period Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing T t RC Interrupt frame period T: t RC : Oscillation stabilization time Figure 15 Direct Transition Timing MCU Operation Sequence: The MCU operation flow is shown in figures 16 and 17. RESET input is asynchronous, and causes an immediate transition to the reset state from any MPU operation state. The low-power mode operation sequence is shown in figure 17. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. 23 HD404339 Series Power on RESET = 0? No Yes MCU operation cycle RAME = 0 Yes IF = 1? MCU reset No No IM = 0 IE = 1 Yes Instruction RAME = 1 execution Reset input Yes SBY/STOP instruction IE ← 0 Stack ← (PC), (CA), (ST) No Power-down mode operation cycle (see figure 17) PC ← (PC)+1 Figure 16 MCU Operation Sequence (Power On) 24 PC ← vector address HD404339 Series Low-power mode operation cycle IF = 1 and IM = 0? No Yes Stop mode Standby mode No IF = 1 and IM = 0? Yes No STOPC = 0? Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC ← Next Iocation PC ← Next Iocation Reset MCU Instruction execution MCU operation cycle Figure 17 MCU Operating Sequence (Low-Power Mode Operation) 25 HD404339 Series Oscillator Circuit Figure 18 shows a block diagram of the clock generation circuit. The system clock frequency of the oscillator connected to OSC1 and OSC2 can be selected by system clock selection registers 1 and 2 (SSR1, 2: $027, $028) as shown in figures 20 and 21. The system clock division ratio can be set by software to be 1/4, 1/8, 1/16, or 1/32. The subsystem clock division ratio can be set by software to be 1/4 or 1/8. LSON OSC2 OSC1 System fOSC 1/4, 1/8, fcyc 1/16, or oscillator tcyc 1/32 division circuit *1 fX X1 Subsystem oscillator Timing generator circuit ø CPU CPU with ROM, RAM, registers, flags, and I/O ø PER Peripheral function interrupt System clock selection fSUB 1/8 or 1/4 Timing division tsubcyc generator circuit *2 circuit TMA3 X2 1/8 division circuit fW tWcyc Timing generator circuit Time-base clock øCLK selection Time-base interrupt Notes: 1. The system clock division ratio can be selected by setting bit 1 or 0 of the system clock select register 2 (SSR2: $028). 2. The system clock division ratio can be selected by setting bit 2 of the system clock select register 1 (SSR1: $027). Figure 18 Clock Generation Circuit 26 HD404339 Series GND RESET OSC1 OSC2 GND X1 X2 AVSS Figure 19 Typical Layout of Crystal and Ceramic Oscillators 27 HD404339 Series Table 4 Oscillator Circuit Examples Circuit Configuration External clock operation Circuit Constants External oscillator OSC 1 Open OSC 2 Ceramic oscillator (OSC1, OSC 2) Ceramic oscillator: CSA4.00MG C1 (Murata) OSC1 Ceramic Rf = 1 MΩ ±20% Rf C1 = C2 = 30 pF ±20% OSC2 C2 GND Crystal oscillator (OSC1, OSC 2) Rf = 1 MΩ ±20% C1 C1 = C2 = 10 to 22 pF ±20% OSC1 Crystal Crystal: Equivalent to circuit shown below C0 = 7 pF max. Rf OSC2 RS = 100 Ω max. C2 GND L CS RS OSC1 OSC2 C0 C1 Crystal oscillator (X1, X2) Crystal: 32.768 kHz: MX38T (Nippon Denpa) X1 C1 = C2 = 20 pF ±20% Crystal RS = 14 kΩ X2 C0 = 1.5 pF C2 GND L CS RS X1 X2 C0 Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC 2, X1, X2 and elements should be as short as possible, and must not cross other wiring (see figure 19). 3. When a 32.768-kHz crystal oscillator is not used, fix pin X1 to GND and leave pin X2 open. 28 HD404339 Series System clock selection register 1 (SSR1: $027) Bit 3 2 1 0 Initial value 0 0 0 — W W W — Read/Write SSR13*1 SSR12 Bit name SSR11 Not used SSR11 System Clock Selection*2 0 0.4 to 1.0 MHz 1 1.6 to 4.5 MHz SSR12 32-kHz Oscillation Division Ratio Selection 0 fSUB = fX/8 1 fSUB = fX/4 SSR13 32-kHz Oscillation Stop 0 Oscillation operates in stop mode 1 Oscillation stops in stop mode Notes: *1 SSR13 will only be cleared to 0 by a RESET input. A STOPC input during stop mode will not clear SSR13. Also note that SSR13 will not be cleared upon transition to stop mode. *2 When the subsystem oscillator (32.768 kHz crystal oscillator) is used, set 0.4 MHz≤ fOSC ≤ 1.0MHz or 1.6 MHz ≤ fOSC ≤ 4.5 MHz. Figure 20 System Clock Selection Register 1 (SSR1) System clock selection register 2 (SSR2: $028) Bit 3 2 1 0 Initial value — — 0 0 Read/Write — — W W Bit name Not used Not used SSR21 SSR20 SSR21 SSR20 0 0 1/4 division 0 1 1/8 division 1 0 1/16 division 1 1 1/32 division Figure 21 System Clock Division Ratio System Clock Selection Register 2 (SSR2) 29 HD404339 Series I/O Ports The MCU has 53 input/output pins (D0–D13, R00–R9 3) and one input-only pin (RA1). • The 30 pins consisting of ports D0–D13, R1, R2, R8, and R9 are all high-voltage I/O pins. RA1 is a highvoltage input-only pin. The high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option. • All standard voltage output pins are CMOS output pins. However, the R0 2/SO pin can be programmed for NMOS open-drain output. • In stop mode, input/output pins go to the high-impedance state. • All standard voltage input/output pins have pull-up MOS built in, which can be individually turned on or off by software (Table 5). Pull-up MOS on/off settings can be made independently of settings as on-chip supporting module pins. Table 5 Control of Standard I/O Pins by Program MIS3 (bit 3 of MIS) 0 DCR 0 PDR 0 1 0 1 0 1 0 1 PMOS — — — On — — — On NMOS — — On — — — On — — — — — — On — On CMOS buffer Pull-up MOS Note: — indicates off. 30 1 1 0 1 HD404339 Series Data control register (DCR0: $030, DCR3 to DCR7: $033 to $037) DCR0, DCR3 to DCR7 Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name Bits 0 to 3 CMOS Buffer Control DCR03, DCR02, DCR01, DCR00, DCR33 DCR32 DCR31 DCR30 to to to to DCR63 DCR72 DCR71 DCR70 0 CMOS buffer off (high impedance) 1 CMOS buffer on Correspondence between ports and DCR bits Register Bit 3 Bit 2 Bit 1 Bit 0 DCR0 R03 R02 R01 R00 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR5 R53 R52 R51 R50 DCR6 R63 R62 R61 R60 DCR7 Not used R72 R71 R70 Figure 22 Data Control Register (DCR) 31 HD404339 Series Table 6 Circuit Configurations of Standard I/O Pins I/O Pin Type Circuit Input/output pins Pins VCC VCC Pull-up control signal Buffer control signal HLT R0 0, R0 1, R0 3, MIS3 R3 0–R3 3, DCR Output data R4 0–R4 3, R5 0–R5 3, PDR R6 0–R6 3, R7 0–R7 2 Input data Input control signal VCC HLT VCC Pull-up control signal Buffer control signal Output data R0 2 MIS3 DCR MIS2 PDR Input data Input control signal Peripheral function Input/ pins output pins VCC HLT VCC Pull-up control signal Output data Input data Output pins VCC SCK Pull-up control signal PMOS control signal Output data VCC VCC SO MIS3 MIS2 SO HLT Pull-up control signal Output data 32 SCK HLT VCC SCK MIS3 MIS3 TOC TOC HD404339 Series I/O Pin Type Circuit Pins VCC Peripheral function Input/ pins pins SI HLT MIS3 PDR SI Input data VCC AN 0–AN 11 HLT MIS3 PDR A/D input Input control Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins enter the high-impedance state. 2. The HLT signal is 1 in active, standby, watch, and subactive modes. Table 7 Circuit Configurations for High-Voltage Input/Output Pins I/O Pin Type Input/output pins With Pull-Down Resistance VCC Without Pull-Down Resistance VCC HLT Output data Pull-down resistance HLT Output data Input data Input control signal Vdisp Pins D0–D 13 , R1 0–R1 3, R2 0–R2 3, R8 0–R8 3, R9 0–R9 3 Input data Input control signal Input data Input pins Input control signal Peripheral function pins Output pins VCC HLT Pull-down resistance Output data VCC RA 1 BUZZ HLT Output data Vdisp Input data Input pins Pull-down resistance Vdisp Input data INT0, INT1, EVNB, STOPC Note: HLT goes high in active, standby, watch, and subactive modes. 33 HD404339 Series Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name PMRA3 PMRA2 PMRA1 PMRA0 PMRA0 PMRA2 R03/TOC Mode Selection 0 R03 1 TOC PMRA3 0 D3 1 BUZZ 0 R02 1 SO PMRA1 D3/BUZZ Mode Selection R02/SO Mode Selection R01/SI Mode Selection 0 R01 1 SI Figure 23 Port Mode Register A (PMRA) Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 W W W W Read/Write Bit name PMRB3* PMRB2 PMRB1 PMRB0 PMRB0 PMRB2 D2/EVNB Mode Selection 0 D2 1 EVNB 0 D4 1 STOPC 0 D0 1 INT0 PMRB1 PMRB3 D4/STOPC Mode Selection D0/INT0 Mode Selection D1/INT1 Mode Selection 0 D1 1 INT1 Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not reset but retains its value. Figure 24 Port Mode Register B (PMRB) 34 HD404339 Series Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W MIS3 MIS2 MIS1 MIS0 MIS3 Pull-Up MOS On/Off Selection 0 Pull-up MOS off 1 Pull-up MOS on (refer to table 5) MIS2 CMOS Buffer On/Off Selection for Pin R02/SO 0 CMOS on 1 CMOS off MIS1 MIS0 tRC selection. Refer to figure 14 in the operation modes section. Note: The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Figure 25 Miscellaneous Register 35 HD404339 Series Prescaler The MCU has two built-in prescalers, S and W (PSS, PSW). They divide the system clock and subsystem clock, and output these divided clocks to the peripheral function modules, as shown in figure 26. Subsystem clock fX/8 Prescaler W Timer A Timer B fX/4 or fX/8 Timer C System clock Clock selector Prescaler S Figure 26 Prescaler Output Supply 36 Serial HD404339 Series Timers The MCU has three built-in timers A, B, and C. The functions of each timer are listed in table 7. Timer A Timer A is an 8-bit free-running timer that can also be used as a clock time-base with a 32.768-kHz subsystem oscillator. Timer A has the following features: • One of eight internal clocks can be selected from prescaler S according to the setting of timer mode register A (TMA: $008) • In time-base mode, one of five internal clocks can be selected from prescaler W according to the setting of timer mode register A • An interrupt request can be generated when timer counter A (TCA) overflows • Input clock frequency must not be modified during timer A operation Table 7 Timer Functions Functions Clock source Timer functions Timer output Timer A Timer B Timer C Prescaler S Available Available Available Prescaler W Available — — External event — Available — Free-running Available Available Available Time base Available — — Event counter — Available — Reload — Available Available Watchdog — — Available Input capture — Available — PWM — — Available 37 HD404339 Series 1/4 fW 1/2 t Wcyc 2 fW Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 t Wcyc Clock Timer counter A (TCA) Overflow System clock øPER ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Figure 27 Timer A Block Diagram 38 Internal data bus Selector Selector HD404339 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMA3 TMA2 TMA1 TMA0 Bit name Source Input Clock TMA3 TMA2 TMA1 TMA0 Prescaler Frequency Operating Mode 0 0 0 1 0 1 1 1 0 0 1 1 0 1 0 PSS 2048 tcyc 1 PSS 1024 tcyc 0 PSS 512 tcyc 1 PSS 128 tcyc 0 PSS 32 tcyc 1 PSS 8 tcyc 0 PSS 4 tcyc 1 PSS 2 tcyc 0 PSW 32t Wcyc 1 PSW 16t Wcyc 0 PSW 8t Wcyc 1 PSW 2t Wcyc 0 PSW 1/2t Wcyc 1 Not used X PSW and TCA reset Timer A mode Time-base mode X = Don’t care. Notes: 1. t Wcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) × 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 28 Timer Mode Register A (TMA) 39 HD404339 Series Timer B Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. These are described as follows. • By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter • By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected. • By setting timer write register BL, U (TWBL, U: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation • By setting timer read register BL, U (TRBL, U: $00A, $00B), the contents of timer counter B can be read out • Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as an external event • An interrupt can be requested when timer counter B overflows or when a trigger input edge is received during input capture operation 40 HD404339 Series Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Timer read register B lower (TRBL) Free-running timer control signal Timer write register B lower (TWBL) ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 Edge detector øPER 2 Overflow Timer write register B upper (TWBU) Selector EVNB System clock Timer counter B (TCB) Internal data bus Clock 3 Prescaler S (PSS) Timer mode register B1 (TMB1) Edge detection control signal Timer mode register B2 (TMB2) Figure 29 Timer B Free-Running and Reload Operation Block Diagram 41 HD404339 Series Input capture status flag (ICSF) Interrupt request flag of timer B (IFTB) Input capture error flag (ICEF) Error controller Timer read register BU (TRBU) Timer read register B lower (TRBL) Read signal Edge detector Clock Timer counter B (TCB) Overflow Input capture timer control signal Selector ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 3 System clock øPER 2 Timer mode register B1 (TMB1) Prescaler S (PSS) Edge detection control signal Timer mode register B2 (TMB2) Figure 30 Timer B Input Capture Operation Block Diagram 42 Internal data bus EVNB HD404339 Series Timer mode register B1 (TMB1: $009) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMB13 TMB12 TMB11 TMB10 Bit name TMB13 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer Input Clock Period and Input Clock Source TMB12 TMB11 TMB10 0 0 0 2048tcyc 1 512tcyc 0 128tcyc 1 32tcyc 0 8tcyc 1 4tcyc 0 2tcyc 1 D2/EVNB (External event input) 1 1 0 1 Figure 31 Timer Mode Register B1 (TMB1) Timer mode register B2 (TMB2: $026) Bit 3 Initial value — 0 0 0 Read/Write — W W W TMB21 TMB20 TMB21 TMB20 0 0 No detection 1 Falling edge detection 0 Rising edge detection 1 Rising and falling edge detection Bit name 2 Not used TMB22 1 1 TMB22 0 EVNB Edge Detection Selection Free-Running/Reload and Input Capture Selection 0 Free-Running/Reload 1 Input Capture Figure 32 Timer Mode Register B2 (TMB2) 43 HD404339 Series Timer C Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows. • By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected • By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled • By setting timer write register CL, U (TWCL, U: $00E, $00F), timer counter C (TCC) can be written to • By setting timer read register CL, U (TRCL, U: $00E, $00F), the contents of timer counter C can be read out • An interrupt can be requested when timer counter C overflows • Timer counter C can be used as a watchdog timer for detecting runaway programs 44 HD404339 Series System reset signal Watchdog on flag (WDON) Interrupt request flag of timer C (IFTC) Watchdog timer controller Timer read register CU (TRCU) TOC Timer output control logic Timer read register C lower (TRCL) Clock Timer output control signal ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector System øPER clock Overflow Internal data bus Timer counter C (TCC) Timer write register C upper (TWCU) Free-running timer control signal Timer write register C lower (TWCL) 3 Prescaler S (PSS) Timer mode register C (TMC) Port mode register A (PMRA) Figure 33 Timer C Block Diagram 45 HD404339 Series Timer mode register C (TMC: $00D) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMC3 TMC2 TMC1 TMC0 Bit name TMC3 Free-Running/Reload Timer Selection 0 Free-running timer 1 Reload timer TMC2 TMC1 TMC0 0 0 0 2048tcyc 1 1024tcyc 0 512tcyc 1 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 2tcyc 1 1 0 1 Input Clock Period Figure 34 Timer Mode Register C (TMC) $FF + 1 Overflow Timer C count value $00 CPU operation Time Normal operation Timer C clear Normal operation Timer C clear Program runaway Reset Figure 35 Watchdog Timer Operation Flowchart 46 Normal operation HD404339 Series T × (N + 1) TMC3 = 0 (Free-running timer) T T × 256 TMC3 = 1 (Reload timer) T × (256 – N) Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are determined by timer mode register C.) N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.) Figure 36 PWM Output Waveform 47 HD404339 Series Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 8. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 8 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer write register updated to value N Free running Timer Write Register is Updated during Low PWM Output Timer write register updated to value N Interrupt request T × (255 – N) T × (N + 1) Interrupt request T × (N' + 1) T × (255 – N) Reload Timer write register updated to value N T Interrupt request T × (255 – N) T Timer write register updated to value N Interrupt request T T × (255 – N) 48 T × (N + 1) T HD404339 Series Alarm Output Function BUZZ Alarm output control signal Alarm output controller System øPER clock 2 ÷2048 ÷1024 ÷512 ÷256 Selector Port mode register A (PMRA) Port mode register C (PMRC) Internal data bus The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of four alarm frequencies supplied from the PSS can be selected. Prescaler S (PSS) Figure 37 Alarm Output Function Block Diagram Table 9 Port Mode Register C PMRC Bit 3 Bit 2 System Clock Divisor 0 0 ÷ 2048 1 ÷ 1024 0 ÷ 512 1 ÷ 256 1 49 HD404339 Series Serial Interface The MCU has a one-channel serial interface built in with the following features. • One of 13 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock. • During idle status, the serial output pin can be controlled to be high or low output • Transmit clock errors can be detected • An interrupt request can be generated after transfer has completed when an error occurs Octal counter (OC) SO Serial interrupt request flag (IFS) Idle controller SCK I/O controller SI Clock 1/2 Selector 1/2 Transfer control signal Selector ÷2 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 2048 3 System clock øPER Prescaler S (PSS) Figure 38 Serial Interface Block Diagram 50 Serial mode register (SMR) Port mode register C (PMRC) Internal data bus Serial data register (SR) HD404339 Series Table 10 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode 1 Transmit mode 0 Receive mode 1 Transmit/receive mode 1 STS wait state (Octal counter = 000, transmit clock disabled) MCU reset SMR write (IFS ← 1) SMR write STS instruction Transmit clock Transmit clock wait state (Octal counter = 000) Transfer state (Octal counter = 000) 8 transmit clocks or STS instruction (IFS ← 1) External clock mode STS wait state (Octal counter = 000, transmit clock disabled) SMR write Continuous clock output state (PMRA 0, 1 = 00) SMR write STS instruction MCU reset 8 transmit clocks or SMR write (IFS← 1) Transmit clock Transmit clock Transmit clock wait state (Octal counter = 000) STS instruction (IFS ← 1) Transfer state (Octal counter = 000) Internal clock mode Figure 39 Serial Interface State Transitions 51 HD404339 Series Transmit clock 1 Serial output data 2 3 4 5 LSB Serial input data latch timing Figure 40 Serial Interface Timing 52 6 7 8 MSB , HD404339 Series Transmit clock wait state State STS wait state Transmit clock wait state Transfer state STS wait state MCU reset Port selection PMRA write External clock selection SMR write Output level control in idle states Dummy write for state transition Output level control in idle states PMRC write Data write for transmission SRL, SRU write STS instruction SCK pin (input) SO pin Undefined LSB MSB IFS External clock mode Flag reset at transfer completion Transmit clock wait state State STS wait state Transfer state STS wait state MCU reset Port selection PMRA write Internal clock selection SMR write Output level control in idle states PMRC write Output level control in idle states Data write for transmission SRL, SRU write STS instruction SCK pin (output) SO pin Undefined LSB MSB IFS Internal clock mode Flag reset at transfer completion Figure 41 Example of Serial Interface Operation Sequence 53 HD404339 Series Transmit clock errors are detected as illustrated in figure 42. Transfer completion (IFS ← 1) Interrupts inhibited IFS ← 0 SMR write Yes IFS = 1 Transmit clock error processing No Normal termination Transmit clock error detection flowchart Transmit clock wait state Transmit clock wait state Transfer state State Transfer state SCK pin (input) Noise 1 2 3 4 5 6 7 8 Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. SMR write IFS Flag set because octal counter reaches 000. Transmit clock error detection procedure Figure 42 Transmit Clock Error Detection 54 Flag reset at transfer completion. HD404339 Series Table 11 Transmit Clock Selection PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 System Clock Divisor Transmit Clock Frequency 0 0 0 0 ÷ 2048 4096t cyc 1 ÷ 512 1024t cyc 0 ÷ 128 256t cyc 1 ÷ 32 64t cyc 0 ÷8 16t cyc 1 ÷2 4t cyc 0 ÷ 4096 8192t cyc 1 ÷ 1024 2048t cyc 0 ÷ 256 512t cyc 1 ÷ 64 128t cyc 0 ÷ 16 32t cyc 1 ÷4 8t cyc 1 1 1 0 0 0 1 1 0 Serial mode register (SMR: $005) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SMR3 SMR2 SMR1 SMR0 Bit name SMR3 R00/SCK Mode Selection 0 R00 1 SCK Clock Source Output Prescaler Refer to table 11 0 Output System clock — 1 Input External clock — SMR1 SMR0 0 0 0 1 1 Prescaler Division Ratio SCK SMR2 0 1 1 0 0 1 1 Figure 43 Serial Mode Register (SMR) 55 HD404339 Series Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 Undefined 0 Read/Write W W W W PMRC2 PMRC1 PMRC0 Bit name PMRC3 PMRC0 Alarm output function. Refer to table 9. Serial Clock Division Ratio 0 Prescaler output divided by 2 1 Prescaler output divided by 4 PMRC1 Output Level Control in Idle States 0 Low level 1 High level Figure 44 Port Mode Register C (PMRC) 56 HD404339 Series A/D Converter The MCU also contains a built-in A/D converter that uses a sequential comparison method with a resistance ladder. It can perform digital conversion of twelve analog inputs with 8-bit resolution. The following describes the A/D converter. • A/D mode register 1 (AMR1: $019) is used to select digital or analog ports • A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or analog ports • The A/D channel register (ACR: $016) is used to select an analog input channel • A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time the A/D start flag is cleared to 0. • By setting the IAD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode • The A/D data register is a read-only register consisting of a lower 4 bits and upper 4 bits (ADRL: $017, ADRU: $018). This register is not cleared by a reset. Data reads during A/D conversion are not guaranteed. After A/D conversion ends, the resultant 8-bit data is set in this register and held until the start of the next conversion (figures 51 to 53). 57 HD404339 Series 4 A/D mode register 1 (AMR1) A/D interrupt request flag (IFAD) 2 Selector Encoder + Comp – AVCC AVSS A/D controller Control signal for conversion time A/D start flag (ADSF) A/D mode register 2 (AMR2) A/D data register (ADRU, L) A/D channel register (ACR) IAD off flag (IAOF) D/A Operating mode signal (1 in stop, watch, and subactive modes) Figure 45 A/D Converter Block Diagram 58 Internal data bus 4 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 HD404339 Series Notes on Usage • Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF) • Do not write to the A/D start flag during A/D conversion • Data in the A/D data register during A/D conversion is undefined • Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop, watch, or subactive mode. In addition, to save power while in these modes, all current flowing through the converter’s resistance ladder is cut off. • If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) • The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode registr as an analog pin will remain pulled up. A/D mode register 1 (AMR1: $019) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W AMR13 AMR12 AMR11 AMR10 Bit name AMR10 AMR12 R32/AN2 Mode Selection 0 R32 1 AN2 AMR13 0 R33 1 AN3 0 R30 1 AN0 AMR11 R33/AN3 Mode Selection R30/AN0 Mode Selection R31/AN1 Mode Selection 0 R31 1 AN1 Figure 46 A/D Mode Register 1 (AMR1) 59 HD404339 Series A/D mode register 2 (AMR2: $01A) Bit 3 Initial value — 0 0 0 Read/Write — W W W AMR21 AMR20 Bit name 2 Not used AMR22 1 0 AMR20 AMR22 R5/AN8–AN11 Pin Selection Conversion Time 0 34tcyc 1 67tcyc AMR21 R4/AN4–AN7 Pin Selection 0 R5 0 R4 1 AN8–AN11 1 AN4–AN7 Figure 47 A/D Mode Register 2 (AMR2) 60 HD404339 Series A/D channel register (ACR: $016) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write Bit name W W W W ACR3 ACR2 ACR1 ACR0 ACR3 ACR2 ACR1 ACR0 0 0 0 1 1 0 1 1 0 0 1 1 Analog Input Selection 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7 0 AN8 1 AN9 0 AN10 1 AN11 Don’t Don’t care care Not used Figure 48 A/D Channel Register (ACR) 61 HD404339 Series A/D start flag (ADSF: $020, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W W R/W DTON ADSF WDON LSON Bit name LSON A/D Start Flag (ADSF) 0 A/D conversion completed 1 A/D conversion started Refer to the description of operating modes DTON WDON Refer to the description of operating modes Refer to the description of timers Figure 49 A/D Start Flag (ADSF) IAD off flag (IAOF: $021, bit 2) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W RAME IAOF ICEF ICSF Bit name ICSF IAD Off Flag (IAOF) 0 IAD current flows 1 IAD current is cut off Refer to the description of timers ICEF RAME Refer to the description of timers Refer to the description of operating modes Figure 50 IAD Off Flag (IAOF) 62 HD404339 Series ADRU: $018 3 2 ADRL: $017 1 0 3 2 1 0 MSB LSB bit 7 bit 0 RESULT Figure 51 A/D Data Register A/D data register (lower) (ADRL: $017) Bit 3 2 1 0 Read/write R R R R Initial value after reset 0 0 0 0 ADRL3 ADRL2 ADRL1 ADRL0 Bit name Figure 52 A/D Data Register (Lower) (ADRL) A/D data register (upper) (ADRU: $018) Bit 3 2 1 0 Read/write R R R R Initial value after reset 1 0 0 0 ADRU3 ADRU2 ADRU1 ADRU0 Bit name Figure 53 A/D Data Register (Upper) (ADRU) 63 HD404339 Series Notes on Mounting Assemble all parts including the HD404339 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 µF) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS . 64 HD404339 Series 1. When not using an A/D converter. VCC AVCC AN 0 0.1 µF AN 1 to AN 11 AVSS GND 2. When using pins AN 0 and AN 1 but not using AN 2 to AN 11. AVCC VCC AN 0 AN 1 AN 2 to AN 11 AVSS GND 0.1 µF × 3 3. When using all analog pins. VCC AVCC AN 0 AN 1 AN 2 to AN 11 GND AVSS 0.1 µF × 13 Figure 54 Example of Connections (AVCC to AVSS ) Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 54. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2. 65 HD404339 Series VCC VCC C1 GND C2 GND Figure 55 Example of Connections (VCC to GND) 66 HD404339 Series Absolute Maximum Ratings Item Symbol Value Unit Notes Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V 1 Pin voltage VT –0.3 to VCC + 0.3 V 2 VCC – 45 to VCC + 0.3 V 3 Total permissible input current ∑IO 70 mA 4 Total permissible output current –∑IO 150 mA 5 Maximum input current IO 4 mA 6, 7 20 mA 6, 8 4 mA 9, 10 30 mA 10, 11 Maximum output current –I O Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD4074339. 2. Applies to all standard voltage pins. 3. Applies to high-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from VCC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports R3, R4, and R5. 8. Applies to ports R0, R6, and R7. 9. Applies to ports R0 and R3 to R7. 10. The maximum output current is the maximum current flowing from V CC to each I/O pin. 11. Applies to ports D0–D 13 , R1, R2, R8, and R9. 67 HD404339 Series Electrical Characteristics DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VC C, T a = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition 0.8V CC — VCC + 0.3 V OSC 1 VCC – 0.5 — VCC + 0.3 V RESET, SCK, SI –0.3 — 0.2V CC V INT0, INT1, VCC – 40 — STOPC, EVNB 0.2V CC V OSC 1 0.5 V SCK, SO, TOC VCC – 0.5 — — V –I OH = 0.5 mA Output low voltage VOL SCK, SO, TOC — — 0.4 V I OL = 0.4 mA I/O leakage current RESET, SCK, SI, SO,TOC, OSC 1 — — 1 µA Vin = 0 V to VCC 1 INT0, INT1, — STOPC, EVNB — 20 µA Vin = VCC – 40 to VCC 1 VCC — 5.0 mA VCC = 5 V, 2, 5 Input high voltage VIH RESET, SCK, SI, INT0, INT1, Notes STOPC, EVNB Input low voltage Output high voltage VIL VOH |IIL| Current dissipation I CC in active mode VCC Current dissipation I SUB in subactive mode VCC — 8.0 mA — — 2.0 mA 2, 6 VCC = 5 V, 3 — — 100 µA VCC = 5 V, 4, 5 32 kHz oscillator VCC Current dissipation I STOP in stop mode VCC 68 — f OSC = 4 MHz Current dissipation I WTC in watch mode VSTOP — — f OSC = 4 MHz Current dissipation I SBY in standby mode Stop mode retaining voltage –0.3 — — 320 µA — — 20 µA 4, 6 VCC = 5 V, 4 32 kHz oscillator — — 10 µA X1 = GND, 4, 5 X2 = Open VCC — — 20 µA 2 — — V 4, 6 HD404339 Series Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. I CC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at GND R0, R30 to R72 at V CC D0–D 13 , R1, R2, R8, R9, RA 1 at V disp 3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at V CC TEST at GND R0, R30 to R72 at V CC D0–D 13 , R1, R2, R8, R9, RA 1 at V disp 4. This is the source current when no I/O current is flowing. Test conditions: Pins: R0, R30 to R72 at V CC D0–D 13 , R1, R2, R8, R9, RA 1 at GND 5. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. 6. Applies to the HD4074339. 69 HD404339 Series I/O Characteristics for High-Voltage Pins (V CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC – 40 V to VCC, T a = –20 to +75°C, unless otherwise specified) Item Symbol Input high voltage VIH Pins Min Typ Max D0–D 13 , R1, 0.7V CC — Unit Test Condition Note VCC + 0.3 V R2, R8, R9, RA 1 Input low voltage VIL D0–D 13 , R1, VCC – 40 — 0.3V CC V VCC – 3.0 — — V –I OH = 15 mA VCC – 2.0 — — V –I OH = 10 mA VCC – 1.0 — — V –I OH = 4 mA — — VCC – 37 V Vdisp = VCC – 40 V 1 — — VCC – 37 V 150 kΩ at V CC – 40 V 2 — — 20 µA Vin = VCC – 40 V to VCC 3 200 600 1000 µA Vdisp = VCC – 35 V, 1 R2, R8, R9, RA 1 Output high voltage VOH D0–D 13 , R1, R2, R8, R9, BUZZ Output low voltage VOL D0–D 13 , R1, R2, R8, R9, BUZZ I/O leakage current |IIL| D0–D 13 , R1, R2, R8, R9, RA 1, BUZZ Pull-down MOS current I PD D0–D 13 , R1, R2, R8, R9 Vin = VCC Notes: 1. Applies to pins with pull-down MOS as selected by the mask option . 2. Applies to pins without pull-down MOS as selected by the mask option. 3. Excludes output buffer current. 70 HD404339 Series A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC – 40 V to VCC, Ta = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Analog supply voltage AVCC AVCC Analog input voltage AVin AN 0–AN 11 Max Unit VCC – 0.3 VCC VCC + 0.3 V AVSS — AVCC V — — 200 µA — — 30 pF Resolution 8 8 8 Bit Number of input channels 0 — 12 Channel Absolute accuracy — — ±2.0 LSB Conversion time 34 — 67 t cyc 1 — — MΩ Current flowing I AD between AV CC and AVSS Analog input capacitance Input impedance CA in AN 0–AN 11 AN 0–AN 11 Typ Test Condition Note 1 VCC = AVCC = 5.0 V Note: 1. Connect this to V CC if the A/D converter is not used. 71 HD404339 Series AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, T a = –20 to +75°C) Item Symbol Pins Clock oscillation frequency f OSC Instruction cycle time Min Typ Max Unit OSC 1, OSC 2 0.4 4 4.5 MHz X1, X2 — 32.768 — kHz t cyc 0.89 1 10 µs t subcyc — 244.14 — µs Test Condition Note System clock 1 divided by 4 1 32-kHz oscillator, 1/8 system clock division ratio — 122.07 — µs 32-kHz oscillator, 1/4 system clock division ratio Oscillation stabilization time t RC (ceramic oscillator) OSC 1, OSC 2 — — 7.5 ms 2 Oscillation stabilization time t RC (crystal oscillator) OSC 1, OSC 2 — — 40 ms 2 X1, X2 — — 2 s 2 External clock high width t CPH OSC 1 92 — — ns 3 External clock low width t CPL OSC 1 92 — — ns 3 External clock rise time t CPr OSC 1 — — 20 ns 3 External clock fall time t CPf OSC 1 — — 20 ns 3 INT0, INT1, EVNB high widths t IH INT0, INT1, 2 — — t cyc / 4 EVNB INT0, INT1, EVNB low widths t IL INT0, INT1, t subcyc 2 — — EVNB t cyc / 4 t subcyc RESET low width t RSTL RESET 2 — — t cyc 5 STOPC low width t STPL STOPC 1 — — t RC 6 RESET rise time t RSTr RESET — — 20 ms 5 STOPC rise time t STPr STOPC — — 20 ms 6 Input capacitance Cin All input — pins except TEST — 30 pF TEST — — f = 1 MHz, Vin = 0 V 30 pF f = 1 MHz, 7 Vin = 0 V — — 180 pF 8 Notes: 1. When using the subsystem oscillator (32.768 kHz), one of the following relationships for f OSC must be applied. 0.4 MHz ≤ fOSC ≤ 1.0 MHz or 1.6 MHz ≤ fOSC ≤ 4.5 MHz The operating range for fOSC can be set with bit 1 of system selection register 1 (SSR1: $027). 2. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: 72 HD404339 Series 3. 4. 5. 6. 7. 8. a. After V CC reaches 4.0 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of t RC. When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. Refer to figure 56. Refer to figure 57. Refer to figure 58. Refer to figure 59. Applies to the HD404334, HD404336, HD404338, HD4043312, and HD404339. Applies to the HD4074339. Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, T a = –20 to +75°C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1 — — t cyc Load shown in figure 61 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc Load shown in figure 61 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc Load shown in figure 61 1 Transmit clock rise time t SCKr SCK — — 80 ns Load shown in figure 61 1 Transmit clock fall time t SCKf SCK — — 80 ns Load shown in figure 61 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 61 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time t Scyc SCK 1 — — t cyc 1 Transmit clock high width t SCKH SCK 0.4 — — t Scyc 1 Transmit clock low width t SCKL SCK 0.4 — — t Scyc 1 Transmit clock rise time t SCKr SCK — — 80 ns 1 Transmit clock fall time t SCKf SCK — — 80 ns 1 Serial output data delay time t DSO SO — — 300 ns Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time t HSI SI 200 — — ns 1 Note: Load shown in figure 61 1 1. Refer to figure 60. 73 HD404339 Series OSC1 1/fCP VCC – 0.5 V tCPL tCPH 0.5 V tCPr tCPf Figure 56 External Clock Timing INT0, INT1, EVNB 0.8VCC tIL tIH 0.2VCC Figure 57 Interrupt Timing RESET 0.8VCC tRSTL 0.2VCC tRSTr Figure 58 RESET Timing STOPC 0.8VCC tSTPL 0.2VCC tSTPr Figure 59 STOPC Timing 74 HD404339 Series t Scyc t SCKf SCK VCC – 2.0 V (0.8VCC )* 0.8 V (0.2VCC)* t SCKr t SCKL t SCKH t DSO VCC – 2.0 V 0.8 V SO t SSI t HSI 0.8V CC 0.2VCC SI Note: * VCC – 2.0 V and 0.8 V are the threshold voltages for transmit clock output, and 0.8VCC and 0.2VCC are the threshold voltages for transmit clock input. Figure 60 Serial Interface Timing VCC RL = 2.6 kΩ Test point C= 30 pF R= 12 kΩ Hitachi 1S2074 or equivalent Figure 61 Timing Load Circuit 75 HD404339 Series Notes on ROM Out Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404334 and HD404336 as an 8-kword version (HD404338), and to create the same data size for the HD4043312 as a 16-kword version (HD404339). The 8-kword and 16-kword data sizes are required to change ROM data to mask manufacturing data since the program used is for an 8-k or 16-kword version. This limitation applies when using an EPROM or a data base. ROM 4-kword version: HD404334 Address $1000–$1FFF $0000 $0000 Vector address Vector address Zero-page subroutine (64 words) Zero-page subroutine (64 words) Pattern & program (4,096 words) Pattern & program (6,144 words) Not used Fill this area with 1s Pattern & program (12,288 words) $2FFF $3000 Not used $1FFF $1FFF Zero-page subroutine (64 words) $003F $0040 $17FF $1800 $0FFF $1000 Vector address $000F $0010 $003F $0040 $003F $0040 76 $0000 $000F $0010 $000F $0010 ROM 12-kword version: HD4043312 Address $3000–$3FFF ROM 6-kword version: HD404336 Address $1800–$1FFF Not used $3FFF HD404339 Series HD404334/HD404336/HD404338/HD4043312/HD404339 Option List Please check off the appropriate applications and enter the necessary information. 1. ROM Size Date of order HD404334 4-kword Customer HD404336 6-kword Department HD404338 8-kword Name HD4043312 12-kword ROM code name HD404339 16-kword LSI number 2. Optional Functions * With 32-kHz CPU operation, with time base for clock * Without 32-kHz CPU operation, with time base for clock Without 32-kHz CPU operation, without time base Note: *Options marked with an asterisk require a subsystem crystal oscillator (X1, X2). 3. I/O Options D: Without pull-down resistance Pin name D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC D5 D6 D7 D8 D9 D10 D11 D12 D13 E: With pull-down resistance I/O option I/O D E I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin name R1 R2 R8 R9 4. RA1/Vdisp R10 R11 R12 R13 R20 R21 R22 R23 R80 R81 R82 R83 R90 R91 R92 R93 I/O I/O option D E I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RA1 without pull-down resistance Vdisp Note: If even only one pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. 5. ROM Code Media Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits are programmed to the same EPROM in alternating order (i.e., LULULU...). EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. 7. Stop Mode 6. System Oscillator (OSC1, OSC2) 8. Package Ceramic oscillator f= MHz Used FP-64B Crystal oscillator f= MHz Not used DP-64S External clock f= MHz 77 HD404339 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 78