MCP6021/1R/2/3/4 Rail-to-Rail Input/Output, 10 MHz Op Amps Features Description • • • • The MCP6021, MCP6021R, MCP6022, MCP6023 and MCP6024 from Microchip Technology Inc. are rail-torail input and output op amps with high performance. Key specifications include: wide bandwidth (10 MHz), low noise (8.7 nV/√Hz), low input offset voltage and low distortion (0.00053% THD+N). The MCP6023 also offers a Chip Select pin (CS) that gives power savings when the part is not in use. • • • • • • Rail-to-Rail Input/Output Wide Bandwidth: 10 MHz (typ.) Low Noise: 8.7 nV/√Hz, at 10 kHz (typ.) Low Offset Voltage: - Industrial Temperature: ±500 µV (max.) - Extended Temperature: ±250 µV (max.) Mid-Supply VREF: MCP6021 and MCP6023 Low Supply Current: 1 mA (typ.) Total Harmonic Distortion: 0.00053% (typ., G = 1) Unity Gain Stable Power Supply Range: 2.5V to 5.5V Temperature Range: - Industrial: -40°C to +85°C - Extended: -40°C to +125°C Typical Applications • • • • • • • • • The single MCP6021 and MCP6021R are available in SOT-23-5. The single MCP6021, single MCP6023 and dual MCP6022 are available in 8-lead PDIP, SOIC and TSSOP. The Extended Temperature single MCP6021 is available in 8-lead MSOP. The quad MCP6024 is offered in 14-lead PDIP, SOIC and TSSOP packages. The MCP6021/1R/2/3/4 family is available in Industrial and Extended temperature ranges. It has a power supply range of 2.5V to 5.5V. Package Types Automotive Driving A/D Converters Multi-Pole Active Filters Barcode Scanners Audio Processing Communications DAC Buffer Test Equipment Medical Instrumentation MCP6021 SOT-23-5 VOUT 1 VSS 2 VIN+ 3 MCP6022 PDIP SOIC, TSSOP 5 VDD VOUTA 1 VINA– 2 4 VIN– VINA+ 3 VSS 4 MCP6021R SOT-23-5 VOUT 1 Available Tools • SPICE Macro Model (at www.microchip.com) • FilterLab® software (at www.microchip.com) Typical Application 5.6 pF Photo Detector VDD 2 VIN+ 3 VIN– 2 MCP6021 VDD/2 6 VINB– 5 VINB+ MCP6023 PDIP SOIC, TSSOP NC 1 VIN– 2 VIN+ 3 8 CS 7 VDD VSS 4 5 VREF 6 VOUT MCP6024 PDIP SOIC, TSSOP MSOP, TSSOP VIN+ 3 VSS 4 100 pF 4 VIN– MCP6021 PDIP SOIC, NC 1 100 kΩ 5 VSS 8 VDD 7 VOUTB 8 NC 7 VDD VOUTA 1 6 VOUT VINA– 2 VINA+ 3 5 V REF VDD 4 VINB+ 5 VINB– 6 VOUTB 7 14 VOUTD 13 VIND– 12 VIND+ 11 VSS 10 VINC+ 9 VINC– 8 VOUTC Transimpedance Amplifier © 2006 Microchip Technology Inc. DS21685C-page 1 MCP6021/1R/2/3/4 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD – VSS ........................................................................7.0V All Inputs and Outputs .................... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short Circuit Current ..................................continuous Current at Input Pins ....................................................±2 mA Current at Output and Supply Pins ............................±30 mA Storage Temperature.....................................-65°C to +150°C Junction Temperature.................................................. +150°C ESD Protection on all pins (HBM; MM) ................ ≥ 2 kV; 200V DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2 and RL = 10 kΩ to VDD/2. Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage: Industrial Temperature Parts VOS -500 — +500 µV Extended Temperature Parts VOS -250 — +250 µV VCM = 0V, VDD = 5.0V Extended Temperature Parts VOS -2.5 — +2.5 mV VCM = 0V, VDD = 5.0V TA = -40°C to +125°C ΔVOS/ΔTA — ±3.5 — PSRR 74 90 — Input Offset Voltage Temperature Drift Power Supply Rejection Ratio VCM = 0V µV/°C TA = -40°C to +125°C dB VCM = 0V Input Current and Impedance IB — 1 — pA Industrial Temperature Parts IB — 30 150 pA TA = +85°C Extended Temperature Parts IB — 640 5,000 pA TA = +125°C Input Offset Current IOS — ±1 — pA Common-Mode Input Impedance ZCM — 1013||6 — Ω||pF Differential Input Impedance ZDIFF — 1013||3 — Ω||pF Common-Mode Input Range VCMR VSS-0.3 — VDD+0.3 V Common-Mode Rejection Ratio CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 5.3V CMRR 70 85 — dB VDD = 5V, VCM = 3.0V to 5.3V CMRR 74 90 — dB VDD = 5V, VCM = -0.3V to 3.0V Input Bias Current Common-Mode Voltage Reference (MCP6021 and MCP6023 only) VREF Accuracy (VREF – VDD/2) VREF_ACC -50 — +50 VREF Temperature Drift ΔVREF/ΔTA — ±100 — mV AOL 90 110 — dB VCM = 0V, VOUT = VSS+0.3V to VDD-0.3V VOL, VOH VSS+15 — VDD-20 mV 0.5V output overdrive µV/°C TA = -40°C to +125°C Open-Loop Gain DC Open-Loop Gain (Large Signal) Output Maximum Output Voltage Swing ISC — ±30 — mA VDD = 2.5V ISC — ±22 — mA VDD = 5.5V Supply Voltage VS 2.5 — 5.5 V Quiescent Current per Amplifier IQ 0.5 1.0 1.35 mA Output Short Circuit Current Power Supply DS21685C-page 2 IO = 0 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units GBWP — 10 — MHz PM — 65 — ° tSETTLE — 250 — ns SR — 7.0 — V/µs Conditions AC Response Gain Bandwidth Product Phase Margin at Unity-Gain Settling Time, 0.2% Slew Rate G = +1 G = +1, VOUT = 100 mVp-p Total Harmonic Distortion Plus Noise f = 1 kHz, G = +1 V/V THD+N — 0.00053 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK), VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +1 V/V, RL = 600Ω THD+N — 0.00064 — % VOUT = 0.25V to 3.25V (1.75V ± 1.50VPK), VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +1 V/V THD+N — 0.0014 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +10 V/V THD+N — 0.0009 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz f = 1 kHz, G = +100 V/V THD+N — 0.005 — % VOUT = 4VP-P, VDD = 5.0V, BW = 22 kHz Input Noise Voltage Eni — 2.9 — µVp-p Input Noise Voltage Density eni — 8.7 — nV/√Hz f = 10 kHz Input Noise Current Density ini — 3 — fA/√Hz Noise f = 0.1 Hz to 10 Hz f = 1 kHz MCP6023 CHIP SELECT (CS) ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units CS Logic Threshold, Low VIL VSS — 0.2 VDD V CS Input Current, Low ICSL -1.0 0.01 — µA CS Logic Threshold, High VIH 0.8 VDD — VDD V CS Input Current, High ICSH — 0.01 2.0 µA Conditions CS Low Specifications CS = VSS CS High Specifications GND Current CS = VDD ISS -2 -0.05 — µA CS = VDD IO(LEAK) — 0.01 — µA CS = VDD CS Low to Amplifier Output Turn-on Time tON — 2 10 µs G = +1, VIN = VSS, CS = 0.2VDD to VOUT = 0.45VDD time CS High to Amplifier Output High-Z Time tOFF — 0.01 — µs G = +1, VIN = VSS, CS = 0.8VDD to VOUT = 0.05VDD time VHYST — 0.6 — V VDD = 5.0V, Internal Switch Amplifier Output Leakage CS Dynamic Specifications Hysteresis © 2006 Microchip Technology Inc. DS21685C-page 3 MCP6021/1R/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Industrial Temperature Range TA -40 Extended Temperature Range TA -40 — +85 °C — +125 °C Operating Temperature Range TA Storage Temperature Range TA -40 — +125 °C -65 — +150 °C Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W Thermal Resistance, 8L-PDIP θJA — 85 — °C/W Thermal Resistance, 8L-SOIC θJA — 163 — °C/W Thermal Resistance, 8L-MSOP θJA — 206 — °C/W Thermal Resistance, 8L-TSSOP θJA — 124 — °C/W Thermal Resistance, 14L-PDIP θJA — 70 — °C/W Thermal Resistance, 14L-SOIC θJA — 120 — °C/W Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: The industrial temperature devices operate over this extended temperature range, but with reduced performance. In any case, the internal junction temperature (TJ) must not exceed the absolute maximum specification of 150°C. CS tON tOFF Amplifier On High-Z ISS -50 nA (typ.) -1 mA (typ.) -50 nA (typ.) ICS 10 nA (typ.) 10 nA (typ.) VOUT High-Z 10 nA (typ.) FIGURE 1-1: Timing diagram for the CS pin on the MCP6023. DS21685C-page 4 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Input Offset Voltage (µV) Input Offset Voltage (µV) FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 2.5V. © 2006 Microchip Technology Inc. 20 20 16 8 4 12 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 Input Offset Voltage (µV) Input Offset Voltage (µV) 3.0 0.5 2.5 -40°C +25°C +85°C +125°C VDD = 5.5V 0.0 2.0 Common Mode Input Voltage (V) 500 400 300 200 100 0 -100 -200 -300 -400 -500 -0.5 1.5 0 FIGURE 2-5: Input Offset Voltage Drift, (Extended Temperature Parts). -40°C +25°C +85°C +125°C 1.0 -4 Input Offset Voltage Drift (µV/°C) FIGURE 2-2: Input Offset Voltage, (Extended Temperature Parts). 500 400 VDD = 2.5V 300 200 100 0 -100 -200 -300 -400 -500 -0.5 0.0 0.5 438 Samples VCM = 0V TA = -40°C to +125°C -8 E-Temp Parts -16 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -20 240 200 160 120 80 0 40 -40 -80 Percentage of Occurances FIGURE 2-4: Input Offset Voltage Drift, (Industrial Temperature Parts). 438 Samples VDD = 5.0V VCM = 0V TA = +25°C -120 -160 -200 -240 Percentage of Occurances E-Temp Parts 16 Input Offset Voltage Drift (µV/°C) FIGURE 2-1: Input Offset Voltage, (Industrial Temperature Parts). 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 12 500 400 300 200 100 0 -100 -200 -300 -400 -500 0% 8 2% 4 4% 0 6% -4 8% 1192 Samples VCM = 0V TA = -40°C to +85°C -8 10% I-Temp Parts -12 12% 24% 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -12 1192 Samples VCM = 0V TA = +25°C 1.0 I-Temp Parts -16 14% -20 Percentage of Occurances 16% Percentage of Occurances Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. Common Mode Input Voltage (V) FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. DS21685C-page 5 MCP6021/1R/2/3/4 100 200 50 150 Input Offset Voltage (µV) 0 -50 -100 -150 -200 VDD = 5.0V VCM = 0V -250 VDD = 5.5V 50 0 VDD = 2.5V -50 -100 -150 Output Voltage (V) FIGURE 2-10: Output Voltage. FIGURE 2-8: vs. Frequency. 1.E+02 1.E+03 1.E+04 100 1k 10k Frequency (Hz) 1.E+05 1.E+06 100k 1M 5.5 1.E+01 10 5.0 1.E+00 1 4.5 1.E-01 0.1 f = 10 kHz 4.0 1 f = 1 kHz 3.5 10 VDD = 5.0V 3.0 100 24 22 20 18 16 14 12 10 8 6 4 2 0 -0.5 Input Noise Voltage Density (nV/√Hz) 1,000 Input Offset Voltage vs. 2.5 Input Offset Voltage vs. 2.0 FIGURE 2-7: Temperature. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 125 1.5 0 25 50 75 100 Ambient Temperature (°C) 1.0 -25 0.5 -50 Input Noise Voltage Density (nV/√Hz) 100 -200 -300 Common Mode Input Voltage (V) Input Noise Voltage Density FIGURE 2-11: Input Noise Voltage Density vs. Common Mode Input Voltage. 110 100 PSRR+ PSRR- 105 PSRR, CMRR (dB) 90 CMRR, PSRR (dB) VCM = VDD/2 0.0 Input Offset Voltage (µV) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. 80 70 60 CMRR 50 40 CMRR 100 95 90 PSRR (VCM = 0V) 85 80 75 30 20 100 1.E+02 70 1.E+03 1k 1.E+04 10k 1.E+05 100k 1.E+06 1M -50 -25 Frequency (Hz) FIGURE 2-9: Frequency. DS21685C-page 6 CMRR, PSRR vs. FIGURE 2-12: Temperature. 0 25 50 75 100 Ambient Temperature (°C) 125 CMRR, PSRR vs. © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 10,000 10,000 VDD = 5.5V 1,000 IB, TA = +125°C IOS, TA = +125°C IB, TA = +85°C 100 10 IOS, TA = +85°C Input Bias, Offset Currents (pA) 1,000 IOS 10 1 1 25 35 45 55 65 75 85 95 105 115 125 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 +125°C +85°C +25°C -40°C Ambient Temperature (°C) FIGURE 2-16: vs. Temperature. Quiescent Current (mA/amplifier) FIGURE 2-13: Input Bias, Offset Currents vs. Common Mode Input Voltage. Quiescent Current (mA/amplifier) IB 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-14: Supply Voltage. Quiescent Current vs. 20 15 +125°C +85°C +25°C -40°C 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage (V) FIGURE 2-15: Output Short-Circuit Current vs. Supply Voltage. © 2006 Microchip Technology Inc. Open-Loop Gain (dB) 30 25 VDD = 2.5V VCM = VDD - 0.5V -25 FIGURE 2-17: Temperature. 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -20 1.E+00 1 Input Bias, Offset Currents VDD = 5.5V -50 35 Output Short Circuit Current (mA) VCM = VDD VDD = 5.5V 0 25 50 75 100 Ambient Temperature (°C) Quiescent Current vs. 0 -15 -30 -45 -60 -75 Phase -90 -105 -120 -135 -150 Gain -165 -180 -195 -210 10 100 1k 10k 100k 1M 10M 100M 1.E+01 125 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 Open-Loop Phase (°) Input Bias, Offset Currents (pA) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. 1.E+08 Frequency (Hz) FIGURE 2-18: Frequency. Open-Loop Gain, Phase vs. DS21685C-page 7 MCP6021/1R/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. 120 VDD = 5.5V DC Open-Loop Gain (dB) 120 110 VDD = 2.5V 100 90 115 110 105 VDD = 2.5V 100 95 90 1.E+02 1.E+03 1.E+04 1.E+05 1k 10k Load Resistance (Ω) FIGURE 2-19: Load Resistance. -50 100k DC Open-Loop Gain vs. 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-22: Temperature. Gain Bandwidth Product (MHz) VCM = VDD/2 110 VDD = 5.5V 100 90 VDD = 2.5V 80 70 0.00 0.05 0.10 0.15 0.20 0.25 0.30 12 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 4 45 30 15 VDD = 5.0V 0 0 FIGURE 2-23: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. Gain Bandwidth Product (MHz) 14 Phase Margin, G = +1 (°) 100 90 80 70 60 50 40 30 20 10 0 125 FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Temperature. DS21685C-page 8 60 Phase Margin, G = +1 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Input Voltage (V) FIGURE 2-20: Small Signal DC Open-Loop Gain vs. Output Voltage Headroom. GBWP, VDD = 5.5V GBWP, VDD = 2.5V PM, VDD = 2.5V PM, VDD = 5.5V 90 75 8 Output Voltage Headroom (V); VDD - VOH or VOL - VSS 10 9 8 7 6 5 4 3 2 1 0 105 Gain Bandwidth Product 10 2 125 DC Open-Loop Gain vs. 14 120 Gain Bandwidth Product (MHz) -25 Phase Margin, G = +1 (°) 80 100 DC Open-Loop Gain (dB) VDD = 5.5V 12 105 Gain Bandwidth Product 10 75 8 Phase Margin, G = +1 6 60 45 4 2 90 30 VDD = 5.0V VCM = VDD/2 15 0 Phase Margin, G = +1 (°) DC Open-Loop Gain (dB) 130 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Voltage (V) FIGURE 2-24: Gain Bandwidth Product, Phase Margin vs. Output Voltage. © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 10 11 10 9 8 7 6 5 4 3 2 1 0 Falling, VDD = 5.5V Rising, VDD = 5.5V Maximum Output Voltage Swing (VP-P) Slew Rate (V/µs) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. Falling, VDD = 2.5V Rising, VDD = 2.5V -50 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-25: 100 1.E+04 THD+N (%) G = +100 V/V G = +10 V/V 0.0100% G = +10 V/V 0.0010% G = +1 V/V f = 20 kHz BWMeas = 80 kHz VDD = 5.0V G = +1 V/V 0.0001% 0.0001% 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Voltage (VP-P) 6 VDD = 5.0V G = +2 V/V 5 VOUT 4 VIN 3 2 1 0 -1 10 20 30 40 50 60 70 Time (10 µs/div) 80 90 100 FIGURE 2-27: The MCP6021/1R/2/3/4 family shows no phase reversal under overdrive. © 2006 Microchip Technology Inc. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Output Voltage (VP-P) FIGURE 2-29: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 20 kHz. Channel to Channel Separation (dB) FIGURE 2-26: Total Harmonic Distortion plus Noise vs. Output Voltage with f = 1 kHz. Input, Output Voltage (V) 1.E+07 10M G = +100 V/V 0.0010% 0 1.E+06 0.1000% f = 1 kHz BWMeas = 22 kHz VDD = 5.0V THD+N (%) 1.E+05 100k 1M Frequency (Hz) FIGURE 2-28: Maximum Output Voltage Swing vs. Frequency. 0.1000% 0.0100% VDD = 2.5V 1 0.1 10k 125 Slew Rate vs. Temperature. VDD = 5.5V 135 130 125 120 115 110 G = +1 V/V 105 1.E+03 1k 1.E+04 1.E+05 10k 100k Frequency (Hz) 1.E+06 1M FIGURE 2-30: Channel-to-Channel Separation vs. Frequency (MCP6022 and MCP6024 only). DS21685C-page 9 MCP6021/1R/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. Output Voltage Headroom VDD-VOH or VOL-VSS (mV) Output Voltage Headroom; VDD-VOH or VOL-VSS (mV) 1,000 100 10 VOL - VSS VDD - VOH 1 0.01 0.1 1 Output Current Magnitude (mA) VOL - VSS VDD - VOH -50 10 FIGURE 2-31: Output Voltage Headroom vs. Output Current. -25 Output Voltage Headroom G = -1 V/V RF = 1 kΩ Output Voltage (10 mV/div) 5.E-02 4.E-02 3.E-02 2.E-02 1.E-02 0.E+00 -1.E-02 -2.E-02 -3.E-02 -4.E-02 4.E-02 3.E-02 2.E-02 1.E-02 0.E+00 -1.E-02 -2.E-02 -3.E-02 -4.E-02 -5.E-02 -5.E-02 -6.E-02 0.E+00 -6.E-02 0.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06 2.E-07 4.E-07 6.E-07 Time (200 ns/div) FIGURE 2-32: Pulse Response. 8.E-07 1.E-06 1.E-06 1.E-06 2.E-06 2.E-06 2.E-06 Time (200 ns/div) Small-Signal Non-inverting FIGURE 2-35: Response. Small-Signal Inverting Pulse 5.0 5.0 G = +1 V/V 4.5 G = -1 V/V RF = 1 kΩ 4.5 4.0 Output Voltage (V) Output Voltage (V) 125 6.E-02 G = +1 V/V 5.E-02 3.5 3.0 2.5 2.0 1.5 1.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-34: vs. Temperature. 6.E-02 Output Voltage (10 mV/div) 10 9 8 7 6 5 4 3 2 1 0 0.5 0.E+00 5.E-07 1.E-06 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 5.E-06 0.0 0.E+00 5.E-07 Time (500 ns/div) FIGURE 2-33: Pulse Response. DS21685C-page 10 Large-Signal Non-inverting 1.E-06 2.E-06 2.E-06 3.E-06 3.E-06 4.E-06 4.E-06 5.E-06 5.E-06 Time (500 ns/div) FIGURE 2-36: Response. Large-Signal Inverting Pulse © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 50 40 30 20 10 0 -10 -20 -30 -40 -50 VREF Accuracy; V REF – V DD/2 (mV) VREF Accuracy; V REF – V DD/2 (mV) Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, RL = 10 kΩ to VDD/2 and CL = 60 pF. 50 40 30 20 10 0 -10 -20 -30 -40 -50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-37: VREF Accuracy vs. Supply Voltage (MCP6021 and MCP6023 only). VDD = 2.5V -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-40: VREF Accuracy vs. Temperature (MCP6021 and MCP6023 only). 1.6 Op Amp shuts off here 1.4 Quiescent Current (mA/amplifier) Op Amp turns on here 1.4 Quiescent Current (mA/amplifier) VDD = 5.5V -50 1.6 1.2 1.0 CS swept high to low 0.8 Hysteresis 0.6 CS swept low to high VDD = 2.5V G = +1 V/V VIN = 1.25V 0.4 0.2 Op Amp turns on here Op Amp shuts off here 1.2 Hysteresis 1.0 0.8 CS swept high to low 0.6 0.4 0.2 VDD = 5.5V G = +1 V/V VIN = 2.75V CS swept low to high 0.0 0.0 0.0 0.5 1.0 1.5 2.0 Chip Select Voltage (V) 2.5 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) FIGURE 2-38: Chip Select (CS) Hysteresis (MCP6023 only) with VDD = 2.5V. Chip Select Voltage, Output Voltage (V) Representative Part FIGURE 2-41: Chip Select (CS) Hysteresis (MCP6023 only) with VDD = 5.5V. VDD = 5.0V G = +1 V/V VIN = VSS CS Voltage VOUT Output on 0.0E+00 5.0E-06 Output on Output High-Z 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 Time (5 µs/div) FIGURE 2-39: Chip Select (CS) to Amplifier Output Response Time (MCP6023 only). © 2006 Microchip Technology Inc. DS21685C-page 11 MCP6021/1R/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6021 (PDIP, MCP6021 MCP6021R SOIC, (SOT-23-5) (SOT-23-5) MCP6022 MCP6023 MCP6024 MSOP, (Note 1) (Note 2) TSSOP) (Note 1) 1 1 1 6 1 2 4 4 2 2 2 VIN–, VINA– Inverting Input (op amp A) 3 3 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) 7 5 2 8 7 4 VDD — — 5 — 5 VINB+ — — 6 — 6 VINB– Inverting Input (op amp B) — — — 7 — 7 VOUTB Analog Output (op amp B) — — — — — 8 VOUTC Analog Output (op amp C) — — — — — 9 VINC– Inverting Input (op amp C) — — — — — 10 VINC+ 4 2 5 4 4 11 VSS — — — — — 12 VIND+ Non-inverting Input (op amp D) Non-inverting Input (op amp B) Non-inverting Input (op amp C) Negative Power Supply — — — — — 13 VIND– Inverting Input (op amp D) — — — — — 14 VOUTD Analog Output (op amp D) 5 — — — 5 — VREF Reference Voltage — — — — 8 — CS Chip Select 1, 8 — — — 1 — NC No Internal Connection The MCP6021 in the 8-pin MSOP package is only available for E-temp (Extended Temperature) parts. The MCP6021 in the 8-pin TSSOP package is only available for I-temp (Industrial Temperature) parts. The MCP6021R is only available in the 5-pin SOT-23 package, and for E-temp (Extended Temperature) parts. Analog Outputs Analog Inputs The op amp non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. VREF Output (MCP6021 and MCP6023) Mid-supply reference voltage provided by the single op amps (except in SOT-23-5 package). This is an unbuffered, resistor voltage divider internal to the part. 3.4 Positive Power Supply — The op amp output pins are low-impedance voltage sources. 3.3 VOUT, VOUTA Analog Output (op amp A) — 2: 3.2 Description 6 Note 1: 3.1 Symbol 3.5 Power Supply (VSS and VDD) The positive power supply pin (VDD) is 2.5V to 5.5V higher than the negative power supply pin (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need a local bypass capacitor (typically 0.01 µF to 0.1 µF) within 2 mm of the VDD pin. These parts need to use a bulk capacitor (typically 1 µF or larger) within 100 mm of the VDD pin; it can be shared with nearby analog parts. CS Digital Input This is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. DS21685C-page 12 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 APPLICATIONS INFORMATION The MCP6021/1R/2/3/4 family of operational amplifiers are fabricated on Microchip’s state-of-the-art CMOS process. They are unity-gain stable and suitable for a wide range of general-purpose applications. 4.1 Rail-to-Rail Input The MCP6021/1R/2/3/4 amplifier family is designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-27 shows an input voltage exceeding both supplies with no resulting phase inversion. The input stage of the MCP6021/1R/2/3/4 family of devices uses two differential input stages in parallel; one operates at low common-mode input voltage (VCM), while the other operates at high VCM. With this topology, the device operates with VCM up to 0.3V past either supply rail (VSS – 0.3V to VDD + 0.3V) at +25°C. The amplifier input behaves linearly as long as VCM is kept within the specified VCMR limits. The input offset voltage is measured at both VCM = VSS – 0.3V and VDD + 0.3V to ensure proper operation. Input voltages that exceed the input voltage range (VCMR) can cause excessive current to flow in or out of the input pins. Current beyond ±2 mA introduces possible reliability problems. Thus, applications that exceed this rating must externally limit the input current with an input resistor (RIN), as shown in Figure 4-1. RIN MCP602X VOUT VIN RIN ≥ RIN ≥ (Maximum expected VIN) - VDD 2 mA VSS - (Minimum expected VIN) FIGURE 4-1: into an input pin. 4.2 4.3 Total Harmonic Distortion Plus Noise (THD+N) can be affected by the common mode input voltage (VCM). As shown in Figure 2-3 and Figure 2-6, the input offset voltage (VOS) is affected by the change from the NMOS to the PMOS input differential pairs. This change in VOS will increase the distortion if the input voltage includes this transition region. This transition occurs between VDD – 1.0V and VDD – 2.0V, depending on VDD and temperature. © 2006 Microchip Technology Inc. Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases, and the closed loop bandwidth is reduced. This produces gain-peaking in the frequency response, with overshoot and ringing in the step response. When driving large capacitive loads with these op amps (e.g., > 60 pF when G = +1), a small series resistor at the output (RISO in Figure 4-2) improves the feedback loop’s phase margin (stability) by making the load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. VIN RISO VOUT MCP602X CL FIGURE 4-2: Output resistor RISO stabilizes large capacitive loads. Figure 4-3 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 2 mA RIN limits the current flow Rail-to-Rail Output The Maximum Output Voltage Swing is the maximum swing possible under a particular output load. According to the specification table, the output can reach within 20 mV of either supply rail when RL = 10 kΩ. See Figure 2-31 and Figure 2-34 for more information concerning typical performance. 1,000 Recommended RISO (Ω) 4.0 GN ≥ +1 100 10 10 100 1,000 10,000 Normalized Capacitance; CL/GN (pF) FIGURE 4-3: Recommended RISO values for capacitive loads. DS21685C-page 13 MCP6021/1R/2/3/4 After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Evaluation on the bench and simulations with the MCP6021/1R/2/3/4 Spice macro model are helpful. 4.4 Gain Peaking Figure 2-35 and Figure 2-36 use RF = 1 kΩ to avoid (frequency response) gain peaking and (step response) overshoot. The capacitance to ground at the inverting input (CG) is the op amp’s common mode input capacitance plus board parasitic capacitance. CG is in parallel with RG, which causes an increase in gain at high frequencies for non-inverting gains greater than 1 V/V (unity gain). CG also reduces the phase margin of the feedback loop for both non-inverting and inverting gains. VIN VOUT 4.5 MCP6023 Chip Select (CS) The MCP6023 is a single amplifier with chip select (CS). When CS is high, the supply current is less than 10 nA (typ) and travels from the CS pin to VSS, with the amplifier output being put into a high-impedance state. When CS is low, the amplifier is enabled. If CS is left floating, the amplifier may not operate properly. Figure 1-1 and Figure 2-39 show the output voltage and supply current response to a CS pulse. 4.6 MCP6021 and MCP6023 Reference Voltage The single op amps (MCP6021 and MCP6023), not in the SOT-23-5 package, have an internal mid-supply reference voltage connected to the VREF pin (see Figure 4-6). The MCP6021 has CS internally tied to VSS, which always keeps the op amp on and always provides a mid-supply reference. With the MCP6023, taking the CS pin high conserves power by shutting down both the op amp and the VREF circuitry. Taking the CS pin low turns on the op amp and VREF circuitry. VDD CG RF RG 50 kΩ VREF FIGURE 4-4: Non-inverting gain circuit with parasitic capacitance. The largest value of RF in Figure 4-4 that should be used is a function of noise gain (see GN in Section 4.3 “Capacitive Loads”) and CG. Figure 4-5 shows results for various conditions. Other compensation techniques may be used, but they tend to be more complicated to the design. Maximum RF (Ω) 1.E+05 100k CS VSS (CS tied internally to VSS for MCP6021) FIGURE 4-6: Simplified internal VREF circuit (MCP6021 and MCP6023 only). GN > +1 V/V See Figure 4-7 for a non-inverting gain circuit using the internal mid-supply reference. The DC-blocking capacitor (CB) also reduces noise by coupling the op amp input to the source. CG = 7 pF CG = 20 pF 10k 1.E+04 50 kΩ 1k 1.E+03 RG CG = 50 pF CG = 100 pF RF 100 1.E+02 1 10 VOUT Noise Gain; GN (V/V) FIGURE 4-5: Non-inverting gain circuit with parasitic capacitance. CB VREF VIN FIGURE 4-7: Non-inverting gain circuit using VREF (MCP6021 and MCP6023 only). DS21685C-page 14 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 To use the internal mid-supply reference for an inverting gain circuit, connect the VREF pin to the non-inverting input, as shown in Figure 4-8. The capacitor CB helps reduce power supply noise on the output. RG RF VOUT VIN 4.9 PCB Surface Leakage In applications where low input bias current is critical, PCB (printed circuit board) surface-leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6021/1R/2/3/4 family’s bias current at +25°C (1 pA, typ). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. Figure 4-10 shows an example of this type of layout. VREF CB Guard Ring FIGURE 4-8: Inverting gain circuit using VREF (MCP6021 and MCP6023 only). VIN– VIN+ If you don’t need the mid-supply reference, leave the VREF pin open. 4.7 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good, high-frequency performance. It also needs a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with nearby analog parts. 4.8 Unused Op Amps ¼ MCP6144 (B) VDD R VDD VDD R FIGURE 4-9: Unused Op Amps. © 2006 Microchip Technology Inc. 1. 2. An unused op amp in a quad package (MCP6024) should be configured as shown in Figure 4-9. These circuits prevent the output from toggling and causing crosstalk. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage, and minimizes the supply current draw of the unused op amp. Circuit B uses the minimum number of components and operates as a comparator; it may draw more current. ¼ MCP6144 (A) FIGURE 4-10: Layout. Example Guard Ring Non-inverting Gain and Unity-Gain Buffer. a) Connect the guard ring to the inverting input pin (VIN–); this biases the guard ring to the common mode input voltage. b) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. Inverting (Figure 4-10) and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors). a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp’s input (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. 4.10 High Speed PCB Layout Due to their speed capabilities, a little extra care in the PCB (Printed Circuit Board) layout can make a significant difference in the performance of these op amps. Good PC board layout techniques will help you achieve the performance shown in Section 1.0 “Electrical Characteristics” and Section 2.0 “Typical Performance Curves”, while also helping you minimize EMC (Electro-Magnetic Compatibility) issues. Use a solid ground plane and connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. DS21685C-page 15 MCP6021/1R/2/3/4 Separate digital from analog, low speed from high speed and low power from high power. This will reduce interference. Keep sensitive traces short and straight. Separating them from interfering components and traces. This is especially important for high-frequency (low rise-time) signals. Sometimes it helps to place guard traces next to victim traces. They should be on both sides of the victim trace, and as close as possible. Connect the guard trace to ground plane at both ends, and in the middle for long traces. Use coax cables (or low inductance wiring) to route signal and power to and from the PCB. 4.11 4.11.2 OPTICAL DETECTOR AMPLIFIER Figure 4-12 shows the MCP6021 op amp used as a transimpedance amplifier in a photo detector circuit. The photo detector looks like a capacitive current source, so the 100 kΩ resistor gains the input signal to a reasonable level. The 5.6 pF capacitor stabilizes this circuit and produces a flat frequency response with a bandwidth of 370 kHz. 5.6 pF Photo Detector 100 kΩ 100 pF Typical Applications MCP6021 4.11.1 A/D CONVERTER DRIVER AND ANTI-ALIASING FILTER Figure 4-11 shows a third-order Butterworth filter that can be used as an A/D converter driver. It has a bandwidth of 20 kHz and a reasonable step response. It will work well for conversion rates of 80 ksps and greater (it has 29 dB attenuation at 60 kHz). VDD/2 FIGURE 4-12: Transimpedance Amplifier for an Optical Detector. 1.0 nF 8.45 kΩ 14.7 kΩ 33.2 kΩ 1.2 nF 100 pF MCP602X FIGURE 4-11: A/D converter driver and anti-aliasing filter with a 20 kHz cutoff frequency. This filter can easily be adjusted to another bandwidth by multiplying all capacitors by the same factor. Alternatively, the resistors can all be scaled by another common factor to adjust the bandwidth. DS21685C-page 16 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 5.0 DESIGN TOOLS Microchip provides the basic design tools needed for the MCP6021/1R/2/3/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model available for the MCP6021/1R/2/3/4 op amps is on Microchip’s web site at www.microchip.com. This model is intended as an initial design tool that works well in the op amp’s linear region of operation at room temperature. Within the macro model file is information on its capabilities. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative tool that simplifies analog active filter (using op amps) design. It is available free of charge from our web site at www.microchip.com. The FilterLab software tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. © 2006 Microchip Technology Inc. DS21685C-page 17 MCP6021/1R/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: (E-temp) 5-Lead SOT-23 (MCP6021/MCP6021R) Device XXNN E-Temp Code MCP6021 EYNN MCP6021R EZNN EY25 Note: Applies to 5-Lead SOT-23 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: MCP6021 I/P256 0331 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN MCP6021 e3 E/P^^256 0549 OR Example: MCP6021 I/SN0331 256 OR MCP6021E e3 SN^^0549 256 Example: 8-Lead MSOP 6021E XXXXXX YWWNNN 549256 Example: 8-Lead TSSOP XXXX 6021 YYWW E549 NNN 256 Legend: XX...X Y YY WW NNN e3 * Note: DS21685C-page 18 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 Package Marking Information (Continued) 14-Lead PDIP (300 mil) (MCP6024) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN MCP6024-I/P XXXXXXXXXXXXXX 0331256 MCP6024 E/P^^ e3 0549256 OR 14-Lead SOIC (150 mil) (MCP6024) Example: MCP6024ISL XXXXXXXXXX 0331256 XXXXXXXXXX XXXXXXXXXX YYWWNNN MCP6024 e3 E/SL^^ 0549256 OR 14-Lead TSSOP (MCP6024) Example: XXXXXX YYWW 6024E 0331 NNN 256 © 2006 Microchip Technology Inc. DS21685C-page 19 MCP6021/1R/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) E E1 p B p1 n D 1 α c A φ L β A1 INCHES* Units Dimension Limits MIN MILLIMETERS NOM MAX Pitch n p .038 Outside lead pitch (basic) p1 .075 Number of Pins Overall Height A2 MIN NOM 5 MAX 5 0.95 1.90 A .035 .046 .057 0.90 1.18 1.45 Molded Package Thickness A2 .035 .043 .051 0.90 1.10 1.30 Standoff A1 .000 .003 .006 0.00 0.08 0.15 Overall Width E .102 .110 .118 2.60 2.80 3.00 Molded Package Width E1 .059 .064 .069 1.50 1.63 1.75 Overall Length D .110 .116 .122 2.80 2.95 3.10 Foot Length L f .014 .018 .022 0.35 Foot Angle Lead Thickness c .004 Lead Width B a .014 Mold Draft Angle Top Mold Draft Angle Bottom b 0 5 10 0.45 0 0.55 5 .006 .008 0.09 0.15 .017 .020 0.35 0.43 10 0.20 0.50 0 5 10 0 5 10 0 5 10 0 5 10 * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Revised 09-12-05 Drawing No. C04-091 DS21685C-page 20 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 © 2006 Microchip Technology Inc. DS21685C-page 21 MCP6021/1R/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21685C-page 22 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c β φ L Units Dimension Limits A2 A1 MILLIMETERS* INCHES MIN NOM MAX MIN NOM MAX Pitch n p Overall Height A .039 .041 .043 1.00 1.05 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Number of Pins 8 8 .026 0.65 Standoff A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L φ .020 .024 .028 0.50 0.60 0.70 Foot Angle Lead Thickness c .004 .006 .008 0.09 0.15 0.20 Lead Width B α .007 .010 .012 0.19 0.25 0.30 Mold Draft Angle Top Mold Draft Angle Bottom β 0° 4° 8° 0° 4° 8° 0° 5° 10° 0° 5° 10° 0° 5° 10° 0° 5° 10° * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 © 2006 Microchip Technology Inc. Revised 07-21-05 DS21685C-page 23 MCP6021/1R/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E E1 p D 2 B n 1 α c φ L F A2 A A1 β Units Dimension Limits INCHES MILLIMETERS* NOM MIN MIN MAX NOM MAX Pitch n p Overall Height A - - .043 - - 1.10 Molded Package Thickness A2 .030 .033 .037 0.75 0.85 0.95 Standoff A1 .000 - .006 0.00 - 0.15 Overall Width E .193 BSC 4.90 BSC Molded Package Width E1 .118 BSC 3.00 BSC Overall Length D .118 BSC Foot Length L 0.60 0.80 Footprint (Reference) Foot Angle F φ Lead Thickness c .003 .006 .009 0.08 - 0.23 Lead Width B α .009 .012 .016 0.22 - 0.40 Mold Draft Angle Top Mold Draft Angle Bottom β Number of Pins 8 8 .026 BSC .016 0.65 BSC 3.00 BSC .024 .031 0.40 .037 REF 0° 0.95 REF - 8° 0° - 8° 5° - 15° 5° - 15° 5° - 15° 5° - 15° * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-187 Drawing No. C04-111 DS21685C-page 24 Revised 07-21-05 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 14-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 eB p B Units Dimension Limits n p MIN INCHES* NOM 14 .100 .155 .130 MAX MILLIMETERS NOM 14 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 18.80 19.05 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width .240 .250 .260 E1 Overall Length D .740 .750 .760 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing § eB .310 .370 .430 α Mold Draft Angle Top 5 10 15 β 5 10 15 Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-005 © 2006 Microchip Technology Inc. MAX 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 DS21685C-page 25 MCP6021/1R/2/3/4 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 α h 45° c A2 A φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .150 .337 .010 .016 0 .008 .014 0 0 INCHES* NOM 14 .050 .061 .056 .007 .236 .154 .342 .015 .033 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .347 .020 .050 8 .010 .020 15 15 MILLIMETERS NOM 14 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 5.99 3.81 3.90 8.56 8.69 0.25 0.38 0.41 0.84 0 4 0.20 0.23 0.36 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 8.81 0.51 1.27 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-065 DS21685C-page 26 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A φ c β L Units Dimension Limits A1 A2 MILLIMETERS* INCHES MIN NOM MAX MIN NOM MAX Pitch n p Overall Height A .039 .041 .043 1.00 1.05 1.10 Molded Package Thickness A2 .033 .035 .037 0.85 0.90 0.95 Standoff A1 .002 .004 .006 0.05 0.10 0.15 Overall Width E .246 .251 .256 6.25 6.38 6.50 Number of Pins 14 14 .026 BSC 0.65 BSC Molded Package Width E1 .169 .173 .177 4.30 4.40 4.50 Molded Package Length D .193 .197 .201 4.90 5.00 5.10 Foot Length .020 .024 .028 0.50 0.60 0.70 Foot Angle L φ Lead Thickness c .004 Lead Width B α .007 Mold Draft Angle Top Mold Draft Angle Bottom β 4° 0° 8° 0° .006 .008 0.09 .010 .012 0.19 4° 8° 0.15 0.20 0.25 0.30 12° REF 12° REF 12° REF 12° REF * Controlling Parameter Notes: Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tole rance, for information purposes only. See ASME Y14.5M JEDEC Equivalent: MO-153 AB-1 Drawing No. C04-087 © 2006 Microchip Technology Inc. Revised: 08-17-05 DS21685C-page 27 MCP6021/1R/2/3/4 NOTES: DS21685C-page 28 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 APPENDIX A: REVISION HISTORY Revision C (March 2006) The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. 8. Added SOT-23-5 package option for single op amps MCP6021 and MCP6021R (E-temp only). Added MSOP-8 package option for E-temp single op amp (MCP6021). Corrected package drawing on front page for dual op amp (MCP6022). Clarified spec conditions (ISC, PM and THD+N) in Section 2.0 “Typical Performance Curves”. Added Section 3.0 “Pin Descriptions”. Updated Section 4.0 “Applications information” for THD+N, unused op amps, and gain peaking discussions. Corrected and updated package marking information in Section 6.0 “Packaging Information”. Added Appendix A: “REVISION HISTORY”. Revision B (November 2003) • Second Release of this Document Revision A (November 2001) • Original Release of this Document © 2006 Microchip Technology Inc. DS21685C-page 29 MCP6021/1R/2/3/4 NOTES: DS21685C-page 30 © 2006 Microchip Technology Inc. MCP6021/1R/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Examples: a) b) Device: MCP6021 MCP6021T Single Op Amp Single Op Amp (Tape and Reel for SOT-23, SOIC, TSSOP, MSOP) MCP6021R Single Op Amp MCP6021RT Single Op Amp (Tape and Reel for SOT-23) MCP6022 Dual Op Amp MCP6022T Dual Op Amp (Tape and Reel for SOIC and TSSOP) MCP6023 Single Op Amp w/ CS MCP6023T Single Op Amp w/ CS (Tape and Reel for SOIC and TSSOP) MCP6024 Quad Op Amp MCP6024T Quad Op Amp (Tape and Reel for SOIC and TSSOP) c) a) MCP6021RT-E/OT:Tape and Reel, Extended temperature, 5LD SOT-23. a) MCP6022-I/P: b) c) a) b) Temperature Range: Package: I E = -40°C to +85°C = -40°C to +125°C OT = Plastic Small Outline Transistor (SOT-23), 5-lead (MCP6021, E-Temp; MCP6021R, E-Temp) MS = Plastic MSOP, 8-lead (MCP6021, E-Temp) P = Plastic DIP (300 mil Body), 8-lead, 14-lead SN = Plastic SOIC (150mil Body), 8-lead SL = Plastic SOIC (150 mil Body), 14-lead ST = Plastic TSSOP, 8-lead (MCP6021,I-Temp; MCP6022, I-Temp, E-Temp; MCP6023, I-Temp, E-Temp;) ST = Plastic TSSOP, 14-lead © 2006 Microchip Technology Inc. MCP6021T-E/OT: Tape and Reel, Extended temperature, 5LD SOT-23. MCP6021-E/P: Extended temperature, 8LD PDIP. MCP6021-E/SN: Extended temperature, 8LD SOIC. c) a) b) c) Industrial temperature, 8LD PDIP. MCP6022-E/P: Extended temperature, 8LD PDIP. MCP6022T-E/ST: Tape and Reel, Extended temperature, 8LD TSSOP. MCP6023-I/P: Industrial temperature, 8LD PDIP. MCP6023-E/P: Extended temperature, 8LD PDIP. MCP6023-E/SN: Extended temperature, 8LD SOIC. MCP6024-I/SL: Industrial temperature, 14LD SOIC. MCP6024-E/SL: Extended temperature, 14LD SOIC. MCP6024T-E/ST: Tape and Reel, Extended temperature, 14LD TSSOP. DS21685C-page 31 MCP6021/1R/2/3/4 NOTES: DS21685C-page 32 © 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2006 Microchip Technology Inc. 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