ON ADT7460ARQZ-REEL Dbcool remote thermal monitor and fan controller Datasheet

ADT7460
dBCOOLR Remote Thermal
Monitor and Fan Controller
The ADT7460 dBCOOL controller is a thermal monitor and
multiple PWM fan controller for noise−sensitive applications
requiring active system cooling. It can monitor the temperature of up
to two remote sensor diodes plus its own internal temperature. It can
measure and control the speed of up to four fans so that they operate at
the lowest possible speed for minimum acoustic noise. The automatic
fan speed control loop optimizes fan speed for a given temperature. A
unique dynamic T MIN control mode enables the system
thermals/acoustics to be intelligently managed. The effectiveness of
the system’s thermal solution can be monitored using the THERM
input. The ADT7460 also provides critical thermal protection to the
system by using the bidirectional THERM pin as an output to prevent
system or component overheating.
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MARKING
DIAGRAM
T7460A
RQZ
#YYWW
QSOP−16
CASE 492
Features
• Controls and Monitors Up to 4 Fans
• 1 On−Chip and 2 Remote Temperature Sensors
• Dynamic TMIN Control Mode Optimizes System Acoustics
•
•
•
•
•
•
•
•
•
Intelligently
Automatic Fan Speed Control Mode Controls System Cooling
Based on Measured Temperature
Enhanced Acoustic Mode Dramatically Reduces User Perception
of Changing Fan Speeds
Thermal Protection Feature via THERM Output
Monitors Performance Impact of Intel PentiumR 4 Processor
Processor Thermal Control Circuit via THERM Input
2−Wire and 3−Wire Fan Speed Measurement
Limit Comparison of All Monitored Values
Meets SMBus 2.0 Electrical Specifications
(Fully SMBus 1.1−Compliant)
This is a Pb−Free Device
xxx
= Device Code
#
= Pb−Free Package
YYWW = Date Code
PIN ASSIGNMENT
SCL 1
16
SDA
GND 2
15
PWM1/XTO
VCC 3
14
VCCP
ADT7460
13
D1+
TOP VIEW
12
D1–
11
D2+
7
10
D2–
PWM3/ 8
ADDR ENABLE
9
TACH4/ADDR SELECT
/THERM
TACH3 4
PWM2/ 5
SMBALERT
TACH1 6
TACH2
APPLICATIONS
• Low Acoustic Noise PCs
• Networking and Telecommunications Equipment
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 5
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 45 of this data sheet.
1
Publication Order Number:
ADT7460/D
ADT7460
ADDR
SELECT
SCL
ADDR_EN
SMBUS
ADDRESS
SELECTION
PWM1
PWM2
PWM3
PWM REGISTERS
AND
CONTROLLERS
SDA SMBALERT
SERIAL BUS
INTERFACE
ADDRESS
POINTER
REGISTER
AUTOMATIC
FAN SPEED
CONTROL
ACOUSTIC
ENHANCEMENT
CONTROL
PWM
CONFIGURATION
REGISTERS
DYNAMIC
TMIN
CONTROL
TACH1
TACH2
FAN SPEED
COUNTER
TACH3
TACH4
INTERRUPT
MASKING
PERFORMANCE
MONITORING
THERMAL
PROTECTION
THERM
VCC
VCC TO ADT7460
INTERRUPT
STATUS
REGISTERS
ADT7460
D1+
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
D1–
D2+
D2–
+2.5VIN
LIMIT
COMPARATORS
10−BIT
ADC
VALUE AND
LIMIT
REGISTERS
BAND GAP
REFERENCE
BAND GAP
TEMP SENSOR
GND
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
Parameter
Positive Supply Voltage (VCC)
Rating
Unit
6.5
V
−0.3 to +6.5
V
Input Current at Any Pin
±5
mA
Package Input Current
±20
mA
150
°C
−65 to +150
°C
Voltage on Any Input or Output Pin
Maximum Junction Temperature (TJMAX)
Storage Temperature Range
°C
Lead Temperature, Soldering
IR Reflow Peak Temperature
IR Reflow Peak Temperature for Pb−Free
Lead Temperature (Soldering, 10 sec)
220
260
300
ESD Rating
1500
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
THERMAL CHARACTERISTICS
Package Type
16−lead QSOP
qJA
qJC
Unit
150
39
°C/W
1. qJA is specified for the worst−case conditions, that is, a device soldered in a circuit board for surface−mount packages.
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2
ADT7460
PIN ASSIGNMENT
Pin No.
Mnemonic
1
SCL
Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pullup.
2
GND
Ground Pin for the ADT7460.
3
VCC
Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required.
VCC is also monitored through this pin. The ADT7460 can also be powered from a 5.0 V supply.
Setting Bit 7 of Configuration Register 1 (Reg. 0x40) rescales the VCC input attenuators to
correctly measure a 5.0 V supply.
4
TACH3
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be
reconfigured as an analog input (AIN3) to measure the speed of 2−wire fans.
5
PWM2
Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse−width modulated output to
control Fan 2 speed.
SMBALERT
Description
Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to
signal out−of−limit conditions.
6
TACH1
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be
reconfigured as an analog input (AIN1) to measure the speed of 2−wire fans.
7
TACH2
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be
reconfigured as an analog input (AIN2) to measure the speed of 2−wire fans.
8
PWM3
Digital I/O (Open Drain). Pulse−width modulated output to control Fan 3/4 speed. Requires
10 kW typical pullup.
ADDRESS ENABLE
9
TACH4
ADDRESS SELECT
THERM
If pulled low on powerup, this places the ADT7460 into address select mode, and the state of
Pin 9 determines the ADT7460’s slave address.
Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be
reconfigured as an analog input (AIN4) to measure the speed of 2−wire fans.
If in address select mode, this pin determines the SMBus device address.
Alternatively, the pin may be reconfigured as a bidirectional THERM pin. Can be used to time
and monitor assertions on the THERM input. For example, can be connected to the PROCHOT
output of Intel’s Pentium 4 processor or to the output of a trip point temperature sensor. Can be
used as an output to signal overtemperature conditions.
10
D2−
Cathode Connection to Second Thermal Diode.
11
D2+
Anode Connection to Second Thermal Diode.
12
D1−
Cathode Connection to First Thermal Diode.
13
D1+
Anode Connection to First Thermal Diode.
14
+2.5 VIN
Analog Input. Monitors 2.5 V supply, typically a chipset voltage.
SMBALERT
Digital Output (Open Drain). This pin may be reconfigured as an SMBALERT interrupt output to
signal out−of−limit conditions.
15
PWM1/XTO
Digital Output (Open Drain). Pulse−width modulated output to control Fan 1 speed. Requires
10 kW typical pullup.
16
SDA
Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pullup.
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3
ADT7460
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
Parameter (Note 1)
Test Conditions/Comments
Min
Typ (Note 2)
Max
Unit
3.0
5.0
5.5
V
3.0
20
mA
mA
±1.5
±3.0
°C
POWER SUPPLY
Supply Voltage
Supply Current, ICC
Interface inactive, ADC active
Standby mode
TEMPERATURE−TO−DIGITAL CONVERTER
Local Sensor Accuracy
0°C ≤ TA ≤ 70°C
−40°C ≤ TA ≤ +120°C
Resolution
Remote Diode Sensor Accuracy
±1.5
±2.5
±3.0
Resolution
Remote Sensor Source Current
°C
0.25
0°C ≤ TA ≤ 70°C; 0°C ≤ TD ≤ 120°C
0°C ≤ TA ≤ 105°C; 0°C ≤ TD ≤ 120°C
0°C ≤ TA ≤ 120°C; 0°C ≤ TD ≤ 120°C
High level
Low level
°C
0.25
°C
180
11
mA
ANALOG−TO−DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE
Differential Non−linearity, DNL
8 bits
±1.5
%
±1.0
LSB
±0.1
Power Supply Sensitivity
%/V
Conversion Time (Voltage Input)
Averaging enabled
11.38
13
ms
Conversion Time (Local Temperature)
Averaging enabled
12.09
13.50
ms
Conversion Time (Remote Temperature)
Averaging enabled
25.59
28
ms
Total Monitoring Cycle Time
Averaging enabled (incl. delay) (Note 3)
Averaging disabled
120.17
13.51
134.50
15
ms
140
200
kW
±7
±11
±13
%
Input Resistance
80
FAN RPM−TO−DIGITAL CONVERTER
Accuracy
0°C ≤ TA ≤ 70°C
0°C ≤ TA ≤ 105°C
−40°C ≤ TA ≤ +120°C
Full−Scale Count
Nominal Input RPM
65,535
Fan count = 0xBFFF
Fan count = 0x3FFF
Fan count = 0x0438
Fan count = 0x021C
109
329
5000
10000
Internal Clock Frequency
82.8
90.0
RPM
97.2
kHz
8.0
mA
0.4
V
1.0
mA
OPEN−DRAIN DIGITAL OUTPUTS, PWM1–PWM3, XTO
Current Sink, IOL
Output Low Voltage, VOL
IOUT = −8.0 mA, VCC = 3.3 V
High Level Output Current, IOH
VOUT = VCC
0.1
OPEN−DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
IOUT = −4.0 mA, VCC = 3.3 V
High Level Output Current, IOH
VOUT = VCC
0.1
0.4
V
1.0
mA
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.0
V
Input Low Voltage, VIL
0.4
Hysteresis
500
V
mV
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
2.0
V
Maximum input voltage
5.5
Input Low Voltage, VIL
+0.8
Minimum input voltage
Hysteresis
0.5
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4
V
−0.3
Vp−p
ADT7460
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.
Parameter (Note 1)
Test Conditions/Comments
Min
Typ (Note 2)
Max
Unit
DIGITAL INPUT LOGIC LEVELS (THERM)
Input High Voltage, VIH
1.7
V
Input Low Voltage, VIL
0.8
V
DIGITAL INPUT CURRENT
Input High Current, IIH
VIN = VCC
Input Low Current, IIL
VIN = 0
mA
−1.0
mA
+1.0
Input Capacitance, CIN
5.0
pF
SERIAL BUS TIMING (Note 4)
Clock Frequency, fSCLK
Glitch Immunity, tSW
See Figure 2
400
kHz
Bus Free Time, tBUF
See Figure 2
1.3
50
ns
ms
Start Setup Time, tSU;STA
See Figure 2
0.6
ms
Start Hold Time, tHD;STA
See Figure 2
0.6
ms
SCL Low Time, tLOW
See Figure 2
1.3
ms
SCL High Time, tHIGH
See Figure 2
0.6
SCL, SDA Rise Time, tR
See Figure 2
300
ns
SCL, SDA Fall Time, tF
See Figure 2
300
ms
Data Setup Time, tSU;DAT
See Figure 2
100
Detect Clock Low Timeout, tTIMEOUT
Can be optionally disabled
15
35
ms
ms
ns
1. All voltages are measured with respect to GND, unless otherwise specified. Logic inputs accept input high voltages up to VMAX even when
the device is operating below VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and at VIH = 2.0 V for a
rising edge.
2. Typicals are at TA = 25°C and represent the most likely parametric norm.
3. The delay is the time between the round robin finishing one set of measurements and starting the next.
4. Guaranteed by design; not production tested
tLOW
tR
tF
tHD; STA
SCL
tHIGH
tHD; STA
tHD; DAT
tSU; STA
tSU; STO
tSU; DAT
SDA
tBUF
P
S
S
Figure 2. Serial Bus Timing Diagram
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P
ADT7460
TYPICAL PERFORMANCE CHARACTERISTICS
3
15
REMOTE TEMPERATURE ERROR (5C)
REMOTE TEMPERATURE ERROR (5C)
REMOTE TEMPERATURE ERROR (5C)
0
10
DXP TO GND
5
0
–5
DXP TO VCC (3.3V)
–10
–15
−3
−6
−9
−12
−15
−18
−21
−24
−27
−30
−33
−36
–20
1
3.3
10.0
30.0
LEAKAGE RESISTANCE (MΩ)
1
100.0
Figure 3. Remote Temperature Error vs. Leakage
Resistance
LOCAL TEMPERATURE ERROR (5C)
REMOTE TEMPERATURE ERROR (5C)
HIGH LIMIT
+3 SIGMA
0
–3 SIGMA
–1
LOW LIMIT
–2
10
60
TEMPERATURE (5C)
HIGH LIMIT
1
+3 SIGMA
0
–3 SIGMA
–1
–2
14
12.5
12
10.0
10
8
6
250mV
4
2
100mV
0
550k
5M
FREQUENCY (Hz)
LOW LIMIT
10
60
TEMPERATURE (5C)
110
Figure 6. Local Temperature Error vs. Actual
Temperature
LOCAL TEMPERATURE ERROR (5C)
REMOTE TEMPERATURE ERROR (5C)
47.0
2
–3
–40
110
Figure 5. Remote Temperature Error vs. Actual
Temperature
–2
100k
22.0
3
1
–3
–40
3.3
4.7
10.0
DXP–DXN CAPACITANCE (nF)
Figure 4. Remote Temperature Error vs.
Capacitance between D+ and D−
3
2
2.2
7.5
250mV
5.0
2.5
100mV
0
–2.5
–5.0
100k
50M
Figure 7. Remote Temperature Error vs. Power
Supply Noise Frequency
550k
5M
FREQUENCY (Hz)
50M
Figure 8. Local Temperature Error vs. Power
Supply Noise Frequency
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ADT7460
TYPICAL PERFORMANCE CHARACTERISTICS
1.90
1.85
SUPPLY CURRENT (mA)
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
2.6
2.5
3.0
3.4
3.8
4.2
4.6
5.0
5.4
5.5
SUPPLY VOLTAGE (V)
Figure 9. Supply Current vs. Supply Voltage
40
20mV
14
REMOTE TEMPERATURE ERROR (5C)
REMOTE TEMPERATURE ERROR (5C)
16
12
10
8
10mV
6
4
2
0
–2
60k 110k
35
100mV
30
25
20
15
10
40mV
5
0
20mV
–5
1M
FREQUENCY (Hz)
10M
–10
10k
50M
Figure 10. Remote Temperature Error vs.
Differential Mode Noise Frequency
100k
1M
FREQUENCY (Hz)
Figure 11. Remote Temperature Error vs.
Common−Mode Noise Frequency
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10M
ADT7460
Product Description
The ADC also accepts input from an on−chip band gap
temperature sensor, which monitors system ambient
temperature.
The ADT7460 is a thermal monitor and multiple fan
controller for any system requiring monitoring and cooling.
The device communicates with the system via a serial
System Management Bus (SMBus). The serial bus
controller has an optional address line for device selection
(Pin 9), a serial data line for reading and writing addresses
and data (Pin 16), and an input line for the serial clock
(Pin 1). All control and programming functions of the
ADT7460 are performed over the serial bus. In addition, two
of the pins can be reconfigured as an SMBALERT output to
indicate out−of−limit conditions.
Sequential Measurement
When the ADT7460 monitoring sequence is started, it
cycles sequentially through the measurement of 2.5 V input
and the temperature sensors. Measured values from these
inputs are stored in value registers. These can be read out
over the serial bus or can be compared with programmed
limits stored in the limit registers. The results of
out−of−limit comparisons are stored in the status registers,
which can be read over the serial bus to flag out−of−limit
conditions.
Measurement Inputs
The device has three measurement inputs, one for voltage
and two for temperature. It can also measure its own supply
voltage and can measure ambient temperature with its
on−chip temperature sensor.
Pin 14 is an analog input with an on−chip attenuator and
is configured to monitor 2.5 V.
Power is supplied to the chip via Pin 3, and the system also
monitors VCC through this pin. In PCs, this pin is normally
connected to a 3.3 V standby supply. This pin can, however,
be connected to a 5.0 V supply and monitor it without
over−ranging.
Remote temperature sensing is provided by the D1± and
D2± inputs, to which diode−connected, external
temperature−sensing transistors, such as a 2N3904 or CPU
thermal diode, may be connected.
Recommended Implementation
Configuring the ADT7460 as in Figure 12 allows the
systems designer the following features:
♦ Two PWM outputs for fan control of up to three
fans (the front and rear chassis fans are connected in
parallel).
♦ Three TACH fan speed measurement inputs.
♦ VCC measured internally through Pin 3.
♦ CPU temperature measured using Remote 1
temperature channel.
♦ Ambient temperature measured through Remote 2
temperature channel.
♦ Bidirectional THERM pin. Allows Intel Pentium 4
PROCHOT monitoring and can function as an
overtemperature THERM output.
♦ SMBALERT system interrupt output.
ADT7460
FRONT
CHASSIS
FAN
CPU FAN
PWM1
TACH2
TACH1
REAR
CHASSIS
FAN
PWM3
D2+
TACH3
D2–
THERM
CPU
PROCHOT
AMBIENT
TEMPERATURE
D1+
SDA
D1–
SCL
SMBALERT
GND
Figure 12. Recommended Implementation
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ICH
ADT7460
ADT7460 Address Selection
Address 0x2E. This function is described in more detail
later.
Pin 8 is the dual−function PWM3/ADDRESS ENABLE
pin. If Pin 8 is pulled low on powerup, the ADT7460 reads
the state of Pin 9 (TACH4/ADDRESS SELECT/THERM)
to determine the ADT7460’s slave address. If Pin 8 is high
on powerup, the ADT7460 defaults to SMBus Slave
Internal Registers of the ADT7460
Table 1 summarizes the ADT7460’s principal internal
registers. Table 38 to Table 78 describe the registers in more
detail.
Table 1. Summary Internal Registers
Register
Configuration
Description
These registers provide control and configuration of the ADT7460, including alternate pinout functionality.
Address Pointer
This register contains the address that selects one of the other internal registers. When writing to the
ADT7460, the first byte of data is always a register address, which is written to the address pointer register.
Status Registers
These registers provide the status of each limit comparison and are used to signal out−of−limit conditions on
the temperature, voltage, or fan speed channels. If Pin 14 or Pin 5 is configured as SMBALERT, this pin
asserts low whenever an unmasked status bit is set.
Interrupt Mask
These registers allow each interrupt status event to be masked when Pin 14 or Pin 5 is configured as an
SMBALERT output.
Value and Limit
The results of analog voltage input, temperature, and fan speed measurements are stored in these
registers, along with their limit values.
Offset
These registers allow each temperature channel reading to be offset by a twos complement value written to
these registers.
TMIN
These registers program the starting temperature for each fan under automatic fan speed control.
TRANGE
Operating Point
Enhance Acoustics
These registers program the temperature−to−fan speed control slope in automatic fan speed control mode
for each PWM output.
These registers define the target operating temperatures for each thermal zone when running under
dynamic TMIN control. This function allows the cooling solution to adjust dynamically in response to
measured temperature and system performance.
These registers allow each PWM output controlling fan to be tweaked to enhance the system’s acoustics.
Theory of Operation
Table 2. Address Select Mode
Serial Bus Interface
Control of the ADT7460 is carried out using the serial
System Management Bus (SMBus). The ADT7460 is
connected to this bus as a slave device, under the control of
a master controller.
The ADT7460 has a 7−bit serial bus address. When the
device is powered up with Pin 8 (PWM3/ ADDRESS
ENABLE) high, the ADT7460 has a default SMBus address
of 0101110 or 0x2E. If more than one ADT7460 is to be used
in a system, each ADT7460 should be placed in address
select mode by strapping Pin 8 low on powerup. The logic
state of Pin 9 then determines the device’s SMBus address.
The logic state of these pins is sampled on powerup.
The device address is sampled and latched on the first
valid SMBus transaction, more precisely, on the
low−to−high transition at the beginning of the eighth SCL
pulse, when the serial address byte matches the selected
slave address. The selected slave address is chosen using the
ADDRESS ENABLE/ADDRESS SELECT pins. Any
attempted changes in the address has no effect after this.
Pin 8
State
Pin 9 State
0
Low (10 kW to GND)
0101100 (0x2C)
0
High (10 kW pullup)
0101101 (0x2D)
1
Don’t Care
0101110 (0x2E) (default)
Address
VCC
ADT7460
ADDR_SEL
9
10kΩ
8
PWM3/ADDR_EN
ADDRESS = 0x2E
Figure 13. Default SMBus Address 0x2E
ADT7460
ADDR_SEL
PWM3/ADDR_EN
9
10kΩ
8
ADDRESS = 0x2C
Figure 14. SMBus Address 0x2C (Pin 9 = 0)
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ADT7460
to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
2. Data is sent over the serial bus in sequences of
nine clock pulses, eight bits of data followed by an
Acknowledge bit from the slave device.
Transitions on the data line must occur during the
low period of the clock signal and remain stable
during the high period, as a low−to−high transition
when the clock is high may be interpreted as a stop
signal. The number of data bytes that can be
transmitted over the serial bus in a single read or
write operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master pulls the data line high during the 10th
clock pulse to assert a stop condition. In read
mode, the master device overrides the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as No Acknowledge. The master
then takes the data line low during the low period
before the 10th clock pulse, then high during the
10th clock pulse to assert a stop condition.
VCC
ADT7460
ADDR_SEL
PWM3/ADDR_EN
10kΩ
9
8
ADDRESS = 0x2D
Figure 15. SMBus Address 0x2D (Pin 9 = 1)
VCC
ADT7460
ADDR_SEL
10kΩ
9
8
PWM3/ADDR_EN
NC
DO NOT LEAVE ADDR_EN
UNCONNECTED. CAN
CAUSE UNPREDICTABLE
ADDRESSES
CARE SHOULD BE TAKEN TO ENSURE THAT PIN 8
(PWM3/ADDR_EN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 8
FLOATING COULD CAUSE THE ADT7460 TO POWERUP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7460 IS PLACED INTO ADDRESS SELECT
MODE, PINS 8 AND 9 CAN BE USED AS THE ALTERNATE FUNCTIONS
(PWM3, TACH4/THERM) ONLY IF THE CORRECT CIRCUIT IS MUXED
IN AT THE CORRECT TIME.
Figure 16. Unpredictable SMBus Address if Pin 8
is Unconnected
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
In the case of the ADT7460, write operations contain
either one or two bytes, and read operations contain one
byte.
To write data to one of the device data registers or read
data from it, the address pointer register must be set so that
the correct data register is addressed. Then data can be
written in that register or read from it. The first byte of a
write operation always contains an address that is stored in
the address pointer register. If data is to be written to the
device, the write operation contains a second data byte that
is written to the register selected by the address pointer
register.
This is illustrated in Figure 17. The device address is sent
over the bus followed by R/W being set to 0. This is followed
by two data bytes. The first data byte is the address of the
internal data register to be written to, which is stored in the
address pointer register. The second data byte is the data to
be written to the internal data register.
The facility to make hardwired changes to the SMBus
slave address allows the user to avoid conflicts with other
devices sharing the same serial bus, for example, if more
than one ADT7460 is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high−to−low transition
on the serial data line SDA while the serial clock
line SCL remains high. This indicates that an
address/data stream will follow. All slave
peripherals connected to the serial bus respond to
the star condition and shift in the next eight bits,
consisting of a 7−bit address (MSB first) plus a
R/W bit, which determine the direction of the data
transfer, that is, whether data is written to or read
from the slave device.
The peripheral whose address corresponds to the
transmitted address responds by pulling the data
line low during the low period before the ninth
clock pulse, known as the Acknowledge bit. All
other devices on the bus now remain idle while the
selected device waits for data to be read from or
written to it. If the R/W bit is a 0, the master writes
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ADT7460
1
9
9
1
SCL
SDA
0
1
0
1
1
A1
A0
D7
R/W
START BY
MASTER
D6
D4
D5
D3
D2
D1
D0
ACK. BY
ADT7460
ACK. BY
ADT7460
FRAME 1
SERIAL BUS ADDRESS
BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
D7
SDA (CONTINUED)
D6
D5
D4
D3
FRAME 3
DATA
BYTE
D2
D1
D0
ACK. BY
ADT7460
STOP BY
MASTER
Figure 17. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
protocol (see System Management Bus specifications
Rev. 2.0 for more information).
If it is required to perform several read or write operations
in succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
When reading data from a register, there are two
possibilities:
♦ If the ADT7460’s address pointer register value is
unknown or not the desired value, it is first
necessary to set it to the correct value before data
can be read from the desired data register. This is
done by performing a write to the ADT7460 as
before, but only the data byte containing the register
address is sent because data is not to be written to
the register. This is shown in Figure 18.
A read operation is then performed, consisting of the
serial bus address, R/W bit set to 1, followed by the
data byte read from the data register. This is shown
in Figure 19.
♦ If the address pointer register is known to be already
at the desired address, data can be read from the
corresponding data register without first writing to
the address pointer register, so Figure 18 can be
omitted.
It is possible to read a data byte from a data register
without first writing to the address pointer register if the
address pointer register is already at the correct value.
However, it is not possible to write data to a register without
writing to the address pointer register because the first data
byte of a write is always written to the address pointer
register.
In Figure 17 and Figure 19, the serial bus address is shown
as the default value 01011(A1) (A0), where A1 and A0 are
set by the address select mode function previously defined.
In addition to supporting the Send Byte and Receive Byte
protocols, the ADT7460 also supports the Read Byte
Write Operations
The SMBus specification defines several protocols for
different types of read and write operations. The ones used
in the ADT7460 are discussed below. The following
abbreviations are used in the diagrams:
S—start
P—stop
R—read
W—write
A—acknowledge
A—no acknowledge
The ADT7460 uses the following SMBus write protocols:
Send Byte
In this operation, the master device sends a single
command byte to a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
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ADT7460
1
9
1
9
SCL
0
SDA
10
1
START BY
MASTER
1
A1
A0
D7
R/W
D6
D4
D5
D2
D3
D1
D0
ACK. BY
ADT7460
FRAME 1
SERIAL BUS ADDRESS
BYTE
ACK. BY
ADT7460
STOP BY
MASTER
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 18. Writing to the Address Pointer Register Only
1
9
1
9
SCL
0
SDA
10
1
START BY
MASTER
1
A1
A0
D7
R/ W
D6
D4
D5
D2
D3
D1
D0
ACK. BY
ADT7460
FRAME 1
SERIAL BUS ADDRESS
BYTE
NO ACK. BY STOP BY
MASTER
MASTER
FRAME 2
DATA BYTE FROM ADT7460
Figure 19. Reading Data from a Previously Selected Register
Read Operations
For the ADT7460, the send byte protocol is used to write
to the address pointer register for a subsequent single−byte
read from the same address. This is illustrated in Figure 20.
1
2
3
SLAVE
W A
ADDRESS
S
4
5 6
REGISTER
ADDRESS
A P
The ADT7460 uses the following SMBus read protocols.
Receive Byte
This is useful when repeatedly reading a single register.
The register address needs to have been set up previously. In
this operation, the master device receives a single byte from
a slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA and
the transaction ends.
In the ADT7460, the receive byte protocol is used to read
a single byte of data from a register whose address has
previously been set by a send byte or by write byte operation.
Figure 20. Setting a Register Address for
Subsequent Read
If it is required to read data from the register immediately
after setting up the address, the master can assert a repeat
start condition immediately after the final ACK and carry
out a single−byte read without asserting an intermediate stop
condition.
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
by the write bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends the register address.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA to end
the transaction.
This is illustrated in Figure 21.
1
2
3
SLAVE
S ADDRESS W A
4
5
REGISTER
ADDRESS
A
6
1
2
3
SLAVE
S ADDRESS R A
4
5 6
DATA
A P
Figure 22. Single−Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus
devices that allows an interrupting device to identify itself
to the host when multiple devices exist on the same bus.
The SMBALERT output can be used as an interrupt
output or can be used as an SMBALERT. One or more
outputs can be connected to a common SMBALERT line
connected to the master. If a device’s SMBALERT line goes
low, the following occurs:
1. SMBALERT is pulled low.
7 8
DATA A P
Figure 21. Single−Byte Write to a Register
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ADT7460
2. Master initiates a read operation and sends the
alert response address (ARA = 0001 100). This is
a general call address, which must not be used as a
specific device address.
3. The device whose SMBALERT output is low
responds to the alert response address, and the
master reads its device address. The address of the
device is now known, and it can be interrogated in
the usual way.
4. If more than one device’s SMBALERT output is
low, the one with the lowest device address has
priority in accordance with normal SMBus
arbitration.
5. Once the ADT7460 has responded to the alert
response address, the master must read the status
registers and the SMBALERT is cleared only if
the error condition has gone away.
to 2.25 V, but the input has built−in attenuators to allow
measurement of 2.5 V without any external components. To
allow the tolerance of the supply voltage, the ADC produces
an output of 3/4 full scale (768d or 0x300) for the nominal
input voltage and so has adequate headroom to deal with
overvoltages.
Input Circuitry
The internal structure for the 2.5 V analog input is shown
in Figure 23. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first−order
low−pass filter that gives the input immunity to high
frequency noise.
Table 4. Voltage Measurement Registers
SMBus Timeout
<6> TODIS
1: SMBus timeout disabled
0x20
2.5 V reading
0x00
0x22
VCC reading
0x00
Register
Description
0: SMBus timeout enabled (default)
Default
Table 5. 2.5 V Limits Registers
Table 3. Configuration Register 1 (Reg. 0x40)
<6> TODIS
Description
Associated with the voltage measurement channels are a
high and low limit register. Exceeding the programmed high
or low limit causes the appropriate status bit to be set.
Exceeding either limit can also generate SMBALERT
interrupts.
The ADT7460 includes an SMBus timeout feature. If
there is no SMBus activity for 25 ms, the ADT7460 assumes
that the bus is locked and releases the bus. This prevents the
device from locking or holding the SMBus expecting data.
Some SMBus controllers cannot handle the SMBus timeout
feature, so it can be disabled.
Bit
Register
Description
Default
0x44
2.5 V low limit
0x00
0x45
2.5 V high limit
0xFF
0x48
VCC low limit
0x00
0x49
VCC high limit
0xFF
Voltage Measurement Input
The ADT7460 has one external voltage measurement
channel. It can also measure its own supply voltage, VCC.
Pin 14 may be configured to measure a 2.5 V supply. The
VCC supply voltage measurement is carried out through the
VCC pin (Pin 3). Setting Bit 7 of Configuration Register 1
(Reg. 0x40) allows a 5.0 V supply to power the ADT7460
and be measured without over−ranging the VCC
measurement channel. The 2.5 V input can be used to
monitor a chipset supply voltage in computer systems.
2.5VIN
45kΩ
94kΩ
30pF
Figure 23. Structure of Analog Inputs
Table 6 shows the input ranges of the analog inputs and
output codes of the 10−bit ADC.
When the ADC is running, it samples and converts a
voltage input in 711 ms and averages 16 conversions to
reduce noise; a measurement takes nominally 11.38 ms.
Analog−to−Digital Converter
All analog inputs are multiplexed into the on−chip,
successive approximation, analog−to−digital converter.
This has a resolution of 10 bits. The basic input range is 0 V
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ADT7460
Table 6. 10−Bit A/D Output Code vs. VIN
Input Voltage
5 VIN
ADC Output
VCC (3.3 VIN) (Note 1)
2.5 VIN
Decimal
Binary (10 Bits)
<0.0042
<0.00293
0
00000000 00
<0.0065
<0.0042
<0.0032
0
00000000 00
0.0065–0.0130
0.0042–0.0085
0.0032–0.0065
1
00000000 01
0.0130–0.0195
0.0085–0.0128
0.0065–0.0097
2
00000000 10
0.0195–0.0260
0.0128–0.0171
0.0097–0.0130
3
00000000 11
0.0260–0.0325
0.0171–0.0214
0.0130–0.0162
4
00000001 00
0.0325–0.0390
0.0214–0.0257
0.0162–0.0195
5
00000001 01
0.0390–0.0455
0.0257–0.0300
0.0195–0.0227
6
00000001 10
0.0455–0.0521
0.0300–0.0343
0.0227–0.0260
7
00000001 11
0.0521–0.0586
0.0343–0.0386
0.0260–0.0292
8
00000010 00
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
1.6675–1.6740
1.1000–1.1042
0.8325–0.8357
256 (1/4 scale)
01000000 00
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
3.3300–3.3415
2.2000–2.2042
1.6650–1.6682
512 (1/2 scale)
10000000 00
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
5.0025–5.0090
3.3000–3.3042
2.4975–2.5007
768 (3/4 scale)
11000000 00
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
6.5983–6.6048
4.3527–4.3570
3.2942–3.2974
1013
11111101 01
6.6048–6.6113
4.3570–4.3613
3.2974–3.3007
1014
11111101 10
6.6113–6.6178
4.3613–4.3656
3.3007–3.3039
1015
11111101 11
6.6178–6.6244
4.3656–4.3699
3.3039–3.3072
1016
11111110 00
6.6244–6.6309
4.3699–4.3742
3.3072–3.3104
1017
11111110 01
6.6309–6.6374
4.3742–4.3785
3.3104–3.3137
1018
11111110 10
6.6374–6.4390
4.3785–4.3828
3.3137–3.3169
1019
11111110 11
6.6439–6.6504
4.3828–4.3871
3.3169v3.3202
1020
11111111 00
6.6504–6.6569
4.3871–4.3914
3.3202–3.3234
1021
11111111 01
6.6569–6.6634
4.3914–4.3957
3.3234–3.3267
1022
11111111 10
>6.6634
>4.3957
>3.3267
1023
11111111 11
1. The VCC output codes listed assume that VCC is 3.3 V. If VCC input is reconfigured for 5.0 V operation (by setting Bit 7 of Configuration
Register 1), the VCC output codes are the same as for the 5.0 VIN column.
Additional ADC Functions for Voltage Measurements
A number of other functions are available on the
ADT7460 to offer the systems designer increased flexibility.
Configuration Register 2 (Reg. 0x73) turns averaging off.
This effectively gives a reading 16 times faster (711 ms), but
the reading may be noisier.
Turn−Off Averaging
Bypass Voltage Input Attenuator
For each voltage measurement read from a value register,
16 readings have actually been made internally and the
results averaged before being placed into the value register.
If the user wants to speed up conversion, setting Bit 4 of
Setting Bit 5 of Configuration Register 2 (Reg. 0x73)
removes the attenuation circuitry from the 2.5 V input. This
allows the user to directly connect external sensors or to
rescale the analog voltage measurement inputs for other
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ADT7460
applications. The input range of the ADC without the
attenuators is 0 V to 2.25 V.
negative temperatures can be measured, the temperature
data is stored in twos complement format, as shown in
Table 9. Theoretically, the temperature sensor and ADC can
measure temperatures from −128°C to +127°C with a
resolution of 0.25°C. However, this exceeds the operating
temperature range of the device, so local temperature
measurements outside this range are not possible.
Single−Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (Reg. 0x73)
places the ADT7460 into single−channel ADC conversion
mode. In this mode, the ADT7460 can be made to read a
single voltage channel only. If the internal ADT7460 clock is
used, the selected input is read every 711 ms. The appropriate
ADC channel is selected by writing to Bits <7:5> of the
TACH1 Minimum High Byte register (Reg. 0x55).
Remote Temperature Measurement
The ADT7460 can measure the temperature of two remote
diode sensors or diode−connected transistors connected to
Pins 12 and 13, or Pins 10 and 11.
The forward voltage of a diode or diode−connected
transistor operated at a constant current exhibits a negative
temperature coefficient of about −2 mV/°C. Unfortunately,
the absolute value of VBE varies from device to device, and
individual calibration is required to null this out, so the
technique is unsuitable for mass production. The technique
used in the ADT7460 is to measure the change in VBE when
the device is operated at two different currents. This is given
by:
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
T is the absolute temperature in Kelvins.
N is the ratio of the two currents.
Figure 24 shows the input signal conditioning used to
measure the output of a remote temperature sensor. This
figure shows the external sensor as a substrate transistor
provided for temperature monitoring on some
microprocessors. It could equally well be a discrete
transistor, such as a 2N3904.
Table 7. Configuration Register 2 (Reg. 0x73)
Bit
Description
<4>
1: Averaging Off
<5>
1: Bypass Input Attenuators
<6>
1: Single−Channel Convert Mode
Table 8. TACH1 Minimum High Byte (Reg. 0x55)
Bit
<7:5>
Description
Selects ADC channel for single−channel convert
mode
Value
Channel Selected
000
2.5 V
010
VCC
Temperature Measurement System
Local Temperature Measurement
The ADT7460 contains an on−chip band gap temperature
sensor whose output is digitized by the on−chip 10−bit ADC.
The 8−bit MSB temperature data is stored in the local
temperature register (Address 0x26). As both positive and
N y I IBIAS
I
VDD
CPU
THERMDA D+
REMOTE
SENSING
TRANSISTOR
THERMDC
D–
VOUT+
BIAS
DIODE
LPF
fC = 65kHz
TO ADC
VOUT–
Figure 24. Signal Conditioning for Remote Diode Temperature Sensors
If a discrete transistor is used, the collector is not
grounded, and it should be linked to the base. If a PNP
transistor is used, the base is connected to the D− input and
the emitter to the D+ input. If an NPN transistor is used, the
emitter is connected to the D− input, and the base to the D+
input. Figure 25 and Figure 26 show how to connect the
ADT7460 to an NPN or PNP transistor for temperature
measurement. To prevent ground noise from interfering
with the measurement, the more negative terminal of the
sensor is not referenced to ground but is biased above ground
by an internal diode at the D− input.
To measure DVBE, the sensor is switched between
operating currents of I and N × I. The resulting waveform is
passed through a 65 kHz low−pass filter to remove noise and
to a chopper stabilized amplifier that performs the functions
of amplification and rectification of the waveform to
produce a dc voltage proportional to DVBE. This voltage is
measured by the ADC to give a temperature output in 10−bit,
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ADT7460
twos complement format. To further reduce the effects of
noise, digital filtering is performed by averaging the results
of 16 measurement cycles. A remote temperature
measurement takes nominally 25.5 ms. The results of
remote temperature measurements are stored in 10−bit, twos
complement format, as illustrated in Table 9. The extra
resolution for the temperature measurements is held in the
Extended Resolution Register 2 (Reg. 0x77). This gives
temperature readings with a resolution of 0.25°C.
Table 11. Extended Resolution Temperature
Measurement Register Bits (Addr = 0x77)
D+
Figure 25. Measuring Temperature Using an
NPN Transistor
ADT7460
D+
Table 9. Temperature Data Format
Digital Output (10−Bit) (Note 1)
1000 0000 00
−125°C
1000 0011 00
−100°C
1001 1100 00
−75°C
1011 0101 00
−50°C
1100 1110 00
−25°C
1110 0111 00
−10°C
1111 0110 00
0°C
0000 0000 00
+10.25°C
0000 1010 01
TDM2
Remote 2 temperature LSBs
<5:4>
LTMP
Local temperature LSBs
<3:2>
TDM1
Remote 1 temperature LSBs
As CPUs run faster, it becomes more difficult to avoid
high frequency clocks when routing the D+, D− traces
around a system board. Even when recommended layout
guidelines are followed, there may still be temperature
errors attributed to noise being coupled onto the D+/D−
lines. High frequency noise generally has the effect of giving
temperature measurements that are too high by a constant
amount. The ADT7460 has temperature offset registers at
Addresses 0x70, 0x72 for the Remote 1 and Remote 2
temperature channels. By doing a one−time calibration of
the system, one can determine the offset caused by system
board noise and null it out using the offset registers. The
offset registers automatically add a twos complement 8−bit
reading to every temperature measurement. The LSB adds
0.25°C offset to the temperature reading so the 8−bit register
effectively allows temperature offsets of up to ±32°C with
a resolution of 0.25°C. This ensures that the readings in the
temperature measurement registers are as accurate as
possible.
Figure 26. Measuring Temperature Using a
PNP Transistor
−128°C
<7:6>
Nulling Out Temperature Errors
D–
Temperature
Description
It is important to note that temperature can be read from
the ADT7460 as an 8−bit value (with 1°C resolution) or as
a 10−bit value (with 0.25°C resolution). If only 1°C
resolution is required, the temperature readings can be read
back at any time and in no particular order.
If the 10−bit measurement is required, this involves a
2−register read for each measurement. The extended
resolution register (Reg. 0x77) should be read first. This
causes all temperature reading registers to be frozen until all
temperature reading registers have been read from. This
prevents an MSB reading from being updated while its two
LSBs are being read, and vice versa.
D–
2N3906
PNP
Mnemonic
Reading Temperature from the ADT7460
ADT7460
2N3904
NPN
Bit
+25.5°C
0001 1001 10
+50.75°C
0011 0010 11
+75°C
0100 1011 00
+100°C
0110 0100 00
Register
Description
Default
+125°C
0111 1101 00
0x70
Remote 1 temperature offset
0x00 (0°C)
+127°C
0111 1111 00
0x71
Local temperature offset
0x00 (0°C)
0x72
Remote 2 temperature offset
0x00 (0°C)
Table 12. Temperature Offset Registers
1. Bold numbers denote 2 LSBs of measurement in the Extended
Resolution Register 2 (0x77) with 0.25°C resolution.
Temperature Measurement Limit Registers
Associated with each temperature measurement channel
are high and low limit registers. Exceeding the programmed
high or low limit causes the appropriate status bit to be set.
Exceeding either limit can also generate SMBALERT
interrupts.
Table 10. Temperature Measurement Registers
Register
Description
Default
0x25
Remote 1 temperature
0x80
0x26
Local temperature
0x80
0x27
Remote 2 temperature
0x80
0x77
Extended Resolution 2
0x00
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ADT7460
Table 13. Temperature Measurement Limit Registers
Table 14. Configuration Register 2 (Reg. 0x73)
Register
Description
Default
Bit
0x4E
Remote 1 temperature low limit
0x81
<4>
1: Averaging Off
0x7F
<6>
1: Single−Channel Convert Mode
0x4F
Remote 1 temperature high limit
0x50
Local temperature low limit
0x81
0x51
Local temperature high limit
0x7F
0x52
Remote 2 temperature low limit
0x81
0x53
Remote 2 temperature high limit
0x7F
Description
Table 15. TACH1 Minimum High Byte (Reg. 0x55)
Bit
<7:5>
Description
Selects ADC channel for single−channel convert
mode
Overtemperature Events
Overtemperature events on any of the temperature
channels can be detected and dealt with automatically in
automatic fan speed control mode. Registers 0x6A to 0x6C
are the THERM limits. When a temperature exceeds its
THERM limit, all fans run at 100% duty cycle. The fans
continue running at 100% until the temperature drops below
THERM – Hysteresis. (This can be disabled by setting the
BOOST bit in Configuration Register 3, Bit 2, Register
0x78). The hysteresis value for that THERM limit is the
value programmed into Registers 0x6D and 0x6E
(hysteresis registers). The default hysteresis value is 4°C.
Value
Channel Selected
101
Remote 1 temp
110
Local temp
111
Remote 2 temp
Limits, Status Registers, and Interrupts
Limit Values
Associated with each measurement channel on the
ADT7460 are high and low limits. These can form the basis
of system status monitoring: a status bit can be set for any
out−of−limit condition and detected by polling the device.
Alternatively, SMBALERT interrupts can be generated to
flag a processor or micro controller of out−of−limit
conditions.
THERM LIMIT
8−Bit Limits
HYSTERESIS (5C)
The following is a list of 8−bit limits on the ADT7460.
TEMPERATURE
Table 16. Voltage Limit Registers
100%
FANS
Figure 27. THERM Limit Operation
Additional ADC Functions for Temperature Measurement
A number of other functions are available on the
ADT7460 to offer the systems designer increased flexibility.
Register
Description
Default
0x44
2.5 V low limit
0x00
0x45
2.5 V high limit
0xFF
0x48
VCC low limit
0x00
0x49
VCC high limit
0xFF
Table 17. Temperature Limit Registers
Turn−Off Averaging
For each temperature measurement read from a value
register, 16 readings have actually been made internally and
the results averaged before being placed into the value
register. Sometimes it may be necessary to take a very fast
measurement, for example, of CPU temperature. Setting
Bit 4 of Configuration Register 2 (Reg. 0x73) turns
averaging off. This takes a reading every 15.5 ms. Each
remote temperature measurement takes 4 ms and the local
temperature measurement takes 1.4 ms.
Single−Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (Reg. 0x73)
places the ADT7460 into single−channel ADC conversion
mode. In this mode, the ADT7460 can be made to read a
single temperature channel only. The appropriate ADC
channel is selected by writing to Bits <7:5> of the TACH1
minimum high byte register (Reg. 0x55).
Register
Description
Default
0x4E
Remote 1 temperature low limit
0x81
0x4F
Remote 1 temperature high limit
0x7F
0x6A
Remote 1 THERM limit
0x64
0x50
Local temperature low limit
0x81
0x51
Local temperature high limit
0x7F
0x6B
Local THERM limit
0x64
0x52
Remote 2 temperature low limit
0x81
0x53
Remote 2 temperature high limit
0x7F
0x6C
Remote 2 THERM limit
0x64
Table 18. THERM Timer Limit Registers
Register
Description
Default
0x7A
THERM timer limit
0x00
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ADT7460
16−Bit Limits
The fan TACH measurements are 16−bit results. The fan
TACH limits are also 16 bits, consisting of a high byte and
low byte. Since fans running under speed or stalled are
normally the only conditions of interest, only high limits
exist for fan TACHs. Since fan TACH period is actually
being measured, exceeding the limit indicates a slow or
stalled fan.
INT
Table 19. Fan Limit Registers
Register
Description
Default
0x54
TACH1 minimum low byte
0xFF
0x55
TACH1 minimum high byte
0xFF
0x56
TACH2 minimum low byte
0xFF
0x57
TACH2 minimum high byte
0xFF
0x58
TACH3 minimum low byte
0xFF
0x59
TACH3 minimum high byte
0xFF
0x5A
TACH4 minimum low byte
0xFF
0x5B
TACH4 minimum high byte
0xFF
LOW LIMIT
TEMP = LOW LIMIT
Figure 29. Temperature = Low Limit: INT Occurs
Out−of−Limit Comparisons
Once all limits have been programmed, the ADT7460 can
be enabled for monitoring. The ADT7460 measures all
parameters in round−robin format and sets the appropriate
status bit for out−of−limit conditions. Comparisons are done
differently depending on whether the measured value is
being compared to a high or low limit.
High limit: > comparison performed
Low limit: < or = comparison performed
NO INT
HIGH LIMIT
TEMP = HIGH LIMIT
NO INT
Figure 30. Temperature = High Limit: No INT
INT
LOW LIMIT
HIGH LIMIT
TEMP > LOW LIMIT
Figure 28. Temperature > Low Limit: No INT
TEMP > HIGH LIMIT
Figure 31. Temperature > High Limit: INT Occurs
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ADT7460
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0) of Configuration Register 1 (Reg. 0x40).
The ADC measures each analog input in turn and, as each
measurement is completed, the result is automatically stored
in the appropriate value register. This round−robin
monitoring cycle continues unless disabled by writing a 0 to
Bit 0 of Configuration Register 1.
As the ADC is normally allowed to free−run in this manner,
the time taken to monitor all the analog inputs is normally not
of interest, since the most recently measured value of any
input can be read out at any time. For applications where the
monitoring cycle time is important, it can easily be calculated.
The total number of channels measured is
♦ Two supply voltage inputs (2.5 V and VCC)
♦ Local temperature
♦ Two remote temperatures
As mentioned previously, the ADC performs round−robin
conversions and takes 11.38 ms for each voltage
measurement, 12 ms for a local temperature reading, and
25.5 ms for each remote temperature reading.
The total monitoring cycle time for averaged voltage and
temperature monitoring is, therefore, nominally:
(2
11.38) ) 12 (2
25.5) + 85.76 ms
OOL = 1 DENOTES A PARAMETER
MONITORED THROUGH STATUS REG 2
IS OUT−OF−LIMIT
Figure 32. Status Register 1
Table 20. Status Register 1 (Reg. 0x41)
Bit
Mnemonic
7
OOL
1 denotes a bit in Status Register 2 is
set and Status Register 2 should be
read.
6
R2T
1 indicates that the Remote 2
temperature high or low limit has been
exceeded.
5
LT
1 indicates that the Local temperature
high or low limit has been exceeded.
4
R1T
1 indicates that the Remote 1
temperature high or low limit has been
exceeded.
3
−
2
VCC
1
−
0
2.5 V
Unused
(eq. 1)
The round robin starts again 35 ms later. Therefore, all
channels are measured approximately every 120 ms.
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
Description
1 indicates that the VCC high or low
limit has been exceeded.
Unused
1 indicates that the 2.5 V high or low
limit has been exceeded.
Status Registers
The results of limit comparisons are stored in Status
Registers 1 and 2. The status register bit for each channel
reflects the status of the last measurement and limit
comparison on that channel. If a measurement is within
limits, the corresponding status register bit is cleared to 0. If
the measurement is out−of−limits, the corresponding status
register bit is set to 1.
The state of the various measurement channels may be
polled by reading the status registers over the serial bus. In
Bit 7 (OOL) of Status Register 1 (Reg. 0x41), 1 means that
an out−of−limit event has been flagged in Status Register 2.
This means that you need only read Status Register 2 when
this bit is set. Alternatively, Pin 5 or Pin 14 can be configured
as an SMBALERT output. This automatically notifies the
system supervisor of an out−of−limit condition. Reading the
status registers clears the appropriate status bit as long as the
error condition that caused the interrupt has cleared. Status
register bits are “sticky.” Whenever a status bit is set,
indicating an out−of−limit condition, it remains set even if the
event that caused it has gone away (until read). The only way
to clear the status bit is to read the status register after the
event has gone away. Interrupt status mask registers (Reg.
0x74, 0x75) allow individual interrupt sources to be masked
from causing an SMBALERT. However, if one of these
masked interrupt sources goes out−of−limit, its associated
status bit is set in the interrupt status registers.
F4P = 1, FAN 4 OR THERM
TIMER IS OUT−OF−LIMIT
Figure 33. Status Register 2
Table 21. Status Register 2 (Reg. 0x42)
Bit
Mnemonic
7
D2
1 indicates an open or short on
D2+/D2− inputs.
6
D1
1 indicates an open or short on
D2+/D2− inputs.
5
F4P
1 indicates that Fan 4 has dropped
below minimum speed. Alternatively,
indicates that THERM timer limit has
been exceeded if the THERM timer
function is used.
4
FAN3
1 indicates that Fan 3 has dropped
below minimum speed.
3
FAN2
1 indicates that Fan 2 has dropped
below minimum speed.
2
FAN1
1 indicates that Fan 1 has dropped
below minimum speed.
1
OVT
1 indicates that a THERM
overtemperature limit has been
exceeded.
0
−
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Description
Unused
ADT7460
SMBALERT Interrupt Behavior
HIGH LIMIT
The ADT7460 can be polled for status, or an SMBALERT
interrupt can be generated for out−of−limit conditions. It is
important to note how the SMBALERT output and status
bits behave when writing interrupt handler software.
Figure 34 shows how the SMBALERT output and sticky
status bits behave. Once a limit is exceeded, the
corresponding status bit is set to 1. The status bit remains set
until the error condition subsides and the status register is
read. The status bits are referred to as sticky since they
remain set until read by software. This ensures that an
out−of−limit event cannot be missed if software is polling
the device periodically. Note that the SMBALERT output
remains low for the entire duration that a reading is
out−of−limit and until the status register has been read. This
has implications on how software handles the interrupt.
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
“STICKY”
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Figure 35. How Masking the Interrupt Source Affects
SMBALERT Output
Masking Interrupt Sources
HIGH LIMIT
Interrupt Mask Registers 1 and 2 are located at Addresses
0x74 and 0x75. These allow individual interrupt sources to
be masked out to prevent SMBALERT interrupts. Note that
masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
as normal.
TEMPERATURE
CLEARED ON READ
(TEMP BELOW LIMIT)
“STICKY”
STATUS BIT
Table 22. Interrupt Mask Register 1 (Reg. 0x74)
SMBALERT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
Figure 34. SMBALERT and Status Bit Behavior
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing
interrupts, it is recommend to handle the SMBALERT
interrupt as follows:
1. Detect the SMBALERT assertion.
2. Enter the interrupt handler.
3. Read the status registers to identify the interrupt
source.
4. Mask the interrupt source by setting the
appropriate mask bit in the interrupt mask registers
(Reg. 0x74, 0x75).
5. Take the appropriate action for a given interrupt
source.
6. Exit the interrupt handler.
7. Periodically poll the status registers. If the
interrupt status bit has cleared, reset the
corresponding interrupt mask bit to 0. This causes
the SMBALERT output and status bits to behave
as shown in Figure 35.
Bit
Mnemonic
7
OOL
1 masks SMBALERT for any alert
condition flagged in Status Register 2.
6
R2T
1 masks SMBALERT for Remote 2
temperature.
5
LT
4
R1T
3
−
2
VCC
1
−
0
2.5 V
Description
1 masks SMBALERT for local
temperature.
1 masks SMBALERT for Remote 1
temperature.
Unused
1 masks SMBALERT for the VCC
channel.
Unused
1 masks SMBALERT for the 2.5 V
channel.
Table 23. Interrupt Mask Register 2 (Reg. 0x75)
Bit
Mnemonic
Description
7
D2
1 masks SMBALERT for Diode 2 errors.
6
D1
1 masks SMBALERT for Diode 1 errors.
5
FAN4
1 masks SMBALERT for Fan 4 failure. If
the TACH4 pin is being used as the
THERM input, this bit masks
SMBALERT for a THERM event.
4
FAN3
1 masks SMBALERT for Fan 3.
3
FAN2
1 masks SMBALERT for Fan 2.
2
FAN1
1 masks SMBALERT for Fan 1.
1
OVT
1 masks SMBALERT for
overtemperature (exceeding THERM
limits).
0
−
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Unused
ADT7460
Enabling the SMBALERT Interrupt Output
THERM Timer
The SMBALERT interrupt function is disabled by
default. Pin 5 or Pin 14 can be reconfigured as an
SMBALERT output to signal out−of−limit conditions.
The ADT7460 has an internal timer to measure THERM
assertion time. For example, the THERM input may be
connected to the PROCHOT output of a Pentium 4 CPU and
measure system performance. The THERM input may also
be connected to the output of a trip point temperature sensor.
The timer is started on the assertion of the ADT7460’s
THERM input and stopped on the negation of the pin. The
timer counts THERM times cumulatively, therefore, the
timer resumes counting on the next THERM assertion. The
THERM timer continues to accumulate THERM assertion
times until the timer is read (it is cleared on read) or until it
reaches full scale. If the counter reaches full scale, it stops
at that reading until cleared.
The 8−bit THERM timer register (Reg. 0x79) is designed
such that Bit 0 is set to 1 on the first THERM assertion. Once
the cumulative THERM assertion time exceeds 45.52 ms,
Bit 1 of the THERM timer is set and Bit 0 becomes the LSB
of the timer with a resolution of 22.76 ms.
Figure 37 illustrates how the THERM timer behaves as the
THERM input is asserted and negated. Bit 0 is set on the first
THERM assertion detected. This bit remains set until the
cumulative THERM assertions exceed 45.52 ms. At this
time, Bit 1 of the THERM timer is set, and Bit 0 is cleared.
Bit 0 now reflects timer readings with a resolution of
22.76 ms.
Table 24. Configuration Register 4 (Reg. 0x7D)
Pin No.
14
Bit Setting
<0> AL2.5V = 1
Table 25. Configuration Register 3 (Reg. 0x78)
Pin No.
5
Bit Setting
<0> ALERT = 1
To Assign THERM Functionality to Pin 9
Pin 9 can be configured as the THERM pin on the
ADT7460. To configure Pin 9 as the THERM pin, set the
THERM ENABLE Bit (Bit 1) in Configuration Register 3
(Address 0x78) = 1.
THERM as an Input
When configured as an input, the THERM pin allows the
user to time assertions on the pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge
system performance. For more information on timing
THERM assertions and generating SMBALERTs based on
THERM, see the Generating Interrupts from Events sections.
The user can also set up the ADT7460 so when the
THERM pin is driven low externally, the fans run at 100%.
The fans run at 100% while the THERM pin is pulled low.
This is done by setting the BOOST bit (Bit 2) in
Configuration Register 3 (Address 0x78) to 1. This works
only if the fan is already running, for example, in manual
mode when the current duty cycle is above 0x00 or in
automatic mode when the temperature is above TMIN. If the
temperature is below TMIN or if the duty cycle in manual
mode is set to 0x00, pulling THERM low externally has no
effect. See Figure 36 for more information.
THERM
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED
3 22.76ms
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 0 1 0
7 6 5 4 3 2 1 0
THERM ASSERTED
. 45.52ms
TMIN
THERM
ACCUMULATE THERM LOW
ASSERTION TIMES
THERM
THERM
TIMER
(REG. 0x79)
0 0 0 0 0 1 0 1
7 6 5 4 3 2 1 0
THERM ASSERTED . 113.8ms
(91.04ms + 22.76ms)
Figure 37. Understanding the THERM Timer
THERM ASSERTED TO LOW AS
AN INPUT. FANS DO NOT GO
TO 100% SINCE TEMPERATURE
IS BELOW TMIN.
When using the THERM timer, be aware of the following:
After a THERM timer read (Reg. 0x79)
♦ The contents of the timer is cleared on read.
♦ The F4P bit (Bit 5) of Status Register 2 needs to be
cleared (assuming the THERM limit has been
exceeded).
THERM ASSERTED TO LOW AS AN
INPUT. FANS GO TO 100% SINCE
TEMPERATURE IS ABOVE TMIN
Figure 36. Asserting THERM Low as an Input in
Automatic Fan Speed Control Mode
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ADT7460
If the THERM timer is read during a THERM assertion
♦ The contents of the timer are cleared.
♦ Bit 0 of the THERM timer is set to 1 (since a
THERM assertion is occurring).
♦ The THERM timer increments from 0.
♦ If the THERM limit (Reg. 0x7A) = 0x00, the F4P
bit is set.
assertion) to 5.825 seconds to be set before an SMBALERT
is generated. The THERM timer value is compared with the
contents of the THERM limit register. If the THERM timer
value exceeds the THERM limit value, the F4P bit (Bit 5) of
Status Register 2 is set and an SMBALERT is generated.
Note that the F4P bit (Bit 5) of Mask Register 2 (Reg. 0x75)
masks out SMBALERTs if this bit is set to 1, although the
F4P bit of Interrupt Status Register 2 is still set if the
THERM limit is exceeded.
Figure 38 is a functional block diagram of the THERM
timer, limit, and associated circuitry. Writing 0x00 to the
THERM limit register (Reg. 0x7A) causes SMBALERT to
be generated on the first THERM assertion. A THERM limit
of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
Generating SMBALERT Interrupts from THERM Events
The ADT7460 can generate SMBALERTs when a
programmable THERM limit has been exceeded. This
allows the systems designer to ignore brief, infrequent
THERM assertions while capturing longer THERM events.
Register 0x7A is the THERM limit register. This 8−bit
register allows a limit from 0 seconds (first THERM
THERM LIMIT
(REG. 0x7A)
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
728.32ms
364.16ms THERM TIMER
(REG. 0x79)
182.08ms
91.04ms
45.52ms
22.76ms
0 1 2 3 4 5 6 7
7 6 5 4 3 2 1 0
THERM
THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT
F4P BIT (BIT 5)
STATUS REGISTER 2
SMBALERT
LATCH
RESET
CLEARED
ON READ
1 = MASK
F4P BIT (BIT 5)
MASK REGISTER 2
(REG. 0x75)
Figure 38. Functional Diagram of the ADT7460 THERM Monitoring Circuitry
Configuring the Desired THERM Behavior
if SMBALERTs based on THERM events are
required.
4. Select a suitable THERM limit value.
This value determines whether an SMBALERT is
generated on the first THERM assertion, or only if
a cumulative THERM assertion time limit is
exceeded. A value of 0x00 causes an SMBALERT
to be generated on the first THERM assertion.
5. Select a THERM monitoring time.
This is how often OS or BIOS level software
checks the THERM timer. For example, BIOS
could read the THERM timer once an hour to
determine the cumulative THERM assertion time.
If, for example, the total THERM assertion time is
<22.76 ms in Hour 1, >182.08 ms in Hour 2, and
>5.825 s in Hour 3, this can indicate that system
performance is degrading significantly since
1. Configure the THERM input.
Setting Bit 1 (THERM ENABLE) of Configuration
Register 3 (Reg. 0x78) enables the THERM
monitoring function.
2. Select the desired fan behavior for THERM events.
Setting Bit 2 (BOOST bit) of Configuration
Register 3 (Reg. 0x78) causes all fans to run at
100% duty cycle whenever THERM is asserted.
This allows fail−safe system cooling. If this bit = 0,
the fans run at their current settings and are not
affected by THERM events.
3. Select whether THERM events should generate
SMBALERT interrupts.
Bit 5 (F4P) of Mask Register 2 (Reg. 0x75), when
set, masks out SMBALERTs when the THERM
limit value is exceeded. This bit should be cleared
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ADT7460
on/off ratio) of a square wave applied to the fan to vary the
fan speed. The external circuitry required to drive a fan using
PWM control is extremely simple. A single MOSFET is the
only drive device required. The specifications of the
MOSFET depend on the maximum current required by the
fan being driven. Typical notebook fans draw a nominal
170 mA, so SOT devices can be used where board space is
a concern. In desktops, fans can typically draw 250 mA to
300 mA each. If the user drives several fans in parallel from
a single PWM output or drives larger server fans, the
MOSFET needs to handle the higher current requirements.
The only other stipulation is that the MOSFET should have
a gate voltage drive, VGS < 3.3 V, for direct interfacing to the
PWM_OUT pin. VGS can be greater than 3.3 V as long as
the pullup on the gate is tied to 5.0 V. The MOSFET should
also have a low on resistance to ensure that there is not
significant voltage drop across the FET. This would reduce
the voltage applied across the fan and, therefore, the
maximum operating speed of the fan.
Figure 40 shows how a 3−wire fan can be driven using
PWM control.
THERM is asserting more frequently on an hourly
basis.
Alternatively, OS or BIOS level software can
time−stamp when the system is powered on. If an
SMBALERT is generated due to the THERM limit
being exceeded, another time−stamp can be taken.
The difference in time can be calculated for a fixed
THERM limit time. For example, if it takes one
week for a THERM limit of 2.914 s to be exceeded
and the next time it takes only one hour, this
indicates a serious degradation in system
performance.
Configuring the ADT7460 THERM Pin as an Output
In addition to the ADT7460 being able to monitor
THERM as an input, the ADT7460 can optionally drive
THERM low as an output. The user can preprogram system
critical thermal limits. If the temperature exceeds a thermal
limit by 0.25°C, THERM asserts low. If the temperature is
still above the thermal limit on the next monitoring cycle,
THERM stays low. THERM remains asserted low until the
temperature is equal to or below the thermal limit. Since the
temperature for that channel is measured only every
monitoring cycle, once THERM asserts, it is guaranteed to
remain low for at least one monitoring cycle.
The THERM pin can be configured to assert low if the
Remote 1, local, or Remote 2 temperature THERM limits
are exceeded by 0.25°C. The THERM limit registers are at
Locations 0x6A, 0x6B, and 0x6C, respectively. Setting
Bit 3 of Registers 0x5F, 0x60, and 0x61 enables the THERM
output feature for the Remote 1, local, and Remote 2
temperature channels, respectively. Figure 39 shows how
the THERM pin asserts low as an output in the event of a
critical overtemperature.
12V
12V
10kΩ
TACH/AIN
10kΩ
4.7kΩ
3.3V
TACH
12V
FAN
1N4148
ADT7460
10kΩ
PWM
Q1
NDT3055L
Figure 40. Driving a 3−Wire Fan Using an N−Channel
MOSFET
THERM LIMIT
0.255C
Figure 40 uses a 10 kW pullup resistor for the TACH
signal. This assumes that the TACH signal is open−collector
from the fan. In all cases, the TACH signal from the fan must
be kept below 5.0 V maximum to prevent damaging the
ADT7460. If in doubt as to whether the fan used has an
open−collector or totem pole TACH output, use one of the
input signal conditioning circuits shown in the Fan Speed
Measurement section.
Figure 41 shows a fan drive circuit using an NPN
transistor such as a general−purpose MMBT2222. While
these devices are inexpensive, they tend to have much lower
current handling capabilities and higher on−resistance than
MOSFETs. When choosing a transistor, care should be taken
to ensure that it meets the fan’s current requirements.
Ensure that the base resistor is chosen such that the
transistor is saturated when the fan is powered on.
THERM LIMIT
TEMP
THERM
ADT7460
MONITORING
CYCLE
Figure 39. Asserting THERM as an Output, Based on
Tripping THERM Limits
Fan Drive Using PWM Control
The ADT7460 uses pulse width modulation (PWM) to
control fan speed. This relies on varying the duty cycle (or
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ADT7460
12V
12V
3.3V
10kΩ
TYPICAL
10kΩ
TACH/AIN
10kΩ
4.7kΩ
3.3V
12V
FAN
TACH
1N4148
TACH4
ADT7460
ADT7460
470Ω
+V
10kΩ
TYPICAL
TACH3
Q1
MMBT2222
PWM
+V
3.3V
3.3V
5V OR
12V FAN
TACH
1N4148
5V OR
12V FAN
TACH
10kΩ
TYPICAL
Figure 41. Driving a 3−Wire Fan Using an NPN
Transistor
Driving Two Fans from PWM3
Figure 43. Interfacing Two Fans in Parallel to the
PWM3 Output Using a Single N−Channel MOSFET
Note that the ADT7460 has four TACH inputs available
for fan speed measurement, but only three PWM drive
outputs. If a fourth fan is being used in the system, it should
be driven from the PWM3 output in parallel with the third
fan. Figure 42 shows how to drive two fans in parallel using
low cost NPN transistors. Figure 43 is the equivalent circuit
using the NDT3055L MOSFET. Note that since the
MOSFET can handle up to 3.5 A, it is simply a matter of
connecting another fan directly in parallel with the first.
Care should be taken in designing drive circuits with
transistors and FETs to ensure that the PWM pins are not
required to source current and that they sink less than the
8 mA maximum current specified on the data sheet.
Table 26. SYNC: Enhance Acoustics Register 1
(Reg. 0x62)
12V
TACH3
PWM3
2.2kΩ
1N4148
3.3V
1kΩ
TACH4
Q1
MMBT3904
10Ω
Mnemonic
<4>
SYNC
Description
1 synchronizes TACH2, TACH3, and
TACH4 to PWM3.
Figure 44 shows how a 2−wire fan may be connected to
the ADT7460. This circuit allows the speed of a 2−wire fan
to be measured, even though the fan has no dedicated TACH
signal. A series resistor, RSENSE, in the fan circuit converts
the fan commutation pulses into a voltage. This is
ac−coupled into the ADT7460 through the 0.01 mF
capacitor. On−chip signal conditioning allows accurate
monitoring of fan speed. The value of RSENSE chosen
depends on the programmed input threshold and on the
current drawn by the fan. For fans drawing approximately
200 mA, a 2 W RSENSE value is suitable when the threshold
is programmed as 40 mV. For fans that draw more current,
such as larger desktop or server fans, RSENSE may be
reduced for the same programmed threshold. The smaller
the threshold programmed the better, since more voltage is
developed across the fan and the fan spins faster. Figure 45
shows a typical plot of the sensing waveform at a
TACH/AIN pin. The most important thing is that the voltage
spikes (either negative going or positive going) are more
than 40 mV in amplitude. This allows fan speed to be
reliably determined.
TACH measurements for fans are synchronized to
particular PWM channels, for example, TACH1 is
synchronized to PWM1. TACH3 and TACH4 are both
synchronized to PWM3, so PWM3 can drive two fans.
Alternatively, PWM3 can be programmed to synchronize
TACH2, TACH3, and TACH4 to the PWM3 output. This
allows PWM3 to drive two or three fans. In this case, the
drive circuitry looks the same as shown in Figure 41,
Figure 42, and Figure 43. The SYNC bit in Register 0x62
enables this function.
3.3V
Bit
Driving 2−Wire Fans
Driving Up to Three Fans from PWM2
ADT7460
Q1
NDT3055L
PWM3
+V
Q2
MMBT2222
ADT7460
10Ω
3.3V
10kΩ
TYPICAL
PWM
Figure 42. Interfacing Two Fans in Parallel to the
PWM3 Output Using Low Cost NPN Transistors
1N4148
5.0V OR
12V FAN
Q1
NDT3055L
0.01μF
TACH/AIN
RSENSE
2Ω
TYPICAL
Figure 44. Driving a 2−Wire Fan
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ADT7460
If the fan TACH output has a resistive pullup to VCC, it can
be connected directly to the fan input, as shown in Figure 47.
n: 250 mV
@: –258mV
VCC
12V
PULLUP
4.7kΩ
TYPICAL
ADT7460
TACH
OUTPUT
FAN SPEED
COUNTER
TACH
Figure 47. Fan with TACH Pullup to VCC
CH1 100mV
CH3 50.0mV
CH2 5.00mV
CH4 50.0mV
M 4.00ms
T
A CH1
If the fan output has a resistive pullup to 12 V (or other
voltage greater than 5.0 V), the fan output can be clamped
with a Zener diode, as shown in Figure 48. The Zener diode
voltage should be greater than VIH of the TACH input but
less than 5.0 V, allowing for the voltage tolerance of the
Zener. A value of between 3 V and 5.0 V is suitable.
–2.00mV
ć1.00000ms
Figure 45. Fan Speed Sensing Waveform at
TACH/AIN Pin
VCC
12V
Laying Out 2−Wire and 3−Wire Fans
PULLUP
4.7kΩ
TYPICAL
Figure 46 shows how to lay out a common circuit
arrangement for 2−wire and 3−wire fans. Some components
are not populated, depending on whether a 2−wire or 3−wire
fan is used.
Figure 48. Fan with TACH Pullup to Voltage . 5.0 V,
for Example, 12 V, Clamped with Zener Diode
If the fan has a strong pullup (less than 1 kW) to 12 V or
a totem−pole output, a series resistor can be added to limit
the Zener current, as shown in Figure 49. Alternatively, a
resistive attenuator may be used, as shown in Figure 50. R1
and R2 should be chosen such that:
2 V < VPULLUP × R2/(RPULLUP + R1 + R2) < 5.0 V
The fan inputs have an input resistance of nominally
160 kW to ground. This should be taken into account when
calculating resistor values.
With a pullup voltage of 12 V and pullup resistor less than
1 kW, suitable values for R1 and R2 would be 100 kW and
47 kW. This gives a high input voltage of 3.83 V.
3.3V OR 5.0V
R5
Q1
MMBT2222
C1
TACH/AIN
R3
R4
FAN SPEED
COUNTER
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 y VCC
1N4148
R2
ADT7460
TACH
ZD1*
12V OR 5.0V
R1
TACH
OUTPUT
PWM
FOR 3-WIRE FANS:
POPULATE R1, R2, R3 R4 = 0Ω
C1 = UNPOPULATED
FOR 2-WIRE FANS:
POPULATE R4, C1
R1, R2, R3 UNPOPULATED
Figure 46. Planning for 2−Wire or 3−Wire Fans on a
PCB
TACH Inputs
Pins 4, 6, 7, and 9 are open−drain TACH inputs for fan
speed measurement.
Signal conditioning in the ADT7460 accommodates the
slow rise and fall times typical of fan tachometer outputs.
The maximum input signal range is 0 V to 5.0 V, even where
VCC is less than 5.0 V. In the event that these inputs are
supplied from fan outputs that exceed 0 V to 5.0 V, either
resistive attenuation of the fan signal or diode clamping
must be included to keep inputs within an acceptable range.
Figure 47 to Figure 50 show circuits for most common fan
TACH outputs.
VCC
5.0V OR 12V
FAN
PULLUP TYP
<1kΩ OR
TOTEM POLE
ADT7460
TACH
TACH
OUTPUT
ZD1
ZENER*
FAN SPEED
COUNTER
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 y V
CC
Figure 49. Fan with Strong TACH Pullup to > VCC or
Totem−Pole Output, Clamped with Zener and Resistor
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ADT7460
high and low byte registers are read from. This prevents
erroneous TACH readings.
The fan tachometer reading registers report the number of
11.11 ms period clocks (90 kHz oscillator) gated to the fan
speed counter, from the rising edge of the first fan TACH
pulse to the rising edge of the third fan TACH pulse
(assuming two pulses per revolution are being counted).
Since the device is essentially measuring the fan TACH
period, the higher the count value the slower the fan is
actually running. A 16−bit fan tachometer reading of
0xFFFF indicates either that the fan has stalled or that it is
running very slowly (<100 RPM).
High Limit: > Comparison Performed
Since the actual fan TACH period is being measured,
exceeding a fan TACH limit by 1 sets the appropriate status bit
and can be used to generate an SMBALERT. The fan TACH
limit registers are 16−bit values consisting of two bytes.
VCC
12V
<1kΩ
ADT7460
R1*
TACH
OUTPUT
TACH
FAN SPEED
COUNTER
R2*
*SEE TEXT
Figure 50. Fan with Strong TACH Pullup to > VCC or
Totem−Pole Output, Attenuated with R1/R2
Fan Speed Measurement
The fan counter does not count the fan TACH output
pulses directly because the fan speed may be less than
1000 RPM. It would take several seconds to accumulate a
reasonably large and accurate count. Instead, the period of
the fan revolution is measured by gating an on−chip 90 kHz
oscillator into the input of a 16−bit counter for N periods of
the fan TACH output (Figure 51). The accumulated count is
actually proportional to the fan tachometer period and
inversely proportional to the fan speed.
Table 28. Fan TACH Limit Registers
CLOCK
PWM
TACH
1
2
Register
Description
Default
0x54
TACH1 minimum low byte
0xFF
0x55
TACH1 minimum high byte
0xFF
0x56
TACH2 minimum low byte
0xFF
0x57
TACH2 minimum high byte
0xFF
0x58
TACH3 minimum low byte
0xFF
0x59
TACH3 minimum high byte
0xFF
0x5A
TACH4 minimum low byte
0xFF
0x5B
TACH4 minimum high byte
0xFF
3
Fan Speed Measurement Rate
4
The fan TACH readings are normally updated once every
second.
The FAST bit (Bit 3) of Configuration Register 3 (Reg.
0x78), when set, updates the fan TACH readings every
250 ms.
If any of the fans are not being driven by a PWM channel
but are instead powered directly from 5.0 V or 12 V, its
associated dc bit in Configuration Register 3 should be set.
This allows TACH readings to be taken on a continuous
basis for fans connected directly to a dc source.
Figure 51. Fan Speed Measurement
N, the number of pulses counted, is determined by the
settings of Register 0x7B (fan pulses per revolution
register). This register contains two bits for each fan,
allowing one, two (default), three, or four TACH pulses to
be counted.
The fan tachometer readings are 16−bit values consisting
of a 2−byte read from the ADT7460.
Table 27. Fan Speed Measurement Registers
Register
Description
Default
0x28
TACH1 low byte
0x00
0x29
TACH1 high byte
0x00
0x2A
TACH2 low byte
0x00
0x2B
TACH2 high byte
0x00
0x2C
TACH3 low byte
0x00
0x2D
TACH3 high byte
0x00
0x2E
TACH4 Low byte
0x00
0x2F
TACH4 high byte
0x00
Calculating Fan Speed
Assuming a fan with a two pulses/revolution (and two
pulses/ revolution being measured), fan speed is calculated
by:
Fan Speed (RPM) = 90,000 × 60/Fan TACH Reading
where:
Fan TACH Reading = 16−Bit Fan Tachometer Reading
For example:
TACH1 High Byte (Reg. 0x29) = 0x17
TACH1 Low Byte (Reg. 0x28) = 0xFF
What is Fan 1 speed in RPM?
Fan 1 TACH Reading = 0x17FF = 6143d
RPM = (f × 60)/Fan 1 TACH Reading
RPM = (90000 × 60)/6143
Fan Speed = 879 RPM
Reading Fan Speed from the ADT7460
If fan speeds are being measured, this involves a
2−register read for each measurement. The low byte should
be read first. This causes the high byte to be frozen until both
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ADT7460
Fan Pulses per Revolution
Table 32. Configuration Register 4 (Reg. 0x7D)
Different fan models can output either 1, 2, 3, or 4 TACH
pulses per revolution. Once the number of fan TACH pulses
is determined, it can be programmed into the fan pulses per
revolution register (Reg. 0x7B) for each fan. Alternatively,
this register can be used to determine the number of
pulses/revolution output by a given fan. By plotting fan
speed measurements at 100% speed with different
pulses/revolution settings, the smoothest graph with the
lowest ripple determines the correct pulses/revolution
value.
Mnemonic
Description
<1:0>
FAN1 Default
2 pulses per revolution
<3:2>
FAN2 Default
2 pulses per revolution
<5:4>
FAN3 Default
2 pulses per revolution
<7:6>
FAN4 Default
2 pulses per revolution
Description
00
1 pulse per revolution
01
2 pulses per revolution
10
3 pulses per revolution
11
4 pulses per revolution
To prevent false interrupts being generated as a fan spins
up (since it is below running speed), the ADT7460 includes
a fan startup timeout function. This is the time limit allowed
for two TACH pulses to be detected on spin−up. For
example, if 2 seconds fan startup timeout is chosen and no
TACH pulses occur within 2 seconds of the start of spin−up,
a fan fault is detected and flagged in the interrupt status
registers.
The ADT7460 is capable of measuring the speed of
2−wire fans, that is, fans without TACH outputs. To do this,
the fan must be interfaced as shown in the Fan Drive
Circuitry section. In this case, the TACH inputs need to be
reprogrammed as analog inputs, AIN.
Table 33. PWM1 to PWM3 Configuration
(Reg. 0x5C to 0x5E)
Table 31. Configuration Register 2 (Reg. 0x73)
Mnemonic
Description
3
AIN4
1 indicates that Pin 9 is reconfigured to
measure the speed of a 2−wire fan
using an external sensing resistor and
coupling capacitor.
2
AIN3
1 indicates that Pin 4 is reconfigured to
measure the speed of a 2−wire fan
using an external sensing resistor and
coupling capacitor.
1
AIN2
1 indicates that Pin 7 is reconfigured to
measure the speed of a 2−wire fan
using an external sensing resistor and
coupling capacitor.
0
AIN1
1 indicates that Pin 6 is reconfigured to
measure the speed of a 2−wire fan
using an external sensing resistor and
coupling capacitor.
Description
These two bits define the input
threshold for 2−wire fan speed
measurements.
00 = ±20 mV
01 = ±40 mV
10 = ±80 mV
11 = ±130 mV
Fan Startup Timeout
2−Wire Fan Speed Measurements
Bit
AINL
The ADT7460 has a unique fan spin−up function. It spins
the fan at 100% PWM duty cycle until two TACH pulses are
detected on the TACH input. Once two pulses are detected,
the PWM duty cycle goes to the expected running value, for
example, 33%. The advantage of this is that fans have
different spin−up characteristics and take different amounts
of time to overcome inertia. The ADT7460 runs the fans just
fast enough to overcome inertia and is quieter on spin−up
than fans programmed to spinup for a given spin−up time.
Table 30. Fan Pulses/Revolution Register Bit Values
Value
Mnemonic
Fan Spin−Up
Table 29. Fan Pulses/Revolution Register (Reg. 0x7B)
Bit
Bit
<3:2>
Bit
Mnemonic
<2:0>
SPIN
Description
These bits control the startup
timeout for PWM1.
000 = no startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
Disabling Fan Startup Timeout
Although fan startup makes fan spin−ups much quieter
than fixed−time spin−ups, the option exists to use fixed
spin−up times. Bit 5 (FSPDIS) = 1 in Configuration Register
1 (Reg. 0x40) disables the spin−up for two TACH pulses.
Instead, the fan spins up for the fixed time as selected in
Registers 0x5C to 0x5E.
PWM Logic State
AIN Switching Threshold
The PWM outputs can be programmed high for 100%
duty cycle (non−inverted) or low for 100% duty cycle
(inverted).
Having configured the TACH inputs as AIN inputs for
2−wire measurements, the user can select the sensing
threshold for the AIN signal.
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ADT7460
Table 34. PWM1 to PWM3 Configuration
(Reg. 0x5C to 0x5E) Bits
Bit
Mnemonic
Description
<4>
INV
0 = logic high for 100% PWM duty cycle
1 = logic low for 100% PWM duty cycle
PWM Drive Frequency
The PWM drive frequency can be adjusted for the
application. Registers 0x5F to 0x61 configure the PWM
frequency for PWM1 to PWM3, respectively.
VARY PWM DUTY
CYCLE WITH 8-BIT
RESOLUTION
Table 35. PWM1 to PWM3 Frequency Registers
(Reg. 0x5F to 0x61)
Bit
Mnemonic
<2:0>
FREQ
Figure 52. Control PWM Duty Cycle Manually with a
Resolution of 0.39%
Description
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8−bit registers,
which allow the PWM duty cycle for each output to be set
anywhere from 0% (0x00) to 100% (0xFF) in steps of 0.39%
(256 steps).
The value to be programmed into the PWMMIN register
is given by:
Value (decimal) = PWMMIN/0.39
Example 1: For a PWM duty cycle of 50%,
Value (decimal) = 50/0.39 = 128d
Value = 128d or 0x80.
Example 2: For a PWM duty cycle of 33%,
Value (decimal) = 33/0.39 = 85d
Value = 85d or 0x54.
Fan Speed Control
The ADT7460 can control fan speed by two different
modes. The first is automatic fan speed control mode. In this
mode, fan speed is automatically varied with temperature
and without CPU intervention, once initial parameters are
set up. The advantage of this is that, in the case of the system
hanging, the system is protected from overheating. The
automatic fan speed control incorporates a feature called
dynamic TMIN calibration. This feature reduces the design
effort required to program the automatic fan speed control
loop. For more information on how to program the
automatic fan speed control loop and dynamic TMIN
calibration, see AN613/D, the Programming the Automatic
Fan Speed Control Loop Application Note.
The second fan speed control method is manual fan speed
control, which is described next.
Table 37. PWM Duty Cycle Registers
The ADT7460 allows the duty cycle of any PWM output
to be manually adjusted. This can be useful if you want to
change fan speed in software or if you want to adjust PWM
duty cycle output for test purposes. Bits <7:5> of Registers
0x5C, 0x5E (PWM configuration) control the behavior of
each PWM output.
<7:5>
BHVR 111
Default
0x30
PWM1 duty cycle
0xFF (100%)
0x31
PWM2 duty cycle
0xFF (100%)
0x32
PWM3 duty cycle
0xFF (100%)
Operating from 3.3 V Standby
The ADT7460 has been specifically designed to operate
from a 3.3 V STBY supply. In computers that support S3 and
S5 states, the core voltage of the processor is lowered in
these states. If using the dynamic TMIN mode, lowering the
core voltage of the processor would change the CPU
temperature and change the dynamics of the system under
dynamic TMIN control. Likewise, when monitoring
THERM, the THERM timer should be disabled during these
states.
Table 36. PWM1 to PWM3 Configuration
(Reg. 0x5C to 0x5E) Bits
Mnemonic
Description
By reading the PWMx current duty cycle registers, users
can keep track of the current duty cycle on each PWM
output, even when the fans are running in automatic fan
speed control mode or in acoustic enhancement mode.
Manual Fan Speed Control
Bit
Register
Description
Manual mode
Once under manual control, each PWM output can be
manually updated by writing to Registers 0x30, 0x32
(PWMx current duty cycle registers).
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ADT7460
XNOR Tree Test Mode
Power−On Default
The ADT7460 includes an XNOR tree test mode. This
mode is useful for in−circuit test equipment at board−level
testing. By applying stimulus to the pins included in the
XNOR tree, it is possible to detect opens or shorts on the
system board. Figure 53 shows the signals that are exercised
in the XNOR tree test mode.
The XNOR tree test is invoked by setting Bit 0 (XEN) of
the XNOR tree test enable register (Reg. 0x6F).
The ADT7460 does not monitor temperature and fan
speed by default on powerup. Monitoring of temperature
and fan speed is enabled by setting the start bit in
configuration Register 1 (Bit 0, Address 0x40) to 1. The fans
run at full speed on powerup. This is because the BHVR bits
(Bits <7:5>) in the PWMx configuration registers are set to
100 (fans run full speed) by default.
TACH1
TACH2
TACH3
TACH4
PWM2
PWM3
PWM1/XTO
Figure 53. XNOR Tree Test
Table 38. ADT7460 Registers
Addr
R/W
0x20
R
0x22
0x25
Desc
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
2.5 V Reading
9
8
7
6
5
4
3
2
0x00
R
VCC Reading
9
8
7
6
5
4
3
2
0x00
R
Remote 1 Temp
9
8
7
6
5
4
3
2
0x80
0x26
R
Local Temperature
9
8
7
6
5
4
3
2
0x80
0x27
R
Remote 2 Temp
9
8
7
6
5
4
3
2
0x80
0x28
R
TACH1 Low Byte
7
6
5
4
3
2
1
0
0x00
0x29
R
TACH1 High Byte
15
14
13
12
11
10
9
8
0x00
0x2A
R
TACH2 Low Byte
7
6
5
4
3
2
1
0
0x00
Lockable
0x2B
R
TACH2 High Byte
15
14
13
12
11
10
9
8
0x00
0x2C
R
TACH3 Low Byte
7
6
5
4
3
2
1
0
0x00
0x2D
R
TACH3 High Byte
15
14
13
12
11
10
9
8
0x00
0x2E
R
TACH4 Low Byte
7
6
5
4
3
2
1
0
0x00
0x2F
R
TACH4 High Byte
15
14
13
12
11
10
9
8
0x00
0x30
R/W
PWM1 Current Duty
Cycle
7
6
5
4
3
2
1
0
0xFF
0x31
R/W
PWM2 Current Duty
Cycle
7
6
5
4
3
2
1
0
0xFF
0x32
R/W
PWM3 Current Duty
Cycle
7
6
5
4
3
2
1
0
0xFF
0x33
R/W
Remote 1 Operating
Point
7
6
5
4
3
2
1
0
0x64
YES
0x34
R/W
Local Temp
Operating Point
7
6
5
4
3
2
1
0
0x64
YES
0x35
R/W
Remote 2 Operating
Point
7
6
5
4
3
2
1
0
0x64
YES
0x36
R/W
Dynamic TMIN
Control Reg. 1
R2T
LT
R1T
PHTR2
PHTL
PHTR1
VCCRES
CYR2
0x00
YES
0x37
R/W
Dynamic TMIN
Control Reg. 2
CYR2
CYR2
CYL
CYL
CYL
CYR1
CYR1
CYR1
0x00
YES
0x3D
R
Device ID Register
7
6
5
4
3
2
1
0
0x27
0x3E
R
Comp ID Number
7
6
5
4
3
2
1
0
0x41
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ADT7460
Table 38. ADT7460 Registers
Addr
R/W
Desc
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
0x3F
R
Revision Number
VER
VER
VER
VER
STP
STP
STP
STP
0x62
or
0x6A
0x40
R/W
0x41
R
Config Register 1
VCC
TODIS
FSPDIS
RES
FSPD
RDY
LOCK
STRT
0x00
Interrupt Stat Reg 1
OOL
R2T
LT
R1T
RES
VCC
RES
2.5 V
0x00
0x42
R
0x44
R/W
Interrupt Stat Reg 2
2.5 V Low Limit
D2
D1
5
FAN3
FAN2
FAN1
OVT
RES
0x00
7
6
5
4
3
2
1
0
0x45
R/W
0x00
2.5 V High Limit
7
6
5
4
3
2
1
0
0xFF
0x48
R/W
VCC Low Limit
7
6
5
4
3
2
1
0
0x00
Lockable
YES
0x49
R/W
VCC High Limit
7
6
5
4
3
2
1
0
0xFF
0x4E
R/W
Remote 1 Temp Low
Limit
7
6
5
4
3
2
1
0
0x81
0x4F
R/W
Remote 1 Temp High
Limit
7
6
5
4
3
2
1
0
0x7F
0x50
R/W
Local Temp Low Limit
7
6
5
4
3
2
1
0
0x81
0x51
R/W
Local Temp High
Limit
7
6
5
4
3
2
1
0
0x7F
0x52
R/W
Remote 2 Temp Low
Limit
7
6
5
4
3
2
1
0
0x81
0x53
R/W
Remote 2 Temp High
Limit
7
6
5
4
3
2
1
0
0x7F
0x54
R/W
TACH1 Min Low Byte
7
6
5
4
3
2
1
0
0xFF
0x55
R/W
TACH1 Min High
Byte
15
14
13
12
11
10
9
8
0xFF
0x56
R/W
TACH2 Min Low Byte
7
6
5
4
3
2
1
0
0xFF
0x57
R/W
TACH2 Min High
Byte
15
14
13
12
11
10
9
8
0xFF
0x58
R/W
TACH3 Min Low Byte
7
6
5
4
3
2
1
0
0xFF
0x59
R/W
TACH3 Min High
Byte
15
14
13
12
11
10
9
8
0xFF
0x5A
R/W
TACH4 Min Low Byte
7
6
5
4
3
2
1
0
0xFF
0x5B
R/W
TACH4 Min High
Byte
15
14
13
12
11
10
9
8
0xFF
0x5C
R/W
PWM1 Config Reg
BHVR
BHVR
BHVR
INV
SLOW
SPIN
SPIN
SPIN
0x62
YES
0x5D
R/W
PWM2 Config Reg
BHVR
BHVR
BHVR
INV
SLOW
SPIN
SPIN
SPIN
0x62
YES
0x5E
R/W
PWM3 Config Reg
BHVR
BHVR
BHVR
INV
SLOW
SPIN
SPIN
SPIN
0x62
YES
0x5F
R/W
Remote 1 TRANGE/
PWM1 Freq.
RANGE
RANGE
RANGE
RANGE
THRM
FREQ
FREQ
FREQ
0xC4
YES
0x60
R/W
Local TRANGE/
PWM2 Freq.
RANGE
RANGE
RANGE
RANGE
THRM
FREQ
FREQ
FREQ
0xC4
YES
0x61
R/W
Remote 2 TRANGE/
PWM3 Freq.
RANGE
RANGE
RANGE
RANGE
THRM
FREQ
FREQ
FREQ
0xC4
YES
0x62
R/W
Enhance Acoustics
Reg. 1
MIN3
MIN2
MIN1
SYNC
EN1
ACOU
ACOU
ACOU
0x00
YES
0x63
R/W
Enhance Acoustics
Reg. 2
EN2
ACOU2
ACOU2
ACOU2
EN3
ACOU3
ACOU3
ACOU3
0x00
YES
0x64
R/W
PWM1 Min Duty
Cycle
7
6
5
4
3
2
1
0
0x80
YES
0x65
R/W
PWM2 Min Duty
Cycle
7
6
5
4
3
2
1
0
0x80
YES
0x66
R/W
PWM3 Min Duty
Cycle
7
6
5
4
3
2
1
0
0x80
YES
0x67
R/W
Remote1 Temp TMIN
7
6
5
4
3
2
1
0
0x5A
YES
0x68
R/W
Local Temp TMIN
7
6
5
4
3
2
1
0
0x5A
YES
0x69
R/W
Remote2 Temp TMIN
7
6
5
4
3
2
1
0
0x5A
YES
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ADT7460
Table 38. ADT7460 Registers
Addr
R/W
0x6A
R/W
Desc
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Lockable
Remote1 THERM
Limit
7
6
5
4
3
2
1
0
0x64
YES
0x6B
R/W
Local THERM Limit
7
6
5
4
3
2
1
0
0x64
YES
0x6C
R/W
Remote2 THERM
Limit
7
6
5
4
3
2
1
0
0x64
YES
0x6D
R/W
Remote1 Local
Hysteresis
HYSR1
HYSR1
HYSR1
HYSR1
HYSL
HYSL
HYSL
HYSL
0x44
YES
0x6E
R/W
Remote2 Temp
Hysteresis
HYSR2
HYSR2
HYSR2
HYSR2
RES
RES
RES
RES
0x40
YES
0x6F
R/W
XNOR Tree Test
Enable
RES
RES
RES
RES
RES
RES
RES
XEN
0x00
YES
0x70
R/W
Remote1 Temp
Offset
7
6
5
4
3
2
1
0
0x00
YES
0x71
R/W
Local Temp Offset
7
6
5
4
3
2
1
0
0x00
YES
0x72
R/W
Remote2 Temp
Offset
7
6
5
4
3
2
1
0
0x00
YES
0x73
R/W
Config Reg 2
SHDN
CONV
ATTN
AVG
AIN4
AIN3
AIN2
AIN1
0x00
YES
0x74
R/W
Interrupt Mask Reg 1
OOL
R2T
LT
R1T
RES
VCC
RES
2.5V
0x00
0x75
R/W
Interrupt Mask Reg 2
D2
D1
F4P
FAN3
FAN2
FAN1
OVT
RES
0x00
0x76
R/W
Ext Resolution 1
RES
RES
VCC
VCC
RES
RES
2.5V
2.5V
0x00
0x77
R/W
Ext Resolution 2
TDM2
TDM2
LTMP
LTMP
TDM1
TDM1
RES
RES
0x00
0x78
R/W
Config Reg 3
DC4
DC3
DC2
DC1
FAST
BOOST
THERM
ENABLE
ALERT
0x00
0x79
R
THERM Status Reg
TMR
TMR
TMR
TMR
TMR
TMR
TMR
ASRT/
TMR
0x00
0x7A
R/W
THERM Limit Reg
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
LIMT
0x00
0x7B
R/W
Fan Pulses per
Revolution
FAN4
FAN4
FAN3
FAN3
FAN2
FAN2
FAN1
FAN1
0x55
0x7D
R/W
Config Reg 4
RES
RES
RES
RES
AINL
AINL
RES
AL2.5V
0x00
YES
0x7E
R
Test Register 1
DO NOT WRITE TO THESE REGISTERS
0x00
YES
0x7F
R
Test Register 2
DO NOT WRITE TO THESE REGISTERS
0x00
YES
YES
Table 39. Voltage Reading Registers (Power−On Default = 0x00) (Note 1)
Register Address
R/W
Description
0x20
Read−only
2.5 V Reading (8 MSBs of reading)
0x22
Read−only
VCC Reading: Measures VCC through the VCC pin (8 MSBs of reading)
1. These voltage readings are in twos complement format. If the extended resolution bits of these readings are also being read, the extended
resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended resolution registers are read, the associated MSB reading
registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.
Table 40. Temperature Reading Registers (Power−On Default = 0x80) (Note 1)
Register Address
R/W
0x25
Read−only
Remote 1 temperature reading−PP(8 MSBs of reading). (Note 2)
0x26
Read−only
Local temperature reading (8 MSBs of reading).
0x27
Read−only
Remote 2 temperature reading (8 MSBs of reading).
Description
1. These voltage readings are in twos complement format.
2. Note that a reading of 0x80 in a temperature reading register indicates a diode fault (open or short) on that channel. If the extended resolution
bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) should be read first. Once the extended
resolution registers are read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB
registers are frozen.
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ADT7460
Table 41. Fan Tachometer Reading Registers (Power−On Default = 0x00) (Note 1)
Register Address
R/W
0x28
Read−only
TACH1 low byte.
Description
0x29
Read−only
TACH1 high byte.
0x2A
Read−only
TACH2 low byte.
0x2B
Read−only
TACH2 high byte.
0x2C
Read−only
TACH3 low byte.
0x2D
Read−only
TACH3 high byte.
0x2E
Read−only
TACH4 low byte.
0x2F
Read−only
TACH4 high byte.
1. The Fan Tachometer Reading registers count the number of 11.11 ms periods (based on an internal 90 kHz clock) that occur between a
number of consecutive fan TACH pulses (default = 2). The number of TACH pulses used to count can be changed using the fan pulses per
revolution register (Reg. 0x7B). This allows the fan speed to be accurately measured. Since a valid fan tachometer reading requires that
two bytes are read, the low byte MUST be read first. Both the low and high bytes are then frozen until read. At power−on, these registers
contain 0x0000 until such time as the first valid fan TACH measurement is read in to these registers. This prevents false interrupts from
occurring while the fans are spinning up.
A count of 0xFFFF indicates that a fan is:
• Stalled or blocked (object jamming the fan).
• Failed (internal circuitry destroyed).
• Not populated. (The ADT7460 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum
high and low byte should be set to 0xFFFF.)
• Alternate function, for example, TACH4 reconfigured as a THERM pin.
• 2−Wire Instead of 3−Wire Fan
Table 42. Current PWM Duty Cycle Registers (Power−On Default = 0xFF) (Note 1)
Register Address
R/W
0x30
R/W
PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
Description
0x31
R/W
PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
0x32
R/W
PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
1. These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7460
reports the PWM duty cycles back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed
control mode. During fan startup, these registers report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty
cycle value by writing to these registers.
Table 43. Operating Point Registers (Power−On Default = 0x64) (Note 1)
Register Address
R/W
Description
0x33
R/W
Remote 1 Operating Point Register (Default = 100°C)
0x34
R/W
Local Temp Operating Point Register (Default = 100°C)
0x35
R/W
Remote 2 Operating Point Register (Default = 100°C)
1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers
will fail. These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled. The
fans being controlled are adjusted to maintain temperature about an operating point.
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ADT7460
Table 44. Register 0x36 — Dynamic TMIN Control Register 1 (Power−On Default = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
Description
<0>
CYR2
R/W
MSB of 3−Bit Remote 2 Cycle Value. The other two bits of the code reside in Dynamic TMIN
Control Register 2 (Reg. 0x37). These three bits define the delay time between making
subsequent TMIN adjustments in the control loop, in terms of number of monitoring cycles. The
system has associated thermal time constants that need to be found to optimize the response
of fans and the control loop.
<1>
Reserved
Read−only
<2>
PHTR1
R/W
PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if
THERM is asserted. The operating point contains the temperature at which THERM is
asserted. This allows the system to run as quietly as possible without affecting system
performance.
PHTR1 = 0 ignores any THERM assertions on the THERM pin. The Remote 1 operating point
register reflects its programmed value.
<3>
PHTL
R/W
PHTL = 1 copies the local channel’s current temperature to the local operating point register if
THERM is asserted. The operating point contains the temperature at which THERM is
asserted. This allows the system to run as quietly as possible without affecting system
performance.
PHTL = 0 ignores any THERM assertions on the THERM pin. The local temperature operating
point register reflects its programmed value.
<4>
PHTR2
R/W
PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if
THERM is asserted. The operating point contains the temperature at which THERM is
asserted. This allows the system to run as quietly as possible without system performance
being affected.
PHTR2 = 0 ignores any THERM assertions on the THERM pin. The Remote 2 operating point
register reflects its programmed value.
<5>
R1T
R/W
R1T = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen
TMIN value is dynamically adjusted based on the current temperature, operating point, and high
and low limits for this zone.
R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the
channel behaves as described in the Automatic Fan Control section.
<6>
LT
R/W
LT = 1 enables dynamic TMIN control on the local temperature channel. The chosen TMIN value
is dynamically adjusted based on the current temperature, operating point, and high and low
limits for this zone.
LT = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel
behaves as described in the Automatic Fan Control section.
<7>
R2T
R/W
R2T = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen
TMIN value is dynamically adjusted based on the current temperature, operating point, and high
and low limits for this zone.
R2T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the
channel behaves as described in the Automatic Fan Control section.
Reserved for future use.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
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ADT7460
Table 45. Register 0x37 — Dynamic TMIN Control Register 2 (Power−On Default = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
Description
<2:0>
CYR1
R/W
3−Bit Remote 1 Cycle Value. These three bits define the delay time between making subsequent
TMIN adjustments in the control loop for the Remote 1 channel, in terms of number of monitoring
cycles. The system has associated thermal time constants that need to be found to optimize the
response of fans and the control loop.
Bits
000
001
010
011
100
101
110
111
<5:3>
CYL
R/W
000
001
010
011
100
101
110
111
CYR2
R/W
Increase Cycle
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
3−Bit Local Temperature Cycle Value. These three bits define the delay time between making
subsequent TMIN adjustments in the control loop for local temperature channel, in terms of
number of monitoring cycles. The system has associated thermal time constants that need to
be found to optimize the response of fans and the control loop.
Bits
<7:6>
Decrease Cycle
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
Decrease Cycle
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
Increase Cycle
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
2 LSBs of 3−Bit Remote 2 Cycle Value. The MSB of the 3−bit code resides in Dynamic TMIN
Control Register 1 (Reg. 0x36). These three bits define the delay time between making
subsequent TMIN adjustments in the control loop for the Remote 2 channel, in terms of number
of monitoring cycles. The system has associated thermal time constants that need to be found
to optimize the response of fans and the control loop.
Bits
000
001
010
011
100
101
110
111
Decrease Cycle
4 Cycles (0.5 s)
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
Increase Cycle
8 Cycles (1 s)
16 Cycles (2 s)
32 Cycles (4 s)
64 Cycles (8 s)
128 Cycles (16 s)
256 Cycles (32 s)
512 Cycles (64 s)
1024 Cycles (128 s)
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
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ADT7460
Table 46. Register 0x40 — Configuration Register 1 (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
Description
<0>
STRT
R/W
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default powerup limit settings. Note
that the limit values programmed are preserved even if a Logic 0 is written to this bit and the
default settings are enabled. This bit becomes read−only and cannot be changed once Bit 1
(lock bit) has been written. All limit registers should be programmed by BIOS before setting this
bit to 1. (Lockable.)
<1>
LOCK
Write
Once
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers
become read−only and cannot be modified until the ADT7460 is powered down and powered
up again. This prevents rogue programs such as viruses from modifying critical system limit
settings. (Lockable.)
<2>
RDY
Read−only
This bit is set to 1 by the ADT7460 to indicate that the device is fully powered−up and ready to
begin systems monitoring.
<3>
FSPD
R/W
<4>
RES
Read−only
<5>
FSPDIS
R/W
Logic 1 disables fan spin−up for two TACH pulses. Instead, the PWM outputs go high for the
entire fan spin−up timeout selected.
<6>
TODIS
R/W
When set to 1, the SMBus timeout feature is disabled. This allows the ADT7460 to be used
with SMBus controllers that cannot handle SMBus timeouts. (Lockable.)
<7>
VCC
R/W
When set to 1, the ADT7460 rescales its VCC pin to measure a 5.0 V supply.
When set to 0, the ADT7460 measures VCC as a 3.3 V supply. (Lockable.)
When set to 1, all fans run at full speed. Power−on default = 0. (This bit cannot be locked.)
Reserved for future use.
Table 47. Register 0x41 — Interrupt Status Register 1 (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
Description
<0>
2.5V
Read−only
A 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<1>
RES
Read−only
Reserved for future use.
<2>
VCC
Read−only
A 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<3>
RES
Read−only
Reserved for future use.
<4>
R1T
Read−only
A 1 indicates that the Remote 1 low or high temperature limit has been exceeded. This bit is
cleared on a read of the status register only if the error condition has subsided.
<5>
LT
Read−only
A 1 indicates the local low or high temperature limit has been exceeded. This bit is cleared on a
read of the Status Register only if the error condition has subsided.
<6>
R2T
Read−only
A 1 indicates that the Remote 2 low or high temperature limit has been exceeded. This bit is
cleared on a read of the status register only if the error condition has subsided.
<7>
OOL
Read−only
A 1 indicates that an out−of−limit event has been latched in Status Register 2. This bit is a
logical OR of all status bits in Status Register 2. Software can test this bit in isolation to
determine whether any of the voltage, temperature, or fan speed readings represented by
Status Register 2 are out−of−limit. This saves the need to read Status Register 2 every
interrupt or polling cycle.
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ADT7460
Table 48. Register 0x42 — Interrupt Status Register 2 (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
<0>
RES
Read−only
Reserved for future use.
Description
<1>
OVT
Read−only
A 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is
cleared on a read of the status register when the temperature drops below THERM − THYST.
<2>
FAN1
Read−only
A 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM1 output is off.
<3>
FAN2
Read−only
A 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM2 output is off.
<4>
FAN3
Read−only
A 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM3 output is off.
<5>
F4P
Read−only
A 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is NOT set
when the PWM3 output is off.
If Pin 9 is configured as the THERM timer input for THERM monitoring, this bit is set when the
THERM assertion time exceeds the limit programmed in the THERM Limit Register (Reg. 0x7A).
<6>
D1
Read−only
A 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.
<7>
D2
Read−only
A 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
Table 49. Voltage Limit Registers (Note 1)
Register Address
R/W
0x44
R/W
2.5 V Low Limit
0x00
0x45
R/W
2.5 V High Limit
0xFF
0x48
R/W
VCC Low Limit.
0x00
0x49
R/W
VCC High Limit.
0xFF
Description (Note 2)
Power−On Default
1. Setting the Configuration Register 1 lock bit has no effect on these registers.
2. High limits: an interrupt is generated when a value exceeds its high limit (> comparison); low limits: an interrupt is generated when a value
is equal to or below its low limit (≤ comparison).
Table 50. Temperature Limit Registers (Note 1)
Register Address
R/W
0x4E
R/W
Remote 1 temperature low limit.
0x81
0x4F
R/W
Remote 1 temperature high limit.
0x7F
0x50
R/W
Local temperature low limit.
0x81
0x51
R/W
Local temperature high limit.
0x7F
0x52
R/W
Remote 2 temperature low limit.
0x81
0x53
R/W
Remote 2 temperature high limit.
0x7F
Description (Note 2)
Power−On Default
1. Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the
Configuration Register 1 lock bit has no effect on these registers.
2. High limits: an interrupt is generated when a value exceeds its high limit (> comparison); low limits: an interrupt is generated when a value
is equal to or below its low limit (≤ comparison).
Table 51. Fan Tachometer Limit Registers (Power−On Default = 0xFF) (Note 1)
Register Address
R/W
Description
0x54
R/W
TACH1 minimum low byte.
0x55
R/W
TACH1 minimum high byte.
0x56
R/W
TACH2 minimum low byte.
0x57
R/W
TACH2 minimum high byte.
0x58
R/W
TACH3 minimum low byte.
0x59
R/W
TACH3 minimum high byte.
0x5A
R/W
TACH4 minimum low byte.
0x5B
R/W
TACH4 minimum high byte.
1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
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ADT7460
Table 52. PWM Configuration Registers (Power−On Default = 0x62) (Note 1)
Register Address
R/W
0x5C
R/W
PWM1 configuration.
Description
0x5D
R/W
PWM2 configuration.
0x5E
R/W
PWM3 configuration.
1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 53. PWM Configuration Register Bits
Bit No.
Mnemonic
R/W
Description
<2:0>
SPIN
R/W
These bits control the startup timeout for PWMx. The PWM output stays high until two valid
TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan
TACH measurement directly after the fan startup timeout period, the TACH measurement reads
0xFFFF and Status Register 2 reflects the fan fault. If the TACH minimum high and low byte
contains 0xFFFF or 0x0000, the Status Register 2 bit is not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 s
110 = 2 s
111 = 4 s
<3>
SLOW
R/W
SLOW = 1 makes the ramp rates for acoustic enhancement four times longer.
<4>
INV
R/W
This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for
100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds
to a logic low output.
<7:5>
BHVR
R/W
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = Local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed (default).
100 = PWMx is disabled.
101 = Fastest speed calculated by Local and Remote 2 Temperature Control PWMx.
110 = Fastest speed calculated by all three Temperature Channels Control PWMx.
111 = Manual mode. PWM duty cycle registers (Reg. 0x30–0x32) become writable.
Table 54. Temp TRANGE/PWM Frequency Registers (Power−On Default = 0xC4) (Note 1)
Register Address
R/W
Description
0x5F
R/W
Remote 1 TRANGE/PWM1 frequency.
0x60
R/W
Local Temp TRANGE/PWM2 frequency.
0x61
R/W
Remote 2 TRANGE/PWM3 frequency.
1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to the is register have no effect.
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ADT7460
Table 55. Temp TRANGE/PWM Frequency Register Bits
Bit No.
Mnemonic
R/W
<2:0>
FREQ
R/W
These bits control the PWMx frequency.
000 = 11.0 Hz
001 = 14.7 Hz
010 = 22.1 Hz
011 = 29.4 Hz
100 = 35.3 Hz (default)
101 = 44.1 Hz
110 = 58.8 Hz
111 = 88.2 Hz
Description
<3>
THRM
R/W
THRM = 1 causes the THERM pin (Pin 9) to assert low as an output when this temperature
channel’s THERM limit is exceeded by 0.25°C. The THERM pin remains asserted until the
temperature is equal to or below the THERM limit. The minimum time that THERM asserts for
is one monitoring cycle. This allows clock modulation of devices that incorporate this feature.
THRM = 0 makes the THERM pin act as an input only, for example, for Pentium 4 PROCHOT
monitoring, when Pin 9 is configured as THERM.
<7:4>
RANGE
R/W
These bits determine the PWM duty cycle vs. temperature slope for automatic fan control.
0000 = 2°C
0001 = 2.5°C
0010 = 3.33°C
0011 = 4°C
0100 = 5°C
0101 = 6.67°C
0110 = 8°C
0111 = 10°C
1000 = 13.33°C
1001 = 16°C
1010 = 20°C
1011 = 26.67°C
1100 = 32°C (Default)
1101 = 40°C
1110 = 53.33°C
1111 = 80°C
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ADT7460
Table 56. Register 0x62 — Enhanced Acoustics Register 1 (Power−On Default = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
Description
[2:0]
ACOU
R/W
These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping
instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate determined
by these bits. This feature enhances the acoustics of the fan being driven by the PWM1 output.
Time Slot Increase
000 = 1
001 = 2
010 = 3
011 = 4
100 = 8
101 = 12
110 = 24
111 = 48
Time for 33% to 100%
35 sec
17.6 sec
11.8 sec
7 sec
4.4 sec
3 sec
1.6 sec
0.8 sec
<3>
EN1
R/W
When this bit is 1, acoustic enhancement is enabled on PWM1 output.
<4>
SYNC
R/W
SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3.
This allows up to three fans to be driven from PWM3 output and their speeds to be measured.
SYNC = 0, only TACH3 and TACH4 are synchronized to PWM3 output.
<5>
MIN1
R/W
When the ADT7460 is in automatic fan control mode, this bit defines whether PWM1 is off
(0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its
TMIN − Hysteresis value.
0 = 0% Duty Cycle below TMIN − Hysteresis
1 = PWM1 Minimum Duty Cycle below TMIN − Hysteresis
<6>
MIN2
R/W
When the ADT7460 is in automatic fan speed control mode, this bit defines whether PWM2 is
off (0% duty cycle) or at PWM2 minimum duty cycle when the controlling temperature is below
its TMIN − Hysteresis value.
0 = 0% Duty Cycle below TMIN − Hysteresis
1 = PWM2 Minimum Duty Cycle below TMIN − Hysteresis
<7>
MIN3
R/W
When the ADT7460 is in automatic fan speed control mode, this bit defines whether PWM3 is
off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below
its TMIN− Hysteresis value.
0 = 0% Duty Cycle below TMIN − Hysteresis
1 = PWM3 Minimum Duty Cycle below TMIN − Hysteresis
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
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ADT7460
Table 57. Register 0x63 — Enhanced Acoustics Register 2 (Power−On Default = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
[2:0]
ACOU3
R/W
Description
These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping
instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate determined
by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output.
Time Slot Increase
000 = 1
001 = 2
010 = 3
011 = 4
100 = 8
101 = 12
110 = 24
111 = 48
Time for 33% to 100%
35 sec
17.6 sec
11.8 sec
7 sec
4.4 sec
3 sec
1.6 sec
0.8 sec
<3>
EN3
R/W
When this bit is 1, acoustic enhancement is enabled on PWM3 output.
<6:4>
ACOU2
R/W
These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping
instantaneously to its newly calculated speed, PWM2 ramps gracefully at the rate determined
by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output.
Time Slot Increase
000 = 1
001 = 2
010 = 3
011 = 4
100 = 8
101 = 12
110 = 24
111 = 48
<7>
EN2
R/W
Time for 33% to 100%
35 sec
17.6 sec
11.8 sec
7 sec
4.4 sec
3 sec
1.6 sec
0.8 sec
When this bit is 1, acoustic enhancement is enabled on PWM2 output.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
Table 58. PWM Min Duty Cycle Registers (Note 1)
Register Address
R/W
Description
Power−On Default
0x64
R/W
PWM1 Min Duty Cycle
0x80 (50% duty cycle)
0x65
R/W
PWM2 Min Duty Cycle
0x80 (50% duty cycle)
0x66
R/W
PWM3 Min Duty Cycle
0x80 (50% duty cycle)
1. These registers become read−only when the ADT7460 is in automatic fan control mode.
Table 59. PWM Min Duty Cycle Register Bits
Bit No.
Mnemonic
R/W
<7:0>
PWM Duty
Cycle
R/W
Description
These bits define the PWMMIN duty cycle for PWMx.
0x00 = 0% Duty Cycle (Fan Off)
0x40 = 25% Duty Cycle
0x80 = 50% Duty Cycle
0xFF = 100% Duty Cycle (Fan Full Speed)
Table 60. TMIN Registers (Note 1)
Register Address
R/W
0x67
R/W
Remote 1 Temperature TMIN
0x5A (90°C)
0x68
R/W
Local Temperature TMIN
0x5A (90°C)
0x69
R/W
Remote 2 Temperature TMIN
0x5A (90°C)
Description (Note 2)
Power−On Default
1. These registers become read−only when the Configuration Register 1 lock bit is set. Further attempts to write to these registers have no
effect.
2. These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at
minimum speed and increase with temperature according to TRANGE.
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ADT7460
Table 61. THERM Limit Registers (Note 1)
Register Address
R/W
0x6A
R/W
Remote 1 THERM Limit
Power−On Default
0x64 (100°C)
0x6B
R/W
Local THERM Limit
0x64 (100°C)
0x6C
R/W
Remote 2 THERM Limit
0x64 (100°C)
Description (Note 2)
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
2. If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail−safe mechanism
incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software
or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below THERM
Limit – Hysteresis. If the THERM pin is programmed as an output, exceeding these limits by 0.25°C can cause the THERM pin to assert
low as an output.
Table 62. Temperature Hysteresis Registers (Note 1)
Register Address
R/W
Power−On Default
0x6D
R/W
Remote 1 Local Temperature Hysteresis
0x44
0x6E
R/W
Remote 2 Temperature Hysteresis
0x40
Description (Note 2)
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
2. Each 4−bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that
channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – Hysteresis. Up to 15°C
of hysteresis may be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel if its
THERM limit is exceeded. The PWM output being controlled goes to 100% if the THERM limit is exceeded and remains at 100% until the
temperature drops below THERM – Hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed less
than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN.
Table 63. XNOR Tree Test Enable Register (Power−On Default = 0x00) (Note 1)
Register Address
R/W
0x6F
R/W
Description
XNOR Tree Test Enable
Bit
Mnemonic
Description
<0>
XEN
If the XEN bit is set to 1, the device enters the XNOR tree test mode.
Clearing the bit removes the device from the XNOR test mode.
<7:1>
RES
Unused. Do not write to these bits.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
Table 64. Remote 1 Temperature Offset Register (Power−On Default = 0x00) (Note 1)
Register Address
R/W
Description
0x70
R/W
Remote 1 Temperature Offset
<7:0>
R/W
Allows a twos complement offset value to be automatically added to or subtracted from the
Remote 1 temperature reading. This is to compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.25°C.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
Table 65. Local Temperature Offset Register (Power−On Default = 0x00) (Note 1)
Register Address
R/W
0x71
R/W
Local Temperature Offset
Description
<7:0>
R/W
Allows a twos complement offset value to be automatically added to or subtracted from the
local temperature reading. LSB value = 0.25°C.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
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ADT7460
Table 66. Remote 2 Temperature Offset Register (Power−On Default = 0x00) (Note 1)
Register Address
R/W
0x72
R/W
Remote 2 Temperature Offset
Description
<7:0>
R/W
Allows a twos complement offset value to be automatically added to or subtracted from the
Remote 2 temperature reading. This is to compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.25°C.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
Table 67. Register 0x73 — Configuration Register 2 (Power−On Default = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
Description
0
AIN1
R/W
AIN1 = 0, Speed of 3−wire fans measured using the TACH output from the fan. AIN1 = 1, Pin 6
is reconfigured to measure the speed of 2−wire fans using an external sensing resistor and
coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
1
AIN2
R/W
AIN2 = 0, Speed of 3−wire fans measured using the TACH output from the fan. AIN2 = 1, Pin 7
is reconfigured to measure the speed of 2−wire fans using an external sensing resistor and
coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
2
AIN3
R/W
AIN3 = 0, Speed of 3−wire fans measured using the TACH output from the fan. AIN3 = 1, Pin 4
is reconfigured to measure the speed of 2−wire fans using an external sensing resistor and
coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
3
AIN4
R/W
AIN4 = 0, Speed of 3−wire fans measured using the TACH output from the fan. AIN4 = 1, Pin 9
is reconfigured to measure the speed of 2−wire fans using an external sensing resistor and
coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (Reg. 0x7D).
4
AVG
R/W
AVG = 1, Averaging on the temperature and voltage measurements is turned off. This allows
measurements on each channel to be made much faster.
5
ATTN
R/W
ATTN = 1, the ADT7460 removes the attenuators from the 2.5 V input. The input can be used
for other functions such as connecting up external sensors.
6
CONV
R/W
CONV = 1, the ADT7460 is put into a single−channel ADC conversion mode. In this mode, the
ADT7460 can be made to read continuously from one input only, for example, Remote 1
temperature. It is also possible to start ADC conversions using an external clock on Pin 6 by
setting Bit 2 of Test Register 2 (Reg. 0x7F). This mode could be useful if, for example, users
wanted to characterize/profile CPU temperature quickly. The appropriate ADC channel is
selected by writing to Bits <7:5> of TACH1 min high byte register (Reg. 0x55).
Bits <7:5> Reg. 0x55
000
010
101
110
111
7
SHDN
R/W
Channel Selected
2.5V
VCC (3.3V)
Remote 1 Temp
Local Temp
Remote 2 Temp
SHDN = 1, ADT7460 goes into shutdown mode. All PWM outputs assert low (or high
depending, on state of INV bit) to switch off all fans. The PWM current duty cycle registers read
0x00 to indicate that the fans are not being driven.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
Table 68. Register 0x74 — Interrupt Mask Register 1 (Power−On Default <7:0> = 0x00)
Bit No.
Mnemonic
R/W
Description
0
2.5V
R/W
A 1 masks SMBALERT for out−of−limit conditions on the 2.5 V channel.
1
RES
R/W
Reserved for future use.
2
VCC
R/W
A 1 masks SMBALERT for out−of−limit conditions on the VCC channel.
3
RES
R/W
Reserved for future use.
4
R1T
R/W
A 1 masks SMBALERT for out−of−limit conditions on the Remote 1 temperature channel.
5
LT
R/W
A 1 masks SMBALERT for out−of−limit conditions on the Local temperature channel.
6
R2T
R/W
A 1 masks SMBALERT for out−of−limit conditions on the Remote 2 temperature channel.
7
OOL
R/W
A 1 masks SMBALERT for any out−of−limit condition in Status Register 2.
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ADT7460
Table 69. Register 0x75 — Interrupt Mask Register 2 (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
0
RES
R/W
Description
1
OVT
Read−only
2
FAN1
R/W
A 1 masks SMBALERT for a Fan 1 fault.
3
FAN2
R/W
A 1 masks SMBALERT for a Fan 2 fault.
4
FAN3
R/W
A 1 masks SMBALERT for a Fan 3 fault.
5
F4P
R/W
A 1 masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM input,
this bit masks SMBALERT for a THERM timer event.
6
D1
R/W
A 1 masks SMBALERT for a diode open or short on Remote 1 channel.
7
D2
R/W
A 1 masks SMBALERT for a diode open or short on Remote 2 channel.
Reserved for future use.
A 1 masks SMBALERT for overtemperature THERM conditions.
Table 70. Register 0x76 — Extended Resolution Register 1
Bit No.
Mnemonic
R/W
<1:0>
2.5V
Read−only
<3:2>
RES
R/W
<5:4>
VCC
Read−only
<7:6>
RES
R/W
Description
2.5 V LSBs. Holds the 2 LSBs of the 10−bit 2.5 V measurement.
Reserved for future use.
VCC LSBs. Holds the 2 LSBs of the 10−bit VCC measurement.
Reserved for future use.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 71. Register 0x77 — Extended Resolution Register 2 (Note 1)
Bit No.
Mnemonic
R/W
<1:0>
RES
R/W
Description
<3:2>
TDM1
Read−only
Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 1 temperature
measurement.
<5:4>
LTMP
Read−only
Local Temperature LSBs. Holds the 2 LSBs of the 10−bit local temperature measurement.
<7:6>
TDM2
Read−only
Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10−bit Remote 2 temperature
measurement.
Reserved for future use.
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 72. Register 0x78 — Configuration Register 3 (Power−On Default = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
Description
<0>
ALERT
R/W
ALERT = 1, Pin 5 (PWM2/ SMBALERT) is configured as an SMBALERT interrupt output to
indicate out−of−limit error conditions.
<1>
THERM
ENABLE
R/W
THERM ENABLE = 1 enables THERM monitoring functionality on Pin 9 when it is configured
as THERM. When THERM is asserted, fans can be run at full speed (if the BOOST bit is set),
or a timer can be triggered to time how long THERM has been asserted for.
<2>
BOOST
R/W
BOOST = 1, assertion of THERM causes all fans to run at 100% duty cycle for fail−safe cooling.
<3>
FAST
R/W
FAST = 1 enables fast TACH measurements on all channels. This increases the TACH
measurement rate from once per second, to once every 250 ms (4×).
<4>
DC1
R/W
DC1 = 1 enables TACH measurements to be continuously made on TACH1.
<5>
DC2
R/W
DC2 = 2 enables TACH measurements to be continuously made on TACH2.
<6>
DC3
R/W
DC3 = 1 enables TACH measurements to be continuously made on TACH3.
<7>
DC4
R/W
DC4 = 1 enables TACH measurements to be continuously made on TACH4.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
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ADT7460
Table 73. Register 0x79 — THERM Status Register (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
Description
<7:1>
TMR
Read−only
Times how long THERM input is asserted. These seven bits read 0 until the THERM assertion
time exceeds 45.52 ms.
<0>
ASRT/TMR0
Read−only
Is set high on the assertion of the THERM input. Cleared on read. If the THERM assertion
time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8−bit TMR reading. This
allows THERM assertion times from 45.52 ms to 5.82 s to be reported back with a resolution
of 22.76 ms.
Table 74. Register 0x7A — THERM Limit Register (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
Description
<7:0>
LIMT
R/W
Sets maximum THERM assertion length allowed before an interrupt is generated. This is an
8−bit limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 s
to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt
Status Register 2 (Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated
immediately upon the assertion of the THERM input.
Table 75. Register 0x7B — Fan Pulses per Revolution Register (Power−On Default = 0x55)
Bit No.
Mnemonic
R/W
Description
<1:0>
FAN1
R/W
Sets number of pulses to be counted when measuring Fan1 speed. Can be used to determine
fan’s pulses per revolution for unknown fan type.
Pulses Counted00 = 1
01 = 2 (Default)
10 = 3
11 = 4
<3:2>
FAN2
R/W
Sets number of pulses to be counted when measuring FAN2 speed. Can be used to determine
fan’s pulses per revolution for unknown fan type.
Pulses Counted00 = 1
01 = 2 (Default)
10 = 3
11 = 4
<5:4>
FAN3
R/W
Sets number of pulses to be counted when measuring FAN3 speed. Can be used to determine
fan’s pulses per revolution for unknown fan type.
Pulses Counted00 = 1
01 = 2 (Default)
10 = 3
11 = 4
<7:6>
FAN4
R/W
Sets number of pulses to be counted when measuring FAN4 speed. Can be used to determine
fan’s pulses per revolution for unknown fan type.
Pulses Counted00 = 1
01 = 2 (Default)
10 = 3
11 = 4
Table 76. Register 0x7D — Configuration Register 4 (Power−On Default = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
<0>
AL2.5V
R/W
<1>
RES
Read−only
<3:2>
AINL
R/W
<7:4>
RES
Description
AL2.5V = 1, Pin 14 (2.5 V/SMBALERT) is configured as an SMBALERT interrupt output to
indicate out−of−limit error conditions.
AL2.5V = 0, Pin 14 (2.5 V/SMBALERT) is configured as a 2.5 V measurement input.
Reserved for future use.
These two bits define the input threshold for 2−wire fan speed measurements:
00 = ±20 mV
01 = ±40 mV
10 = ±80 mV
11 = ±130 mV
Reserved for future use.
1. This register becomes read−only when the Configuration Register 1 lock bit is set to 1. Further attempts to write to this register have no effect.
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ADT7460
Table 77. Register 0x7E — Manufacturer’s Test Register 1 (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
<7:0>
RES
Read−only
Description
Manufacturer’s Test Register. These bits are reserved for manufacturer’s test purposes and
should NOT be written to under normal operation.
Table 78. Register 0x7F — Manufacturer’s Test Register 2 (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
Description
<7:0>
RES
Read−only
Manufacturer’s Test Register. These bits are reserved for manufacturer’s test purposes and
should NOT be written to under normal operation.
ORDERING INFORMATION
Temperature Range
Package Type
Package Option
Shipping†
ADT7460ARQZ
−40°C to +120°C
16−Lead QSOP
RQ−16
98 Rail
ADT7460ARQZ−REEL
−40°C to +120°C
16−Lead QSOP
RQ−16
2500 Tape & Reel
ADT7460ARQZ−RL7
−40°C to +120°C
16−Lead QSOP
RQ−16
1000 Tape & Reel
Device Number
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*The “Z’’ suffix indicates Pb−Free part.
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ADT7460
PACKAGE DIMENSIONS
QSOP16
CASE 492−01
ISSUE O
−A−
Q
R
H x 45_
U
RAD.
0.013 X 0.005
DP. MAX
−B−
MOLD PIN
MARK
RAD.
0.005−0.010
TYP
G
L
0.25 (0.010)
M
P
T
DETAIL E
V
K
C
N 8 PL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. THE BOTTOM PACKAGE SHALL BE BIGGER THAN
THE TOP PACKAGE BY 4 MILS (NOTE: LEAD SIDE
ONLY). BOTTOM PACKAGE DIMENSION SHALL
FOLLOW THE DIMENSION STATED IN THIS
DRAWING.
4. PLASTIC DIMENSIONS DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 6 MILS PER
SIDE.
5. BOTTOM EJECTOR PIN WILL INCLUDE THE
COUNTRY OF ORIGIN (COO) AND MOLD CAVITY I.D.
INCHES
DIM
MIN
MAX
A
0.189
0.196
B
0.150
0.157
C
0.061
0.068
D
0.008
0.012
F
0.016
0.035
G
0.025 BSC
H
0.008
0.018
J 0.0098 0.0075
K
0.004
0.010
L
0.230
0.244
M
0_
8_
N
0_
7_
P
0.007
0.011
Q
0.020 DIA
R
0.025
0.035
U
0.025
0.035
8_
V
0_
MILLIMETERS
MIN
MAX
4.80
4.98
3.81
3.99
1.55
1.73
0.20
0.31
0.41
0.89
0.64 BSC
0.20
0.46
0.249
0.191
0.10
0.25
5.84
6.20
0_
8_
0_
7_
0.18
0.28
0.51 DIA
0.64
0.89
0.64
0.89
0_
8_
−T−
D 16 PL
0.25 (0.010)
SEATING
PLANE
M
T B
S
A
S
J
M
F
DETAIL E
dBCOOL is a registered trademarks of Semiconductor Components Industries, LLC (SCILLC). Pentium is a registered trademark of Intel Corporation.
Protected by U.S. Patent Nos. 6,188,189; 6,169,442; 6,097,239; 5,982,221; and 5,867,012. Other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
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Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
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For additional information, please contact your local
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ADT7460/D