MC74HCT365A Hex 3-State Noninverting Buffer with Common Enables and LSTTL Compatible Inputs http://onsemi.com High−Performance Silicon−Gate CMOS The MC74HCT365A is identical in pinout to the LS365. The device inputs are compatible with LSTTL outputs. This device is a high−speed hex buffer with 3−state outputs and two common active−low Output Enables. When either of the enables is high, the buffer outputs are placed into high−impedance states. The HCT365A has noninverting outputs. MARKING DIAGRAMS 16 SOIC−16 D SUFFIX CASE 751B 16 1 1 Features • • • • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 90 FETs or 22.5 Equivalent Gates These are Pb−Free Devices* HCT365AG AWLYWW 16 16 1 TSSOP−16 DT SUFFIX CASE 948F HCT 365A ALYWG G 1 A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2011 June, 2011 − Rev. 1 1 Publication Order Number: MC74HCT365A/D MC74HCT365A OUTPUT ENABLE 1 A0 1 16 2 15 Y0 3 14 VCC OUTPUT ENABLE 2 A5 A1 4 13 Y5 Y1 5 12 A4 A2 6 11 Y4 Y2 7 10 A3 GND 8 9 Y3 A0 A1 A2 A3 A4 Figure 1. Pin Assignment A5 1 OUTPUT ENABLE 1 15 OUTPUT ENABLE 2 FUNCTION TABLE Inputs Output Enable 1 Enable 2 A Y L L H X L L X H L H X X L H Z Z 2 3 4 5 6 7 10 9 12 11 14 13 Y0 Y1 Y2 Y3 Y4 Y5 PIN 16 = VCC PIN 8 = GND Figure 2. Logic Diagram X = don’t care Z = high impedance ORDERING INFORMATION Package Shipping† MC74HCT365ADG SOIC−16 (Pb−Free) 48 Units / Rail MC74HCT365ADR2G SOIC−16 (Pb−Free) 2500 Units / Reel MC74HCT365ADTG TSSOP−16* (Pb−Free) 96 Units / Rail MC74HCT365ADTR2G TSSOP−16* (Pb−Free) 2500 Units / Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 2 MC74HCT365A MAXIMUM RATINGS* Symbol Parameter Value Unit – 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin ± 20 mA Iout DC Output Current, per Pin ± 25 mA ICC DC Supply Current, VCC and GND Pins ± 50 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature – 65 to + 150 _C SOIC Package† TSSOP Package† This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. †Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C TSSOP Package: − 6.1 mW/_C from 65_ to 125_C ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min DC Supply Voltage (Referenced to GND) Max Unit 4.5 5.5 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature Range, All Package Types –55 +125 _C tr, tf Input Rise/Fall Time (Figure 1) 0 500 ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V – 55 to 25_C v 85_C v 125_C Unit VIH Minimum High−Level Input Voltage Vout = VCC – 0.1 V |Iout| v 20 μA 4.5 to 5.5 2.0 2.0 2.0 V VIL Maximum Low−Level Input Voltage Vout = 0.1 V |Iout| v 20 μA 4.5 to 5.5 0.8 0.8 0.8 V VOH Minimum High−Level Output Voltage Vin = VIH |Iout| v 20 μA 4.5 4.4 4.4 4.4 V 4.5 3.98 3.84 3.70 VOL Maximum Low−Level Output Voltage 4.5 0.1 0.1 0.1 4.5 0.26 0.33 0.40 Symbol Parameter Test Conditions Vin = VIH |Iout| v 6.0 mA Vin = VIL |Iout| v 20 μA Vin = VIL |Iout| v 6.0 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 4.5 ±0.1 ±1.0 ±1.0 μA IOZ Maximum Three−State Leakage Current Output in High−Impedance State Vin = VIL or VIH Vout = VCC or GND 4.5 ±0.5 ±5.0 ±10 μA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 μA 4.5 4 40 160 μA DICC Additional Quiescent Supply Current Vin = 2.4V, Any One Input Vin = VCC or GND, Other Inputs Iout = 0mA http://onsemi.com 3 5.5 ≥ −55°C 25 to 125°C 2.9 2.4 mA MC74HCT365A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V – 55 to 25_C v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, Input A to Output Y (Figures 1 and 3) 4.5 24 30 36 ns tPLZ, tPHZ Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) 4.5 44 55 66 ns tPZL, tPZH Maximum Propagation Delay, Output Enable to Output Y (Figures 2 and 4) 4.5 44 55 66 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 3) 4.5 12 15 18 ns Cin Maximum Input Capacitance — 10 10 10 pF Cout Maximum Three−State Output Capacitance (Output in High−Impedance State) — 15 15 15 pF Typical @ 25°C, VCC = 5.0 V CPD 60 Power Dissipation Capacitance (Per Buffer)* * Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . http://onsemi.com 4 pF MC74HCT365A SWITCHING WAVEFORMS (VI = 0 to 3 V, VM = 1.3 V) VCC tf tr INPUT A (VI) VCC 90% VM 10% OUTPUT ENABLE (VI) GND tPLH tPHL OUTPUT Y 90% 50% 10% OUTPUT Y VM GND tPZL tTLH HIGH IMPEDANCE 50% tPZH OUTPUT Y tPLZ tPHZ 10% VOL 90% VOH 50% HIGH IMPEDANCE tTHL Figure 1. Figure 2. TEST CIRCUITS TEST POINT TEST POINT OUTPUT DEVICE UNDER TEST OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. 1 kΩ CL* *Includes all probe and jig capacitance Figure 3. Figure 4. LOGIC DETAIL TO OTHER FIVE BUFFERS ONE OF 6 BUFFERS VCC Y INPUT A OUTPUT ENABLE 1 OUTPUT ENABLE 2 http://onsemi.com 5 MC74HCT365A PACKAGE DIMENSIONS TSSOP−16 DT SUFFIX CASE 948F−01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE D H G DIM A B C D F G H J J1 K K1 L M DETAIL E SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 6 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HCT365A PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE K −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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