Burr-Brown BUF07703 Multi-channel lec gamma correction buffer Datasheet

¨
¨
¨
SBOS269A – MARCH 2003 – REVISED JUNE 2003
FEATURES
D Gamma Correction Channels: 6, 4
D Integrated VCOM Buffer
D Excellent Output Current Drive:
D
D
D
D
D
D
D
DESCRIPTION
– Gamma Channels: > 10mA
– VCOM: > 100mA typ
Large Capacitive Load Drive Capability
Rail-to-Rail Output
PowerPAD Package: BUF07703
Low-Power/Channel: < 250µA
Wide Supply Range: 4.5V to 16V
Specified for 0°C to 85°C
High ESD Rating: 4kV HBM, 1.5kV CDM
APPLICATIONS
D LCD Flat Panel Displays
D LCD Television Displays
GAMMA
CHANNELS
VCOM CHANNELS
BUF07703
6
1
BUF06703
6
0
BUF05703
4
1
MODEL
RELATED PRODUCTS
MODEL
GAMMA
CHANNELS
VCOM CHANNELS
BUF11702
10
1
BUF04701
4
—
TLV2374
4
—
The BUFxx703 are a series of multi-channel buffers
targeted towards gamma correction in high-resolution
liquid crystal display (LCD) panels. The number of
gamma correction channels required depends on a
variety of factors and differs greatly from design to
design. Therefore, various channel options are offered.
For additional space and cost savings, a VCOM channel
with higher current drive capability is integrated in the
BUF07703 and BUF05703.
A flow through pin out has been adopted to allow simple
PCB routing and maintain the cost effectiveness of this
solution. All inputs and outputs of the BUFxx703
incorporate internal ESD protection circuits that prevent
functional failures at voltages up to 4kV HBM and 1.5kV
CDM.
The various buffers within the BUFxx703 are carefully
matched to the voltage I/O requirements for the gamma
correction application. Each buffer is capable of driving
heavy capacitive loads and offers fast load current
switching. The VCOM channel has increased output
drive of > 100mA and can handle even larger capacitive
loads.
The BUF07703 is available in the HTSSOP
PowerPAD package for dramatically increased power
dissipation capability. The BUF06703 and BUF05703
are available in standard TSSOP-16 and TSSOP-14
packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright  2003, Texas Instruments Incorporated
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PARAMETERS
Supply, VDD(2)
Input Voltage Range, VI
BUFXX703
UNIT
16.5
V
VDD
V
See Dissipation Rating Table
Continuous Total Power Dissipation
0 to +85
°C
Maximum Junction Temperature, TJ
150
°C
Storage Temperature Range, TSTG
–65 to 150
°C
Operating Free–Air Temperature Range, TA
Lead Temperature 1.6mm (1/16 inch) from Case for 10s
260
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to GND.
ORDERING INFORMATION
PRODUCT
PACKAGE–LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
BUF07703
HTSSOP 20
HTSSOP–20
PWP
0°C to +85°C
85°C
BUF06703
TSSOP 16
TSSOP–16
PW
0°C to +85°C
85°C
BUF05703
TSSOP 14
TSSOP–14
PW
0°C to +85°C
85°C
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
BUF07703PWP
Tube, 70
BUF07703PWPR
Reels, 2000
BUF06703PW
Tube, 90
BUF06703PWR
Reels, 2000
BUF05703PW
Tube. 90
BUF05703PWR
Reels, 2000
(1) For the most current specification and package information, refer to our web site at www.ti.com.
DISSIPATION RATING TABLE
PACKAGE TYPE
PACKAGE
DESIGNATOR
θJC
( C/W)
θJA
( C/W)
TA ≤ 25°C
POWER RATING
TSSOP–20 PowerPAD
PWP (20)
1.40(1)
32.63(1)
3.83W(1)
TSSOP–16
PW (16)
—
108
1.15W
TSSOP–14
PW (14)
—
112
1.11W
(1) Thermal specifications assume 2oz trace and copper pad with solder.
RECOMMENDED OPERATING CONDITIONS
MIN
Supply Voltage, VDD
4.5
2
MAX
UNI
T
16
V
+85
°C
TSSOP-20 PowerPAD
+125
°C
TSSOP-16, 14
+150
°C
Operating Free-Air Temperature, TA
Junction Temperature
NOM
0
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
EQUIVALENT SCHEMATICS OF INPUTS AND OUTPUTS
INPUT STAGE OF BUFFERS
INPUT STAGE OF BUFFERS
BUF07703: 1 to 3 and VCOM
BUF06703: 1 to 3
BUF05703: 1 to 2 and VCOM
BUF07703: 4 to 6
BUF06703: 4 to 6
BUF05703: 3 to 4
VS
OUTPUT STAGE OF ALL BUFFERS
VS
Previous
Stage
VS
Next
Stage
Buffer
Input
Buffer
Input
Inverting
Input
Buffer
Output
Buffer
Output
Buffer
Output
Previous
Stage
Next Stage
GND
GND
GND
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VDD = 4.5V to 16V, TA = 25°C, unless otherwise noted.
PARAMETER
VIO
TEST CONDITIONS
VI = VDD/2, RS = 50 Ω
Input offset voltage
TA†
25°C
MIN
TYP
MAX
1.5
12
Full
Range(1)
15
25°C
UNIT
mV
1
IIB
Input bias current
VI = VDD/2
kSVR
Supply voltage rejection ratio (∆VDD/∆VIO)
VDD = 4.5V to 16V
Buffer gain
VI = 5V
25°C
0.9995
V/V
Full
Range(1)
200
25°C
62
Full
Range(1)
60
pA
80
dB
BW_3dB
3dB Bandwidth
Gamma Buffers
VCOM Buffer
CL = 100pF, RL = 2kΩ
25°C
0.8
0.7
MHz
SR
Slew Rate
Gamma Buffers
VCOM Buffer
CL = 100pF, RL = 2kΩ
VIN = 2V to 8V
25°C
1
0.7
V/µs
Transient Load Regulation
IO = 0 to ±5mA VO = 5V
CL = 100pF tT = 0.1µs
25°C
900
mV
Transient Load Response
See Figure 2
25°C
160
mV
tS (I–sink)
Settling Time–Current
IO = 0 to –5mA VO = 5V
CL = 100pF RL = 2kΩ
Full
Range(1)
1
µs
tS (I–src)
Settling Time–Current
Full
Range(1)
2
µs
6
4.6
µs
tS
Settling Time–
Voltage
IO = 0 to +5mA VO = 5V
CL = 100pF RL = 2kΩ
VI = 4.5V to 5.5V 0.1%
VI = 5.5V to 4.5V 0.1%
5.8
5.6
µs
Vn
Noise Voltage
Crosstalk
(1) Full Range is 0°C to +85°C.
Gamma Buffers
25°C
VCOM Buffer
VI = 4.5V to 5.5V 0.1%
VI = 5.5V to 4.5V 0.1%
Gamma Buffers
VCOM Buffer
VI = 5V f = 1kHz
25°C
45
40
nv/√Hz
VIP–P = 6V, f = 1kHz
25°C
85
dB
3
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS: BUF07703
over operating free-air temperature range, VDD = 4.5V to 16V, TA = 25°C, unless otherwise noted.
PARAMETER
IDD
Supply Current
ALL
TEST CONDITIONS
VO = VDD/2, VI = VDD/2
VDD = 10V
TA(1)
25°C
25°C
25
C
VCOM Buffer
VCOM buffer sinking
VDD = 10V,
IO = 1mA to 30mA
VCOM buffer sourcing
VDD = 10V,
IO = –1mA to –30mA
Buffers 1–6
1 6 sinking
VDD = 10V,
IO = 1mA to 10mA
1
Full Range
0.85
Full Range
VDD = 16V,
VI = 0V
IO = 5mA,
VOH1
Buffer 1
VDD = 10V,
VI = 9.8V
IO = –10mA,
VOH2/3
Buffer 2/3
VDD = 10V,
VI = 9.5V
IO = –10mA,
Buffer 4/5
VDD = 10V,
VI = 8V
IO = –10mA,
VOH6
Buffer 6
VDD = 10V,
VI = 8V
IO = –10mA,
VOHCOM
VCOM Buffer
VDD = 10 V,
VI = 8V
IO = –30mA,
VOL1
Buffer 1
VDD = 10V,
VI = 2 V
IO = 10mA,
0.85
VOL2/3
Buffer 2/3
VDD = 10V,
VI = 2 V
IO = 10mA,
Buffer 4/5
VDD = 10V,
VI = 0.5 V
IO = 10mA,
VOL6
Buffer 6
VDD = 10V,
VI = 0.2 V
IO = 10mA,
VOLCOM
VCOM Buffer
VDD = 10V,
VI = 2V
IO = 30mA,
25°C
9.75
9.7
25°C
9.45
Full range
9.4
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
V
V
8
V
8
V
2.05
2.1
2
2.05
2.1
0.5
Full range
0.55
0.6
0.2
Full range
25°C
V
8
2
0.25
0.3
2
V
V
9.5
Full range
Full range
0.15
9.8
Full range
25°C
1
0.2
25°C
25°C
mV/mA
15.9
0.1
Full range
25°C
1
1.5
Full range
25°C
1.2
1.5
25°C
15.8
Buffer 6
V
VDD
1.2
2.5
25°C
15.85
Low-level
saturated output
voltage
UNIT
2.5
25°C
25°C
VOSL6
4
Full Range
Full range
IO = –5mA,
(1) Full Range is 0°C to +85°C.
mA
VDD
VDD–1
1
Full Range
VDD = 16V,
VI = 16V
Low-level output
out ut
voltage
25°C
VDD = 10V,
IO = –1mA to –10mA
Buffer 1
VOL4/5
mA
3
0
Buffers 1
1–6
6 sourcing
High-level
g
saturated output
voltage
High-level output
out ut
voltage
2
1
VOSH1
VOH4/5
MAX
1.7
1
Buffers 4–6
Load regulation
TYP
Full Range
Buffers 1–3
Common Mode Input
In ut Range
MIN
V
V
V
V
2.05
2.1
V
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS: BUF06703
over operating free-air temperature range, VDD = 4.5V to 16V, TA = 25°C, unless otherwise noted.
PARAMETER
IDD
Supply Current
ALL
TEST CONDITIONS
VO = VDD/2, VI = VDD/2
VDD = 10V
TA(1)
25°C
TYP
MAX
1.7
2
mA
3
mA
Full Range
Buffers 1–3
Common Mode Input Range
MIN
1
VDD
0
VDD–1
25°C
Buffers 4–6
Buffers 1–6
1 6 sinking
VDD = 10V,
IO = 1mA to 10mA
Buffers 1
1–6
6 sourcing
VDD = 10V,
IO = –1mA to –10mA
Load regulation
VOSH1
High-level
g
saturated output
voltage
Buffer 1
VDD = 16V,
VI = 16V
IO = –5mA,
VOSL6
Low-level
saturated output
voltage
Buffer 6
VDD = 16V,
VI = 0V
IO = 5mA,
VOH1
Buffer 1
VDD = 10V,
VI = 9.8V
IO = –10mA,
VOH2/3
Buffer 2/3
VDD = 10V,
VI = 9.5V
IO = –10mA,
VOH4/5
Buffer 4/5
VDD = 10V,
VI = 8V
IO = –10mA,
VOH6
Buffer 6
VDD = 10V,
VI = 8V
IO = –10mA,
VOL1
Buffer 1
VDD = 10V,
VI = 2 V
IO = 10mA,
VOL2/3
Buffer 2/3
VDD = 10V,
VI = 2 V
IO = 10mA,
VOL4/5
Buffer 4/5
VDD = 10V,
VI = 0.5 V
IO = 10mA,
VOL6
Buffer 6
VDD = 10V,
VI = 0.2 V
IO = 10mA,
High-level output
out ut
voltage
Low-level output
out ut
voltage
25°C
0.85
Full Range
0.85
Full Range
15.85
Full range
15.8
25°C
V
0.1
25°C
9.75
9.7
25°C
9.45
Full range
9.4
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
9.8
V
8
V
2.05
2.1
2
Full range
2.05
2.1
0.5
Full range
25°C
V
8
2
0.55
0.6
0.2
V
V
9.5
Full range
Full range
0.15
0.2
Full range
25°C
mV/mA
15.9
Full range
25°C
1
1.5
25°C
25°C
V
1
1.5
25°C
UNIT
V
V
V
0.25
0.3
V
(1) Full Range is 0°C to +85°C.
5
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS: BUF05703
over operating free-air temperature range, VDD = 4.5V to 16V, TA = 25°C, unless otherwise noted.
PARAMETER
IDD
Supply Current
ALL
TEST CONDITIONS
VO = VDD/2, VI = VDD/2
VDD = 10V
TA(1)
25°C
25°C
25
C
VCOM Buffer
VCOM buffer sinking
VDD = 10V,
IO = 1mA to 30mA
VCOM buffer sourcing
VDD = 10V,
IO = –1mA to –30mA
Buffers 1–4
1 4 sinking
VDD = 10V,
IO = 1mA to 10mA
1
Full Range
0.85
Full Range
VDD = 16V,
VI = 16V
IO = 5mA,
VOH1
Buffer 1
VDD = 10V,
VI = 9.8V
IO = –10mA,
VOH2
Buffer 2
VDD = 10V,
VI = 9.5V
IO = –10mA,
Buffer 3
VDD = 10V,
VI = 8V
IO = –10mA,
VOH4
Buffer 4
VDD = 10V,
VI = 8V
IO = –10mA,
VOHCOM
VCOM Buffer
VDD = 10 V,
VI = 8V
IO = –30mA,
VOL1
Buffer 1
VDD = 10V,
VI = 2 V
IO = 10mA,
0.85
VOL2
Buffer 2
VDD = 10V,
VI = 2 V
IO = 10mA,
Buffer 3
VDD = 10V,
VI = 0.5 V
IO = 10mA,
VOL4
Buffer 4
VDD = 10V,
VI = 0.2 V
IO = 10mA,
VOLCOM
VCOM Buffer
VDD = 10V,
VI = 2V
IO = 30mA,
25°C
9.75
9.7
25°C
9.45
Full range
9.4
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
25°C
7.95
Full range
7.9
V
V
8
V
8
V
2.05
2.1
2
2.05
2.1
0.5
Full range
0.55
0.6
0.2
Full range
25°C
V
8
2
0.25
0.3
2
V
V
9.5
Full range
Full range
0.15
9.8
Full range
25°C
1
0.2
25°C
25°C
mV/mA
15.9
0.1
Full range
25°C
1
1.5
Full range
25°C
1.2
1.5
25°C
15.8
Buffer 4
V
VDD
1.2
2.5
25°C
15.85
Low-level
saturated output
voltage
UNIT
2.5
25°C
25°C
VOSL4
6
Full Range
Full range
IO = –5mA,
(1) Full Range is 0°C to +85°C.
mA
VDD
VDD–1
1
Full Range
VDD = 16V,
VI = 0V
Low-level output
out ut
voltage
25°C
VDD = 10V,
IO = –1mA to –10mA
Buffer 1
VOL3
mA
3
0
Buffers 1
1–4
4 sourcing
High-level
g
saturated output
voltage
High-level output
out ut
voltage
2
1
VOSH1
VOH3
MAX
1.7
1
Buffers 3–4
Load regulation
TYP
Full Range
Buffers 1–2
Common Mode Input
In ut Range
MIN
V
V
V
V
2.05
2.1
V
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
BUF07703 Pin Configuration and Landing Pattern
BUF06703 Pin Configuration
BUF05703 Pin Configuration
7
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
PARAMETER MEASUREMENT INFORMATION
Buffer
RNULL
CL
RL
Figure 1. Bandwidth and Phase Shift Test Circuit
Buffer
VO
RS
5V
CS
5V
LCD Driver
CL
Equivalent Load
RL
VTL
tT
V1
Source
Test
Gamma Channels
V1
0V
VTL
2V
tT
0.1 µs
CS
100 pF
RS
100 Ω
CL
100 pF
RL
1 kΩ
Sink
Gamma Channels
10 V
2V
0.1 µs
100 pF
100 Ω
100 pF
1 kΩ
Figure 2. Transient Load Response Test Circuit
Buffer
tT
VO
5V
RNULL
RL
CL
10 V
5V
0V
VTL
VTL
Figure 3. Transient Load Regulation Test Circuit
8
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DC CURVES
VDD = 10V, unless otherwise noted.
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
20
20
5
0
–5
–10
–15
–20
VCOM Buffer
10
5
0
–5
–10
–15
–20
2
3 4
5 6 7
VI – Input Voltage – V
8
9
10
Figure 4
2
4
6
VI – Input Voltage – V
8
V OH – High-Level Output Voltage – V
200
150
100
50
0
10 20 30 40 50 60 70
TA – Free-Air Temperature – °C
9.5
9
TA = 0°C
8
TA = 25°C
TA = 85°C
6.5
BUF06703
BUF07703
Channels 2 to 3
TA = 0°C
8
TA = 25°C
TA = 85°C
7
6
25
50
75
100
125 150
IOH – High-Level Output Current – mA
2
4
6
VI – Input Voltage – V
8
10
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
Channel 1
9.9
TA = 0°C
9.8
9.7
TA = 25°C
9.6
9.5
9.4
TA = 85°C
9.3
9.2
9.1
9
0
0
50
100
150
200
250
IOH – High-Level Output Current – mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
10
BUF05703
Channels 3 to 4
9
8
7
TA = 0°C
TA = 25°C
6
TA = 85°C
5
4
3
BUF06703
BUF07703
Channels 4 to 6
2
1
0
25
50
75
100
125
150
IOH – High-Level Output Current – mA
Figure 11
5 10 15 20 25 30 35 40 45 50
IOH – High-Level Output Current – mA
Figure 9
0
5
Figure 10
0
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
V OH – High-Level Output Voltage – V
BUF05703
Channel 2
0
–15
Figure 8
10
5.5
–10
10
9
5
80 85
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
6
–5
Figure 6
Channel 1
Figure 7
7
0
10
10
7.5
5
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
250
8.5
10
Figure 5
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
0
15
–20
0
V OH – High-Level Output Voltage – V
1
10
V OH – High-Level Output Voltage – V
0
I IB – Input Bias Current – pA
BUF06703
BUF07703
Channels 4 to 6
V IO – Input Offset Voltage – mV
10
20
BUF05703
Channels 3 to 4
15
V IO – Input Offset Voltage – mV
V IO – Input Offset Voltage – mV
BUF06703
BUF07703
Channels 1 to 3
BUF05703
Channels 1 to 2
15
V OH – High-Level Output Voltage – V
INPUT OFFSET VOLTAGE
vs
INPUT VOLTAGE
VCOM Buffer
9
8
TA = 0°C
7
6
5
TA = 25°C
4
3
TA = 85°C
2
1
0
0
50
100
150
200
250
IOH – High-Level Output Current – mA
Figure 12
9
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SBOS269A – MARCH 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DC CURVES (continued)
VDD = 10V, unless otherwise noted.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
5
8
BUF06703
BUF07703
Channels 1 to 3
7
6
5
4
TA = 0°C
3
TA = 25°C
TA = 85°C
2
1
0
0
5
BUF05703
Channel 3
4.5
4
BUF06703
BUF07703
Channels 4 to 5
3.5
3
2.5
2
TA = 0°C
1.5
TA = 25°C
1
TA = 85°C
0.5
125
50
100
150
25
75
IOL – Low-Level Output Current – mA
0.5
0.4
TA = 0°C
0.3
TA = 25°C
TA = 85°C
0.1
0
0
BUF06703
BUF07703
Channel 6
1
0
50
100
150
200
250
IOL – Low-Level Output Current – mA
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
4
TA = 0°C
VCOM Buffer
9
3.5
8
7
6
5
TA = 25°C
4
3
TA = 85°C
2
0
50
100
150
200
IOL – Low-Level Output Current – mA
250
Figure 17
2.5
2
TA = 85°C
1.5
1
4
15 V
3.5
10 V
3
5V
2.5
2
1.5
1
0.5
0
0
10
20
30
40
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VDD – Supply Voltage – V
Figure 18
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
I DD – Supply Current – mA
TA = 70°C
0
0
10 15 20 25 30 35 40 45 50
IOL – Low-Level Output Current – mA
5
3
TA = 25°C
0.5
TA = 0°C
1
Figure 16
50
60
70
TA – Free-Air Temperature – °C
Figure 19
10
2
Figure 15
I DD – Supply Current – mA
BUF06703
BUF07703
Channel 6
V OL– Low-Level Output Voltage – V
0.8
0.2
TA = 85°C
1.5
0
10
BUF05703
Channel 4
0.6
3
2.5
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
1
0.7
TA = 0°C
TA = 25°C
Figure 14
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.9
4
3.5
25
75
125
50
100
150
IOL – Low-Level Output Current – mA
0
BUF05703
Channel 4
4.5
0.5
0
Figure 13
V OL – Low-Level Output Voltage – V
V OL– Low-Level Output Voltage – V
BUF05703
Channels 1 to 2
9
V OL– Low-Level Output Voltage – V
V OL – Low-Level Output Voltage – V
10
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
80
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
AC CURVES
VDD = 10V, unless otherwise noted.
–3 dB BANDWIDTH
vs
SUPPLY VOLTAGE
–3 dB BANDWIDTH
vs
FREE-AIR TEMPERATURE
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
PSRR – Power Supply Rejection Ratio – dB
1.2
1.25
1
0.75
BUF05703
Channel 3
BW – –3 dB Bandwidth – MHz
BW – –3 dB Bandwidth – MHz
Gamma Channels
BUF06703
BUF07703
Channel 5
VCOM Buffer
0.5
0.25
RL = 2 kΩ
CL = 100 pF
TA = 25°C
0
0
2
4
6
8
10 12
VDD – Supply Voltage – V
Figure 20
14
1
5V
0.8
10, 15 V
5, 10, 15 V
0.6
VCOM Buffer
0.4
0.2
RL = 2 kΩ
CL = 100 pF
0
16
0
10 20 30 40 50 60 70
TA – Free-Air Temperature – °C
Figure 21
RL = 2 kΩ
CL = 100 pF
80
70
60
Gamma Channels
50
VCOM Buffer
40
30
20
10
0
80
10
100
1k
10 k 100 k
f – Frequency – Hz
1M
10 M
Figure 22
11
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
TRANSIENT CURVES
SUPPLY VOLTAGE, OUTPUT VOLTAGE
AND SUPPLY CURRENT
16
VDD
12
8
4
3
VDD = 0 to 15 V
RL = 2 kΩ
CL = 100 pF
VI = VDD/2
TA = 25°C
1
0
–1
0
5
10
15
20
25
30
35
40
45
50
4
VCOM
Buffer
3
2
Gamma Channels
1
0
0
2
Figure 23
4
6
8 10 12
t – Time – s
15
4
VO – Output Voltage – V
0
10
8
2
Gamma Channels
0
0
5
10
15
20
t – Time – s
Figure 25
12
25
30
VDD = 15 V
VI = 9 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
VI
12
9
6
3
VO – Output Voltage – V
6
VI – Input Voltage – V
8
2
4
16 18
LARGE SIGNAL VOLTAGE FOLLOWER
10
VDD = 10 V
VI = 6 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
VCOM
Buffer
14
Figure 24
LARGE SIGNAL VOLTAGE FOLLOWER
6
1
0
t – Time – s
VI
2
0
15
12
9
VCOM
Buffer
6
Gamma Channels
3
0
0
4
8
12 16 20
t – Time – s
Figure 26
24
28
32
36
VI – Input Voltage – V
IDD
3
5
0
2
4
VDD = 5 V
VI = 3 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
VI
VO – Output Voltage – V
IDD – Supply Current – mA
VO – All Channels
5
V I – Input Voltage – V
20
VO – Output Voltage – V
VDD – Supply Voltage – V
LARGE SIGNAL VOLTAGE FOLLOWER
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
TRANSIENT CURVES (continued)
2.55
VDD = 5 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = 25°C
2.50
2.45
VO – Output Voltage – V
2.40
2.60
VI
5.05
VDD = 10 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = 25°C
5
4.95
Gamma Channels
Gamma Channels
5.05
2.55
VCOM Buffer
VCOM Buffer
4.95
2.45
2.40
0 0.5
1
1.5 2 2.5 3 3.5
t – Time – s
4 4.5
0
5
0.50
Figure 27
1
1.50 2 2.50 3
t – Time – s
3.50
4
4.90
4.50
Figure 28
TRANSIENT LOAD RESPONSE – SOURCING
7.55
VDD = 15 V
VI = 100 mV
RL = 2 kΩ
CL = 100 pF
TA = 25°C
7.50
7.45
VI – Input Voltage – V
7.60
VI
VLT – Input Voltage – V
SMALL SIGNAL VOLTAGE FOLLOWER
VO – Output Voltage – V
5
2.50
7
6
5
4
3
2
1
0
Transient Load
Pulse
Channel 1
VDD = 10 V, VI = 5 V,
CS = 100 pF, RS = 100 Ω,
CL = 100 pF, RL = 1 kΩ,
tT = 0.1 µs, TA = 25°C
5.15
5.1
5.05
7.40
7.60
5
7.55
4.95
7.50
VCOM Buffer
Output Voltage
7.45
7.40
Gamma Channels
0
0.5
1
1.5
2
2.5
t – Time – s
Figure 29
4.9
4.85
3
3.5
4
4.5
0
0.1
0.2
0.3 0.4 0.5 0.6
t – Time – s
0.7
0.8
0.9
VO – Output Voltage – V
VI
5.10
VO – Output Voltage – V
2.60
VI – Input Voltage – V
SMALL SIGNAL PULSE RESPONSE
V I – Input Voltage – V
SMALL SIGNAL VOLTAGE FOLLOWER
4.8
1
Figure 30
13
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
TYPICAL CHARACTERISTICS
TRANSIENT CURVES (continued)
5.1
5.05
5
4.95
4.9
4.85
0.1 0.2 0.3 0.4 0.5
0.6
0.7 0.8 0.9
1
Channel 1
VDD = 10 V, VI = 5 V,
RL = 1 kΩ, tT = 0.1 µs,
TA = 25°C
5.8
CL = 100 pF
5.4
5.2
5
CL = 10 nF
RNULL = 100 Ω
4.6
0
1
2
3
4
5
t – Time – s
Figure 31
IL– Load Current – mA
IL– Load Current – mA
Sinking
6
VCOM Buffer
VDD = 10 V, VI = 5 V,
RL = 500 Ω, tT = 0.1 µs,
TA = 25°C
0
–6
5.2
5
4.8
CL = 10 nF
RNULL = 100 Ω
4.6
CL = 500 pF and
1000 pF
Sourcing
6
VO – Output Voltage – V
5.4
CL = 1000 pF
CL = 10 nF
5.5
5
CL = 100 nF
RNULL = 20 Ω
4.5
4
t – Time – s
3.5
6 7 8 9 10 11 12 13 14 15
t – Time – s
Figure 33
Figure 34
4.4
14
8
12
–12
CL = 100 pF
2
7
TRANSIENT LOAD REGULATION – VCOM BUFFER
Channel 1
VDD = 10 V, VI = 5 V,
RL = 1 kΩ, tT = 0.1 µs,
TA = 25°C
1
6
Figure 32
TRANSIENT LOAD REGULATION – SOURCING
0
4.8
4.8
t – Time – s
6
5
4
3
2
1
0
5.6
CL = 1000 pF
3
4
5
6
7
8
0
1
2
3
4
5
VO – Output Voltage – V
0
6
5
4
3
2
1
0
VO – Output Voltage – V
Channel 1
VDD = 10 V, VI = 5 V,
CS = 100 pF, RS = 100 Ω,
CL = 100 pF, RL = 1 kΩ,
tT = 0.1 µs, TA = 25°C
IL– Load Current – mA
TRANSIENT LOAD REGULATION – SINKING
VO – Output Voltage – V
VLT – Input Voltage – V
TRANSIENT LOAD RESPONSE – SINKING
7
6
5
4
3
2
1
0
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
APPLICATION INFORMATION
The requirements on the number of gamma correction
channels vary greatly from panel to panel. Therefore, the
BUFxx703 series of gamma correction buffers offers
different channel combinations. The VCOM channel can be
used to drive the VCOM node on the LCD panel.
Gamma correction voltages are often generated using
a simple resistor ladder, as shown in Figure 35. The
BUFxx703 buffers the various nodes on the gamma
correction resistor ladder. The low output impedance of
the BUFxx703 forces the external gamma correction
voltage on the respective reference node of the LCD
source driver. Figure 35 shows an example of the
BUFxx703 in a typical block diagram driving an LCD
source driver with 6-channel gamma correction
reference inputs.
Figure 35. LCD Source Driver Typical Block Diagram.
15
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
INPUT VOLTAGE RANGE GAMMA BUFFERS
COMMON BUFFER (VCOM)
Figure 36 shows a typical gamma correction curve with 10
gamma correction reference points (GMA1 through
GMA10). As can be seen from this curve, the voltage
requirements for each buffer varies greatly. The swing
capability of the input stages of the various buffers in the
BUFxx703 is carefully matched to the application. Using
the example of the BUF07703 with six gamma correction
channels, buffers 1 to 3 have input stages that include
VDD, but will only swing within 1V to GND. Buffers 1
through 5 have only a single NMOS input stage. Buffers
4 through 6 have only a single PMOS input stage. The
input range of the PMOS input stage includes GND.
The common buffer output of the BUF07703 and
BUF05703 has a greater output drive capability than the
gamma correction buffers, to meet the heavier current
demands of driving the common node of the LCD panel.
It was also designed to drive heavier capacitive loads
and still remain stable, as shown in Figure 37.
35
30
25
20
15
10
5
0
GMA2
GMA3
GMA4
GMA5
VDD = 10 V
RL = 2 kΩ
VCOM
40
Phase Shift – Deg
VDD1
GMA1
45
10
100
CL – Load Capacitance – pF
1000
Figure 37. Phase Shift vs Load Capacitance.
GMA6
CAPACITIVE LOAD DRIVE
GMA10
VSS1
0
10
20
Input Data HEX0
30
40
Figure 36. Gamma Correction Curve.
OUTPUT VOLTAGE SWING GAMMA BUFFERS
The output stages have been designed to match the
characteristic of the input stage. Once again using the
example of the BUF07703 means that the output stage of
buffer 1 swings very close to VDD, typically VCC – 100mV
at 5mA; its ability to swing to GND is limited. Buffers 2 and
3 have smaller output stages with slightly larger output
resistances, as they will not have to swing as close to the
positive rail as buffer 1. Buffers 4 through 6 swing closer
to GND than VDD. Buffer 6 is designed to swing very close
to GND, typically GND + 100mV at a 5mA load current.
See the typical characteristics for more details. This
approach significantly reduces the silicon area and cost of
the whole solution. However, due to this architecture, the
correct buffer needs to be connected to the correct
gamma correction voltage. Connect buffer 1 to the
gamma voltage closest to VDD, and buffers 2 and 3 to the
sequential voltages. Buffer 6 should be connected to the
gamma correction voltage closest to GND (or the
negative rail), buffers 4 and 5 to the sequential higher
voltages.
16
The BUFxx703 has been designed to be able to
sink/source DC currents in excess of 10mA. Its output
stage has been designed to deliver output current
transients with little disturbance of the output voltage.
However, there are times when very fast current pulses
are required. Therefore, in LCD source-driver buffer
applications, it is quite normal for capacitors to be
placed at the outputs of the reference buffers. These
are to improve the transient load regulation. These will
typically vary from 100pF and more. The BUFxx703
gamma buffers were designed to drive capacitances in
excess of 100pF and retain effective phase margins
above 50°, as shown in Figure 38.
140
BUF07703: Channels 1 to 6
Phase Shift – Deg
GMA7
GMA8
GMA9
120
BUF06703: Channels 1 to 6
100
BUF05703: Channels 1 to 4
80
VDD = 10 V
RL = 2 kΩ
60
40
20
0
10
100
CL – Load Capacitance – pF
1000
Figure 38. Phase Shift Between Output and Input
vs Load Capacitance for the gamma buffers
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
APPLICATIONS WITH >10 GAMMA CHANNELS
MULTIPLE VCOM CHANNELS
When a greater number of gamma correction channels
are required, two or more BUFxx703 devices can be
used in parallel, as shown in Figure 39. This provides
a cost-effective way of creating more reference
voltages over the use of quad-channel op amps or
buffers. The suggested configuration in Figure 39
simplifies layout. The various different channel versions
provide a high degree of flexibility and also minimize
total cost and space.
In some LCD panels, more than one VCOM driver is
required for best panel performance. Figure 40 uses
three BUF07703s to create a total of 18
gamma-correction and three VCOM channels. This
solution saves considerable space and cost over the
more conventional approach of using five or six
quad-channel buffers or op amps.
Figure 39. Creating > 10 Gamma Voltage
Channels
Table 1. > 10 Channel Gamma Combinations
BUF11702
BUF07703
BUF06703
BUF05703
12ch
—
—
2
—
12ch + VCOM
—
1
1
—
14ch + VCOM
1
—
—
1
16ch + VCOM
1
—
1
—
18ch + VCOM
2
—
—
—
20ch + VCOM
2
—
—
—
Figure 40. 18-Channel Application with Five
Integrated VCOM Channels
17
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
COMPLETE LCD SOLUTION FROM TI
Besides the BUFxx703 line of gamma correction
buffers, TI offers a complete set of ICs for the LCD panel
market: source and gate drivers, various power-supply
solutions, as well audio power solutions. Figure 41
shows the Total IC solution from TI.
Audio Power Amplifier for TV Speakers
The TPA3002D2 is a 7W (per channel) stereo audio
amplifier specifically targeted towards LCD monitors
and TVs. It offers highly efficient, filter-free Class-D
operation for driving bridged tied stereo speakers. The
TPA3002D2 is designed to drive stereo speakers as low
as 8Ω without an output filter. The high efficiency of the
TPA3002D2 eliminates the need for external heatsinks
when playing music. Stereo speaker volume is
controlled with a DC voltage applied to the volume
control terminal offering a range of gain from –40dB to
+36dB. Line outputs, for driving external headphone
amplifier inputs, are also DC voltage controlled with a
range of gain from –56dB to +20dB. An integrated +5V
regulated supply is provided for powering an external
headphone amplifier. Texas Instruments offers a full line
of linear and switch-mode audio power amplifiers. For
excellent audio performance TI recommends the
OPA364 or OPA353 as headphone drivers. For more
information visit www.ti.com.
Integrated DC/DC Converter for LCD Panels:
TPS65100
The TPS65100 offers a very compact and small power
supply solution to provide all three power-supply
voltages required by TFT (thin film transistor) LCD
displays. Additionally the device has an integrated
VCOM buffer. The auxiliary linear regulator controller
can be used to generate the 3.3V logic power rail for
systems powered by a 5V supply rail only. The main
output can power the LCD source drivers as well as the
BUFxx703. An integrated adjustable charge pump
doubler/tripler provides the positive LCD gate drive
voltage. An externally adjustable negative charge pump
provides the negative gate drive voltage. The
TPS65100 has an integrated VCOM buffer to power the
LCD backplane. A version of the BUFxx703 without the
integrated VCOM buffer could be used for minimum
redundancy and lowest cost. For LCD panels powered
by 5V only, the TPS65100 has a linear regulator
controller that uses an external transistor to provide a
regulated 3.3V output for the digital circuits. Contact the
local sales office for more information.
Figure 41. TI LCD Solution
18
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
GENERAL POWERPAD DESIGN
CONSIDERATIONS
The BUF07703 is available in the thermally enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the
die is mounted; see Figure 42(a) and (b). This
arrangement results in the lead frame being exposed as
a thermal pad on the underside of the package; see
Figure 42(c). Due to this thermal pad having direct
thermal contact with the die, excellent thermal
performance is achieved by providing a good thermal
path away from the thermal pad.
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat-dissipating device.
1. Prepare the PCB with a top-side etch pattern, (see
Pin Configurations). There must be etching for the
leads as well as etch for the thermal pad.
2. Place 18 holes in the area of the thermal pad. These
holes must be 13 mils in diameter. Keep them small,
so that solder wicking through the holes is not a
problem during reflow.
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the
BUF07703 IC. These additional vias may be larger
than the 13-mil diameter vias directly under the
thermal pad. They can be larger because they are
not in the thermal pad area to be soldered, so that
wicking is not a problem.
resistance connection that is useful for slowing the
heat transfer during soldering operations. This
makes the soldering of vias that have plane
connections easier. In this application, however, low
thermal resistance is desired for the most efficient
heat transfer. Therefore, the holes under the
BUF07703 PowerPAD package must make their
connection to the internal ground plane with a
complete
connection
around
the
entire
circumference of the plated-through hole.
6. The top-side solder mask must leave the terminals
of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The
bottom-side solder mask must cover the five or nine
holes of the thermal pad area. This prevents solder
from being pulled away from the thermal pad area
during the reflow process.
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8. With these preparatory steps in place, the
BUF07703 IC is simply placed in position and run
through the solder reflow operation as any standard
surface-mount component. This results in a part that
is properly installed.
For a given θJA, the maximum power dissipation is
calculated by the following formula:
PD +
ǒT
* TA
q JA
MAX
Ǔ
4. Connect all holes to the internal ground plane.
Where:
PD = maximum power dissipation (W)
TMAX = absolute maximum junction temperature (150°C)
TA = free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = thermal coefficient from junction to case (°C/W)
θCA = thermal coefficient from case-to-ambient air (°C/W)
5. When connecting these holes to the ground plane,
do not use the typical web or spoke via connection
methodology. Web connections have a high thermal
This lower thermal resistance enables the BUF07703 to
deliver maximum output currents even at high ambient
temperatures.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
NOTE A:
Bottom View (c)
The thermal pad is electrically isolated from all terminals in the package.
Figure 42. Views of Thermally Enhanced DGN Package
19
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE
20 PINS SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/F 10/98
NOTES:A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments.
20
www.ti.com
SBOS269A – MARCH 2003 – REVISED JUNE 2003
MECHANICAL DATA (CONTINUED)
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
21
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
BUF05703PW
ACTIVE
TSSOP
PW
14
90
None
CU NIPDAU
Level-1-220C-UNLIM
BUF05703PWR
ACTIVE
TSSOP
PW
14
2000
None
CU NIPDAU
Level-1-220C-UNLIM
BUF05703PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BUF06703PW
ACTIVE
TSSOP
PW
16
90
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR
BUF06703PWR
ACTIVE
TSSOP
PW
16
2000
Pb-Free
(RoHS)
CU NIPDAU
Level-2-250C-1 YEAR
BUF06703PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
BUF07703PWP
ACTIVE
HTSSOP
PWP
20
70
None
CU NIPDAU
Level-1-220C-UNLIM
BUF07703PWPR
ACTIVE
HTSSOP
PWP
20
2000
None
CU NIPDAU
Level-1-220C-UNLIM
BUF07703PWPRG4
ACTIVE
HTSSOP
PWP
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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