DRV632 www.ti.com SLOS681A – JANUARY 2011 – REVISED JULY 2013 DirectPath™, 2-VRMS Audio Line Driver With Adjustable Gain Check for Samples: DRV632 FEATURES DESCRIPTION • The DRV632 is a 2-VRMS pop-free stereo line driver designed to allow the removal of the output dcblocking capacitors for reduced component count and cost. The device is ideal for single-supply electronics where size and cost are critical design parameters. 1 23 • • • • • • • • • • • • Stereo DirectPath™ Audio Line Driver – 2 Vrms Into 10 kΩ With 3.3-V Supply Low THD+N < 0.01% at 2 Vrms Into 10 kΩ High SNR, >90 dB 600-Ω Output Load Compliant Differential Input and Single-Ended Output Adjustable Gain by External Gain-Setting Resistors Low DC Offset, <1 mV Ground-Referenced Outputs Eliminate DCBlocking Capacitors – Reduce Board Area – Reduce Component Cost – Improve THD+N Performance – No Degradation of Low-Frequency Response Due to Output Capacitors Short-Circuit Protection Click- and Pop-Reduction Circuitry External Undervoltage Mute Active Mute Control for Pop-Free Audio On/Off Control Space-Saving TSSOP Package APPLICATIONS • • • • • • Designed using TI’s patented DirectPath™ technology, The DRV632 is capable of driving 2 VRMS into a 10-kΩ load with 3.3-V supply voltage. The device has differential inputs and uses external gainsetting resistors to support a gain range of ±1 V/V to ±10 V/V, and gain can be configured individually for each channel. Line outputs have ±8-kV IEC ESD protection, requiring just a simple resistor-capacitor ESD protection circuit. The DRV632 has built-in active-mute control for pop-free audio on/off control. The DRV632 has an external undervoltage detector that mutes the output when the power supply is removed, ensuring a pop-free shutdown. Using the DRV632 in audio products can reduce component count considerably compared to traditional methods of generating a 2-VRMS output. The DRV632 does not require a power supply greater than 3.3 V to generate its 5.6-Vpp output, nor does it require a split-rail power supply. The DRV632 integrates its own charge pump to generate a negative supply rail that provides a clean, pop-free ground-biased 2-VRMS output. The DRV632 is available in a 14-pin TSSOP. Set-Top Boxes Blu-ray Disc™, DVD Players LCD and PDP TV Mini/Micro Combo Systems Sound Cards Laptops 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DirectPath, FilterPro are trademarks of Texas Instruments. Blu-ray Disc is a trademark of Blu-ray Disc Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated DRV632 SLOS681A – JANUARY 2011 – REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) TA PACKAGE DESCRIPTION –40°C to 85°C DRV632PW 14-Pin For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range Supply voltage, VDD to GND VI Input voltage RL Minimum load impedance – line outputs – OUTL, OUTR Mute to GND, UVP to GND VALUE UNIT –0.3 to 4 V VSS – 0.3 to VDD + 0.3 V 600 Ω –0.3 to VDD + 0.3 V TJ Maximum operating junction temperature range –40 to 150 °C Tstg Storage temperature range –40 to 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION DRV632 THERMAL METRIC (1) PW UNIT 14 PINS Junction-to-ambient thermal resistance (2) θJA (3) 130 °C/W θJCtop Junction-to-case (top) thermal resistance 49 °C/W θJB Junction-to-board thermal resistance (4) 63 °C/W ψJT Junction-to-top characterization parameter (5) 3.6 °C/W ψJB Junction-to-board characterization parameter (6) 62 °C/W θJCbot Junction-to-case (bottom) thermal resistance (7) n/a °C/W (1) (2) (3) (4) (5) (6) (7) 2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 DRV632 www.ti.com SLOS681A – JANUARY 2011 – REVISED JULY 2013 RECOMMENDED OPERATING CONDITIONS VDD Supply voltage DC supply voltage RL Load impedance VIL Low-level input voltage Mute VIH High-level input voltage Mute TA Operating free-air temperature MIN NOM MAX 3 3.3 3.6 UNIT 0.6 10 kΩ 40 % of VDD V 60 –40 % of VDD 25 85 °C ELECTRICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS |VOS| Output offset voltage PSRR Power-supply rejection ratio VOH High-level output voltage VDD = 3.3 V VOL Low-level output voltage VDD = 3.3 V VUVP_ External UVP detect voltage MIN VDD = 3.3 V TYP MAX 0.5 1 80 UNIT mV dB 3.1 V –3.05 V 1.25 V 5 µA EX VUVP_ External UVP detect hysteresis current EX_HYS TERESI S fCP Charge pump switching frequency 400 kHz |IIH| High-level input current, Mute VDD = 3.3 V, VIH = VDD 200 1 µA |IIL| Low-level input current, Mute VDD = 3.3 V, VIL = 0 V 1 µA IDD Supply current VDD = 3.3 V, no load, Mute = VDD 5 VDD = 3.3 V, no load, Mute = GND, disabled 300 14 25 14 mA OPERATING CHARACTERISTICS VDD = 3.3 V, RDL = 10 kΩ, RFB = 30 kΩ, RIN = 15 kΩ, TA = 25°C, Charge pump: CP = 1 µF (unless otherwise noted) PARAMETER TEST CONDITIONS MIN THD+N = 1%, VDD = 3.3 V, f = 1 kHz, RL = 10 kΩ THD+N Total harmonic distortion plus noise VO = 2 VRMS, f = 1 kHz SNR Signal-to-noise ratio (1) A-weighted 105 DNR Dynamic range A-weighted 105 dB VN Noise voltage A-weighted 11 μV ZO Output Impedance when muted Mute = GND 110 mΩ Input-to-output attenuation when muted Mute = GND 80 dB Crosstalk—L to R, R to L VO = 1 Vrms –110 dB 25 mA (1) Current limit 2.4 UNIT Output voltage, outputs in phase ILIMIT 2 TYP MAX VO Vrms 0.002% dB SNR is calculated relative to 2-Vrms output. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 3 DRV632 SLOS681A – JANUARY 2011 – REVISED JULY 2013 www.ti.com PW PACKAGE (TOP VIEW) +INR 1 14 +INL –INR 2 13 –INL OUTR 3 12 OUTL 11 UVP External UnderVoltage Detector GND 4 Mute 5 10 GND VSS 6 9 VDD CN 7 8 CP Charge Pump PIN FUNCTIONS PIN NAME NO. I/O (1) DESCRIPTION CN 7 I/O Charge-pump flying capacitor negative connection CP 8 I/O Charge-pump flying capacitor positive connection GND 4, 10 P Ground –INL 13 I Left-channel OPAMP negative input +INL 14 I Left-channel OPAMP positive input –INR 2 I Right-channel OPAMP negative input +INR 1 I Right-channel OPAMP positive input Mute 5 I Mute, active-low OUTL 12 O Left-channel OPAMP output OUTR 3 O Right-channel OPAMP output UVP 11 I Undervoltage protection, internal pullup; unconnected if UVP function is unused. VDD 9 P Positive supply VSS 6 P Supply voltage (1) 4 I = input, O = output, P = power Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 DRV632 www.ti.com SLOS681A – JANUARY 2011 – REVISED JULY 2013 FUNCTIONAL BLOCK DIAGRAM +INL +INR Line Driver –INL Line Driver –INR OUTL OUTR GND UVP Click and Pop Suppression Short-Circuit Protection GND Mute VSS Bias Circuitry CN VDD CP Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 5 DRV632 SLOS681A – JANUARY 2011 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS VDD = 3.3 V , TA = 25°C, C(PUMP) = C(VSS) = 1 µF , CIN = 2.2 µF, RIN = 15 kΩ, Rfb = 30 kΩ, ROUT = 32 Ω, COUT = 1 nF (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE 10 10 Active Filter Gain = 2V/V RL = 600Ω 1 1 0.1 0.1 THD+N (%) THD+N (%) Active Filter Gain = 2V/V RL = 10 kΩ 0.01 0.001 0.01 0.001 100 Hz 1 kHz 10 kHz 100 Hz 1 kHz 10 kHz 0.0001 0.1 1 0.0001 0.1 3 1 Output Voltage (V) Figure 1. Figure 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 Active Filter Gain = 2V/V RL = 600 Ω Ch1 1 Vrms Ch1 2 Vrms 1 1 0.1 0.1 THD+N (%) THD+N (%) Active Filter Gain = 2V/V RL = 10 kΩ 0.01 0.001 0.0001 Ch1 1 Vrms Ch1 2 Vrms 0.01 0.001 20 100 1k Frequency (Hz) 10k 20k 0.0001 20 Figure 3. 6 3 Output Voltage (V) 100 1k Frequency (Hz) 10k 20k Figure 4. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 DRV632 www.ti.com SLOS681A – JANUARY 2011 – REVISED JULY 2013 TYPICAL CHARACTERISTICS (continued) VDD = 3.3 V , TA = 25°C, C(PUMP) = C(VSS) = 1 µF , CIN = 2.2 µF, RIN = 15 kΩ, Rfb = 30 kΩ, ROUT = 32 Ω, COUT = 1 nF (unless otherwise noted) CROSSTALK vs FREQUENCY 0 RL = 10 kΩ VO = 1 Vrms VREF = 1 V −20 Left to Right Right to Left Crosstalk (dBrA) −40 −60 −80 −100 −120 −140 20 100 1k Frequency (Hz) 10k 20k Figure 5. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 7 DRV632 SLOS681A – JANUARY 2011 – REVISED JULY 2013 www.ti.com APPLICATION INFORMATION LINE DRIVER AMPLIFIERS Single-supply line-driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 6 illustrates the conventional line-driver amplifier connection to the load and output signal. DC blocking capacitors are often large in value. The line load (typical resistive values of 600 Ω to 10 kΩ) combines with the dc blocking capacitors to form a high-pass filter. Equation 1 shows the relationship between the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC). 1 fc = 2p R L CO (1) CO can be determined using Equation 2, where the load impedance and the cutoff frequency are known. 1 CO = 2p R L f c (2) If fC is low, the capacitor must then have a large value because the load resistance is small. Large capacitance values require large package sizes. Large package sizes consume PCB area, stand high above the PCB, increase cost of assembly, and can reduce the fidelity of the audio output signal. 9 V–12 V Conventional Solution VDD + + OPAMP Mute Circuit Co + Output VDD/2 – GND Enable 3.3 V DirectPath DRV632 Solution VDD Mute Circuit + DRV632 Output GND – VSS Enable Figure 6. Conventional and DirectPath Line Drivers The DirectPath amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the IC, the device operates in what is effectively a split-supply mode. The output voltages are now centered at zero volts with the capability to swing to the positive rail or negative rail. Combining this with the built-in click and pop reduction circuit, the DirectPath amplifier requires no output dc blocking capacitors. The bottom block diagram and waveform of Figure 6 illustrate the ground-referenced line-driver architecture. This is the architecture of the DRV632. 8 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 DRV632 www.ti.com SLOS681A – JANUARY 2011 – REVISED JULY 2013 CHARGE-PUMP FLYING CAPACITOR AND PVSS CAPACITOR The charge-pump flying capacitor serves to transfer charge during the generation of the negative supply voltage. The PVSS capacitor must be at least equal to the charge-pump capacitor in order to allow maximum charge transfer. Low-ESR capacitors are an ideal selection, and a value of 1 μF is typical. Capacitor values that are smaller than 1 μF can be used, but the maximum output voltage may be reduced and the device may not operate to specifications. If the DRV632 is used in highly noise-sensitive circuits, it is recommended to add a small LC filter on the VDD connection. DECOUPLING CAPACITORS The DRV632 is a DirectPath line-driver amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good, low equivalent-series-resistance (ESR) ceramic capacitor, typically 1 μF, placed as close as possible to the device VDD lead works best. Placing this decoupling capacitor close to the DRV632 is important for the performance of the amplifier. For filtering lower-frequency noise signals, a 10-μF or greater capacitor placed near the audio power amplifier would also help, but it is not required in most applications because of the high PSRR of this device. GAIN-SETTING RESISTOR RANGES The gain-setting resistors, RIN and Rfb, must be chosen so that noise, stability, and input capacitor size of the DRV632 are kept within acceptable limits. Voltage gain is defined as Rfb divided by RIN. Selecting values that are too low demands a large input ac-coupling capacitor, CIN. Selecting values that are too high increases the noise of the amplifier. Table 1 lists the recommended resistor values for different invertinginput gain settings. Table 1. Recommended Resistor Values GAIN INPUT RESISTOR VALUE, RIN FEEDBACK RESISTOR VALUE, Rfb –1 V/V 10 kΩ 10 kΩ –1.5 V/V 8.2 kΩ 12 kΩ –2 V/V 15 kΩ 30 kΩ –10 V/V 4.7 kΩ 47 kΩ USING THE DRV632 AS A SECOND-ORDER FILTER Several audio DACs used today require an external low-pass filter to remove out-of-band noise. This is possible with the DRV632, as it can be used like a standard operational amplifier. Several filter topologies can be implemented, both single-ended and differential. In Figure 7, multi-feedback (MFB) with differential input and single-ended input are shown. An ac-coupling capacitor to remove dc content from the source is shown; it serves to block any dc content from the source and lowers the dc gain to 1, helping to reduce the output dc offset to a minimum. The component values can be calculated with the help of the TI FilterPro™ program available on the TI Web site at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 9 DRV632 SLOS681A – JANUARY 2011 – REVISED JULY 2013 www.ti.com Inverting Input Differential Input R2 C3 R1 R2 C3 C1 R3 –IN R1 R3 C1 –IN – DRV632 + C2 C2 – DRV632 + +IN C3 R1 R3 C1 R2 Figure 7. Second-Order Active Low-Pass Filter The resistor values should have a low value for obtaining low noise, but should also have a high enough value to get a small-size ac-coupling capacitor. With the proposed values of R1 = 15 kΩ, R2 = 30 kΩ, and R3 = 43 kΩ, a dynamic range (DYR) of 106 dB can be achieved with a 1-μF input ac-coupling capacitor. INPUT-BLOCKING CAPACITORS DC input-blocking capacitors are required to be added in series with the audio signal into the input pins of the DRV632. These capacitors block the dc portion of the audio source and allow the DRV632 inputs to be properly biased to provide maximum performance. These capacitors form a high-pass filter with the input resistor, RIN. The cutoff frequency is calculated using Equation 3. For this calculation, the capacitance used is the input-blocking capacitor, and the resistance is the input resistor chosen from Table 1; then the frequency and/or capacitance can be determined when one of the two values is given. It is recommended to use electrolytic capacitors or high-voltage-rated capacitors as input blocking capacitors to ensure minimal variation in capacitance with input voltages. Such variation in capacitance with input voltages is commonly seen in ceramic capacitors and can increase low-frequency audio distortion. fcIN = 1 2p R INCIN or CIN = 1 2p fcIN R IN (3) DRV632 UVP OPERATION The shutdown threshold at the UVP pin is 1.25 V. The customer must use a resistor divider to obtain the shutdown threshold and hysteresis desired for a particular application. The customer-selected thresholds can be determined as follows: EXTERNAL UNDERVOLTAGE DETECTION External undervoltage detection can be used to mute/shut down the DRV632 before an input device can generate a pop. The shutdown threshold at the UVP pin is 1.25 V. The user selects a resistor divider to obtain the shutdown threshold and hysteresis for the specific application. The thresholds can be determined as follows: VUVP = (1.25 – 6 μA × R3) × (R1 + R2) / R2 Hysteresis = 5 μA × R3 × (R1 + R2) / R2 For example, to obtain VUVP = 3.8 V and 1-V hysteresis, we can use R1 = 3 kΩ, R2 = 1 kΩ, and R3 = 50 kΩ. 10 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 DRV632 www.ti.com SLOS681A – JANUARY 2011 – REVISED JULY 2013 VSUP_MO R1 R3 UVP R2 LAYOUT RECOMMENDATIONS A proposed layout for the DRV632 can be seen in the DRV632EVM User's Guide, and the Gerber files can be downloaded from http://www.ti.com. To access this information, open the DRV632 product folder and look in the Tools and Software folder. GAIN-SETTING RESISTORS The gain-setting resistors, RIN and Rfb, must be placed close to pins 13 and 17, respectively, to minimize capacitive loading on these input pins and to ensure maximum stability of the DRV632. For the recommended PCB layout, see the DRV632EVM User's Guide. Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 11 DRV632 SLOS681A – JANUARY 2011 – REVISED JULY 2013 www.ti.com APPLICATION CIRCUIT R1 C3 C3 R1 R1 R3 R2 R2 C2 C3 R1 C2 R3 R3 + C3 LEFT – INPUT + RIGHT – INPUT R3 + C1 C1 R2 R2 DRV632 +INR –INR +INL Line Driver Line Driver –INL C1 C1 RIGHT OUTPUT OUTR UVP GND Click and Pop Suppression Short-Circuit Protection R11 GND EN VSS LEFT OUTPUT OUTL 3.3-V Supply Bias Circuitry R12 VDD 1mF 1mF CN CP 1mF Linear Low-Dropout Regulator System Supply 10 mF R1 = 15 kΩ, R2 = 30 kΩ, R3 = 43 kΩ, C1 = 47 pF, C2 = 180 pF Differential-input, single-ended output, second-order filter 12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 DRV632 www.ti.com SLOS681A – JANUARY 2011 – REVISED JULY 2013 REVISION HISTORY Changes from Original (January 2011) to Revision A Page • Deleted min value for SNR and DNR in OPERATING CHARACTERISTICS table ............................................................. 3 • Changed description of UVP in PIN FUNCTIONS table ....................................................................................................... 4 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: DRV632 13 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DRV632PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632 DRV632PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 DRV632 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device DRV632PWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DRV632PWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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