ISL54220 Features The Intersil ISL54220 is a single supply dual 2:1 multiplexer that can operate from a single 2.7V to 5.5V supply. It contains two SPDT (Single Pole/Double Throw) switches configured as a DPDT. The part was designed for switching or routing of USB High-Speed signals and/or USB Full-speed signals in portable battery powered products. • High-Speed (480Mbps) and Full-Speed (12Mbps) Signaling Capability per USB 2.0 The 6Ω switches can swing rail-to-rail and were specifically designed to pass USB full speed data signals that range from 0V to 3.3V and USB high speed data signals that range from 0V to 400mV. They have high bandwidth and low capacitance to pass USB high-speed data signals with minimal distortion. • -3dB Frequency . . . . . . . . . . . . . . . . . . 742MHz The digital logic inputs are 1.8V logic compatible when operated with a 2.7V to 3.6V supply. The ISL54220 has an output enable pin to open all the switches. • Available in µTQFN, TDFN, and MSOP Packages The ISL54220 is available in 10 Ld 1.8mmx1.4mm µTQFN, 10 Ld TDFN and 10 Ld MSOP packages. It operates over a temperature range of -40 to +85°C. Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • 1.8V Logic Compatible (2.7V to +3.6V supply) • Enable Pin to Open all Switches • Power OFF Protection • D-/D+ Pins Overvoltage Tolerant to 5.5V • Low ON Capacitance @ 240MHz . . . . . . . . . 4.2pF • Low ON-Resistance @ VDD = 5.5V . . . . . . . 4.5Ω • Low ON-Resistance @ VDD = 3.3V . . . . . . . 6.0Ω • Single Supply Operation (VDD) . . . . . 2.7V to 5.5V • Pb-Free (RoHS Compliant) • Compliant with USB 2.0 Short Circuit and Overvoltage Requirements Without Additional External Components Applications*(see page 15) • MP3 and other Personal Media Players • Cellular/Mobile Phones • PDA’s • Application Note AN1449 “ISL54220IRUEVAL1Z Evaluation Board User’s Manual” • Digital Cameras and Camcorders Application Block Diagram USB 2.0 HS Eye Pattern With Switches In The Signal Path • USB Switching ISL54220 USB CONNECTOR SEL LOGIC VBUS OE USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER HSD1- D- D- D+ D+ HSD1+ HSD2- USB HIGH_SPEED OR FULL-SPEED TRANSCEIVER HSD2+ GND GND PORTABLE MEDIA DEVICE February 4, 2010 FN6819.1 1 VOLTAGE SCALE (0.1V/DIV) µCONTROLLER VDD TIME SCALE (0.2ns/DIV) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL54220 High-Speed USB 2.0 (480Mbps) Multiplexer ISL54220 Pin Configurations ISL54220 (10 LD MSOP) TOP VIEW ISL54220 (10 LD 3.0X3.0 TDFN) TOP VIEW PD LOGIC CONTROL SEL 1 HSD1+ 2 9 HSD2+ 3 8 D+ GND LOGIC CONTROL SEL 1 OE HSD1+ 2 9 OE HSD1- HSD2+ 3 8 HSD1- 4 7 HSD2- D+ 4 7 HSD2- 5 6 GND 5 6 10 VDD D- 10 VDD D- ISL54220 (10 LD 1.8X1.4 µTQFN) TOP VIEW HSD1- HSD2- 7 6 VDD 9 SEL 10 LOGIC CONTROL OE 8 1 5 D- 4 GND 3 D+ 2 HSD1+ HSD2+ NOTE: 1. Switches Shown for SEL = Logic “1” and OE = Logic “0”. Truth Table OE SEL Pin Descriptions HSD1-, HSD1+ HSD2-, HSD2+ TDFN MSOP µTQFN NAME FUNCTION 10 10 9 VDD Power Supply (2.7V to 5.5V) 1 1 10 SEL Select Logic Control Input 2 2 1 HSD1+ USB Data Port (Channel 1 Positive Input) 3 3 2 HSD2+ USB Data Port (Channel 2 Positive Input) 4 4 3 D+ USB Data Common Positive Port 5 5 4 GND Ground Connection 6 6 5 D- USB Data Common Negative Port 7 7 6 HSD2- USB Data Port (Channel 2 Negative Input) 8 8 7 HSD1- USB Data Port (Channel 1 Negative Input) 9 9 8 OE Bus Switch Enable PD - - PD Thermal Pad. Tie to Ground or Float 0 0 ON OFF 0 1 OFF ON 1 X OFF OFF Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V Supply. 2 FN6819.1 February 4, 2010 ISL54220 Ordering Information PART NUMBER (Note 5) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL54220IRUZ-T (Notes 2, 4) H -40 to +85 10 Ld 1.8mmx1.4mm µTQFN (Tape and Reel) L10.1.8x1.4A ISL54220IRTZ (Note 3) 4220 -40 to +85 10 Ld 3x3 TDFN L10.3x3A ISL54220IRTZ-T (Notes 2, 3) 4220 -40 to +85 10 Ld 3x3 TDFN (Tape and Reel) L10.3x3A ISL54220IUZ (Note 3) 54220 -40 to +85 10 Ld MSOP M10.118 ISL54220IUZ-T (Notes 2, 3) 54220 -40 to +85 10 Ld MSOP (Tape and Reel) M10.118 ISL54220IRUEVAL1Z Evaluation Board NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 5. For Moisture Sensitivity Level (MSL), please see device information page for ISL54220. For more information on MSL please see techbrief TB363. 3 FN6819.1 February 4, 2010 ISL54220 Absolute Maximum Ratings Thermal Information VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 6.5V Input Voltages HSD2x, HSD1x (Note 6) . . . . . . . . . . . . . . - 0.3V to 6.5V SEL, OE (Note 6) . . . . . . . . . . . . . -0.3 to ((VDD) + 0.3V) Output Voltages D+, D- (Note 6) . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Continuous Current (HSD2x, HSD1x) . . . . . . . . . . . ±40mA Peak Current (HSD2x, HSD1x) (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . ±100mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >500V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . >2kV Latch-up Tested per JEDEC; Class II Level A . . . . . at +85°C Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld µTQFN (Notes 8, 10) . . . . . . 160 105 10 Ld TDFN (Notes 8, 9) . . . . . . . . 55 18 10 Ld MSOP (Note 7, 10) . . . . . . . 165 65 Maximum Junction Temperature (Plastic Package). . +150°C Maximum Storage Temperature Range. . . . . -65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . VDD Supply Voltage Range . Logic Control Input Voltage Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C . . 2.7V to 5.5V . . . . 0V to VDD . . . . 0V to VDD CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. Signals on HSD1x, HSD2x, D+,D- exceeding GND by specified amount are clamped. Signals on OE and SEL exceeding VDD or GND by specified amount are clamped. Limit current to maximum current ratings. 7. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 9. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 10. For θJC, the “case temp” location is the center of the package top. Electrical Specifications - 2.7V to 5.5V Supply PARAMETER Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. TEST CONDITIONS TEMP MIN (°C) (Notes 12, 13) TYP MAX (Notes 12, 13) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG VDD = VDD, SEL = 0V or VDD , OE = 0V Full 0 - VDD V ON-Resistance, rON (High-Speed) VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, VHSD1x or VHSD2 x = 0V to 400mV (see Figure 3, Note 16) 25 - 6.7 8 Ω Full - - 10 Ω 25 - 0.117 0.45 Ω Full - - 0.55 Ω 25 - 0.94 1.2 Ω Full - - 1.3 Ω 25 -15 0.31 15 nA Full -20 - 20 nA 25 -20 2.2 20 nA Full -25 - 25 nA 25 -15 0.26 15 nA Full -20 - 20 nA rON Matching Between Channels, ΔrON (High-Speed) VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, V VHSD1x or VHSD2 x = Voltage at max rON, (Notes 15, 16) rON Flatness, RFLAT(ON) (High-Speed) VDD = 2.7V, SEL = 0.5V or 1.4V, OE = 0.5V, IDx = 40mA, VHSD1x or VHSD2 x = 0V to 400mV, (Notes 14, 16) OFF Leakage Current, IHSD1x(OFF) VDD = 5.5V, SEL = VDD and OE = 0V or OE = VDD, VDx = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V ON Leakage Current, IHSD1x(ON) VDD = 5.5V, SEL = OE = 0V, VDx = 0.3V, 3.3V, VHSD1X = 0.3V, 3.3V, VHSD2x = 3.3V, 0.3V OFF Leakage Current, IHSD2x(OFF) VDD = 5.5V, SEL = OE = 0V or OE = VDD, VDx = 3.3V, 0.3V, VHSD2x = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V 4 FN6819.1 February 4, 2010 ISL54220 Electrical Specifications - 2.7V to 5.5V Supply PARAMETER Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEST CONDITIONS ON Leakage Current, IHSD2x(ON) Power OFF Leakage Current, ID+, ID- VDD = 5.5V, SEL = VDD, OE = 0V, VDx= 0.3V, 3.3V, VHSD2x = 0.3V, 3.3V, VHSD1X = 3.3V, 0.3V VDD = 0V, VD+ = 0V to 5.25V, VD-= 0V to 5.25V, SEL = OE = VDD TEMP MIN (°C) (Notes 12, 13) TYP MAX (Notes 12, 13) UNITS 25 -20 2.1 20 nA Full -25 - 25 nA 25 - 0.0047 0.025 µA Full - - 0.40 µA DYNAMIC CHARACTERISTICS Turn-ON Time, tON VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 1) 25 - 35 - ns Turn-OFF Time, tOFF VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 1) 25 - 27 - ns Break-Before-Make Time Delay, tD VDD = 3.3V, RL = 50Ω, CL = 10pF (see Figure 2) 25 - 10 - ns Skew, (tSKEWOUT - tSKEWIN) VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, RL = 45Ω, CL = 10pF, tR = tF = 500ps at 480Mbps, (Duty Cycle = 50%) (see Figure 6) 25 - 50 - ps Rise/Fall Degradation (Propagation VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, Delay), tPD RL = 45Ω, CL = 10pF, (see Figure 6) 25 - 250 - ps Crosstalk VDD = 3.3V, RL = 50Ω, f = 240MHz (see Figure 5) 25 - -36 - dB OFF-Isolation VDD = 3.3V, OE = 3.3V, RL = 50Ω, f = 240MHz 25 - -32 - dB -3dB Bandwidth Signal = 0dBm, 0.2VDC offset, RL = 50Ω 25 - 742 - MHz OFF Capacitance, CHSxOFF f = 1MHz, VDD = 3.3V, SEL = 0V, OE = 3.3V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4) 25 - 2.8 - pF COM ON Capacitance, CDX(ON) f = 1MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4) 25 - 7.4 - pF COM ON Capacitance, CDX(ON) f = 240MHz, VDD = 3.3V, SEL = 0V or 3.3V, OE = 0V, VHSD1x or VHSD2x = VDx = 0V (see Figure 4) 25 - 4.2 - pF Full 2.7 5.5 V 25 - 0.009 0.03 µA Full - - 1 µA 25 - 0.159 0.6 µA Full - - 1.6 µA 25 - 6.6 10 µA Full - - 12 µA POWER SUPPLY CHARACTERISTICS Power Supply Range, VDD Positive Supply Current, IDD VDD = 5.5V, SEL = 0V or VDD, OE = 0V or VDD Positive Supply Current, IDD VDD = 4.3V, SEL = 2.6V, OE = 0V or 2.6V Positive Supply Current, IDD VDD = 3.6V, SEL = 1.4V, OE = 0V or 1.4V DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VSELL, VOEL VDD = 2.7V to 3.6V Full - - 0.5 V Input Voltage High, VSELH, VOEH VDD = 2.7V to 3.6V Full 1.4 - - V Input Voltage Low, VSELL, VOEL VDD = 4.3V to 5.5V Full - - 0.8 V 5 FN6819.1 February 4, 2010 ISL54220 Electrical Specifications - 2.7V to 5.5V Supply PARAMETER Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V, VOEH = 1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) TEMP MIN (°C) (Notes 12, 13) TEST CONDITIONS TYP MAX (Notes 12, 13) UNITS Input Voltage High, VSELH, VOEH VDD = 4.3V to 5.5V Full 2.0 - - V Input Current, ISELL, IOEL VDD = 5.5V, SEL = 0V, OE = 0V Full - 3.3 - nA Input Current, ISELH VDD = 5.5V, SEL = 5.5V Full - -3.6 - nA Input Current, IOEH VDD = 5.5V, OE = 5.5V Full - -8.2 - nA NOTES: 11. VLOGIC = Input voltage to perform proper function. 12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-. 16. Limits established by characterization and are not production tested. Test Circuits and Waveforms VDD LOGIC INPUT 50% C 0V VINPUT tOFF SWITCH INPUT VINPUT SWITCH INPUT VOUT HSDxx Dx SEL VOUT 90% SWITCH OUTPUT VDD tr < 20ns tf < 20ns 90% VIN GND OE 0V RL 50Ω CL 10pF tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (INPUT) -----------------------R L + r ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES 6 FN6819.1 February 4, 2010 ISL54220 Test Circuits and Waveforms (Continued) VDD C VDD LOGIC INPUT HSD2x VINPUT 0V RL 50Ω SEL SWITCH OUTPUT VOUT 90% GND VIN 0V VOUT Dx HSD1x CL 10pF OE tD Repeat test for all switches. CL includes fixture and stray capacitance. FIGURE 2B. TEST CIRCUIT FIGURE 2A. MEASUREMENT POINTS FIGURE 2. BREAK-BEFORE-MAKE TIME VDD C rON = V1/40mA HSDx VHSDX SEL V1 40mA OV OR VDD Dx GND OE Repeat test for all switches. FIGURE 3. rON TEST CIRCUIT 7 FN6819.1 February 4, 2010 ISL54220 Test Circuits and Waveforms (Continued) VDD VDD C C HSDxx SIGNAL GENERATOR HSD1x 50Ω Dx SEL SEL IMPEDANCE ANALYZER 0V OR VDD Dx GND VIN OE HSD2x Dx ANALYZER GND NC OE RL Repeat test for all switches. Signal direction through switch is reversed, worst case values are recorded. Repeat test for all switches. FIGURE 5. CROSSTALK TEST CIRCUIT FIGURE 4. CAPACITANCE TEST CIRCUIT VDD C tri 90% DIN+ DIN- 10% 50% VIN tskew_i 90% SEL 15.8Ω 50% 143Ω 10% DIN- tfi tro 15.8Ω OUT+ D2 COMD2 DIN+ CL COMD1 OUT- D1 OE 143Ω 45Ω CL 45Ω 90% OUT+ OUT- 10% 50% GND tskew_o 50% 90% 10% tf0 |tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals. |tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals. |tskew_0| Change in Skew through the Switch for Output Signals. |tskew_i| Change in Skew through the Switch for Input Signals. FIGURE 6A. MEASUREMENT POINTS FIGURE 6B. TEST CIRCUIT FIGURE 6. SKEW TEST 8 FN6819.1 February 4, 2010 ISL54220 Application Block Diagram µCONTROLLER VDD SEL USB CONNECTOR VBUS ISL54220 LOGIC CIRCUITRY OE HSD1- D- D- HSD1+ D+ D+ HSD2HSD2+ GND GND USB HIGH-SPEED OR FULL-SPEED TRANSCEIVER #1 USB HIGH_SPEED OR FULL-SPEED TRANSCEIVER #2 PORTABLE MEDIA DEVICE Detailed Description The ISL54220 device is a dual single pole/double throw (SPDT) analog switch configured as a DPDT that operates from a single DC power supply in the range of 2.7V to 5.5V. It was designed to function as a dual 2-to-1 multiplexer to select between two USB high-speed differential data signals in portable battery powered products. It is offered in a TDFN, MSOP, and a small µTQFN packages for use in MP3 players, cameras, PDAs, cell phones, and other personal media players. The device has an enable pin to open all switches. The part consists of four 6Ω high speed (HSx) switches. These switches have high bandwidth and low capacitance to pass USB high-speed (480Mbps) differential data signals with minimal edge and phase distortion. They can also swing from 0V to VDD to pass USB full speed (12Mbps) differential data signals with minimal distortion. The ISL54220 was designed for MP3 players, cameras, cell phones, and other personal media player applications that have multiple high-speed or full-speed transceivers sections and need to multiplex between these USB sources to a single USB host (computer). A typical application block diagram of this is shown on page 9. A detailed description of the HS switches is provided in the following section. High-Speed (HSx) Switches The HSx switches (HSD1-, HSD1+, HSD2-, HSD2+) are bi-directional switches that can pass rail-to-rail signals. When powered with a 3.3V supply, these switches have a nominal rON of 6Ω over the signal range of 0V to 400mV with a rON flatness of 0.94Ω. The rON matching between 9 the HSD1 and HSD2 switches over this signal range is only 0.12Ω, ensuring minimal impact by the switches to USB high speed signal transitions. As the signal level increases, the rON switch resistance increases. At signal level of 3.3V, the switch resistance is nominally 129Ω. See Figures 7, 8, 9, 10 in the “Typical Performance Curves” beginning on page 11. The HSx switches were specifically designed to pass USB 2.0 high-speed (480Mbps) differential signals in the range of 0V to 400mV. They have low capacitance and high bandwidth to pass the USB high-speed signals with minimum edge and phase distortion to meet USB 2.0 high speed signal quality specifications. See Figure 11 in the “Typical Performance Curves” on page 12 for USB High-speed Eye Pattern taken with switch in the signal path. The HSx switches can also pass USB full-speed signals (12Mbps) with minimal distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 12 in the “Typical Performance Curves” on page 13 for USB Full-speed Eye Pattern taken with switch in the signal path. The maximum normal operating signal range for the HSx switches is from 0V to VDD. The signal voltage should not be allow to exceed the VDD voltage rail or go below ground by more than -0.3V for normal operation. However, in the event that the USB 5.25V VBUS voltage gets shorted to one or both of the D-/D+ pins, the ISL54220 has special fault protection circuitry to prevent damage to the ISL54220 part. The fault circuitry allows the signal pins (D-, D+, HS1D-, HS1D+, HS2D-, HS2D+) to be driven up to 5.5V while the VDD supply voltage is in the range of 0V to 5.5V. In this condition the part draws < 500µA of current and causes no stress to the IC. In addition when VDD is at 0V (ground) all switches are OFF FN6819.1 February 4, 2010 ISL54220 and the fault voltage is isolated from the other side of the switch. When VDD is in the range of 2.7V to 5.5V the fault voltage will pass through to the output of an active switch channel. The HS1 channel switches are active (turned ON) whenever the SEL voltage is logic “0” (Low) and the OE voltage is logic “0” (Low). The HS2 channel switches are active (turned ON) whenever the SEL voltage is logic “1” (High) and the OE voltage is logic “0” (Low). ISL54220 Operation The following will discuss using the ISL54220 shown in the “Application Block Diagram” on page 9. POWER The power supply connected at the VDD pin provides the DC bias voltage required by the ISL54220 part for proper operation. The ISL54220 can be operated with a VDD voltage in the range of 2.7V to 5.5V. When used in a USB application, the VDD voltage should be kept in the range of 3.0V to 5.5V to ensure you get the proper signal levels for good signal quality. A 0.01µF or 0.1µF decoupling capacitor should be connected from the VDD pin to ground to filter out any power supply noise from entering the part. The capacitor should be located as close to the VDD pin as possible. In a typical application, VDD will be in the range of 2.8V to 4.3V and will be connected to the battery or LDO of the portable media device. LOGIC CONTROL The state of the ISL54220 device is determined by the voltage at the SEL pin and the OE pin. SEL is only active when the OE pin is logic “0” (Low). Refer to “Truth Table” on page 2. The ISL54220 logic pins are designed to minimize current consumption when the logic control voltage is lower than the VDD supply voltage. With VDD = 3.6V and logic pins at 1.4V the part typically draws only 6.6µA. With VDD = 4.3V and logic pins at 2.6V, the part typically draws only 0.2µA. Driving the logic pins to the VDD supply rail minimizes power consumption. The logic pins must be held High or Low and must not float. Logic Control Voltage Levels With VDD supply voltage in the range of 2.7V to 3.6V the logic levels are: OE = Logic “0” (Low) when VOE ≤ 0.5V OE = Logic “1” (High) when VOE ≥ 1.4V SEL = Logic “0” (Low) when VSEL ≤ 0.5V SEL = Logic “1” (High) when VSEL ≥ 1.4V 10 With VDD supply voltage in the range of 4.3V to 5.5V the logic levels are: OE = Logic “0” (Low) when VOE ≤ 0.8V OE = Logic “1” (High) when VOE ≥ 2.0V SEL = Logic “0” (Low) when VSEL ≤ 0.8V SEL = Logic “1” (High) when VSEL ≥ 2.0V HSD1 USB Channel If the SEL pin = Logic “0” and the OE pin = Logic “0”, high-speed Channel 1 will be ON. The HSD1- and HSD1+ switches are ON and the HSD2- and HSD2+ switches are OFF (high impedance). When a computer or USB hub is plugged into the common USB connector and channel one is active, a link will be established between the USB 1 driver section of the media player and the computer. The device will be able to transmit and receive data from the computer at a data rate of 480Mbps. HSD2 USB Channel If the SEL pin = Logic “1” and the OE pin = Logic “0”, high-speed Channel 2 will be ON. The HSD2- and HSD2+ switches are ON and the HSD1- and HSD1+ switches are OFF (high impedance). When a USB cable from a computer or USB hub is connected at the common USB connector and the part has Channel 2 active, a link will be established between the USB 2 driver section of the media player and the computer. The device will be able to transmit and receive data from the computer at a data rate of 480Mbps. All Switches OFF Mode If the SEL pin = Logic “0” or Logic “1” and the OE pin = Logic “1”, all of the switches will turn OFF (high impedance). The all OFF state can be used to switch between the two USB sections of the media player. When disconnecting from one USB device to the other USB device, you can momentarily put the ISL54220 switch in the “all off” state in order to get the computer to disconnect from the one device so it can properly connect to the other USB device when that channel is turned ON. USB 2.0 VBUS Short Requirements The USB specification in section 7.1.1 states a USB device must be able to withstand a VBUS short to the D+ or D- signal lines when the device is either powered off or powered on for at least 24 hours. The ISL54220 part has special fault protection circuitry to meet these short circuit requirements. The fault protection circuitry allows the signal pins (D-, D+, HS1D-, HS1D+, HS2D-, HS2D+) to be driven up to 5.5V while the VDD supply voltage is in the range of 0V to 5.5V. In this overvoltage condition the part draws <500µA of current and causes no stress/damage to the IC. FN6819.1 February 4, 2010 ISL54220 In addition when VDD is at 0V (ground), all switches are OFF and the shorted VBUS voltage is isolated from the other side of the switch. When VDD is in the range of 2.7V to 5.5V, the shorted VBUS voltage will pass through to the output of an active (turned ON) switch channel but not through a turned OFF channel. Any components connected on the active Typical Performance Curves channel must be able to withstand the overvoltage condition. Note: During the fault condition normal operation of the USB channel is not guaranteed until the fault condition is removed. TA = +25°C, Unless Otherwise Specified 200 8 ICOM = 1mA ICOM = 40mA VDD = 3.0V 150 7 VDD = 2.7V rON (Ω) rON (Ω) VDD = 2.7V VDD = 3.3V 6 VDD = 3.6V 5 4 0 50 VDD = 5.5V 0.05 0.10 0.15 0.20 0.25 VCOM (V) 0.30 0.35 V+ = 2.7V ICOM = 40mA 8 0 0.40 FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 9 8 +85°C rON (Ω) rON (Ω) -40°C 4 4 3 0.3 0.4 FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE 11 ICOM = 40mA 1.5 2.0 VCOM (V) 2.5 3.0 3.3 2 +85°C +25°C 5 5 0.2 VCOM (V) 1.0 6 6 0.1 0.5 V+ = 3.3V 7 +25°C 0 0 FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 7 3 VDD = 3.3V 100 -40°C 0 0.1 0.2 VCOM (V) 0.3 0.4 FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE FN6819.1 February 4, 2010 ISL54220 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE SCALE (0.1V/DIV) VDD = 3.3V TIME SCALE (0.2ns/DIV) FIGURE 11. EYE PATTERN: 480Mbps WITH USB SWITCHES IN THE SIGNAL PATH 12 FN6819.1 February 4, 2010 ISL54220 Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued) VOLTAGE SCALE (0.5V/DIV) VDD = 3.3V TIME SCALE (10ns/DIV) 1 -10 0 -20 -1 -30 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) FIGURE 12. EYE PATTERN: 12Mbps WITH USB SWITCHES IN THE SIGNAL PATH -2 -3 -4 RL = 50Ω VIN = 0dBm, 0.2VDC BIAS RL = 50Ω VIN = 0dBm, 0.2VDC BIAS -40 -50 -60 -70 -80 -90 -100 1M 10M 100M FREQUENCY (Hz) FIGURE 13. FREQUENCY RESPONSE 13 1G -110 0.001 0.01 0.1 1M 10M FREQUENCY (Hz) 100M 500M FIGURE 14. OFF-ISOLATION FN6819.1 February 4, 2010 ISL54220 Typical Performance Curves -10 NORMALIZED GAIN (dB) -20 TA = +25°C, Unless Otherwise Specified (Continued) RL = 50Ω VIN = 0dBm, 0.2VDC BIAS Die Characteristics SUBSTRATE AND TDFN THERMAL PAD POTENTIAL (POWERED UP): -30 GND -40 TRANSISTOR COUNT: -50 325 -60 PROCESS: -70 Submicron CMOS -80 -90 -100 -110 0.001 0.01 0.1 1M 10M FREQUENCY (Hz) 100M 500M FIGURE 15. CROSSTALK 14 FN6819.1 February 4, 2010 ISL54220 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 2/4/10 FN6819.1 Updated to new Intersil data sheet format. Page 1 Updated with Related Literature and Marketing graphics. In Pin Configurations on page 2: 10 Ld MSOP and 10 Ld TDFN used to have same Pinout. Made separate pinout for the 10 Ld TDFN Updated Pin Description Table on page 2 to new format by adding pin number and package type columns. Added MSL note to Ordering information on page 3. Added Latchup to “Absolute Maximum Ratings” on page 4. “Thermal Information” on page 4: Added Theta JC value of 105 and applicable Theta JC note for the 10 Ld µTQFN. Added Theta JC value of 65 and applicable Theta JC note for 10 Ld MSOP. 10 Ld µTQFN Theta JA note changed from: “θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.” to: θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379.” Updated package outline drawings L10.1.8x1.4A and L10.3x3A to most recent revisions. Changes to L10.1.8x1.4A were to add solder footprint. Changes to L10.3x3A were to change tolerance in top view from 0.15 to 0.10. Changes to L10.1.8x1.4A were to add solder footprint. Changes to L10.3x3A were to change tolerance in top view from 0.15 to 0.10. On“” on page 1 in Features section changed On Capacitance from 7.4pF to 4.2pF at 240MHz. Page 1 in Features section changed from: • Low ON-Resistance . . . . . . . . . . . . . . . . . . . . . . 6.7Ω to: • Low ON-Resistance @ VDD = 5.5V . . . . . . . . . . . 4.5Ω • Low ON-Resistance @ VDD = 3.3V . . . . . . . . . . . 6.0Ω Page 5 in Electrical Specification table added COM ON Capacitance, CDX(ON) at f = 240MHz 12/16/08 FN6819.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL54220 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php 15 FN6819.1 February 4, 2010 ISL54220 Package Outline Drawing L10.1.8x1.4A 10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 9/09 (DATUM A) 1.80 A PIN #1 ID 1 2 0.50 1.40 6 INDEX AREA 2X B NX 0.40 NX 0.20 5 10X 0.10 M C A B 0.05 M C 5 0.10 C 1 2X (DATUM B) 7 2 0.10 C 0.40 BSC BOTTOM VIEW TOP VIEW 0.10 C C 0.5 0.05 C SEATING PLANE 0.05 MAX 2.20 1.00 0.60 1.00 SIDE VIEW 0.50 1.80 0.40 0.20 0.20 0.40 5 NX (0.20) CL (0.05 MAX) 0.127 REF 0.40 e SECTION "C-C" TYPICAL RECOMMENDED LAND PATTERN TERMINAL TIP C C 10 LAND PATTERN 0.40 BSC DETAIL "X" NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. Total 10 leads. 3. Nd and Ne refer to the number of terminals on D (4) and E (6) side, respectively. 4. All dimensions are in millimeters. Tolerances ±0.05mm unless otherwise noted. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions. 9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 16 FN6819.1 February 4, 2010 ISL54220 Thin Dual Flat No-Lead Plastic Package (TDFN) L10.3x3A 2X 0.10 C A A 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.10 C B SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - E A3 6 INDEX AREA TOP VIEW B // A C SEATING PLANE 0.08 C b 0.20 0.25 0.30 5, 8 D 2.95 3.0 3.05 - D2 2.25 2.30 2.35 7, 8 E 2.95 3.0 3.05 - E2 1.45 1.50 1.55 7, 8 e 0.50 BSC - k 0.25 - - - L 0.25 0.30 0.35 8 A3 SIDE VIEW D2 (DATUM B) 0.10 C 0.20 REF 7 8 N 10 2 Nd 5 3 Rev. 4 8/09 D2/2 NOTES: 6 INDEX AREA 1 2 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. NX k 3. Nd refers to the number of terminals on D. (DATUM A) 4. All dimensions are in millimeters. Angles are in degrees. E2 E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 NX b 8 e (Nd-1)Xe REF. BOTTOM VIEW 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 0.10 M C A B 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions. CL NX (b) (A1) L1 5 9 L ( 2.30 ) e SECTION "C-C" C C ( 2.00 ) TERMINAL TIP FOR ODD TERMINAL/SIDE ( 10X 0.50) (1.50) ( 2.90 ) Pin 1 (8x 0.50) ( 10X 0.25) TYPICAL RECOMMENDED LAND PATTERN 17 FN6819.1 February 4, 2010 ISL54220 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 b -H- A1 e D 0.10 (0.004) 4X θ L SEATING PLANE C -A0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- MILLIMETERS MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e L1 MIN 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - 0.07 - - R1 0.003 - 0.07 - - θ 5o 15o 5o 15o - α 0o 6o 0o 6o - END VIEW Rev. 0 12/02 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN6819.1 February 4, 2010