16 M EDO DRAM (2-Mword × 8-bit) 2 k Refresh E0156H10 (Ver. 1.0) (Previous ADE-203-630D (Z)) Jun. 27, 2001 LP EO Description HM5117805 Series The HM5117805 is a C MOS dynamic R AM orga nize d 2, 097,152-w ord × 8-bit. It employs the most adva nce d C MOS tec hnology for high per forma nce and low powe r. The HM5117805 off ers Extende d Da ta Out (ED O) P age Mode as a high spee d ac ce ss mode. Multiplexe d addr ess input per mits the HM5117805 to be packaged in standard 28-pin plastic SOJ and 28-pin TSOP. Features ct du ro • Single 5 V (±10%) • Access time: 50 ns/60 ns/70 ns (max) • Power dissipation Active mode: 605 mW/550 mW/495 mW (max) Standby mode : 11 mW (max) : 0.83 mW (max) (L-version) • EDO page mode capability • Long refresh period 2048 refresh cycles : 32 ms : 128 ms (L-version) • 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) • Battery backup operation (L-version) Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd. EO HM5117805 Series Ordering Information Type No. Access time Package HM5117805J-5 HM5117805J-6 HM5117805J-7 50 ns 60 ns 70 ns 400-mil 28-pin plastic SOJ (CP-28DA) HM5117805LJ-5 HM5117805LJ -6 HM5117805LJ -7 50 ns 60 ns 70 ns HM5117805LS-5 HM5117805LS-6 HM5117805LS-7 HM5117805TT-5 HM5117805TT-6 HM5117805TT-7 HM5117805LTT-5 HM5117805LTT-6 HM5117805LTT-7 LP HM5117805S-5 HM5117805S-6 HM5117805S-7 50 ns 60 ns 70 ns 300-mil 28-pin plastic SOJ (CP-28DNA) 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 400-mil 28-pin plastic TSOP II (TTP-28DA) 50 ns 60 ns 70 ns ro HM5117805TS-5 HM5117805TS-6 HM5117805TS-7 50 ns 60 ns 70 ns HM5117805LTS-5 HM5117805LTS-6 HM5117805LTS-7 50 ns 60 ns 70 ns 300-mil 28-pin plastic TSOP II (TTP-28DB) ct du Data Sheet E0156H10 2 EO HM5117805 Series Pin Arrangement HM5117805TT/LTT Series HM5117805TS/LTS Series HM5117805J/LJ Series HM5117805S/LS Series VCC 1 28 VSS I/O0 2 27 I/O7 I/O6 I/O1 3 26 I/O6 25 I/O5 I/O2 4 25 I/O5 5 24 I/O4 I/O3 5 24 I/O4 6 23 CAS WE 6 23 CAS 7 22 OE RAS 7 22 OE 8 21 A9 NC 8 21 A9 9 20 A8 A10 9 20 A8 10 19 A7 A0 10 19 A7 11 18 A6 A1 11 18 A6 12 17 A5 A2 12 17 A5 13 16 A4 A3 13 16 A4 14 15 VSS 14 15 VSS 28 VSS I/O0 2 27 I/O7 I/O1 3 26 4 I/O2 I/O3 WE RAS NC A10 A0 A1 A3 VCC (Top view) ro A2 VCC LP 1 Function A0 to A10 Address input — Row/Refresh address A0 to A10 — Column address A0 to A9 I/O0 to I/O7 Data input/Data output RAS Row address strobe CAS Column address strobe WE Read/Write enable OE Output enable VCC Power supply VSS Ground NC No connection ct Pin name (Top view) du Pin Description VCC Data Sheet E0156H10 3 EO HM5117805 Series Block Diagram A9 • • • buffers Row address Column decoder 2M array 2M array 2M array 2M array I/O buffers 2M array 2M array ro buffers A10 OE address Row decoder • • • WE Timing and control Column A1 to CAS LP A0 RAS 2M array 2M array ct du Data Sheet E0156H10 4 I/O0 to I/O7 EO HM5117805 Series Absolute Maximum Ratings Symbol Value Unit Voltage on any pin relative to VSS VT –1.0 to +7.0 V Supply voltage relative to VSS VCC –1.0 to +7.0 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 °C –55 to +125 °C LP Parameter Storage temperature Tstg Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Supply voltage Input high voltage Input low voltage Note: Symbol Min Typ Max Unit Note VCC 4.5 5.0 5.5 V 1 VIH 2.4 — 6.5 V 1 VIL –1.0 — 0.8 V 1 1. All voltage referred to VSS . ct du ro Data Sheet E0156H10 5 EO HM5117805 Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM5117805 -5 Parameter -6 -7 Symbol Min Max Min Max Min Max Unit Test conditions I CC1 — 110 — 100 — 90 mA t RC = min I CC2 — 2 — 2 — 2 mA TTL interface RAS, CAS = VIH Dout = High-Z — 1 — 1 — 1 mA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC2 — 150 — 150 — 150 µA CMOS interface RAS, CAS ≥ VCC – 0.2 V Dout = High-Z I CC3 — 110 — 100 — 90 mA t RC = min I CC5 — 5 5 5 mA RAS = VIH CAS = VIL Dout = enable CAS-before-RAS refresh current I CC6 — 110 — 90 mA t RC = min EDO page mode current* 1, * 3 I CC7 — 85 mA t HPC = min Battery backup current* 4 (Standby with CBR refresh) (L-version) I CC10 — Self refresh mode current (L-version) I CC11 — Input leakage current I LI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 7 V Output leakage current I LO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 7 V Dout = disable Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –2 mA Output low voltage VOL 0 0.4 0.4 0.4 V Low Iout = 2 mA 1, Operating current* * 2 Standby current RAS-only refresh current* 2 Standby current* 1 — — 100 — ro LP Standby current (L-version) 90 500 — 500 — 300 — 300 — 0 — 500 µA du 100 — 0 300 µA CMOS interface Dout = High-Z CBR refresh: t RC = 62.5 µs t RAS ≤ 0.3 µs CMOS interface RAS, CAS ≤ 0.2V Dout = High-Z ct Notes: 1. I CC depends on output load condition when the device is selected. I CC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. CAS = L (≤ 0.2 V) while RAS = L (≤ 0.2 V). Data Sheet E0156H10 6 EO HM5117805 Series Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 — 5 pF 1 Input capacitance (Clocks) CI2 — 7 pF 1 Output capacitance (Data-in, Data-out) CI/O — 7 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. LP AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)*1, *2, *18 Test Conditions Input rise and fall time: 2 ns Input levels: VIL = 0 V, VIH = 3 V Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) ct du ro • • • • • Data Sheet E0156H10 7 EO HM5117805 Series Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM5117805 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Random read or write cycle time t RC 84 — 104 — 124 — ns RAS precharge time t RP 30 — 40 — 50 — ns CAS precharge time t CP 7 — 10 — 13 — ns t RAS 50 10000 60 10000 70 10000 ns t CAS 7 10000 10 10000 13 10000 ns Row address setup time t ASR 0 — 0 — 0 — ns Row address hold time t RAH 7 — 10 — 10 — ns Column address setup time t ASC 0 — 0 — 0 — ns Column address hold time t CAH 7 — 10 — 13 — ns RAS to CAS delay time t RCD 11 37 14 45 14 52 ns 3 RAS to column address delay time t RAD 9 25 12 30 12 35 ns 4 RAS hold time t RSH 10 — 13 — 13 — ns t CSH 35 — 40 — 45 — ns 5 — 5 — 5 — ns 13 — 15 — 18 — ns 5 0 — 0 — 0 — ns 6 0 — 0 — 0 — ns 6 2 50 2 50 2 50 ns 7 RAS pulse width CAS pulse width CAS to RAS precharge time t CRP OE to Din delay time t OED OE delay time from Din t DZO CAS delay time from Din t DZC Transition time (rise and fall) tT ct du ro CAS hold time LP Parameter Data Sheet E0156H10 8 Notes EO HM5117805 Series Read Cycle HM5117805 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes Access time from RAS t RAC — 50 — 60 — 70 ns 8, 9 Access time from CAS t CAC — 13 — 15 — 18 ns 9, 10, 17 Access time from address t AA — 25 — 30 — 35 ns 9, 11, 17 Access time from OE t OEA — 13 — 15 — 18 ns 9 Read command setup time t RCS 0 — 0 — 0 — ns Read command hold time to CAS t RCH 0 — 0 — 0 — ns Read command hold time from RAS t RCHR 50 — 60 — 70 — ns Read command hold time to RAS t RRH 0 — 0 — 0 — ns Column address to RAS lead time t RAL 25 — 30 — 35 — ns Column address to CAS lead time t CAL 15 — 18 — 23 — ns CAS to output in low-Z t CLZ 0 — 0 — 0 — ns Output data hold time t OH 3 — 3 — 3 — ns Output data hold time from OE t OHO 3 — 3 — 3 — ns Output buffer turn-off time t OFF — 13 — 15 — 15 ns 13, 20 Output buffer turn-off to OE t OEZ — 13 — 15 — 15 ns 13 CAS to Din delay time t CDD 13 — 15 — 18 — ns 5 Output data hold time from RAS t OHR 3 — 3 — 3 — ns 20 Output buffer turn-off to RAS t OFR — 13 — 15 — 15 ns 20 Output buffer turn-off to WE t WEZ — 13 — 15 — 15 ns WE to Din delay time t WED 13 — RAS to Din delay time t RDD 13 — RAS next CAS delay time t RNCD 50 — du ro LP Parameter 15 — 18 — ns 15 — 18 — ns 60 — 70 — ns 12 12 20 ct Data Sheet E0156H10 9 EO HM5117805 Series Write Cycle HM5117805 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes Write command setup time t WCS 0 — 0 — 0 — ns 14 Write command hold time t WCH 7 — 10 — 13 — ns Write command pulse width t WP 7 — 10 — 10 — ns Write command to RAS lead time t RWL 7 — 10 — 13 — ns Write command to CAS lead time t CWL 7 — 10 — 13 — ns Data-in setup time t DS 0 — 0 — 0 — ns 15 t DH 7 — 10 — 13 — ns 15 Notes Data-in hold time LP Parameter Read-Modify-Write Cycle -5 -6 -7 Symbol Min Max Min Max Min Max Unit Read-modify-write cycle time t RWC 111 — 135 — 161 — ns RAS to WE delay time t RWD 67 — 79 — 92 — ns 14 CAS to WE delay time t CWD 30 — 34 — 40 — ns 14 Column address to WE delay time t AWD 42 — 49 — 57 — ns 14 OE hold time from WE t OEH 13 — 15 — 18 — ns Refresh Cycle du ro Parameter HM5117805 HM5117805 -5 Parameter Symbol -6 -7 Max Min Max Min Max Unit CAS setup time (CBR refresh cycle) t CSR 5 — 5 — 5 — ns CAS hold time (CBR refresh cycle) t CHR 7 — 10 — 10 — ns WE setup time (CBR refresh cycle) t WRP 0 — 0 — 0 — ns WE hold time (CBR refresh cycle) t WRH 7 — 10 — 10 — ns RAS precharge to CAS hold time t RPC 5 — 5 — 5 — ns Data Sheet E0156H10 10 ct Min Notes EO HM5117805 Series EDO Page Mode Cycle HM5117805 -5 -6 -7 Symbol Min Max Min Max Min Max Unit Notes EDO page mode cycle time t HPC 20 — 25 30 ns 19 EDO page mode RAS pulse width t RASP — 100000 — 100000 — 100000 ns 16 Access time from CAS precharge t CPA — 28 — 35 — 40 ns 9, 17 RAS hold time from CAS precharge t CPRH 28 — 35 — 40 — ns Output data hold time from CAS low t DOH 3 — 3 — 3 — ns CAS hold time referred OE t COL 7 — 10 — 13 — ns CAS to OE setup time t COP 5 — 5 — 5 — ns 28 — 35 — 40 — ns LP Parameter Read command hold time from CAS t RCHC precharge — — 9, 17 EDO Page Mode Read-Modify-Write Cycle HM5117805 ro -5 Parameter Symbol EDO page mode read- modify-write t HPRWC cycle time WE delay time from CAS precharge t CPW -6 -7 Min Max Min Max Min 57 — 68 — 79 ns 45 — 54 — 62 ns Parameter Symbol Refresh period t REF Refresh period (L-version) t REF du Refresh Max Unit Notes 14 Max Unit Note 32 ms 2048 cycles 128 ms 2048 cycles ct Data Sheet E0156H10 11 EO HM5117805 Series Self Refresh Mode (L-version) HM5117805L -5 -6 -7 Parameter Symbol Min Max Min Max Min Max Unit RAS pulse width (self refresh) t RASS 100 — 100 — 100 — µs RAS precharge time (self refresh) t RPS 90 — 110 — 130 — ns CAS hold time (self refresh) t CHS –50 — –50 — –50 — ns Notes ct du ro LP Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the t RCD (max) limit insures that t RAC (max) can be met, t RCD (max) is specified as a reference point only; if t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by t CAC . 4. Operation with the t RAD (max) limit insures that t RAC (max) can be met, t RAD (max) is specified as a reference point only; if t RAD is greater than the specified t RAD (max) limit, then access time is controlled exclusively by t AA . 5. Either t OED or t CDD must be satisfied. 6. Either t DZO or t DZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that t RCD ≤ t RCD (max) and t RAD ≤ t RAD (max). If t RCD or t RAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ t RCD (max) and t RAD ≤ t RAD (max). 11. Assumes that t RCD ≤ t RCD (max) and t RAD ≥ t RAD (max). 12. Either t RCH or t RRH must be satisfied for a read cycles. 13. t OFF (max) and t OEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD≥ t RWD (min), t CWD ≥ t CWD (min), and t AWD ≥ t AWD (min), or t CWD ≥ t CWD (min), t AWD ≥ t AWD (min) and t CPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + t CP + 2 t T) becomes greater than the specified t HPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). Data Sheet E0156H10 12 EO HM5117805 Series ct du ro LP 20. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between t OFR and t OFF. 21. Please do not use t RASS timing, 10 µs ≤ t RASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS ≥ 100 µs, then RAS precharge time should use t RPS instead of t RP. 22. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycles, 2048 cycles of distributed CBR refresh with 15.6 µs interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 23. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. Data Sheet E0156H10 13 EO HM5117805 Series Timing Waveforms*25 Read Cycle t RC t RAS t RP RAS LP t CSH t CRP t RCD t RSH t CAS tT CAS t RAD t ASR Address t RAH t ASC t RAL t CAL t CAH Column Row ro t RRH t RCHR t RCS WE t DZC t DZO t OEA OE t RDD t OED t OEZ t OHO t OFF t AA ct t CAC t WED t CDD du High-Z Din t RCH t OH t OFR t OHR t RAC t CLZ t WEZ Dout Dout Data Sheet E0156H10 14 EO HM5117805 Series Early Write Cycle tRC tRAS tRP RAS tCSH tCRP LP tRCD tRSH tCAS tT CAS tASR Address tRAH Row tASC tCAH Column ro tWCS WE tWCH Din tDH Din du tDS High-Z* Dout ct * t WCS t WCS (min) Data Sheet E0156H10 15 EO HM5117805 Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t CRP LP t RCD t RSH t CAS tT CAS t ASR Address t RAH t ASC Row t CAH Column t CWL WE t DZC t DS t RWL t WP t DH du Din ro t RCS High-Z Din t DZO t OEH t OED t OEZ t CLZ High-Z Dout Invalid Dout Data Sheet E0156H10 16 ct OE EO HM5117805 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS t RCD LP CAS tT t CAS t CRP t RAD t ASR Address tRAH t ASC Row t CAH Column t RCS tCWL t AWD t RWL t RWD t WP ro WE t CWD t DZC du High-Z Din t DH t DS Din t OED t DZO t OEH t OEA OE t CAC t RAC t OHO Dout Dout t CLZ ct t OEZ t AA High-Z Data Sheet E0156H10 17 EO HM5117805 Series RAS-Only Refresh Cycle t RC t RAS t RP RAS t CRP LP CAS tT t ASR Address t RPC t CRP t RAH Row t OFR t OFF ! ct du Data Sheet E0156H10 18 High-Z ro Dout EO HM5117805 Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP RAS t CSR t CHR t RPC t CRP LP , t RPC tT CAS t CP WE Address t OFF Dout t CP t WRH ro t OFR t WRP High-Z ct du Data Sheet E0156H10 19 EO HM5117805 Series Hidden Refresh Cycle t RC t RC t RP t RAS t RAS t RC t RP t RAS t RP RAS tT LP t RSH t CHR t CRP t RCD CAS t RAD t ASR t RAH Address t RAL t ASC Row t CAH Column t WRH t WRP t WRP tWRH ro t RCS t RRH WE t DZC t RRH t RCH High-Z t DZO t OEA OE t CAC t AA t CLZ Dout Dout t OHR Data Sheet E0156H10 t OED t OFF t OH t OFR 20 t CDD t RDD t OEZ t WEZ t OHO ct t RAC du Din t WED EO HM5117805 Series EDO Page Mode Read Cycle t RP t RNCD t RASP RAS tT t CSH Address tRAH tASC Row t HPC t CPRH t CP t tCAH Column 1 tCAS t RCHC t ASC t CAH t ASC t CAH Column 2 Column 3 t CAL t CRP RSH tCAS t RCH t RCS LP tASR t CP t CAS t RCHR t RCS WE t HPC t CP t CAS CAS t HPC t CAL t RRH t RCH t RAL t CAH tASC t WED Column 4 t CAL t CAL tRDD tCDD tDZC Din High-Z tCOL tCOP tOED ro tDZO OE tCPA tOEA tAA tCAC tCAC tAA tWEZ tRAC Dout 1 tOHO tAA tOEZ tOEA Dout 2 tDOH tOHO du Dout tOEZ tOFR tOHR tOEZ tCPA tCPA tAA tCAC Dout 2 Dout 3 tCAC tOHO tOFF tOH tOEA Dout 4 ct Data Sheet E0156H10 21 EO HM5117805 Series EDO Page Mode Early Write Cycle tRP tRASP RAS tT tASR Address tHPC tCAS tRCD LP CAS tCSH Row tRAH tASC tCAH Column 1 tWCH WE tDS Dout tDH Din 1 tASC tCAH Column 2 tWCS tDS tWCH tDH tCP tCAS tASC tCRP tCAH Column N tWCS tDS tWCH tDH du Din tCAS ro tWCS tCP tRSH Din 2 Din N High-Z* ct * t WCS Data Sheet E0156H10 22 t WCS (min) EO HM5117805 Series EDO Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CP LP t CSH t RCD CAS t CRP t CP t HPC t CAS t CAS t RSH t CAS t RAD t ASR t ASC t RAH Address t ASC t CAH Row t ASC t CAH Column 1 t CAH Column 2 t CWL t RCS t WP t DZC t DS t CWL t RCS t WP t WP t DZC t DS t DZC t DS t DH Din 1 Din t DH t DH Din 2 Din N du t DZO t DZO # t DZO t CWL t RWL t RCS ro WE Column N t OED t OED t OED t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ Invalid Dout t OEZ High-Z ct Dout Invalid Dout t OEH Invalid Dout Data Sheet E0156H10 23 EO HM5117805 Series EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t HPRWC t RCD CAS t RSH t CP LP t CP t CAS t CAS t CRP t CAS t RAD t ASR Address t ASC t RAH Row t ASC t CAH t CAH Column 1 t RWD Column 2 t CWL t WP t RCS t DZC t DS t DH t OED t DH Din 2 t OED t DZO t DH du t DZO Din N t OED t DZO t OEH t OEH #* t OEH t RWL t WP t DZC t DS Din 1 t CWL t CWD t WP t DZC t DS Din t CPW t AWD t CWD ro t RCS t CWL t AWD t RCS WE Column N t CPW t AWD t CWD t ASC t CAH OE t OHO t OEA t CAC t OHO t OEA t CAC t AA t AA t CPA t RAC t AA t CPA t OEZ t CLZ t CLZ t OEZ ct t OEZ t CLZ t OHO t OEA t CAC High-Z Dout Dout 1 Dout 2 Data Sheet E0156H10 24 Dout N EO HM5117805 Series EDO Page Mode Mix Cycle (1) t RP t RASP RAS tT t CAS CAS t CRP t CP t CP t CP t CAS tCAS tCAS t CSH LP tRSH t RCD t WCS WE t ASC tRAH tASR Address Row t WCH tCAH Column 1 t CAL t DS tCPW tAWD t ASC t CAH tASC t CAH Column 2 Column 3 t CAL tASC t RAL t CAH Column 4 t CAL t DH Din 1 tWP High-Z tRDD tCDD t CAL t DH t DS Din 3 ro tOED tWED Din t RRH t RCH t RCS t RCS OE tCPA tAA tOEA tCAC tAA t DOH tAA t OEZ Dout 2 tCAC t OHO Dout 3 tOEZ tCAC du Dout tOFR tWEZ tCPA tCPA tOHO tOEA tOFF tOH Dout 4 ct Data Sheet E0156H10 25 EO HM5117805 Series EDO Page Mode Mix Cycle (2) t RNCD t RP t RASP RAS tT CAS t CSH t CAS t ASC tRAH tASR Address Row t RCH tCAH Column 1 tWCS t WCH tCAS Column 2 Column 3 High-Z t CAL t RAL t CAH tASC Column 4 t CAL t CAL t DS t DH tRDD tCDD t DH ro Din 2 tOED t RRH t RCH tWP tCPW t ASC t CAH t DS tRSH t RCS t RCS t ASC t CAH t CAL Din tCAS t RCHR t RCS WE t CAS LP t RCD t CRP t CP t CP Din 3 tOED tCOP tWED tCOL OE tAA tOEA tCAC tOEZ t OHO Dout Dout 1 tOFR tWEZ tCPA tCPA tAA tCAC tOEZ du tRAC t OEA t OHO Dout 3 tAA tCAC tOEZ tOEA tOFF tOH tOHO Dout 4 ct Data Sheet E0156H10 26 EO HM5117805 Series Self Refresh Cycle (L-version) *21, 22, 23, 24 t RASS t RP t RPS RAS tT , , t RPC LP CAS t CP t WRP WE t CRP t CSR t CHS t WRH $%&+, t OFR t OFF ro Dout High-Z ct du Data Sheet E0156H10 27 EO HM5117805 Series Package Dimensions HM5117805J/LJ Series (CP-28DA) Unit: mm 18.17 18.54 Max 11.18 ± 0.13 LP 1.27 0.10 Dimension including the plating thickness Base material dimension 9.40 ± 0.25 Hitachi Code JEDEC EIAJ Weight (reference value) CP-28DA Conforms Conforms 1.16 g ct du ro 0.43 ± 0.10 0.41 ± 0.08 0.80 +0.25 –0.17 1.30 Max 2.85 ± 0.12 14 0.74 3.50 ± 0.26 1 10.16 ± 0.13 15 28 Data Sheet E0156H10 28 EO HM5117805 Series HM5117805S/LS Series (CP-28DNA) Unit: mm 18.41 18.84 Max 0.25 2.45 +– 0.36 1.165 Max 0.43 ± 0.10 0.41 ± 0.08 8.51 ± 0.12 14 0.90 ± 0.26 0.74 3.50 ± 0.26 LP 1 7.62 ± 0.12 15 28 6.79 ± 0.18 1.27 ro 0.10 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) CP-28DNA — — 0.95 g ct du Data Sheet E0156H10 29 EO HM5117805 Series HM5117805TT/LTT Series (TTP-28DA) Unit: mm 18.41 18.81 Max 0.21 14 0.80 M 11.76 ± 0.20 Dimension including the plating thickness Base material dimension 0.145 ± 0.05 0.125 ± 0.04 0.10 0° – 5° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Weight (reference value) TTP-28DA Conforms — 0.43 g ct du ro 1.20 Max 1.15 Max Data Sheet E0156H10 30 0.68 1.27 0.13 ± 0.05 0.42 ± 0.08 0.40 ± 0.06 LP 1 15 10.16 28 EO HM5117805 Series HM5117805TS/LTS Series (TTP-28DB) Unit: mm 18.41 18.81 Max 15 LP 0.42 ± 0.08 0.40 ± 0.06 1.27 14 0.21 M 0.80 9.22 ± 0.2 Dimension including the plating thickness Base material dimension 0.13 ± 0.05 0.50 ± 0.10 0.145 ± 0.05 0.125 ± 0.04 0.10 0° – 5° ro 1.20 Max 1.15 Max Hitachi Code JEDEC EIAJ Weight (reference value) 0.63 1 7.62 28 TTP-28DB — — 0.35 g ct du Data Sheet E0156H10 31 EO HM5117805 Series Cautions ct du ro LP 1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products. Data Sheet E0156H10 32