ETC NT5DS32M8AT-66 256mb ddr333/300 sdram Datasheet

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Features
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions.
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch
CSP.
CAS Latency and Frequency
CAS Latency
2
2.5
Maximum Operating Frequency (MHz)*
DDR333 (-6)
DDR300 (-66)
133
133
166
150
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is centeraligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 268,435,456 bits. It is
internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II compatible.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edgealigned with data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write command. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
Preliminary
10/01
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Pin Configuration - 400mil TSOP II
VDD
VDD
1
66
VSS
VSS
NC
DQ0
2
65
DQ7
NC
VDDQ
VDDQ
3
64
VSSQ
VSSQ
NC
NC
4
63
NC
NC
DQ0
DQ1
5
62
DQ6
DQ3
VSSQ
VSSQ
6
61
VDDQ
VDDQ
NC
NC
7
60
NC
NC
NC
DQ2
8
59
DQ5
NC
VDDQ
VDDQ
9
58
VSSQ
VSSQ
NC
NC
10
57
NC
NC
DQ1
DQ3
11
56
DQ4
DQ2
VSSQ
VSSQ
12
55
VDDQ
VDDQ
NC
NC
13
54
NC
NC
NC
NC
14
53
NC
NC
VDDQ
VDDQ
15
52
VSSQ
VSSQ
NC
NC
16
51
DQS
DQS
NC
NC
17
50
NC
NC
VDD
VDD
18
49
VREF
VREF
NU
NU
19
48
VSS
VSS
NC
NC
20
47
DM*
DM*
WE
CAS
WE
CAS
21
46
22
45
CK
CK
CK
CK
RAS
RAS
23
44
CKE
CKE
CS
CS
24
43
NC
NC
NC
NC
25
42
A12
A12
BA0
26
A11
27
41
40
A11
BA1
BA0
BA1
A10/AP
A10/AP
28
39
A9
A8
A9
A8
A0
A0
29
38
A7
A7
A1
A1
30
37
A6
A6
A2
A2
31
36
A5
A5
A3
A3
VDD
VDD
32
33
35
34
A4
VSS
A4
VSS
66-pin Plastic TSOP-II 400mil
32Mb x 8
NT5DS32M8AT
64Mb x 4
NT5DS64M4AT
Column Address Table
Organization
Column Address
64Mb x 4
A0-A9, A11
32Mb x 8
A0-A9
*DM is internally loaded to match DQ and DQS identically.
Preliminary
10/01
2
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
64 X 4
1
2
3
7
8
9
VSSQ
NC
VSS
A
VDD
NC
VDDQ
NC
VDDQ
DQ3
B
DQ0
VSSQ
NC
NC
VSSQ
NC
C
NC
VDDQ
NC
NC
VDDQ
DQ2
D
DQ1
VSSQ
NC
NC
VSSQ
DQS
E
QFC
VDDQ
NC
VREF
VSS
DQM
F
NC
VDD
NC
CLK
CLK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
7
8
9
32 X 8
Preliminary
10/01
1
2
3
VSSQ
DQ7
VSS
A
VDD
DQ0
VDDQ
NC
VDDQ
DQ6
B
DQ1
VSSQ
NC
NC
VSSQ
DQ5
C
DQ2
VDDQ
NC
NC
VDDQ
DQ4
D
DQ3
VSSQ
NC
NC
VSSQ
DQS
E
QFC
VDDQ
NC
VREF
VSS
DQM
F
NC
VDD
NC
CLK
CLK
G
WE
CAS
A12
CKE
H
RAS
CS
A11
A9
J
BA1
BA0
A8
A7
K
A0
A10/AP
A6
A5
L
A2
A1
A4
VSS
M
VDD
A3
3
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Input/Output Functional Description
Symbol
Type
Function
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing).
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control
of stacked devices.
CS, CS0, CS1
Input
Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. During a Read, DM can be driven high, low, or floated.
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
A0 - A12
Input
Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
DQ
Input/Output
Data Input/Output: Data bus.
DQS
Input/Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.
CK, CK
CKE, CKE0, CKE1
NC
No Connect: No internal electrical connection is present.
NU
Electrical connection is present. Should not be connected at second level of assembly.
VDDQ
Supply
DQ Power Supply: 2.5V ± 0.2V.
VSSQ
Supply
DQ Ground
VDD
Supply
Power Supply: 2.5V ± 0.2V.
VSS
Supply
Ground
VREF
Supply
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
Preliminary
10/01
4
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Ordering Information
Part Number
Org.
NT5DS64M4AT-6
x4
NT5DS32M8AT-6
x8
NT5DS64M4AT-66
x4
NT5DS32M8AT-66
x8
NT5DS64M4AW-6
x4
NT5DS32M8AW-6
x8
NT5DS64M4AW-66
x4
NT5DS32M8AW-66
x8
CAS
Latency
Clock
(MHz)
CAS
Latency
Clock
(MHz)
Speed
2.5
166
2
133
DDR333
Package
66 pin TSOP-II
2.5
150
2
133
DDR300
2.5
166
2
133
DDR333
60 balls CSP
2.5
Preliminary
10/01
150
2
133
DDR300
5
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Control Logic
2
Bank2
Bank3
CK, CK
DLL
2
8192
4
8
8
1024
(x8)
Write
FIFO
&
Drivers
1
DQS
Generator
Input
Register
1
Mask 1
2
1
1
4
4
8
4
clk clk
out in Data
10
Column-Address
Counter/Latch
4
COL0
I/O Gating
DM Mask Logic
Column
Decoder
11
Drivers
8
Sense Amplifiers
Data
4
MUX
Bank0
Memory
Array
(8192 x 1024 x 8)
Read Latch
8192
CK,
CK
COL0
4
DQS
DQ0-DQ3,
DM
DQS
1
Receivers
15
Refresh Counter 13
A0-A12,
BA0, BA1
13
Address Register
15
13
Bank Control Logic
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Block Diagram (64Mb x 4)
4
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Preliminary
10/01
6
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Control Logic
CK, CK
DLL
16
Sense Amplifiers
2
Data
8
8
16
16
512
(x16)
1
DQS
Generator
Write
FIFO
&
Drivers
1
1
8
8
8
clk clk
out in Data
8
9
Column-Address
Counter/Latch
Input
Register
1
Mask 1
2
16
Column
Decoder
10
8
COL0
I/O Gating
DM Mask Logic
CK,
CK
COL0
Drivers
Bank0
Memory
Array
(8192 x 512 x 16)
MUX
8192
DQS
DQ0-DQ7,
DM
DQS
1
Receivers
2
Bank3
Read Latch
Refresh Counter 13
15
Address Register
A0-A12,
BA0, BA1
Bank2
8192
13
15
13
Bank Control Logic
Mode
Registers
Bank0
Row-Address Latch
& Decoder
Bank1
Row-Address MUX
CKE
CK
CK
CS
WE
CAS
RAS
Command
Decode
Block Diagram (32Mb x 8)
8
COL0
1
1
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidirectional DQ and DQS signals.
Preliminary
10/01
7
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Mode Register Operation
BA1
BA0
0*
0*
A12 - A9
A8
A12
A11 A10
A9
A8
A7
A6
A6 - A0
Operating Mode
0
0
0
Valid
Normal operation
Do not reset DLL
0
1
0
Valid
Normal operation
in DLL Reset
0
0
1
−
−
−
A4
CAS Latency
Operating Mode
A7
A5
A3
A2
BT
A1
Burst Length
A3
Burst
Type
0
Sequential
1
Interleave
A0
Address Bus
Mode Register
Vendor-Specific
Test Mode
VS**
Reserved
CAS Latency
Burst Length
A6
A5
A4
Latency
A2
A1
A0
Burst Length
0
0
0
Reserved
0
0
0
Reserved
0
0
1
Reserved
0
0
1
2
0
1
0
2
0
1
0
4
0
1
1
Reserved
0
1
1
8
1
0
0
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
0
Reserved
1
1
1
Reserved
1
1
1
Reserved
VS** Vendor Specific
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
Preliminary
10/01
8
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Burst Definition
Starting Column Address
Order of Accesses Within a Burst
Burst Length
A2
A1
A0
Type = Sequential
Type = Interleaved
0
0-1
0-1
1
1-0
1-0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
2
4
8
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition on page 9.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Preliminary
10/01
9
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Extended Mode Register Definition
BA1
BA0
0*
1*
A12
A11
A10
A8
A9
A7
A6
A5
A4
A3
Operating Mode
A2
A1
A0
Address Bus
0**
DS
DLL
Extended
Mode Register
Drive Strength
A12 - A3
A2 - A0
Operating Mode
0
Valid
Normal Operation
−
−
All other states
Reserved
A2
QFC
0
Disable
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register
(vs. the base Mode Register)
Preliminary
10/01
A1
Drive Strength
0
Normal
1
Reserved
A0
DLL
0
Enable
1
Disable
10
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each
commands follows.
Truth Table 1a: Commands
Name (Function)
CS
RAS
CAS
WE
Address
MNE
Notes
Deselect (Nop)
H
X
X
X
X
NOP
1, 9
No Operation (Nop)
L
H
H
H
X
NOP
1, 9
Active (Select Bank And Activate Row)
L
L
H
H
Bank/Row
ACT
1, 3
Read (Select Bank And Column, And Start Read Burst)
L
H
L
H
Bank/Col
Read
1, 4
Write (Select Bank And Column, And Start Write Burst)
L
H
L
L
Bank/Col
Write
1, 4
Burst Terminate
L
H
H
L
X
BST
1, 8
Precharge (Deactivate Row In Bank Or Banks)
L
L
H
L
Code
PRE
1, 5
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
L
L
L
H
X
AR / SR
1, 6, 7
Mode Register Set
L
L
L
L
Op-Code
MRS
1, 2
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode
Register.)
3. BA0-BA1 provide bank address and A0-A12 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Precharge feature (nonpersistent), A10 low disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refreshif CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function)
DM
DQs
Notes
Write Enable
L
Valid
1
Write Inhibit
H
X
1
1. Used to mask write data; provided coincident with the corresponding data.
Preliminary
10/01
11
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Truth Table 2: Clock Enable (CKE)
1.
2.
3.
4.
CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
Current state is the state of the DDR SDRAM immediately prior to clock edge n.
Command n is the command registered at clock edge n, and action n is a result of command n.
All states and sequences not shown are illegal or reserved.
CKE n-1
CKEn
Current State
Previous
Cycle
Current
Cycle
Command n
Self Refresh
L
L
X
Self Refresh
L
H
Deselect or NOP
Power Down
L
L
X
Power Down
L
H
Deselect or NOP
Exit Power-Down
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
All Banks Idle
H
L
Auto Refresh
Bank(s) Active
H
L
Deselect or NOP
H
H
See “Truth Table 3: Current State
Bank n - Command to Bank n (Same
Bank)” on page 13
Action n
Notes
Maintain Self-Refresh
Exit Self-Refresh
1
Maintain Power-Down
Self Refresh Entry
Active Power-Down Entry
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t XSNR) period. A minimum of
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Preliminary
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Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
H
X
X
X
Deselect
NOP. Continue previous operation
1-6
L
H
H
H
No Operation
NOP. Continue previous operation
1-6
L
L
H
H
Active
Select and activate row
1-6
L
L
L
H
Auto Refresh
L
L
L
L
Mode Register Set
L
H
L
H
Read
Select column and start Read burst
1-6, 10
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Deactivate row in bank(s)
1-6, 8
L
H
L
H
Read
Select column and start new Read burst
1-6, 10
L
L
H
L
Precharge
Truncate Read burst, start Precharge
1-6, 8
L
H
H
L
Burst Terminate
Burst Terminate
1-6, 9
L
H
L
H
Read
Select column and start Read burst
1-6, 10, 11
L
H
L
L
Write
Select column and start Write burst
1-6, 10
L
L
H
L
Precharge
Any
Idle
Row Active
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
1-7
1-7
Truncate Write burst, start Precharge
1-6, 8, 11
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging:
Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle
state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row
active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t RP has been
met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing:
Starts with registration of an Auto Refresh command and ends when tRFC is met. Once t RFC is met, the DDR SDRAM is
in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once t MRD is
met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle
state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
11. Requires appropriate DM masking.
Preliminary
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 1 of 2)
Current State
CS
RAS
CAS
WE
Command
Action
Notes
H
X
X
X
Deselect
NOP/continue previous operation
1-6
L
H
H
H
No Operation
NOP/continue previous operation
1-6
X
X
X
X
Any Command Otherwise
Allowed to Bank m
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-7
L
H
L
L
Write
Select column and start Write burst
1-7
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start new Read burst
1-7
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
1-6
L
H
L
H
Read
Select column and start Read burst
1-8
L
H
L
L
Write
Select column and start new Write burst
1-7
L
L
H
L
Precharge
Any
Idle
Row Activating,
Active, or
Precharging
Read
(Auto Precharge
Disabled)
Write
(Auto Precharge
Disabled)
1-6
1-6
1-6
1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The
access period starts with registration of the command and ends where the precharge period (or t RP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
Preliminary
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 2 of 2)
Current State
Read (With
Auto Precharge)
Write (With
Auto Precharge)
CS
RAS
CAS
WE
Command
L
L
H
H
Active
Select and activate row
Action
Notes
L
H
L
H
Read
Select column and start new Read burst
L
H
L
L
Write
Select column and start Write burst
L
L
H
L
Precharge
L
L
H
H
Active
Select and activate row
L
H
L
H
Read
Select column and start Read burst
1-7,10
L
H
L
L
Write
Select column and start new Write burst
1-7,10
L
L
H
L
Precharge
1-6
1-7,10
1-7,9,10
1-6
1-6
1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t XSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active:
A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read:
A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write:
A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The
access period starts with registration of the command and ends where the precharge period (or t RP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
Preliminary
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Absolute Maximum Ratings
Symbol
VIN, VOUT
Parameter
Voltage on I/O pins relative to VSS
Rating
Units
−0.5 to VDDQ+ 0.5
V
VIN
Voltage on Inputs relative to V SS
−0.5 to +3.6
V
VDD
Voltage on VDD supply relative to VSS
−0.5 to +3.6
V
Voltage on VDDQ supply relative to VSS
−0.5 to +3.6
V
0 to +70
°C
−55 to +150
°C
Power Dissipation
1.0
W
Short Circuit Output Current
50
mA
VDDQ
TA
TSTG
PD
IOUT
Operating Temperature (Ambient)
Storage Temperature (Plastic)
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Preliminary
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Capacitance
Parameter
Input Capacitance: CK, CK
Delta Input Capacitance: CK, CK
Symbol
Min.
Max.
Units
Notes
CI1
2.0
3.0
pF
1
0.25
pF
1
3.0
pF
1
0.5
pF
1
5.0
pF
1, 2
0.5
pF
1
delta CI1
Input Capacitance: All other input-only pins (except DM)
CI2
Delta Input Capacitance: All other input-only pins (except DM)
2.0
delta CI2
Input/Output Capacitance: DQ, DQS, DM
CIO
Delta Input/Output Capacitance: DQ, DQS, DM
4.0
delta CIO
1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2 , VOPeak -Peak = 0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is
required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)
Symbol
Min
Max
Units
Notes
Supply Voltage
2.3
2.7
V
1
VDDQ
I/O Supply Voltage
2.3
2.7
V
1
VSS, VSSQ
Supply Voltage
I/O Supply Voltage
0
0
V
I/O Reference Voltage
0.49 x VDDQ
0.51 x VDDQ
V
1, 2
I/O Termination Voltage (System)
VREF − 0.04
VREF + 0.04
V
1, 3
VIH(DC)
Input High (Logic1) Voltage
VREF + 0.15
VDDQ + 0.3
V
1
VIL(DC)
Input Low (Logic0) Voltage
− 0.3
VREF − 0.15
V
1
VIN(DC)
Input Voltage Level, CK and CK Inputs
− 0.3
VDDQ + 0.3
V
1
VID(DC)
Input Differential Voltage, CK and CK Inputs
0.30
VDDQ + 0.6
V
1, 4
VIRatio
V-I Matching Pullup Current to Pulldown Current Ratio
0.71
1.4
Input Leakage Current
Any input 0V ≤ VIN ≤ VDD ; (All other pins not under test = 0V)
−5
5
µA
1
Output Leakage Current
(DQs are disabled; 0V ≤ Vout ≤ VDDQ
−5
5
µA
1
mA
1
VDD
VREF
VTT
II
IOZ
IOH
IOL
Parameter
Output Current: Nominal Strength Driver
High current (VOUT = VDDQ -0.373V, min VREF, min VTT )
Low current (VOUT= 0.373V, max VREF, max V TT)
5
− 16.8
16.8
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on V REF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in tHalf-he DC level of V REF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
Preliminary
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DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)
Symbol
IOHW
IOLW
Parameter
Min
Output Current: Half- Strength Driver
High current (VOUT = VDDQ -0.763V, min VREF, min VTT )
Low current (VOUT= 0.763V, max VREF, max V TT)
Max
Units
Notes
mA
1
− 9.0
9.0
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on V REF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in tHalf-he DC level of V REF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK.
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
Preliminary
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AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I DD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, I DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and I DD tests may use a V IL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V IL(AC) and
VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.
AC Output Load Circuit Diagrams
VTT
50Ω
Output
Timing Reference Point
(VOUT)
30pF
Preliminary
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DQS/DQ/DM Slew Rate
Parameterl
Symbol
DCS/DQ/DM
input slew rate
1. Measured between V IH (DC), V
DDR333
(-6)
DCSLEW
IL (DC),
and V
IL (DC),
V
Min
Max
TBD
TBD
Unit
Notes
V/ns
1,2
IH (DC).
2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-sition
through the DC region must be monotonic..
Preliminary
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AC Input Operating Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
VIH(AC)
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
VIL(AC)
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
VID(AC)
Input Differential Voltage, CK and CK Inputs
VIX(AC)
Input Crossing Point Voltage, CK and CK Inputs
1.
2.
3.
4.
Min
Max
Unit
Notes
V
1, 2
VREF − 0.31
V
1, 2
0.62
VDDQ + 0.6
V
1, 2, 3
0.5*V DDQ − 0.2
0.5*VDDQ + 0.2
V
1, 2, 4
VREF + 0.31
Input slew rate = 1V/ns.
Inputs are not recognized as valid until VREF stabilizes.
VID is the magnitude of the difference between the input level on CK and the input level on CK.
The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
IDD Specifications and Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
Characteristics)
DDR333
tCK=6ns
Symbol
Parameter/Condition
IDD0
Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle
IDD1
Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC
(min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock
cycle
IDD2P
DDR333
tCK=6.6ns
Unit
Notes
85
mA
1
110
mA
1
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE ≤ VIL (max)
15
mA
1
IDD2N
Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min);
address and control inputs changing once per clock cycle
35
mA
1
IDD3P
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VIL (max)
15
mA
1
IDD3N
Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);
CKE ≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing once per clock cycle
60
mA
1
IDD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; IOUT = 0mA
165
mA
1
IDD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5
150
mA
1
IDD5
Auto-Refresh Current: tRC = t RFC (min)
170
mA
1
IDD6
Self-Refresh Current: CKE ≤ 0.2V
3
mA
1, 2
IDD7
Operating current: four bank; four bank interleaving with BL = 4, address and
control inputs randomly changing; 50% of data changing at every transfer;
t RC = t RC (min); I OUT = 0mA.
150
mA
1
1. IDD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
Preliminary
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Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; V DD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
DDR333
(-6)
Parameter
DDR300
(-66)
Unit
Notes
+ 0.75
ns
1-4
− 0.75
+ 0.75
ns
1-4
0.55
0.45
0.55
tCK
1-4
0.45
0.55
0.45
0.55
tCK
1-4
CL = 2.5
6
12
6.6
12
ns
1-4
CL = 2.0
7.5
12
7.5
12
0.5
ns
1-4,
15,16
0.45
0.5
ns
1-4,
15,16
DQ and DM input pulse width (each input)
1.75
1.75
ns
1-4
tHZ
Data-out high-impedance time from CK/CK
− 0.7
+ 0.7
− 0.75
+ 0.57
ns
1-4, 5
tLZ
Data-out low-impedance time from CK/CK
− 0.7
+ 0.7
− 0.75
+ 0.75
ns
1-4, 5
+ 0.5
ns
1-4
Min
Max
Min
Max
DQ output access time from CK/CK
− 0.7
+ 0.7
− 0.75
DQS output access time from CK/CK
− 0.7
+ 0.7
tCH
CK high-level width
0.45
tCL
CK low-level width
tCK
Clock cycle time
tDH
DQ and DM input hold time
0.45
tDS
DQ and DM input setup time
tDIPW
tAC
tDQSCK
tDQSQ
+ 0.4
DQS-DQ skew (DQS & associated DQ signals)
tHP
minimum half clk period for any given cycle;
defined by clk high (tCH ) or clk low (t CL) time
tQH
Data output hold time from DQS
min
(tCH, tCL)
min
(tCH, tCL)
tCK
1-4
tHP - tQHS
tHP - tQHS
tCK
1-4
tCK
1-4
Write command to 1st DQS latching
transition
0.75
DQS input low (high) pulse width (write cycle)
0.35
0.35
tCK
1-4
tDSS
DQS falling edge to CK setup time (write cycle)
0.2
0.2
tCK
1-4
tDSH
DQS falling edge hold time from CK (write cycle)
0.2
0.2
tCK
1-4
tMRD
Mode register set command cycle time
2 x tCK
2 x tCK
ns
1-4
0
0
ns
1-4, 7
tCK
1-4, 6
tDQSS
tDQSL,H
tWPRES
Write preamble setup time
1.25
Write postamble
0.40
tWPRE
Write preamble
0.25
0.25
tCK
1-4
tIH
Address and control input hold time
(fast slew rate)
0.75
0.9
ns
2-4,
9,11,12
tIS
Address and control input setup time
(fast slew rate)
0.75
0.9
ns
2-4,
9,11,12
tIH
Address and control input hold time
(slow slew rate)
0.8
1.0
ns
2-4, 10,
11,12,14
tIS
Address and control input setup time
(slow slew rate)
0.8
1.0
ns
2-4, 10,
11,12,14
Input pulse width
2.2
2.2
ns
2-4, 12
tRPRE
Read preamble
0.9
1.1
0.9
1.1
tCK
1-4
tRPST
Read postamble
0.40
0.60
0.40
0.60
tCK
1-4
tRAS
Active to Precharge command
42
120,000
45
120,000
ns
1-4
Preliminary
10/01
0.40
1.25
tWPST
tIPW
0.60
0.75
0.60
22
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; V DD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)
Symbol
DDR333
(-6)
Parameter
Min
DDR300
(-66)
Max
Min
Unit
Notes
Max
tRC
Active to Active/Auto-refresh command period
60
65
ns
1-4
tRFC
Auto-refresh to Active/Auto-refresh
command period
72
75
ns
1-4
tRCD
Active to Read or Write delay
18
20
ns
1-4
tRAP
Active to Read Command with Autoprecharge
18
20
ns
1-4
tRP
Precharge command period
18
20
ns
1-4
tRRD
Active bank A to Active bank B command
12
15
ns
1-4
tWR
Write recovery time
15
15
ns
1-4
tDAL
Auto precharge write recovery
+ precharge time
(tWR /tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
1-4,13
tWTR
Internal write to read command delay
1
1
tCK
1-4
tXSNR
Exit self-refresh to non-read command
75
75
ns
1-4
tXSRD
Exit self-refresh to read command
200
200
tCK
1-4
tREFI
Average Periodic Refresh Interval
µs
1-4, 8
Preliminary
10/01
7.8
7.8
23
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Electrical Characteristics & AC Timing - Absolute Specifications
Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V TT .
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on t DQSS .
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC).
10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC).
11. CK/CK slew rates are ≥ 1.0V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. t CK is equal to the actual
system clock cycle time.
Preliminary
10/01
24
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew
rate is below 0.5 V/ns.
Input Slew Rate
delta ( t IS)
delta ( t IH)
Unit
Notes
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+50
0
ps
1,2
0.3 V/ns
+100
0
ps
1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC) to
V
IL (AC) or
V IH (DC) to V IL (DC) , similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below
0.5 V/ns.
Input Slew Rate
delta ( t DS)
delta ( t DH)
Unit
Notes
0.5 V/ns
0
0
ps
1,2
0.4 V/ns
+75
+75
ps
1,2
0.3 V/ns
+150
+150
ps
1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V
IL (AC) or
V IH (DC) to V
IL (DC) ,
similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH) in the case where DQ, DM, and DQS slew rates
differ.
Input Slew Rate
delta ( t DS)
delta ( t DH)
Unit
Notes
0.0 V/ns
0
0
ps
1,2,3,4
0.25 V/ns
+50
+50
ps
1,2,3,4
0.5 V/ns
+100
+100
ps
1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V
IH (AC) to
V
IL (AC) or
V IH (DC) to V IL (DC) , similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]
= -0.5 ns/V
Using the table above, this would result in an increase in t
DS and
t
DH of
100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
Preliminary
10/01
25
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Package Dimensions (400mil; 66 lead; Thin Small Outline Package)
Detail A
11.76 ± 0.20
10.16 ±. 0.13
22.22 ± 0.10
Lead #1
Seating Plane
0.10
0.65 Basic
0.30
+ 0.03
- 0.08
0.71REF
1.20 Max
Detail A
0.25 Basic
Gage Plane
0.5 ± 0.1
0.05 Min
Preliminary
10/01
26
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Package Dimensions (
60 balls ; 0.8mmx1.0mm Pitch ; CSP Package)
8.5
0.80
15.50
0.50
1.00
1.05
2.25
Dia.
0.45
0.35
0.80
1.15
Note : All dimensions are typical unless otherwise stated.
Unit : Millimeters
Preliminary
10/01
27
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.