IDT IDT72V36110L10PF 3.3 volt high-density supersyncâ ¢ ii 36-bit fifo Datasheet

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x36, 131,072 x 36
FEATURES:
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Choose among the following memory organizations:Commercial
IDT72V3640  1,024 x 36
IDT72V3650  2,048 x 36
IDT72V3660  4,096 x 36
IDT72V3670  8,192 x 36
IDT72V3680  16,384 x 36
IDT72V3690  32,768 x 36
IDT72V36100  65,536 x 36
IDT72V36110  131,072 x 36
133 MHz operation (7.5 ns read/write cycle time)
User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
Big-Endian/Little-Endian user selectable byte representation
5V input tolerant
Fixed, low first word latency
IDT72V3640, IDT72V3650
IDT72V3660, IDT72V3670
IDT72V3680, IDT72V3690
IDT72V36100, IDT72V36110
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Zero latency retransmit
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
Program programmable flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
Available in the 128-pin Thin Quad Flat Pack (TQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°°C to +85°°C) is available
FUNCTIONAL BLOCK DIAGRAM
D0 -Dn (x36, x18 or x9)
WEN
WCLK
INPUT REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
BE
IP
BM
IW
OW
MRS
PRS
LD SEN
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
FLAG
LOGIC
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
CONTROL
LOGIC
OUTPUT REGISTER
BUS
CONFIGURATION
RESET
LOGIC
READ POINTER
READ
CONTROL
LOGIC
RT
RM
RCLK
REN
OE
Q0 -Qn (x36, x18 or x9)
The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
 2001 Integrated Device Technology, Inc.
4667 drw 01
APRIL 2001
DSC-4667/3
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
DESCRIPTION:
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Bus-Matching Sync FIFOs are particularly appropriate for network, video,
telecommunications, data communications and other applications that need to
buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and BusMatching (BM) pin during the Master Reset cycle.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (REN) input. Data is read from the FIFO on every rising edge
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110 are exceptionally deep, high speed, CMOS First-InFirst-Out (FIFO) memories with clocked read and write controls and a flexible
Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user
benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 4 Mbit
WCLK
PRS
MRS
LD
FWFT/SI
FF/IR
VCC
PAF
GND
OW
FS0
HF
GND
FS1
BE
IP
BM
VCC
PAE
PFM
EF/OR
RM
GND
RCLK
REN
RT
PIN CONFIGURATIONS
D10
D9
D8
D7
D6
GND
D5
D4
D3
VCC
D2
D1
D0
GND
Q0
Q1
Q2
Q3
Q4
Q5
GND
Q6
VCC
Q7
Q8
Q9
DNC(1)
IW
D35
D34
D33
D32
VCC
D31
D30
GND
D29
D28
D27
D26
D25
D24
D23
GND
D22
VCC
D21
D20
D19
D18
GND
D17
D16
D15
D14
D13
VCC
D12
GND
D11
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
DNC(1)
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
WEN
SEN
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
INDEX
NOTE:
1. DNC = Do Not Connect.
TQFP (PK128-1, order code: PF)
TOP VIEW
2
OE
VCC
VCC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
VCC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
VCC
VCC
Q15
Q14
Q13
Q12
GND
Q11
Q10
4667 drw 02
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
DESCRIPTION (CONTINUED)
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
of RCLK when REN is asserted. An Output Enable (OE) input is provided for
three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
PARTIAL RESET (PRS)
MASTER RESET (MRS)
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
(x36, x18, x9) DATA IN (D0 - Dn)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
READ ENABLE (REN)
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
PROGRAMMABLE ALMOST-FULL (PAF)
OUTPUT ENABLE (OE)
(x36, x18, x9) DATA OUT (Q0 - Qn)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
4667 drw 03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUSMATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
3
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during MasterReset by the state of the Programmable Flag
Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more than
once. A LOW on the RT input during a rising RCLK edge initiates a retransmit
operation by setting the read pointer to the first location of the memory array.
A zero-latency retransmit timing mode can be selected using the Retransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero latency retransmit operation is selected, the first data word to be
retransmitted will be placed on the output register with respect to the same RCLK
edge that initiated the retransmit based on RT being LOW.
Refer to Figure 11 and 12 for Retransmit Timing with normal latency. Refer
to Figure 13 and 14 for Zero Latency Retransmit Timing.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFO will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 4 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effect during parallel programming of the offset registers. It does not effect the data
written to and read from the FIFO.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110 are fabricated using IDT’s high speed submicron CMOS
technology.
TABLE 1  BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
L
L
x36
x36
H
L
L
x36
x18
H
L
H
x36
x9
H
H
L
x18
x36
H
H
H
x9
x36
NOTE:
1. Pin status during Master Reset.
4
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
D0–D35
MRS
Name
Data Inputs
Master Reset
I/O
Description
I
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the
FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmable
flag default settings, serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero
latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
PRS
Partial Reset
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, the
existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable
flag settings. RT is useful to reread data from the first physical location of the FIFO.
FWFT/SI First Word Fall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
Through/Serial In
functions as a serial input for loading offset registers.
(1)
OW
Output Width
I
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
IW(1)
Input Width
I
This pin, along with OW and MB, selects the bus width of the write port. See Table 1 for bus size configuration.
(1)
Bus-Matching
I
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration.
BM
BE(1)
Big-Endian/
I
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
Little-Endian
will select Little-Endian format.
RM(1)
Retransmit Timing I
During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select
Mode
normal latency mode.
(1)
PFM
Programmable
I
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
Flag Mode
will select Synchronous Programmable flag timing mode.
IP(1)
Interspersed Parity I
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity
mode. Interspersed Parity control only has an effect during parallel programming of the offset registers. It does not effect
the data written to and read from the FIFO.
(1)
Flag Select Bit 0
I
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable
FSEL0
flags PAE and PAF. There are up to eight possible settings available.
I
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable
FSEL1(1) Flag Select Bit 1
flags PAE and PAF. There are up to eight possible settings available.
WCLK
Write Clock
I
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers
for parallel programming, and when enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN
Write Enable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable
registers.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
Output Enable
I
OE controls the output impedance of Qn.
SEN
Serial Enable
I
SEN enables serial loading of programmable flag offsets.
LD
Load
I
This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines
one of eight default offset values for the PAE and PAF flags, along with the method by which these offset registers can
be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing to and reading from the
offset registers.
FF/IR
Full Flag/
O In the IDT Standard mode, the FF function is selected. FF indicates whether or Input Ready not the FIFO memory
is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing
to the FIFO memory.
EF/OR
Empty Flag/
O In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
Output Ready
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs.
PAF
Programmable
O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-Full Flag
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PAE
Programmable
O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-Empty Flag
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
HF
Half-Full Flag
O HF indicates whether the FIFO memory is more or less than half-full.
O Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
Q0–Q35 Data Outputs
state. Outputs are not 5V tolerant regardless of the state of OE.
NOTE:
1. Inputs should not change state after Master Reset.
5
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
ABSOLUTE MAXIMUM RATINGS
Symbol
VTERM(2)
TSTG
IOUT
Rating
Terminal Voltage
with respect to GND
Com’l & Ind’l
–0.5 to +4.5
Storage
Temperature
–55 to +125
DC Output Current
–50 to +50
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RECOMMENDED DC OPERATING
CONDITIONS
Unit
V
Symbol
(1)
GND
VCC
°C
Typ.
Max.
Unit
Supply Voltage Com’l/Ind’l
3.15
3.3
3.45
V
Supply Voltage Com’l/Ind’l
0
0
0
V
—
5.5
V
Input High Voltage Com’l/Ind’l
2.0
(3)
Input Low Voltage Com’l/Ind’l
—
—
0.8
V
TA
Operating Temperature
Commercial
0
—
70
°C
TA
Operating Temperature
Industrial
-40
—
85
°C
VIL
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminal only.
Min.
(2)
VIH
mA
Parameter
NOTES:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V3640L
IDT72V3650L
IDT72V3660L
IDT72V3670L
IDT72V3680L
IDT72V3690L
IDT72V36100L
IDT72V36110L
Commercial and Industrial(1)
tCLK = 7.5, 10, 15 ns
Symbol
(2)
ILI
ILO(3)
VOH
VOL
ICC1(4,5,6)
ICC2(4,7)
NOTES:
Parameter
Input Leakage Current
Output Leakage Current
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
Standby Current
1.
2.
3.
4.
5.
6.
Min.
Max.
Unit
–1
–10
2.4
—
—
—
1
10
—
0.4
40
15
µA
µA
V
V
mA
mA
Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
Measurements with 0.4 ≤ VIN ≤ VCC.
OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
Tested with outputs open (IOUT = 0).
RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
Typical ICC1 = 4.2 + 1.4*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
Capacitance
VIN = 0V
10
pF
COUT(1,2)
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
6
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Symbol
fS
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tLDS
tLDH
tRS
tRSS
tRSR
tRSF
tRTS
tOLZ
tOE
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
tSKEW1
tSKEW2
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
Reset Pulse Width(3)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Setup Time
Output Enable to Output in Low Z(4)
Output Enable to Output Valid
Output Enable to Output in High Z(4)
Write Clock to FF or IR
Read Clock to EF or OR
Clock to Asynchronous Programmable
Almost-Full Flag
Write Clock to Synchronous Programmable
Almost-Full Flag
Clock to Asynchronous Programmable
Almost-Empty Flag
Read Clock to Synchronous Programmable
Almost-Empty Flag
Clock to HF
Skew time between RCLK and WCLK for
EF/OR and FF/IR
Skew time between RCLK and WCLK for
PAE and PAF
Commercial
IDT72V3640L7.5
IDT72V3640L10
IDT72V3650L7.5
IDT72V3650L10
IDT72V3660L7.5
IDT72V3660L10
IDT72V3670L7.5
IDT72V3670L10
IDT72V3680L7.5
IDT72V3680L10
IDT72V3690L7.5
IDT72V3690L10
IDT72V36100L7.5
IDT72V36100L10
IDT72V36110L7.5
IDT72V36110L10
Com’l & Ind’l(2)
IDT72V3640L15
IDT72V3650L15
IDT72V3660L15
IDT72V3670L15
IDT72V3680L15
IDT72V3690L15
IDT72V36100L15
IDT72V36110L15
Min.
—
2
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
10
15
10
—
3.5
0
2
2
—
—
—
Max.
133.3
5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
6
6
5
5
12.5
Min.
—
2
10
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
15
10
—
3.5
0
2
2
—
—
—
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
6
6
6.5
6.5
16
Min.
—
2
15
6
6
4
1
4
1
4
1
15
15
15
—
4
0
2
2
—
—
—
Max.
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
8
8
10
10
20
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
5
—
6.5
—
10
ns
—
12.5
—
16
—
20
ns
—
5
—
6.5
—
10
ns
—
5
12.5
—
—
7
16
—
—
9
20
—
ns
ns
7
—
10
—
14
—
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range is available by special order for speed grades faster than 15ns.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
7
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
AC TEST CONDITIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC TEST LOADS - 7.5ns Speed Grade
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load for tCLK = 10ns, 15 ns
Output Load for tCLK = 7.5ns
GND to 3.0V
3ns(1)
1.5V
1.5V
See Figure 2a
See Figure 2b & 2c
1.5V
50Ω
I/O
Z0 = 50Ω
NOTE:
1. For 133MHz operation input rise/fall times are 1.5ns.
4667 drw04a
Figure 2b. AC Test Load
AC TEST LOADS - 10ns, 15ns Speed Grades
6
3.3V
tCD
(Typical, ns)
5
330Ω
D.U.T.
510Ω
30pF*
4
3
2
1
4667 drw04
20 30 50
80 100
Capacitance (pF)
200
4667 drw04b
Figure 2a. Output Load
* Includes jig and scope capacitances.
Figure 2c. Lumped Capacitive Load, Typical Derating
8
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
FUNCTIONAL DESCRIPTION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
writes for the IDT72V36100 and 131,072 writes for the IDT72V36110,
respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7,8,11 and 13.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110 support two different timing modes of operation: IDT
Standard mode or First Word Fall Through (FWFT) mode. The selection of
which mode will operate is determined during Master Reset, by the state of the
FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag function
(FF) to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
the first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of Table
2. This parameter is also user programmable. See section on Programmable
Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 514th word
for the IDT72V3640, 1,026th word for the IDT72V3650, 2,050th word for the
IDT72V3660, 4,098th word for the IDT72V3670, 8,194th word for the
IDT72V3680, 16,386th word for the IDT72V3690, 32,770th word for the
IDT72V36100 and 65,538th word for the IDT72V36110, respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the PAF
to go LOW. Again, if no reads are performed, the PAF will goLOW after (1,025-m)
writes for the IDT72V3640, (2,049-m) writes for the IDT72V3650, (4,097-m)
writes for the IDT72V3660 and (8,193-m) writes for the IDT72V3670, 16,385
writes for the IDT72V3680, 32,769 writes for the IDT72V3690, 65,537 writes
for the IDT72V36100 and 131,073 writes for the IDT72V36110, where m is the
full offset value. The default setting for these values are stated in the footnote
of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. D = 1,025 writes for the IDT72V3640, 2,049 writes for
the IDT72V3650, 4,097 writes for the IDT72V3660 and 8,193 writes for the
IDT72V3670,16,385 writes for the IDT72V3680, 32,769 writes for the
IDT72V3690, 65,537 writes for the IDT72V36100 and 131,073 writes for the
IDT72V36110, respectively. Note that the additional word in FWFT mode is due
to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10, 12,
and 14.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
the 513rd word for IDT72V3640, 1,025th word for IDT72V3650, 2,049th word
for IDT72V3660, 4,097th word for IDT72V3670, 8,193th word for the
IDT72V3680, 16,385th word for the IDT72V3690, 32,769th word for the
IDT72V36100 and 65,537th word for the IDT72V36110, respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, the PAF will go LOW after (1,024-m) writes for the IDT72V3640,
(2,048-m) writes for the IDT72V3650, (4,096-m) writes for the IDT72V3660,
(8,192-m) writes for the IDT72V3670, (16,384-m) writes for the IDT72V3680,
(32,768-m) writes for the IDT72V3690, (65,536-m) writes for the IDT72V36100
and (131,072-m) writes for the IDT72V36110. The offset “m” is the full offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. D = 1,024 writes for the IDT72V3640, 2,048 writes for the
IDT72V3650, 4,096 writes for the IDT72V3660, 8,192 writes for the IDT72V3670,
16,384 writes for the IDT72V3680, 32,768 writes for the IDT72V3690, 65,536
9
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
TABLE 2  DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72V3640, 72V3650
LD
L
L
L
L
H
H
H
H
FSEL1
H
L
L
H
L
H
L
H
FSEL0
L
H
L
H
L
L
H
H
Offsets n,m
511
255
127
63
31
15
7
3
LD
H
FSEL1
X
FSEL0
X
Program Mode
Serial(3)
L
X
X
Parallel(4)
IDT72V3660, 72V3670, 72V3680, 72V3690
LD
H
L
L
L
L
H
H
H
FSEL1
L
H
L
L
H
H
L
H
FSEL0
L
L
H
L
H
L
H
H
Offsets n,m
1,023
511
255
127
63
31
15
7
LD
H
L
FSEL1
X
X
FSEL0
X
X
Program Mode
Serial(3)
Parallel(4)
IDT72V36100, 72V36110
LD
L
L
L
H
H
H
H
L
FSEL1
H
L
H
H
L
L
H
L
FSEL0
L
H
H
L
L
H
H
L
Offsets n,m
16,383
8,191
4,095
2,047
1,023
511
255
127
LD
H
L
FSEL1
X
X
FSEL0
X
X
Program Mode
Serial(3)
Parallel(4)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690/72V36100/72V36110 have
internal registers for these offsets. There are eight default offset values selectable
during Master Reset. These offset values are shown in Table 2. Offset values
can also be programmed into the FIFO in one of two ways; serial or parallel
loading method. The selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of the LD input determines whether serial
or parallel flag offset programming is enabled. A HIGH on LD during Master
Reset selects serial loading of offset values. A LOW on LD during Master Reset
selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time after
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110 can be configured during the Master Reset cycle with
either synchronous or asynchronous timing for PAF and PAE flags by use of
the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 17 for synchronous
PAF timing and Figure 18 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure
19 for asynchronous PAF timing and Figure 20 for asynchronous PAE timing.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
10
Number of
Words in
FIFO
STATUS FLAGS FOR IDT STANDARD MODE
IDT72V3640
IDT72V3650
0
0
1 to n
(1)
(n+1) to 512
513 to (1,024-(m+1))
(1024-m) to 1,023
1,024
IDT72V3680
IDT72V3670
0
0
1 to n
(1)
1 to n
(n+1) to 1,024
(1)
(n+1) to 2,048
1 to n
(1)
(n+1) to 4,096
FF
PAF HF
PAE
EF
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
1,025 to (2048-(m+1))
2,049 to (4,096-(m+1))
4,097 to (8,192-(m+1))
H
H
L
H
H
(2048-m) to 2,047
(4,096-m) to 4,095
(8,192-m) to 8,191
H
L
L
H
H
4,096
8,192
L
L
L
H
H
FF
PAF HF
2,048
IDT72V3690
0
Number of
Words in
FIFO
IDT72V3660
IDT72V36100
0
IDT72V36110
0
H
0
PAE EF
H
H
L
L
L
H
H
H
H
(n+1) to 8,192
(n+1) to 16,384
(n+1) to 32,768
(n+1) to 65,536
H
H
H
H
H
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
32,769 to (65,536-(m+1))
65,537 to (131,072-(m+1))
H
H
L
H
H
L
H
H
L
H
H
1 to n
(1)
1 to n
(1)
(16,384-m) to 16,383
(32,768-m) to 32,767
16,384
32,768
(1)
1 to n
1 to n
(1)
(131,072-m) to 131,071
H
L
65,536
131,072
L
L
IDT72V3660
IDT72V3670
IR
(65,536-m) to 65,535
NOTE:
1. See table 2 for values for n, m.
11
TABLE 4
Number of
Words in
FIFO
IDT72V3640
IDT72V3650
0
0
1 to n+1
1 to n+1
(n+2) to 513
(n+2) to 1,025
514 to (1,025-(m+1))
1,026 to (2,049-(m+1))
(1,025-m) to 1,024
(2,049-m) to 2,048
1,025
2,049
IDT72V3680
IDT72V3690
PAF HF
PAE OR
0
0
L
H
H
L
1 to n+1
1 to n+1
L
H
H
L
L
(n+2) to 4,097
L
H
H
H
L
4,098 to (8,193-(m+1))
L
H
L
H
L
to 8,192
L
L
L
H
L
H
L
L
H
L
(n+2) to 2,049
2,050 to (4,097-(m+1))
to 4,096
(4,097-m)
4,097
IDT72V36100
(8,193-m)
8,193
IDT72V36110
IR
PAF HF
H
PAE OR
0
0
0
0
L
H
H
L
1 to n+1
1 to n+1
1 to n+1
1 to n+1
L
H
H
L
L
(n+2) to 8,193
(n+2) to 16,385
(n+2) to 32,769
(n+2) to 65,537
L
H
H
H
L
8,194 to (16,385-(m+1))
16,386 to (32,769-(m+1))
32,770 to (65,537-(m+1))
65,538 to (131,073-(m+1))
L
H
L
H
L
(16,385-m) to 16,384
(32,769-m) to 32,768
(65,537-m) to 65,536
(131,073-m) to 131,072
L
L
L
H
L
16,385
32,769
131,073
H
L
L
H
NOTE:
1. See table 2 for values for n, m.
65,537
H
L
4667 drw 05
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Number of
Words in
FIFO
STATUS FLAGS FOR FWFT MODE
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
TABLE 3
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
LD
WEN
REN
SEN
0
0
1
1
0
1
0
1
0
1
1
0
WCLK
RCLK
X
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
IDT72V36100
IDT72V36110
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
Serial shift into registers:
X
20 bits for the 72V3640
22 bits for the 72V3650
24 bits for the 72V3660
26 bits for the 72V3670
28 bits for the 72V3680
30 bits for the 72V3690
32 bits for the 72V36100
34 bits for the 72V36110
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
X
No Operation
X
Write Memory
Read Memory
X
No Operation
4667 drw 06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
12
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1st Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q0
D/Q17
17
D/Q8
EMPTY OFFSET REGISTER (PAE)
17 16 15 14 13 12 11 10 9 8 7 6
16 15 14 13 12 11 10 9
5 4 3 2 1
8 7 6 5 4 3 2 1
Non-Interspersed
Parity
Interspersed
Parity
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q35
D/Q19
17
D/Q0
D/Q8
FULL OFFSET REGISTER (PAF)
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
D/Q17
Non-Interspersed
Parity
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
# of Bits Used:
10 bits for the IDT72V3640
11 bits for the IDT72V3650
12 bits for the IDT72V3660
13 bits for the IDT72V3670
14 bits for the IDT72V3680
15 bits for the IDT72V3690
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
Interspersed
Parity
# of Bits Used
IDT72V3640/50/60/70/80/90/100/110  x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (PAE)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
EMPTY OFFSET (LSB) REGISTER (PAE)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
D/Q8
# of Bits Used
Non-Interspersed
Parity
2nd Parallel Offset Write/Read Cycle
D/Q17 D/Q16
Data Inputs/Outputs
Interspersed
Parity
# of Bits Used
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
EMPTY OFFSET (MSB) REGISTER (PAE)
17
17
2nd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
3rd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
D/Q0
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q17 D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET (MSB) REGISTER (PAF)
17
17
IDT72V3640/50/60/70/80/90/100  x18 Bus Width
IDT72V36110  x18 Bus Width
4667 drw 07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
13
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1st Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
8
7
6
5
4
3
1st Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
D/Q0
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
8
7
6
5
4
3
D/Q0
2
2nd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
2nd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
16
15
14
13
12
11
16
D/Q0
10
15
14
13
12
11
D/Q0
10
3rd Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER (PAE)
9
1
9
D/Q0
17
3rd Parallel Offset Write/Read Cycle
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
D/Q0
FULL OFFSET REGISTER (PAF)
8
7
6
5
4
3
2
1
8
7
6
5
4
3
D/Q0
2
5th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
16
15
14
13
12
11
16
15
14
13
12
11
1
D/Q0
10
9
D/Q0
10
6th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER (PAF)
9
D/Q0
17
IDT72V3640/50/60/70/80/90/100  x9 Bus Width
IDT72V36110  x9 Bus Width
# of Bits Used:
10 bits for the IDT72V3640
11 bits for the IDT72V3650
12 bits for the IDT72V3660
13 bits for the IDT72V3670
14 bits for the IDT72V3680
15 bits for the IDT72V3690
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
4667 drw07a
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
14
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One, two or more offset registers can be written
and then by bringing LD HIGH, write operations can be redirected to the FIFO
memory. When LD is set LOW again, and WEN is LOW, the next offset register
in sequence is written to. As an alternative to holding WEN LOW and toggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling WEN.
Note that the status of a programmable flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when LD is set LOW and REN is set LOW. For x36 output bus width, data
are read via Qn from the Empty Offset Register on the first LOW-to-HIGH
transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are
read from the Full Offset Register. The third transition of RCLK reads, once
again, from the Empty Offset Register. For x18 output bus width, a total of four
read cycles are required to obtain the values of the offset registers. Starting with
the Empty Offset Register LSB and finishing with the Full Offset Register MSB.
For x9 output bus width, a total of six read cycles must be performed on the offset
registers. See Figure 3, Programmable Flag Offset Programming Sequence.
See Figure 17, Parallel Read of Programmable Flag Registers, for the timing
diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written,
one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 20 bits for the IDT72V3640, 22 bits for the
IDT72V3650, 24 bits for the IDT72V3660, 26 bits for the IDT72V3670, 28 bits
for the IDT72V3680, 30 bits for the IDT72V3690, 32 bits for the IDT72V36100
and 34 bits for the IDT72V36110. See Figure 15, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does
not have to occur at once. A select number of bits can be written to the SI input
and then, by bringing LD and SEN HIGH, data can be written to FIFO memory
via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN
restored to a LOW, the next offset bit in sequence is written to the registers via
SI. If an interruption of serial programming is desired, it is sufficient either to set
LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD
and SEN are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above criteria;
PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid
after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF
proceeds as follows: LD and WEN must be set LOW. For x36 bit input bus width,
data on the inputs Dn are written into the Empty Offset Register on the first LOWto-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of
WCLK, data are written into the Full Offset Register. The third transition of WCLK
writes, once again, to the Empty Offset Register. For x18 bit input bus width,
data on the inputs Dn are written into the Empty Offset Register LSB on the first
LOW-to-HIGH transition of WCLK. Upon the 2nd LOW-to-HIGH transition of
WCLK data are written into the Empty Offset Register MSB. The third transition
of WCLK writes to the Full Offset Register LSB, the fourth transition of WCLK then
writes to the Full Offset Register MSB. The fifth transition of WCLK writes once
again to the Empty Offset Register LSB. A total of four writes to the offset registers
is required to load values using a x18 input bus width. For an input bus width
of x9 bits, a total of six write cycles to the offset registers is required to load values.
See Figure 3, Programmable Flag Offset Programming Sequence. See
Figure 16, Parallel Loading of Programmable Flag Registers, for the timing
diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW. At least two words,
but no more than D - 2 words should have been written into the FIFO, and read
from the FIFO, between Reset (Master or Partial) and the time of Retransmit
setup. D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for
the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680,
32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the
IDT72V36110. In FWFT mode, D = 1,025 for the IDT72V2640, 2,049 for the
IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385
for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100
and 131,073 for the IDT72V36110.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be noticeable
15
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup,
the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK
that RT is setup will update HF. PAF is synchronized to WCLK, thus the second
rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that RT
is setup will update PAF. RT is synchronized to RCLK.
The Retransmit function has the option of two modes of operation, either
“normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
latency” retransmit operation. Zero latency basically means that the first data
word to be retransmitted, is placed onto the output register with respect to the
RCLK pulse that initiated the retransmit.
16
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
SIGNAL DESCRIPTION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
is selected, every word read including the first word following Retransmit setup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
In Retransmit operation, zero latency mode can be selected using the
Retransmit Mode (RM) pin during a Master Reset. This can be applied to both
IDT Standard mode and FWFT mode.
INPUTS:
DATA IN (D0 - Dn)
Data inputs for 36-bit wide data (D0 - D35), data inputs for 18-bit wide data
(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).
CONTROLS:
MASTER RESET ( MRS )
A Master Reset is accomplished whenever the MRS input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
All control settings such as OW, IW, BM, BE, RM, PFM and IP are defined
during the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Qn after three RCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
PARTIAL RESET ( PRS )
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word Fall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming programmable flag offset settings may not be
convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW.) The Write and Read Clocks can either be
independent or coincident.
RETRANSMIT ( RT )
The Retransmit operation allows data that has already been read to be
accessed again. There are 2 modes of Retransmit operation, normal latency
and zero latency. There are two stages to Retransmit: first, a setup procedure
that resets the read pointer to the first location of memory, then the actual
retransmit, which consists of reading out the memory contents, starting at the
beginning of the memory.
Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.
REN and WEN must be HIGH before bringing RT LOW. When zero latency is
utilized, REN does not need to be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be noticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard mode
WRITE ENABLE ( WEN )
When the WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
17
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data can be
read on the outputs, on the rising edge of the RCLK input. It is permissible to
stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and HF flags will
not be updated. (Note that RCLK is only capable of updating the HF flag to
HIGH.) The Write and Read Clocks can be independent or coincident.
READ ENABLE ( REN )
When Read Enable is LOW, data is loaded from the RAM array into the output
register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the last
word has been read from the FIFO, the Empty Flag (EF) will go LOW, inhibiting
further read operations. REN is ignored when the FIFO is empty. Once a write
is performed, EF will go HIGH allowing a read to occur. The EF flag is updated
by two RCLK cycles + tSKEW after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write. REN does not need to be asserted LOW. In order to access
all other words, a read must be executed using REN. The RCLK LOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW), inhibiting further read
operations. REN is ignored when the FIFO is empty.
SERIAL ENABLE ( SEN )
The SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset. SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of WCLK.
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE ( OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When OE is HIGH, the output data bus (Qn) goes
into a high impedance state.
LOAD ( LD )
This is a dual purpose pin. During Master Reset, the state of the LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset, LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
After Master Reset, the LD pin is used to activate the programming process
of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values.
BUS-MATCHING (BM, IW, OW)
The pins BM, IW and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 4 for BusMatching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 4 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable
flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM,
LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH transition
of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by the
state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode.
A HIGH will select Interspersed Parity mode. The IP bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bits are located in bit position D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D28 are is assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin. Interspersed Parity control only has an
effect during parallel programming of the offset registers. It does not effect the data
written to and read from the FIFO.
OUTPUTS:
FULL FLAG ( FF/IR )
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
18
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the
IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768
for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the
IDT72V36110). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard
Mode), for the relevant timing information.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
any free space left, IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either MRS or PRS), IR will go HIGH after D writes
to the FIFO (D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097
for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680,
32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the
IDT72V36110). See Figure 9, Write Timing (FWFT Mode), for the relevant
timing information.
The IR status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V3660 and (8,193-m) writes for the IDT72V3670, (16,385-m) writes for
the IDT72V3680, (32,769-m) writes for the IDT72V3690, (65,537-m) writes for
the IDT72V36100 and (131,073-m) writes for the IDT72V36110, where m is
the full offset value. The default setting for this value is stated in Table 2.
See Figure 18, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 20, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode).
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 19, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
If asynchronous PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
EMPTY FLAG ( EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
function is selected. When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty. See Figure 8, Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts
the last word from the FIFO memory to the outputs. OR goes HIGH only with
a true read (RCLK with REN = LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited until OR goes
LOW again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode, OR is a triple register-buffered output.
HALF-FULL FLAG ( HF )
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets HF
HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192
for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690,
65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for
the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,
65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (1,024-m) writes for the IDT72V3640,
(2,048-m) writes for the IDT72V3650, (4,096-m) writes for the IDT72V3660,
(8,192-m) writes for the IDT72V3670, (16,384-m) writes for the IDT72V3680,
(32,768-m) writes for the IDT72V3690, (65,536-m) writes for the IDT72V36100
and (131,072-m) writes for the IDT72V36110. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the PAF will go LOW after (1,025-m) writes for the
IDT72V3640, (2,049-m) writes for the IDT72V3650, (4,097-m) writes for the
DATA OUTPUTS (Q0-Qn)
(Q0-Q35) are data outputs for 36-bit wide data, (Q0 - Q17) are data outputs
for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
19
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
BYTE ORDER ON INPUT PORT:
D35-D27
A
BYTE ORDER ON OUTPUT PORT:
BE
BM
IW
OW
X
L
L
L
D26-D18
B
Q35-Q27
A
Q26-Q18
B
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D17-D9
D8-D0
C
D
Q17-Q9
Q8-Q0
C
D
Write to FIFO
Read from FIFO
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
BE
BM
IW
OW
L
H
L
L
Q26-Q18
Q17-Q9
A
Q35-Q27
Q26-Q18
Q8-Q0
B
Q17-Q9
Q8-Q0
C
D
1st: Read from FIFO
2nd: Read from FIFO
(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN
Q35-Q27
BE
BM
IW
OW
H
H
L
L
Q26-Q18
Q17-Q9
C
Q35-Q27
Q26-Q18
Q17-Q9
A
Q8-Q0
D
1st: Read from FIFO
Q8-Q0
B
2nd: Read from FIFO
(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN
Q35-Q27
BE
L
BM
IW
OW
H
L
H
Q26-Q18
Q17-Q9
Q8-Q0
A
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
B
Q35-Q27
Q26-Q18
Q17-Q9
Q26-Q18
Q17-Q9
2nd: Read from FIFO
Q8-Q0
C
Q35-Q27
1st: Read from FIFO
3rd: Read from FIFO
Q8-Q0
D
4th: Read from FIFO
(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN
Q35-Q27
BE
BM
IW
OW
H
H
L
H
Q26-Q18
Q17-Q9
Q8-Q0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
C
Q35-Q27
Q26-Q18
Q17-Q9
Q26-Q18
Q17-Q9
Figure 4. Bus-Matching Byte Arrangement
20
3rd: Read from FIFO
Q8-Q0
A
(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN
2nd: Read from FIFO
Q8-Q0
B
Q35-Q27
1st: Read from FIFO
4th: Read from FIFO
4667 drw 08
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
D35-D27
BYTE ORDER ON INPUT PORT:
D35-D27
BYTE ORDER ON OUTPUT PORT:
BE
BM
IW
OW
L
H
H
L
Q35-Q27
A
D26-D18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
D17-D9
D8-D0
A
B
D17-D9
D8-D0
C
D
Q26-Q18
Q17-Q9
Q8-Q0
B
C
D
D26-D18
1st: Write to FIFO
2nd: Write to FIFO
Read from FIFO
(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN
Q35-Q27
BE
BM
IW
OW
H
H
H
L
C
Q26-Q18
Q17-Q9
Q8-Q0
D
A
B
Read from FIFO
(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN
D35-D27
BYTE ORDER ON INPUT PORT:
D26-D18
D17-D9
D8-D0
A
D35-D27
D26-D18
D17-D9
D8-D0
B
D35-D27
D26-D18
D17-D9
D26-D18
D17-D9
BE
BM
L
H
IW
OW
H
H
3rd: Write to FIFO
D8-D0
D
BYTE ORDER ON OUTPUT PORT:
2nd: Write to FIFO
D8-D0
C
D35-D27
1st: Write to FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
A
B
C
D
4th: Write to FIFO
Read from FIFO
(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN
BE
BM
IW
OW
H
H
H
H
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
D
C
B
A
Read from FIFO
(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN
4667 drw 09
Figure 4. Bus-Matching Byte Arrangement (Continued)
21
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN
WEN
FWFT/SI
LD
tRSS
FSEL0,
FSEL1
tRSS
BM,
OW, IW
tRSS
BE
tRSS
RM
tRSS
PFM
tRSS
IP
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
tRSF
If FWFT = LOW, FF = HIGH
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
Figure 5. Master Reset Timing
22
4667 drw 10
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
tRSS
tRSR
REN
tRSS
tRSR
WEN
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
tRSF
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
Figure 6. Partial Reset Timing
23
4667 drw 11
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t CLK
t CLKH
NO WRITE
WCLK
t SKEW1
NO WRITE
tCLKL
2
1
1
(1)
(1)
t DS
D0 - Dn
2
t SKEW1
t DH
t DS
t DH
DX
DX+1
t WFF
t WFF
t WFF
t WFF
FF
WEN
RCLK
t ENS
t ENS
t ENH
t ENH
REN
tA
Q0 - Qn
tA
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
4667 drw 12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than t SKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
1
RCLK
tENS
tCLKL
2
tENH
tENS
REN
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
LAST WORD
Q0 - Qn
tOLZ
OE
LAST WORD
tA
D0
D1
t OLZ
tOHZ
tOE
(1)
tSKEW1
WCLK
tENS
tENH
tENS
tDH
tDS
tENH
WEN
tDS
D0 - Dn
D0
tDH
D1
4667 drw 13
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
24
1
tENS
WEN
D0 - D17
tDS
W1
W3
W2
W4
1
W[n +2]
W[n+3]
W[n+4]
W[ D-1
]
W[ D-1
]
W[ D-1
]
W[D-m-2]
tENH
W[D-m-1]
W[D-m]
W[D-m+1]
W[D-m+2]
W[D-1]
WD
tSKEW2(2)
tSKEW1(1)
RCLK
tDS
tDS
tDS
tDH
2
3
1
2
REN
tA
Q0 - Q17
DATA IN OUTPUT REGISTER
W1
tREF
OR
PAE
tPAES
tHF
HF
25
tPAFS
PAF
tWFF
IR
4667 drw 14
Figure 9. Write Timing (First Word Fall Through Mode)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
WCLK
tENS
1
(1)
tSKEW1
tENH
2
tSKEW2
(2)
WEN
tDS
D0 - D17
tDH
WD
1
RCLK
tENS
tENS
REN
OE
tOHZ
Q0 - Q17
tOE
W1
W1
tA
tA
W2
tA
tA
W3
Wm+2
W[m+3]
W[m+4]
W [ D-1
]
W [ D-1
tA
tA
]
W[D-n-1]
W[D-n]
W[D-n+1]
W[D-n+2]
W[D-1]
WD
tREF
OR
tPAES
PAE
tHF
HF
26
tPAFS
PAF
tWFF
tWFF
IR
4667 drw 15
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 10. Read Timing (First Word Fall Through Mode)
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
WCLK
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1
RCLK
tENS
tENH
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
2
tENS
tRTS
tENH
REN
tA
Q0 - Qn
tA
Wx
Wx+1
tA
W1
(3)
W2
(3)
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
tREF
tREF
EF
tPAES
PAE
tHF
HF
tPAFS
PAF
4667 drw 16
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100
and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
27
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1
RCLK
tENH
tENS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
3
2
4
tENH
tENS
tRTS
REN
tA
Q0 - Qn
Wx
tA
tA
Wx+1
W1
(4)
W2
(4)
tA
W3
(4)
W4
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
tREF
tREF
OR
tPAES
PAE
tHF
HF
tPAFS
PAF
4667 drw 17
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537
for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
28
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
2
1
RCLK
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
3
tENS
tENH
REN
tA
tA
Q0 - Qn
Wx
tA
tA
W2(3)
W1(3)
W0
Wx+1
tA
W3
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
EF
tPAES
PAE
tHF
HF
tPAFS
PAF
4667 drw 18
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100
and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
29
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
2
1
RCLK
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
4
3
5
tENH
tENS
REN
tA
Q0 - Qn
Wx
tA
Wx+1
tA
tA
W1
W2
(4)
W3
(4)
tA
W4
(4)
W5
tSKEW2
1
WCLK
2
tRTS
WEN
tENS
tENH
RT
OR
tPAES
PAE
tHF
HF
tPAFS
PAF
4667 drw 19
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537
for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
t ENS
tENH
tENH
SEN
tLDS
tLDH
tLDH
LD
tDH
tDS
SI
BIT 0
BIT X
EMPTY OFFSET
(1)
BIT 0
BIT X
FULL OFFSET
(1)
4667 drw 20
NOTE:
1. X = 9 for the IDT72V3640, X = 10 for the IDT72V3650, X = 11 for the IDT72V3660, X = 12 for the IDT72V3670, X = 13 for the IDT72V3680, X = 14 for the IDT72V3690, X = 15 for
the IDT72V36100 and X = 16 for the IDT72V36110.
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
30
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
t CLK
t CLKH
t CLKL
WCLK
t LDS
t LDH
t LDH
t ENS
t ENH
t ENH
LD
WEN
t DS
t DH
t DH
PAF
OFFSET
PAE
OFFSET
D0 - Dn
4667 drw 21
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t CLK
t CLKH
t CLKL
RCLK
t LDS
t LDH
t LDH
LD
t ENS
t ENH
t ENH
REN
tA
tA
PAE OFFSET
DATA IN OUTPUT REGISTER
Q0 - Qn
PAF OFFSET
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
4667 drw 22
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKL
tCLKL
WCLK
1
tENS
1
2
2
tENH
WEN
tPAFS
PAF
tPAFS
(2)
(2)
D - (m+1) words in FIFO
D - m words in FIFO
tSKEW2(3)
D-(m+1) words
in FIFO(2)
RCLK
tENS
tENH
REN
4667 drw 23
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768
for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,
65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
31
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
tCLKH
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2),
n+1 words in FIFO (3)
(4)
tSKEW2
RCLK
1
n+1 words in FIFO
n+2 words in FIFO
tPAES
2
n words in FIFO (2),
n+1 words in FIFO (3)
(2)
,
(3)
tPAES
1
tENS
2
tENH
REN
4667 drw 24
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAFA
PAF
D - m words
in FIFO
D - (m + 1) words in FIFO
D - (m + 1) words
in FIFO
tPAFA
RCLK
tENS
REN
4667 drw25
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the
IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT Mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,
65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
32
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
tCLKH
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
n words in FIFO(2),
n + 1 words in FIFO(3)
PAE
n + 1 words in FIFO(2),
n + 2 words in FIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
tPAEA
RCLK
tENS
REN
4667 drw 26
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
tHF
HF
[
D/2 words in FIFO(1),
D-1
(2)
2 + 1 words in FIFO
[
]
D/2 + 1 words in FIFO(1),
D-1
(2)
2 + 2 words in FIFO
]
[
D/2 words in FIFO(1),
D-1
(2)
2 + 1 words in FIFO
]
tHF
RCLK
tENS
REN
4667 drw 27
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the
IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680,
32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
33
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
OPTIONAL CONFIGURATIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
Figure 22 demonstrates a width expansion using two IDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690/72V36100/72V36110 devices. D0 - D35 from each device form a 72-bit wide input bus and Q0-Q35 from
each device form a 72-bit wide output bus. Any word width can be attained by
adding additional IDT72V3640/72V3650/72V3660/72V3670/72V3680/
72V3690/72V36100/72V36110 devices.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m+n
DATA IN
D0 - Dm
m
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR) #1
(1)
GATE
n
FULL FLAG/INPUT READY (FF/IR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
FIFO
#1
FIFO
#2
m
Q0 - Qm
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
n
Qm+1 - Qn
GATE
m+n
DATA OUT
4667 drw 28
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 23. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,536 x 72 and 131,072 x 72 Width Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V3640 can easily be adapted to applications requiring depths
greater than 1,024, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660,
8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the
IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110
with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series
(the data outputs of one FIFO connected to the data inputs of the next) with no
external logic necessary. The resulting configuration provides a total depth
equivalent to the sum of the depths associated with each single FIFO. Figure
23 shows a depth expansion using two IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690/72V36100/72V36110 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
34
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT/SI
TRANSFER CLOCK
WRITE CLOCK
FWFT/SI
WCLK
WRITE ENABLE
WEN
INPUT READY
IR
DATA IN
n
Dn
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
FWFT/SI
RCLK
WCLK
OR
WEN
REN
OE
Qn
IR
GND
n
Dn
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
READ CLOCK
RCLK
REN
READ ENABLE
OR
OUTPUT READY
OE
OUTPUT ENABLE
n
DATA OUT
Qn
4667 drw 29
Figure 24. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36 and 262,144 x 36 Depth Expansion
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
For an empty expansion configuration, the amount of time it takes for OR of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK period.
Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
35
ORDERING INFORMATION
IDT
XXXXX
X
XX
X
Device Type
Power
Speed
Package
X
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
Thin Plastic Quad Flatpack (TQFP, PK128-1)
7.5
10
15
Commercial Only
Commercial Only
Com’l & Ind’l
L
Low Power
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
1,024 x 36 
2,048 x 36 
4,096 x 36 
8,192 x 36 
16,384 x 36 
32,768 x 36 
65,536 x 36 
131,072 x 36 
Clock Cycle Time (tCLK)
Speed in Nanoseconds
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
NOTE:
1. Industrial temperature range is available by special order for speed grades faster than 15ns.
4667 drw 30
DATASHEET DOCUMENT HISTORY
05/25/2000
07/28/2000
12/14/2000
03/27/2001
04/06/2001
pgs.1, 6, 7, 8, 34 and 35.
pgs. 13, 14 and 34.
pgs. 6, 7 and 8.
pg. 7.
pgs. 4, 5 and 18.
CORPORATE HEADQUARTERS
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Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com*
for Tech Support:
408-330-1753
email: [email protected]
PFPkg: www.idt.com/docs/PSC4045.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The SuperSync ll FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
36