[ /Title (CD74H C157, CD74H CT157, CD74H C158, CD74H CT158) /Subject (High Speed The CD54HC158 and CD74HC158 are obsolete and no longer are supplied. CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 Data sheet acquired from Harris Semiconductor SCHS153C High-Speed CMOS Logic Quad 2-Input Multiplexers September 1997 - Revised October 2003 Features Description • Common Select Inputs The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2input multiplexers which select four bits of data from two sources under the control of a common Select input (S). The Enable input (E) is active Low. When (E) is High, all of the outputs in the 158, the inverting type, (1Y-4Y) are forced High and in the 157, the non-inverting type, all of the outputs (1Y-4Y) are forced Low, regardless of all other input conditions. • Separate Enable Inputs • Buffered inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC Moving data from two groups of registers to four common output buses is a common use of these devices. The state of the Select input determines the particular register from which the data comes. They can also be used as function generators. • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V Ordering Information • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout CD54HC157, CD54HCT157, CD54HC158, CD54HCT158 (CERDIP) CD74HC157, CD74HCT157, CD74HC158 (PDIP, SOIC) CD74HCT158 (PDIP) TOP VIEW S 1 16 VCC 1I0 2 15 E 1I1 3 14 4I0 1Y 4 13 4I1 2I0 5 12 4Y 2I1 6 11 3I0 2Y 7 10 3I1 GND 8 9 3Y TEMP. RANGE (oC) PACKAGE CD54HC157F3A -55 to 125 16 Ld CERDIP CD54HCT157F3A -55 to 125 16 Ld CERDIP CD54HCT158F3A -55 to 125 16 Ld CERDIP CD74HC157E -55 to 125 16 Ld PDIP CD74HC157M -55 to 125 16 Ld SOIC CD74HC157MT -55 to 125 16 Ld SOIC CD74HC157M96 -55 to 125 16 Ld SOIC CD74HCT157E -55 to 125 16 Ld PDIP CD74HCT157M -55 to 125 16 Ld SOIC CD74HCT157MT -55 to 125 16 Ld SOIC CD74HCT157M96 -55 to 125 16 Ld SOIC CD74HCT158E -55 to 125 16 Ld PDIP PART NUMBER NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 Functional Diagram HC/HCT HC/HCT 157 158 1I0 1I1 2I0 2I1 3I0 3I1 4I0 4I1 2 4 3 5 1Y 1Y 2Y 2Y 3Y 3Y 4Y 4Y 7 6 11 9 10 14 12 13 1 15 S E TRUTH TABLE OUTPUT ENABLE SELECT INPUT E S I0 H X L DATA INPUTS 157 158 I1 Y Y X X L H L L X L H L L H X H L L H X L L H L H X H H L H = High Voltage Level, L = Low Voltage Level, X = Don’t Care 2 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V II VCC or GND - 6 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 6 - - 8 - 80 - 160 µA 3 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 0 5.5 - ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA ∆ICC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOADS INPUT HCT157 HCT158 I (All) 0.95 0.4 E 0.6 0.6 S 3 2.8 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 125 - 155 - 190 ns 4.5 - - 25 - 31 - 38 ns 5 - 10 - - - - - ns - 12 - - - - - ns - - 21 - 26 - 32 ns HC/HCT157 TYPES Propagation Delay (Figure 1) tPLH, tPHL CL = 50pF Data to Output HC157 CL =15pF HCT157 CL = 50pF 6 4 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL Enable to Output (Continued) TEST CONDITIONS tPLH, tPHL CL = 50pF HC157 CL =15pF 25oC Select to Output tPLH, tPHL CL = 50pF -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns 5 - 11 - - - - - ns - 12 - - - - - ns - - 23 - 29 - 35 ns HCT157 CL = 50pF -40oC TO 85oC VCC (V) 6 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns 5 - 12 - - - - - ns - 15 - - - - - ns - - 25 - 31 - 38 ns HC157 - 62 - - - - - pF HCT157 - 70 - - - - - pF 2 - - 140 - 175 - 210 ns 4.5 - - 28 - 35 - 42 CL =15pF 5 - 11 - - - - - ns - 13 - - - - - ns CL = 50pF 6 - - 24 - 30 - 36 ns tPLH, tPHL CL = 50pF 2 - - 160 - 200 - 240 ns 4.5 - - 32 - 40 - 48 ns HC157 CL =15pF HCT157 CL = 50pF Power Dissipation Capacitance (Notes 3, 4) CPD - 6 5 HC/HCT158 TYPES Data to Output tPLH, tPHL CL = 50pF HC158 HCT 158 Enable to Output HC158 CL =15pF 5 HCT 158 Select to Output - - - - - ns - - - - - ns 6 - - 27 - 34 - 41 ns tPLH, tPHL CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns 5 - 12 - - - - - ns - 14 - - - - - ns 6 - - 26 - 33 - 38 ns CL =15pF HCT 158 CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC158 - 35 - - - - - pF HCT 158 - 35 - - - - - pF - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) Input Capacitance 13 15 CL = 50pF HC158 Output Transition Time - tTLH, tTHL CPD CIN CL = 50pF - CL = 50pF 5 - NOTES: 3. CPD is used to determine the dynamic power consumption, per multiplexer. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. 5 CD54/74HC157, CD54/74HCT157, CD54/74HC158, CD54/74HCT158 Test Circuits and Waveforms tr = 6ns tf = 6ns VCC 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9070201MEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type 5962-9070301MEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) CD54HC157F ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HC157F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT157F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD54HCT158F3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD74HC157E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC157EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC157M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC157SM OBSOLETE SSOP DB 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT157EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT157M ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157M96 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157M96E4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157M96G4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157ME4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157MG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157MT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT157MTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT157MTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT158E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT158EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC157M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT157M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC157M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT157M96 SOIC D 16 2500 333.2 345.9 28.6 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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