Fairchild FIN212AC 12-bit serializer deserializer with multiple frequency range Datasheet

FIN212AC
12-Bit Serializer Deserializer with Multiple Frequency Ranges
Features
Description
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Low Power Consumption
The FIN212AC µSerDes is a low-power serializer /
deserializer optimized for use in cell phone displays and
camera paths. The device reduces a 12-bit data path to
four wires. The device can be configured as a serializer
or deserializer through the DIRI pin, minimizing
component types in the system. For camera
applications, an additional master clock can be passed
in the opposite direction of data flow.
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Adjustable Parallel Edge Rate
Low Power, Proprietary, CTL I/O Serial Interface
Wide PLL Input Frequency Range
Wide Parallel Supply Voltage Range: 1.65 to 3.6V
Low Power Core Operation: VDDS/A=2.5 to 3.6V
Built-in LV-CMOS Voltage Translation Capability
with no External Components
Operates as Serializer or Deserializer
Standby Power-Down Mode Support
Built-in Differential Termination
The device utilizes Fairchild’s proprietary ultra-low
power, low-EMI technology. LV-CMOS parallel output
buffers have been implemented with slew rate control to
adjust for capacitive loading and to minimize EMI. The
device also supports an ultra-low power-down mode for
conserving power in battery-operated applications
The device is available in a 5x5mm MLP package to
attach directly to a flex circuit, or in two choices of BGA,
where space constraints are a concern.
Applications
ƒ 8-Bit LCD Displays for Cell Phones
ƒ 8/10-Bit Cell Phone Camera Interface
ƒ 8-Bit LCD Displays for Printers
Related Application Notes
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AN-5058 µSerDes™ Family Frequently Asked
Questions
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AN-5061 µSerDes™ Layout Guidelines
Ordering Information
Order Number
Package
PbFree
Operating
Temperature
Range
Package Description
Packing
Method
FIN212ACMLX
MLP032A
Yes
-30 to 70°C
32-Terminal Molded Leadless Package
(MLP), Quad, JEDEC MO-220, 5mm square
Tape &
Reel
FIN212ACGFX
BGA42A
Yes
-30 to 70°C
42-Ball Ultra Small-Scale Ball Grid Array
(USS-BGA), JEDEC MO-195, 3.5 x 4.5mm
wide, 0.5mm Ball Pitch
Tape &
Reel
FIN212ACBFX
BGA36A
(Preliminary)
Yes
-30 to 70°C
36-Ball Ultra Small Scale Ball Grid Array
(USS-BGA), JEDEC MO-xxx 2.5mm square,
0.4mm Ball Pitch
Tape &
Reel
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
March 2007
Pin
I/O type
# of
Pins
DP[1:12]
CMOS-I/O
12
LV-CMOS Parallel I/O. Direction controlled by DIRI pin.
CKREF
CMOS-IN
1
LV-CMOS clock input and PLL reference.
STROBE
CMOS-IN
1
LV-CMOS strobe input for latching data into the serializer.
CKP
CMOSOUT
1
LV-CMOS word clock output.
DSO+(DSI-)(1)
DSO-(DSI+)
DIFF-I/O
2
CTL Differential serial I/O data signals.(2)
DS(I)+: Positive signal of DS(I) pair; DS(I)-: Negative signal of DS(I) pair.
CKSI+, CKSI-
DIFF-IN
2
CTL Differential deserializer input bit clock.
CKSI+: Positive signal of CKSI pair; CKSI-: Negative signal of CKSI pair.
CKSO+,
CKSO-
DIFF-OUT
2
CTL Differential serializer output bit clock.
CKSO+: Positive signal of CKSO pair;
CKSO-: Negative signal of CKSO pair.
S0, S1
CMOS-IN
1
DIRI=1: signals are used to define frequency range for the PLL. DIRI=0:
Signals are used to define the edge rate of the deserializer parallel I/Os.
PLL0(PWS0)
CMOS-IN
1
DIRI=1: PLL0 signal is used to divide or adjust the serial frequency.
DIRI=0: PWS0 signal is used to set the width of the CKP output pulse.
PLL1(PWS1)
CMOS-IN
1
DIRI=1: PLL1 Signal is used to divide the serial frequency.
DIRI=0: PWS1 pin controls the output pulse width.
TEST /
(XTRM)
CMOS_IN
1
DIRI=1: TEST=0, Normal Operation. DIRI=0: Termination enable
functionality for deserializer. XTRM=0 Internal termination. XTRM=1
External termination required. Ground this pin for serializer.
CTL_ADJ
(GND)
CMOS_IN
1
Adjusts CTL drive for serializer. Ground this pin for deserializer.
DIRI
IN
1
LV-CMOS Control Input. Used to control direction of data flow: DIRI= “1”
Serializer, DIRI=“0” Deserializer
/DIRO
OUT
1
LV-CMOS Output. Inversion of DIRI in normal operation mode.
VDDP
Supply
1
Power supply for parallel I/O and translation circuitry.
VDDS
Supply
1
Power supply for core and serial I/O.
VDDA
Supply
1
Power supply for analog PLL circuitry.
GND
Supply
0
Ground center pad, ground D4, E3 and NCs for 42-ball BGA. Ground B5,
C2, C4 for 36-ball BGA.
Description of Signals
Notes:
1. () Indicate deserializer functionality when DIRI=0.
2. The DS serial port pins are arranged such that when one device is rotated 180 degrees from the other device,
the serial connections properly align without the need for any traces or cable signals to cross. Other layout
orientations may require that traces or cables cross.
3. All unused LV-CMOS input signals should be connected to GND or VDDP. Signals can be connected directly to
the rail or through a resistor.
4. All unused LV-CMOS output signals should be allowed to float.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pin Definitions
www.fairchildsemi.com
2
DP[3]
DP[2]
DP[1]
(XTRM)
CTL_ADJ
STROBE
CKREF
DIRO
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
CKSO+
CKSODSO+/DSIDSO-/DSI+
CKSICKSI+
DIRI
VDDS
DP[10]
DP[11]
DP[12]
PLL1(PWS1)
PLL0(PWs0)
S1
S0
VDDA
9
10
11
12
13
14
15
16
DP[4]
DP[5]
DP[6]
VDDP
CKP
DP[7]
DP[8]
DP[9]
Figure 1.
1
2
3
4
5
Pin Assignments for 32-Pin MLP (5x5mm, .5mm Pitch, Top View)
6
1
2
3
4
5
6
CKREF
A
A
DP4
DP2
XTRM
CTL_ADJ
n/c
B
B
DP6
DP5
DP1
n/c
STROBE
/DIRO
C
C
CKP
N/C
DP3
n/c
CKSO+
CKSO-
D
D
N/C
DP7
VDDP
GND
DSO-/DSI+
DS0+/DSI-
E
E
DP8
DP9
GND
VDDS
CKSI+
CKSI-
n/c
VDDA
n/c
DIRI
S1
S0
F
F
DP10
DP11
G
G
DP12
n/c
Figure 2.
(
1
p
2
3
)
4
5
PLL1(PWS1) PLL0(PWS0)
Pin Assignments for 42 BGA (3.5x4.5mm, .5mm Pitch, Top View)
6
1
2
3
4
5
6
CKREF
A
A
DP4
DP2
DP1
(XTRM)
STROBE
B
B
DP6
DP5
DP3
CTL_ADJ
GND
/DIRO
C
C
CKP
GND
VDDP
GND
CKSO+
CKSO-
D
D
DP7
DP8
GND
VDDS
DSO-/DSI+
DS0+/DSI-
E
E
DP9
DP10
S0
CKSI+
CKSI-
F
F
DP11
DP12
PLL1(PWS1)
/
PLL0(PWS0)
S1
VDDA
DIRI
Figure 3.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pin Assignments
Pin Assignments for 36 BGA (2.5x2.5mm, .4mm Pitch) Preliminary
www.fairchildsemi.com
3
Mode
PLL0
PLL1 S1 S0
0
X
X
0
0
1
1
0
0
1
1
0
0
0
1
1
X
X
0
1
2
1
0
1
0
2
0
0
1
0
2
X
X
1
0
3
1
0
1
1
3
0
0
1
1
3
x
X
1
1
Table 1. Control Logic Circuitry
DIRI
X
1
1
0
1
1
0
1
1
0
Description
Power-Down Mode
12-Bit Serializer, Standard Clocking, 20MHz to 40MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 19MHz to 38.2MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 5MHz to 14MHz CKREF
12-Bit Serializer, Over-0Clocked PLL, 4.7MHz to 13.3MHz CKREF
12-Bit Deserializer
12-Bit Serializer, Standard Clocking, 8MHz to 28MHz CKREF
12-Bit Serializer, Over-Clocked PLL, 9.5MHz to 26.7MHz CKREF
12-Bit Deserializer
No-Divide mode should be used for standard 8-bit pixel
interface where the STROBE and CKREF frequencies
are identical.
[DIRI] Direction Logic: The FIN212 can be configured
as a 12-bit serializer or deserializer based on the state
of the DIRI signal. When DIRI is 1, the device is a
serializer. When DIRI is 0, the device is a deserializer.
The /DIRO signal is an inversion of the DIRI signal. The
/DIRO signal of the master can be used to drive the DIRI
signal of the slave in applications where the interface
needs to be turned around.
Divide-by-2 and Divide-by-3 modes are useful in
microcontroller interfaces where the CKREF frequency is
significantly higher than the required STROBE frequency.
[S0, S1] Mode Select: The mode select signals, S1 and
S0, are used for different purposes when the device is a
serializer or a deserializer. For the serializer, the pins
need to be set to the correct value of the input CKREF
Frequency range.
PLL1
For the deserializer the signals are used to select an
edge rate value. The fastest edge rates correspond to
the highest frequency mode. This relationship is
maintained for all modes.
DIRI=0
S1
S0
Frequency
Range
0
0
0
Power-Down
1
0
1
FAST
2
1
0
SLOW
Mode #
3
1
1
Table 2. Deserializer Edge Rates
Serializer Frequency
Multiplier
0
0
7.3x
Over-clocking
0
1
7x
No Divide
1
0
3.5x
Divide by 2
1
1
2.3x
Table 3. Frequency Multipliers
Divide by 3
Internal STROBE Filter: When the PLL starts, the
STROBE signal is internally held off until the PLL is
locked. This prevents any spurious data from being
passed through the device.
[PWS0, PWS1] Pulse Width Adjust Circuitry: The
word clock strobe output (CKP) pulse width can be
adjusted through the PWS0 and PWS1 signals. The
signals can be used to lengthen the width of the LOW
pulse or invert the pulse in RGB applications with a 50%
duty cycle.
MEDIUM
DIRI=0
PWS1
PWS0
[PLL0, PLL1] PLL Frequency Select Signals: The
PLL1 and PLL0 signals provide additional flexibility in
generating the serial clock frequency. The PLLn signals
only function when the device is a serializer (DIRI=1).
When the device is a slave, these pins are used for
pulse width adjustment.
Over-clocking mode is used when the input reference
clock has been implemented with significant spread
spectrum. Over-clocking allows the serializer to tolerate
a large amount of CKREF frequency spread.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
DIRI=1
PLL0
Low Time
(Bits)
No Divide
Polarity (CKP
Read Edge)
0
0
7
LH
0
1
7
HL
1
0
13
LH
1
1
17
LH
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Control Logic Circuitry
Table 4. Pulse Width Adjust Circuitry at Serial
CLK Period
www.fairchildsemi.com
4
Signal Pins
DIRI=1
DIRI=0
DP[10:1]
Inputs Disabled
Outputs HIGH-Z
DP[12:11]
Inputs Disabled
Outputs HIGH-Z
CKP
HIGH
Outputs HIGH-Z
STROBE
Input Disabled
Input Disabled
CKREF
Input Disabled
Input Disabled
/DIRO
0
Table 5. Output States
CTL_ADJ
0
Description
Standard CTL Drive
1
High CTL Drive
Table 6. CTL_ADJ Functionality
[(/XTRM]] Test / XTRM Mode Functionality: For the
deserializer, the (XTRM) signal can be used to enable
or disable the internal termination resistor on the CKS
and DS signals of the deserializer. When the internal
termination is disabled, an external termination resistor
is required for the CTL I/O to operate properly.
1
When an input is disabled, it does not draw current,
regardless of the state or level of the input signal.
(XTRM)
All of the LV-CMOS inputs must remain driven during
power-down to ensure a low-power state
Turn-Around Functionality: The device passes and
inverts the DIRI signal asynchronously to the /DIRO
signal. Care must be taken by the system designer to
ensure that no contention occurs between the
deserializer outputs and the other devices on this port.
Optimally the peripheral device driving the serializer
should be put into a HIGH-impedance state prior to the
DIRI signal being asserted. When a device with
dedicated data outputs turns from a deserializer to a
serializer, the dedicated outputs remain at the last
logical value asserted. This value only changes if the
device is once again turned around into a deserializer
and the values are overwritten.
DIRI=0 (/XTRM)
0
Internal Termination
1
External Termination
Table 7. (/XTRM) Functionality
Serializer Configuration (DIRI=1)
1.
Master CLK transmitted out of SER CKP
2.
Drive the pixel_CLK [(/XTRM)] into SER TROBE
Deserializer Configuration (DIRI=0)
1.
Strobe Pass-Through Mode: For some applications,
it is desirable to pass a word clock across a
differential signal pair in the opposite direction of
serialization. The FIN212 supports this mode of
operation. The following describes how to enable this
functionality.
Pixel_CLK transmitted out of DES CKP
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
[CTL_ADJ] CTL Drive Adjustment: The drive
characteristics of the CTL I/O can be adjusted through
the CTL_ADJ pin. Standard-level CTL drive is
provided when the CTL_ADJ pin is zero. High- level
drive is provided when CTL_ADJ pin is HIGH. Highdrive should be used in noisy environments or when
driving cables longer than 20cm. When in high-drive
mode, CTL drive increases by approximately by 50%.
Power-Down Functionality: When both S1 and S0
signals are 0, regardless of the state of the DIRI
signal, the FIN212AC resets and powers down. The
power-down mode shuts down all internal analog
circuitry, disables the serial input and output of the
device, and resets all internal digital logic. Table 5
indicates the state of the output buffers in PowerDown mode.
Deserializer Configuration (DIRI=0)
1.
CKREF LOW
2.
Master clock connected DES to STROBE
Serializer Configuration (DIRI=1)
1.
CKSI passes signal to serializer CKP
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
5
be provided to the CKREF signal. The CKREF clock
signal must be continuously running for as long as data is
being transferred. The actual serial transfer rate is
dependent on the CKREF and the parallel transfer rate
depends on the STROBE frequency. A data value of zero
is sent when no valid data is present in the serial bit
stream. The operation of the serializer otherwise remains
the same. The exact frequency that the reference clock
needs to run is dependent upon the stability of the CKREF
and STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the minimum
frequency of this spread spectrum clock should be used in
calculating the ratio of STROBE frequency to the CKREF
frequency. Similarly if the STROBE signal has significant
cycle-to-cycle variation, the maximum cycle-to-cycle time
needs to be factored into the selection of the CKREF
frequency. A STROBE frequency of 7MHz and a CKREF
of 11MHz results in serial CLK frequency seven times the
CKREF (77MHz) and a data transfer rate of 154Mbps.
The serializer configurations are described in the
following sections. The basic serialization circuitry works
similarly in all modes, but the actual data and clock
streams differ if the frequency of CKREF is the same as
or greater than the STROBE frequency. When CKREF
equals STROBE, the CKREF and STROBE signals are
physically connected together and are one signal. When
CKREF does not equal STROBE, each signal is distinct
and CKREF must be running at a frequency high
enough to avoid any loss of data condition. CKREF
must never be a lower frequency than STROBE. For
proper serialization, the PLL should be stable and
locked prior to sending valid data. For the following
modes, refer to Table 1.
MODE 1,2,3; PLL1=0, PLL0=1;
CKREF Equals STROBE
This mode is typically used when sending pixel data at a
constant rate. Data is captured on the rising edge of the
STROBE signal and serialized. The serial CLK
frequency is exactly seven times the clock frequency.
For example, a CKREF frequency of 10MHz results in a
serial CLK frequency of 70MHz and a data transfer rate
of 140Mbps. The serialized data stream is synchronized
and sent source synchronously with a bit clock.
MODES (1,2,3); PLL1=1,PLL0=0 (Divide-by-2) or
PLL1=1,PLL0=1 (Divide-by-3)
For some microcontroller applications, the available
reference frequency is significantly faster than the
STROBE frequency required for the application. To
more closely match the serial frequency with the strobe,
the reference frequency can be divided by two or three.
The serializer works identically to when CKREF is not
equal to STROBE. Refer to the Deserializer Operation
Mode section below for details.
MODE 1,2,3; PLL1=0, PLL0=1;
CKREF Does Not Equal STROBE
For microcontroller interfaces, a reference clock at the
same frequency as the strobe is typically not available.
Data transfers are typically not synchronous. To
accommodate this type of transfer, a reference clock of a
higher frequency than the fastest strobe frequency must
Deserializer Operation Mode
serial port and deserialized through a bit clock sent with
the data. The falling edge of CKP occurs coincident with
the parallel data transition.
The operation of the deserializer is dependent upon the
data received on the DSI data signal pair and the CKSI
clock signal pair. The following sections describe the
operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and
STROBE signals refer to the signals associated with the
serializer device used to generate the serial data and
clock signals. When operating in this mode, the internal
serializer circuitry is disabled, including the parallel data
input buffers. If there is a CKREF signal provided, the
CKSO serial clock continues to transmit bit clocks.
DIRI=0; Serializer Source:
CKREF Does Not Equal STROBE
The logical operation of the deserializer remains the
same whether CKREF is equal in frequency to STROBE
or at a higher frequency than STROBE. The duty cycle
of CKP varies based on the ratio of the frequency of the
CKREF signal to the STROBE signal. The average
frequency of the CKP signal is equal to the STROBE
frequency. The falling edge of CKP is coincident with
data transition. The LOW time of the CKP signal is set
by the state of the PWS1 and PWS0 signals.
DIRI = 0; Serializer Source: CKREF Equals STROBE
When the DIRI signal is asserted LOW, the device is
configured as a deserializer. Data is captured on the
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Serializer Operation Mode (DIRI=1)
www.fairchildsemi.com
6
Pulse Width Low Tpwl = (divOut*Pwdth)/(CKREF*14)
To meet minimum pulse width specification, divOut*Pwdth≥Tpwl*(TCKREF*14).
Bit times based on PWS0, PWS1 (Pwdth = 7, 13, 17), divide by divOut = 0.954, 1, 2, 3.
Example: Tpwl=60ns CKREF=26MHz
CKP Pulsewidth = (2*13)/(26MHz*14)
if DivOut=2, Pwdth=13 bitTimes=26. Tpwl=71.4ns
Serializer Setup
PLL1
PLL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Deserializer Setup
PWS1
PWS0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PLL
DivOut
Pwidth
CKP-PWL
Bit Times
0.954
0.954
0.954
0.954
1
1
1
1
2
2
2
2
3
3
3
3
7
7
13
17
7
7
13
17
7
7
13
17
7
7
13
17
6.7
6.7
12.4
16.2
7
7
13
17
14
14
26
34
21
21
39
51
CKREF Frequency
19.2MHz
26Mhz
24.8
24.8
46.1
60.3
26.0
26.0
48.4
63.2
52.1
52.1
96.7
126.5
78.1
78.1
145.1
189.7
18.3
18.3
34.1
44.6
19.2
19.2
35.7
46.7
38.5
38.5
71.4
93.4
57.7
57.7
107.1
140.1
(5)
Table 8. CKP Pulse Widths (in nanoseconds) for Standard Cell Phone Operating Frequencies
Note:
5. CKP Pwidth assumes minimal slew rate at the 50% transition point.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
7
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Pulse Width Calculations
The following application diagrams illustrate the most typical applications for the FIN212 device. Specific
configurations of the control pins may vary based on the needs of a given system. The following recommendations
are valid for all of the applications shown.
Figure 4.
8-Bit RGB Application (Example Shows BGA 42-Pin Package)
Serializer Configuration:
ƒ PLL Frequency Mode: MODE 3 (S1=S0=1) 10-30MHz Frequency Range
ƒ PLL Divide Mode: Over-Clocked Mode (PLL1=PLL0=0); 7.3 Serial Frequency Multiplier
Deserializer Configuration:
ƒ
ƒ
ƒ
ƒ
Edge Rate Mode: Medium MODE 3 (S1=S0=1)
Pulse Width Mode: Standard Non-Inverting, (PWS1=PWS0=0) Pulse Width; 3.5 x Serial CLK Period
Pixel CLK is used to STROBE Display
Pin number for BGA packages
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
8
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Application Diagrams
Figure 5.
8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package)
Serializer Configuration:
ƒ PLL Frequency Mode: MODE 3 (S1=S0=1) 10-30MHz Frequency Range
ƒ PLL Divide Mode: Standard Not Over-Clocked (PLL1=0, PLL0=1) Multiplier 7x
ƒ Master Clock Bypass Mode: (clock passes from CKSI to CKP)
Deserializer Configuration:
ƒ Edge Rate Mode: Fast MODE 1 (S1=0, S0=1)
ƒ Pulse Width Mode: Standard Non-Inverting, (PWS1=PWS0=0) Pulse Width; 3.5 x Serial CLK Period
ƒ Master Clock Bypass Mode: Clock passes from STROBE to CKSO
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
9
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Application Diagrams (Continued)
Figure 6.
Dual Display with 8-Bit WRITE-Only Microcontroller Interface
(Example Shows BGA 42-Pin Package)
Serializer Configuration:
ƒ PLL Frequency Mode: MODE 1 (S1=0, S0=1) CKREF=26MHz
ƒ STROBE Frequency = 10 MHz
ƒ PLL Divide Mode: Divide-by 2 (PLL1=1, PLL0=0) Multiplier x 3.5
Deserializer Configuration:
ƒ Edge Rate Mode: SLOW MODE 1 (S1=1, S0=0)
ƒ Pulse Width Mode: 13-Bit Time Mode (PWS1=PWS0=0) (~71.4ns)
Additional Application Information
Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this
serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB.
ƒ
ƒ
Keep all four differential Serial Wires the same length.
ƒ
ƒ
ƒ
ƒ
ƒ
Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
Do not allow noisy signals over or near differential serial wires.
Example: No LVCMOS traces over differential serial wires.
Design goal of 100-ohms differential characteristic impedance.
Do not place test points on differential serial wires.
Use differential serial wires a minimum of 2cm away from the antenna.
For additional applications notes or flex guidelines see your sales rep or contact Fairchild directly.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
10
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Application Diagrams (Continued)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VDD
Parameter
Supply Voltage
All Input/Output Voltage
CTL Output Short-Circuit Duration
TSTG
TJ
TL
ESD
Min.
Max.
Unit
-0.5V
+4.6
V
-0.5
VDD+0.5
V
+150
°C
Continuous
Storage Temperature Range
-65
Maximum Junction Temperature
+150
Lead Temperature (Soldering, four seconds)
+260
°C
°C
Human Body Model, 1.5KΩ, 100pF
8
kV
Human Body Model, 1.5KΩ, Serial I/O Pins
14
kV
Machine Model, 0Ω, 200pF
400
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VDDA, VDDS
Supply Voltage
2.5
3.6
V
VDDP
Supply Voltage
1.65
3.6
V
Operating Temperature
-30
+70
ºC
Supply Noise Voltage
100
TA
VDDA-PP
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
mVp-p
www.fairchildsemi.com
11
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Absolute Maximum Ratings
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.(6)
Max.
Unit
LVCMOS I/O
VIH
Input High Voltage
0.65xVDDP
VDDP
VIL
Input Low Voltage
GND
0.35xVDDP
V
0.75xVDDP
VDDP
V
0
0.25xVDDP
V
-5.0
5.0
µA
IOH=-2.0mA, S1=0,S0=1
VOH
Output High Voltage
IOH=-0.4mA, S1=1,S0=0
IOH=-1.0mA, S1=1,S0=1
IOL=2.0mA, S1=0,S0=1
VOL
Output Low Voltage
IOL=0.4mA, S1=1,S0=0
IOL=1.0mA, S1=1,S0=1
IIN
Input Current
VIN= 0V to 3.6V
DIFFERENTIAL I/O
IODH
Output HIGH Source
Current
VOS=1.0V
IODL
Output LOW Sink Current
VOS=1.0V
VGO(7)
RTRM
CTL_ADJ=0
-2.0
CTL_ADJ=1
-3.4
CTL_ADJ=0
1.2
CTL_ADJ=1
2.0
Input Voltage Ground
Offset
mA
mA
0
V
CKS Internal Receiver
Termination Resistor
VID= 50mV, VIC= 925mV,
DIRI = 0
80
100
120
Ω
DS Internal Receiver
Termination Resistor
VID=50mV, VIC= 925mV,
DIRI = 0
80
100
120
Ω
Notes:
6. Typical values are given for VDD=2.775V and TA=25 °C. Positive current values refer to the current flowing into
the device and negative values refer to the current flowing out of pins. Voltages are referenced to GROUND
unless otherwise specified (except ΔVOD and VOD).
7. VGO is the difference in device ground levels between the CTL driver and the CTL receiver.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
12
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
DC Electrical Characteristics
Symbol
IDD_PD
Parameter
VDD Power-Down Supply
Current
IDD_PD= IDDA + IDDS + IDDP
Test Conditions
IDD_SER1
fCKREF = fSTRB,
PLL1=0,PLL0=1;
CTL_ADJ=0; CL = 0pF
S1=H
S0=L
S1=H
S0=H
S1=L
S0=H
IDD_DES1
Dynamic Deserializer Power
Supply Current
IDD_DES1= IDDA+IDDS+IDDP
fCKREF = fSTRB,
PLL1=0,PLL0=1;
CTL_ADJ=0; CL = 0pF
S1=H
S0=L
S1=H
S0=H
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
Typ.
Max.
Unit
0.1
µA
20MHz
13.0
mA
40MHz
19.0
mA
5MHz
9.5
mA
14MHz
17.0
mA
8MHz
11.0
mA
28MHz
20.0
mA
20MHz
10.0
mA
40MHz
14.0
mA
5MHz
8.0
mA
14MHz
9.0
mA
8MHz
9.0
mA
28MHz
12.0
mA
S1 = S0 = 0, All Inputs at GND or VDD
S1=L
S0=H
Dynamic Serializer Power
Supply Current
IDD_SER1= IDDA+IDDS+IDDP
Min.
www.fairchildsemi.com
13
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Power Supply Currents
Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Serializer Input Operating Conditions
fCKREF
fSTRB
CKREF Clock Frequency
(5MHz - >40MHz)
Strobe Frequency
Relative to CKREF
Frequency
fCKREF =
fSTRB
fCKREF ≠
fSTRB
S1=0, S0=1
18
40
S1=1, S0=0
5
14
S1=1, S0=1
10
28
PLL1=0, PLL0=0
100
PLL1=0, PLL0=1
100
PLL1=1, PLL0=0
50
PLL1=1, PLL0=1
331/3
MHz
% of
fCKREF
tCPWH
CKREF DC
T=1/fCKREF
0.2
0.5
0.8
T
tCPWL
CKREF DC
T=1/fCKREF
0.2
0.5
0.8
T
tCLKT
LVCMOS Input
(8)
Transition Time
10-90%
20
ns
STROBE Pulse Width
HIGH/LOW
T=1/fCKREF
T x 10/14
ns
tSPWH/L
tSTC
DP(n) Setup to STROBE
tHTC
DP(n) Hold to STROBE
T x 4/14
DIRI=1, f=5MHz
See Figure 7
2.5
ns
2.0
ns
Serializer AC Electrical Characteristics
tTCCD
Transmitter Clock Input
(9)
to Clock Output Delay
DIRI=1, fCKREF = fSTRB
See Figure 9
21a+1.5
23a+6.5
ns
200
600
μs
Phase Lock Loop (PLL) AC Electrical Characteristics
tTPLLS0
Serializer PLL
Stabilization Time
tTPLLD0
PLL Disable Time Loss
of Clock
30.0
μs
tTPLLD1
PLL Power-Down Time
20.0
ns
CKREF toggling and stable
Notes:
8. Parameter is characterized, but not production tested.
9. The average bit time “a” is a function of the serializer CKREF frequency; a=(1/f)/14.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
14
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
AC Electrical Characteristics
Values are provided for over-supply and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Deserializer AC Electrical Characteristics
tRCOL
CKP OUT Low Time
See Figure 8(10)
tPDV
Data Valid to CKP
HIGH
tRFD
Output Rise/Fall
Time Data (20% to
80%)
tRFC
Output Rise/Fall
Time CKP (20% to
80%)
PWS1
PWS0
fSTRB = fCKREF
0
0
7a-3
7a+3
fSTRB = fCKREF
0
1
7a-3
7a+3
fSTRB = .5x fCKREF
1
0
13a-3
13a+3
fSTRB = .5x fCKREF
1
1
17a-3
17a+3
, CL=5pF
8a-3
8a+3
(Rising Edge STROBE)
See Figure 8
CL=8pF
CL=8pF
ns
(10)
S1=0,S0=1
3.0
S1=1,S0=0
8.0
S1=1,S0=1
5.0
S1=0,S0=1
2.0
S1=1,S0=0
7.0
S1=1,S0=1
4.0
ns
ns
ns
Notes:
10. Skew is measured from the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
11. Signals are transmitted from the serializer source synchronously. In some cases, data is transmitted when the
clock remains at a high state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew is a combination of output skew from the serializer, load variations, and ISI and
jitter effects.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
15
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
AC Electrical Characteristics (Continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
t PHL_DIR,
tPLH_DIR
Propagation Delay
DIRI to /DIRO
DIRI L->H or H->L
17
ns
tPLZ, tPHZ
Propagation Delay
DIRI to DP
DIRI L->H or H->L
25
ns
tDISDES
Deserializer Disable Time: S0
or S1 LOW to DPTri-State
DIRI=0, See Figure 10
25
ns
tDISSER
Serializer Disable Time: S0 or
S1 LOW to CKP HIGH
DIRI=1; S1(0) and S0(1)=H->L
25
ns
Max.
Unit
Pin Capacitance Tables
Symbol
Parameter
Test Conditions
Min.
Typ.
CIN
Capacitance of Input Only
Signals
DIRI=1, S1=0, S0=0, VDD=2.5V
2.0
pF
CIO
Capacitance of Parallel Port
Pins DP[1:12]
DIRI=1, S1=0, S0=0, VDD=2.5V
2.0
pF
Capacitance of Differential I/O
Signals.
DIRI=1, S1=0, S0=0, VDD=2.5V
2.0
pF
CIO-DIFF
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
16
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Logic Timing Controls
Setup Time
Data Valid
tS TC
S TR OBE
CKP
DP[1:12]
DP[1:12]
Data
Hold Time
Data
tRCOP
tHTC
75%
S TR OBE
DP [1:12]
tPDV
CKP
50%
50%
25%
Data
tRCOH
Setup: MODE0= “0” or “1”, MODE1=“1”, SER/DES=“1”
Figure 7.
tRCOL
Setup: DIRI= 0, CKSI and DS are valid signals.
Figure 8.
Serializer Setup and Hold Time
Deserializer Data Valid Time and
Clock Output Parameters
tTCCD
STROBE
tRCCD
VDD/2
CKS -
VDIFF=0
CKS +
CKP
VDD/2
Note: STROBE=CKREF
Figure 9.
Clock Propagation Delay
tDISDES
S1 or S2
DP
Note: If S1(2) is transitioning, S2(1) must =0 for test to be valid.
Figure 10.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
Deserializer Disable Timing
www.fairchildsemi.com
17
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Typical Performance Characteristics
MLP Embossed Tape Dimensions
Dimensions are in millimeters unless otherwise noted.
D
P0
T
P2
E
F
K0
W
Wc
B0
Tc
A0
Package
A0
B0
D
5x5
5.35±0.1
5.35±0.1
6x6
6.30±0.1
6.30±0.1
1.55
±0.05
D1
P1
D1
E
F
K0
1.5 min.
1.75
±0.1
5.5
±0.1
1.4
±0.1
User Direction of Feed
P1
8 typ.
P0
P2
T
TC
W
WC
4 typ.
2.0
0.05±
0.3
typ.
0.07
±0.005
12
±0.3
9.3 typ.
Notes:
A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
MLP Shipping Reel Dimensions
Dimensions are in millimeters unless otherwise noted.
1.0mm
maximum
10° maximum
Typical component
cavity center line
Typical component
center line
B0
10° maximum component rotation
Sketch A (Side or Front Sectional View)
1.0mm
maximum
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
Component Lateral Movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min
Dia C
Dia A
max
Dia D
min
Dia N
DETAIL AA
See detail AA
Tape
Width
Dia A
Dim B
Dia C
1.5 min.
13.0
+0.5/-0.2
8
12
330.0 max.
Dia D
20.2 min.
16
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
W3
Dim N
Dim W1
178.0 min.
8.4
+2.0/-0
Dim W2
Dim W3
(LSL-USL)
14.4 max.
7.9 ~ 10.4
18.4 max.
11.9 ~ 15.4
22.4 max.
15.9 ~ 19.4
www.fairchildsemi.com
18
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Tape and Reel Specifications
BGA Embossed Tape Dimensions
Dimensions are in millimeters unless otherwise noted.
D
P0
T
P2
E
F
K0
W
Wc
B0
Tc
A0
Package
3.5 x 4.5
A0
TBD±0.1
P1
D1
User Direction of Feed
B0
D
D1
E
F
K0
P1
P0
P2
T
TC
W
WC
TBD±0.1
1.55
±0.05
1.5
min.
1.75
±0.1
5.5
±0.1
1.1
±0.1
8.0
typ.
4.0
typ.
2.0
±0/05
0.3
typ.
0.07
±0.005
12
±0.3
9.3
typ.
Notes:
A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
BGA Shipping Reel Dimensions
Dimensions are in millimeters unless otherwise noted.
1.0mm
maximum
10° maximum
B0
10° maximum component rotation
Sketch A (Side or Front Sectional View)
Typical component
cavity center line
Typical component
center line
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
1.0mm
maximum
Component Lateral Movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min
Dia C
Dia A
max
Dia D
min
Dia N
DETAIL AA
See detailAA
Tape
Width
Dia A
Dim B
Dia C
Dia D
Dim N
Dim W1
330.0 max.
1.5 min.
13.0
+0.5/-0.2
20.2 min.
178.0 min.
8.4
+2.0/-0
8
12
W3
16
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
Dim W2
Dim W3
(LSL-USL)
14.4 max.
7.9 ~ 10.4
18.4 max.
11.9 ~ 15.4
22.4 max.
15.9 ~ 19.4
www.fairchildsemi.com
19
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Tape and Reel Specifications (Continued)
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
Figure 11.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
32-Lead, Molded Leadless Package (MLP)
www.fairchildsemi.com
20
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 12.
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
42-Ball, Ball Grid Array (BGA) Package
www.fairchildsemi.com
21
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FACT
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FASTr™
FPS™
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FRFET
GlobalOptoisolator™
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Programmable Active Droop™
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QFET
QS™
QT Optoelectronics™
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RapidConfigure™
RapidConnect™
ScalarPump™
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STEALTH™
SuperFET™
SuperSOT™-3
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DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Definition
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
© 2006 Fairchild Semiconductor Corporation
FIN212AC Rev. 1.0.1
www.fairchildsemi.com
22
µSerDes™ FIN212AC — 12-Bit Serializer Deserializer with Multiple Frequency Ranges
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.